1 //===- RDFRegisters.cpp ---------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/ADT/BitVector.h"
10 #include "llvm/CodeGen/MachineFunction.h"
11 #include "llvm/CodeGen/MachineInstr.h"
12 #include "llvm/CodeGen/MachineOperand.h"
13 #include "llvm/CodeGen/RDFRegisters.h"
14 #include "llvm/CodeGen/TargetRegisterInfo.h"
15 #include "llvm/MC/LaneBitmask.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/Support/ErrorHandling.h"
18 #include "llvm/Support/raw_ostream.h"
19 #include <cassert>
20 #include <cstdint>
21 #include <set>
22 #include <utility>
23 
24 using namespace llvm;
25 using namespace rdf;
26 
27 PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
28       const MachineFunction &mf)
29     : TRI(tri) {
30   RegInfos.resize(TRI.getNumRegs());
31 
32   BitVector BadRC(TRI.getNumRegs());
33   for (const TargetRegisterClass *RC : TRI.regclasses()) {
34     for (MCPhysReg R : *RC) {
35       RegInfo &RI = RegInfos[R];
36       if (RI.RegClass != nullptr && !BadRC[R]) {
37         if (RC->LaneMask != RI.RegClass->LaneMask) {
38           BadRC.set(R);
39           RI.RegClass = nullptr;
40         }
41       } else
42         RI.RegClass = RC;
43     }
44   }
45 
46   UnitInfos.resize(TRI.getNumRegUnits());
47 
48   for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
49     if (UnitInfos[U].Reg != 0)
50       continue;
51     MCRegUnitRootIterator R(U, &TRI);
52     assert(R.isValid());
53     RegisterId F = *R;
54     ++R;
55     if (R.isValid()) {
56       UnitInfos[U].Mask = LaneBitmask::getAll();
57       UnitInfos[U].Reg = F;
58     } else {
59       for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
60         std::pair<uint32_t,LaneBitmask> P = *I;
61         UnitInfo &UI = UnitInfos[P.first];
62         UI.Reg = F;
63         if (P.second.any()) {
64           UI.Mask = P.second;
65         } else {
66           if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
67             UI.Mask = RC->LaneMask;
68           else
69             UI.Mask = LaneBitmask::getAll();
70         }
71       }
72     }
73   }
74 
75   for (const uint32_t *RM : TRI.getRegMasks())
76     RegMasks.insert(RM);
77   for (const MachineBasicBlock &B : mf)
78     for (const MachineInstr &In : B)
79       for (const MachineOperand &Op : In.operands())
80         if (Op.isRegMask())
81           RegMasks.insert(Op.getRegMask());
82 
83   MaskInfos.resize(RegMasks.size()+1);
84   for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) {
85     BitVector PU(TRI.getNumRegUnits());
86     const uint32_t *MB = RegMasks.get(M);
87     for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
88       if (!(MB[i/32] & (1u << (i%32))))
89         continue;
90       for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U)
91         PU.set(*U);
92     }
93     MaskInfos[M].Units = PU.flip();
94   }
95 }
96 
97 std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
98   // Do not include RR in the alias set.
99   std::set<RegisterId> AS;
100   assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg));
101   if (isRegMaskId(Reg)) {
102     // XXX SLOW
103     const uint32_t *MB = getRegMaskBits(Reg);
104     for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
105       if (MB[i/32] & (1u << (i%32)))
106         continue;
107       AS.insert(i);
108     }
109     for (const uint32_t *RM : RegMasks) {
110       RegisterId MI = getRegMaskId(RM);
111       if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI)))
112         AS.insert(MI);
113     }
114     return AS;
115   }
116 
117   for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI)
118     AS.insert(*AI);
119   for (const uint32_t *RM : RegMasks) {
120     RegisterId MI = getRegMaskId(RM);
121     if (aliasRM(RegisterRef(Reg), RegisterRef(MI)))
122       AS.insert(MI);
123   }
124   return AS;
125 }
126 
127 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const {
128   assert(Register::isPhysicalRegister(RA.Reg));
129   assert(Register::isPhysicalRegister(RB.Reg));
130 
131   MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
132   MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
133   // Reg units are returned in the numerical order.
134   while (UMA.isValid() && UMB.isValid()) {
135     // Skip units that are masked off in RA.
136     std::pair<RegisterId,LaneBitmask> PA = *UMA;
137     if (PA.second.any() && (PA.second & RA.Mask).none()) {
138       ++UMA;
139       continue;
140     }
141     // Skip units that are masked off in RB.
142     std::pair<RegisterId,LaneBitmask> PB = *UMB;
143     if (PB.second.any() && (PB.second & RB.Mask).none()) {
144       ++UMB;
145       continue;
146     }
147 
148     if (PA.first == PB.first)
149       return true;
150     if (PA.first < PB.first)
151       ++UMA;
152     else if (PB.first < PA.first)
153       ++UMB;
154   }
155   return false;
156 }
157 
158 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const {
159   assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg));
160   const uint32_t *MB = getRegMaskBits(RM.Reg);
161   bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32));
162   // If the lane mask information is "full", e.g. when the given lane mask
163   // is a superset of the lane mask from the register class, check the regmask
164   // bit directly.
165   if (RR.Mask == LaneBitmask::getAll())
166     return !Preserved;
167   const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
168   if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask)
169     return !Preserved;
170 
171   // Otherwise, check all subregisters whose lane mask overlaps the given
172   // mask. For each such register, if it is preserved by the regmask, then
173   // clear the corresponding bits in the given mask. If at the end, all
174   // bits have been cleared, the register does not alias the regmask (i.e.
175   // is it preserved by it).
176   LaneBitmask M = RR.Mask;
177   for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) {
178     LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex());
179     if ((SM & RR.Mask).none())
180       continue;
181     unsigned SR = SI.getSubReg();
182     if (!(MB[SR/32] & (1u << (SR%32))))
183       continue;
184     // The subregister SR is preserved.
185     M &= ~SM;
186     if (M.none())
187       return false;
188   }
189 
190   return true;
191 }
192 
193 bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
194   assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg));
195   unsigned NumRegs = TRI.getNumRegs();
196   const uint32_t *BM = getRegMaskBits(RM.Reg);
197   const uint32_t *BN = getRegMaskBits(RN.Reg);
198 
199   for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) {
200     // Intersect the negations of both words. Disregard reg=0,
201     // i.e. 0th bit in the 0th word.
202     uint32_t C = ~BM[w] & ~BN[w];
203     if (w == 0)
204       C &= ~1;
205     if (C)
206       return true;
207   }
208 
209   // Check the remaining registers in the last word.
210   unsigned TailRegs = NumRegs % 32;
211   if (TailRegs == 0)
212     return false;
213   unsigned TW = NumRegs / 32;
214   uint32_t TailMask = (1u << TailRegs) - 1;
215   if (~BM[TW] & ~BN[TW] & TailMask)
216     return true;
217 
218   return false;
219 }
220 
221 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const {
222   if (RR.Reg == R)
223     return RR;
224   if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg))
225     return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
226   if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) {
227     const RegInfo &RI = RegInfos[R];
228     LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
229                                   : LaneBitmask::getAll();
230     LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask);
231     return RegisterRef(R, M & RCM);
232   }
233   llvm_unreachable("Invalid arguments: unrelated registers?");
234 }
235 
236 bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
237   if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
238     return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
239 
240   for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
241     std::pair<uint32_t,LaneBitmask> P = *U;
242     if (P.second.none() || (P.second & RR.Mask).any())
243       if (Units.test(P.first))
244         return true;
245   }
246   return false;
247 }
248 
249 bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
250   if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
251     BitVector T(PRI.getMaskUnits(RR.Reg));
252     return T.reset(Units).none();
253   }
254 
255   for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
256     std::pair<uint32_t,LaneBitmask> P = *U;
257     if (P.second.none() || (P.second & RR.Mask).any())
258       if (!Units.test(P.first))
259         return false;
260   }
261   return true;
262 }
263 
264 RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
265   if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
266     Units |= PRI.getMaskUnits(RR.Reg);
267     return *this;
268   }
269 
270   for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
271     std::pair<uint32_t,LaneBitmask> P = *U;
272     if (P.second.none() || (P.second & RR.Mask).any())
273       Units.set(P.first);
274   }
275   return *this;
276 }
277 
278 RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) {
279   Units |= RG.Units;
280   return *this;
281 }
282 
283 RegisterAggr &RegisterAggr::intersect(RegisterRef RR) {
284   return intersect(RegisterAggr(PRI).insert(RR));
285 }
286 
287 RegisterAggr &RegisterAggr::intersect(const RegisterAggr &RG) {
288   Units &= RG.Units;
289   return *this;
290 }
291 
292 RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
293   return clear(RegisterAggr(PRI).insert(RR));
294 }
295 
296 RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) {
297   Units.reset(RG.Units);
298   return *this;
299 }
300 
301 RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const {
302   RegisterAggr T(PRI);
303   T.insert(RR).intersect(*this);
304   if (T.empty())
305     return RegisterRef();
306   RegisterRef NR = T.makeRegRef();
307   assert(NR);
308   return NR;
309 }
310 
311 RegisterRef RegisterAggr::clearIn(RegisterRef RR) const {
312   return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();
313 }
314 
315 RegisterRef RegisterAggr::makeRegRef() const {
316   int U = Units.find_first();
317   if (U < 0)
318     return RegisterRef();
319 
320   auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) {
321     for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R)
322       for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S)
323         Regs.set(*S);
324   };
325 
326   // Find the set of all registers that are aliased to all the units
327   // in this aggregate.
328 
329   // Get all the registers aliased to the first unit in the bit vector.
330   BitVector Regs(PRI.getTRI().getNumRegs());
331   AliasedRegs(U, Regs);
332   U = Units.find_next(U);
333 
334   // For each other unit, intersect it with the set of all registers
335   // aliased that unit.
336   while (U >= 0) {
337     BitVector AR(PRI.getTRI().getNumRegs());
338     AliasedRegs(U, AR);
339     Regs &= AR;
340     U = Units.find_next(U);
341   }
342 
343   // If there is at least one register remaining, pick the first one,
344   // and consolidate the masks of all of its units contained in this
345   // aggregate.
346 
347   int F = Regs.find_first();
348   if (F <= 0)
349     return RegisterRef();
350 
351   LaneBitmask M;
352   for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
353     std::pair<uint32_t,LaneBitmask> P = *I;
354     if (Units.test(P.first))
355       M |= P.second.none() ? LaneBitmask::getAll() : P.second;
356   }
357   return RegisterRef(F, M);
358 }
359 
360 void RegisterAggr::print(raw_ostream &OS) const {
361   OS << '{';
362   for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
363     OS << ' ' << printRegUnit(U, &PRI.getTRI());
364   OS << " }";
365 }
366 
367 RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG,
368       bool End)
369     : Owner(&RG) {
370   for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
371     RegisterRef R = RG.PRI.getRefForUnit(U);
372     Masks[R.Reg] |= R.Mask;
373   }
374   Pos = End ? Masks.end() : Masks.begin();
375   Index = End ? Masks.size() : 0;
376 }
377