1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MachineOperand.h"
15 #include "llvm/Analysis/Loads.h"
16 #include "llvm/CodeGen/MIRPrinter.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
20 #include "llvm/CodeGen/TargetRegisterInfo.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/IRPrintingPasses.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Target/TargetIntrinsicInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 
27 using namespace llvm;
28 
29 static cl::opt<int>
30     PrintRegMaskNumRegs("print-regmask-num-regs",
31                         cl::desc("Number of registers to limit to when "
32                                  "printing regmask operands in IR dumps. "
33                                  "unlimited = -1"),
34                         cl::init(32), cl::Hidden);
35 
36 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
37   if (const MachineInstr *MI = MO.getParent())
38     if (const MachineBasicBlock *MBB = MI->getParent())
39       if (const MachineFunction *MF = MBB->getParent())
40         return MF;
41   return nullptr;
42 }
43 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
44   return const_cast<MachineFunction *>(
45       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
46 }
47 
48 void MachineOperand::setReg(unsigned Reg) {
49   if (getReg() == Reg)
50     return; // No change.
51 
52   // Otherwise, we have to change the register.  If this operand is embedded
53   // into a machine function, we need to update the old and new register's
54   // use/def lists.
55   if (MachineFunction *MF = getMFIfAvailable(*this)) {
56     MachineRegisterInfo &MRI = MF->getRegInfo();
57     MRI.removeRegOperandFromUseList(this);
58     SmallContents.RegNo = Reg;
59     MRI.addRegOperandToUseList(this);
60     return;
61   }
62 
63   // Otherwise, just change the register, no problem.  :)
64   SmallContents.RegNo = Reg;
65 }
66 
67 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
68                                   const TargetRegisterInfo &TRI) {
69   assert(TargetRegisterInfo::isVirtualRegister(Reg));
70   if (SubIdx && getSubReg())
71     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
72   setReg(Reg);
73   if (SubIdx)
74     setSubReg(SubIdx);
75 }
76 
77 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
78   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
79   if (getSubReg()) {
80     Reg = TRI.getSubReg(Reg, getSubReg());
81     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
82     // That won't happen in legal code.
83     setSubReg(0);
84     if (isDef())
85       setIsUndef(false);
86   }
87   setReg(Reg);
88 }
89 
90 /// Change a def to a use, or a use to a def.
91 void MachineOperand::setIsDef(bool Val) {
92   assert(isReg() && "Wrong MachineOperand accessor");
93   assert((!Val || !isDebug()) && "Marking a debug operation as def");
94   if (IsDef == Val)
95     return;
96   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
97   // MRI may keep uses and defs in different list positions.
98   if (MachineFunction *MF = getMFIfAvailable(*this)) {
99     MachineRegisterInfo &MRI = MF->getRegInfo();
100     MRI.removeRegOperandFromUseList(this);
101     IsDef = Val;
102     MRI.addRegOperandToUseList(this);
103     return;
104   }
105   IsDef = Val;
106 }
107 
108 bool MachineOperand::isRenamable() const {
109   assert(isReg() && "Wrong MachineOperand accessor");
110   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
111          "isRenamable should only be checked on physical registers");
112   return IsRenamable;
113 }
114 
115 void MachineOperand::setIsRenamable(bool Val) {
116   assert(isReg() && "Wrong MachineOperand accessor");
117   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
118          "setIsRenamable should only be called on physical registers");
119   if (const MachineInstr *MI = getParent())
120     if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
121         (isUse() && MI->hasExtraSrcRegAllocReq()))
122       assert(!Val && "isRenamable should be false for "
123                      "hasExtraDefRegAllocReq/hasExtraSrcRegAllocReq opcodes");
124   IsRenamable = Val;
125 }
126 
127 void MachineOperand::setIsRenamableIfNoExtraRegAllocReq() {
128   if (const MachineInstr *MI = getParent())
129     if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
130         (isUse() && MI->hasExtraSrcRegAllocReq()))
131       return;
132 
133   setIsRenamable(true);
134 }
135 
136 // If this operand is currently a register operand, and if this is in a
137 // function, deregister the operand from the register's use/def list.
138 void MachineOperand::removeRegFromUses() {
139   if (!isReg() || !isOnRegUseList())
140     return;
141 
142   if (MachineFunction *MF = getMFIfAvailable(*this))
143     MF->getRegInfo().removeRegOperandFromUseList(this);
144 }
145 
146 /// ChangeToImmediate - Replace this operand with a new immediate operand of
147 /// the specified value.  If an operand is known to be an immediate already,
148 /// the setImm method should be used.
149 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
150   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
151 
152   removeRegFromUses();
153 
154   OpKind = MO_Immediate;
155   Contents.ImmVal = ImmVal;
156 }
157 
158 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
159   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
160 
161   removeRegFromUses();
162 
163   OpKind = MO_FPImmediate;
164   Contents.CFP = FPImm;
165 }
166 
167 void MachineOperand::ChangeToES(const char *SymName,
168                                 unsigned char TargetFlags) {
169   assert((!isReg() || !isTied()) &&
170          "Cannot change a tied operand into an external symbol");
171 
172   removeRegFromUses();
173 
174   OpKind = MO_ExternalSymbol;
175   Contents.OffsetedInfo.Val.SymbolName = SymName;
176   setOffset(0); // Offset is always 0.
177   setTargetFlags(TargetFlags);
178 }
179 
180 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
181   assert((!isReg() || !isTied()) &&
182          "Cannot change a tied operand into an MCSymbol");
183 
184   removeRegFromUses();
185 
186   OpKind = MO_MCSymbol;
187   Contents.Sym = Sym;
188 }
189 
190 void MachineOperand::ChangeToFrameIndex(int Idx) {
191   assert((!isReg() || !isTied()) &&
192          "Cannot change a tied operand into a FrameIndex");
193 
194   removeRegFromUses();
195 
196   OpKind = MO_FrameIndex;
197   setIndex(Idx);
198 }
199 
200 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
201                                          unsigned char TargetFlags) {
202   assert((!isReg() || !isTied()) &&
203          "Cannot change a tied operand into a FrameIndex");
204 
205   removeRegFromUses();
206 
207   OpKind = MO_TargetIndex;
208   setIndex(Idx);
209   setOffset(Offset);
210   setTargetFlags(TargetFlags);
211 }
212 
213 /// ChangeToRegister - Replace this operand with a new register operand of
214 /// the specified value.  If an operand is known to be an register already,
215 /// the setReg method should be used.
216 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
217                                       bool isKill, bool isDead, bool isUndef,
218                                       bool isDebug) {
219   MachineRegisterInfo *RegInfo = nullptr;
220   if (MachineFunction *MF = getMFIfAvailable(*this))
221     RegInfo = &MF->getRegInfo();
222   // If this operand is already a register operand, remove it from the
223   // register's use/def lists.
224   bool WasReg = isReg();
225   if (RegInfo && WasReg)
226     RegInfo->removeRegOperandFromUseList(this);
227 
228   // Change this to a register and set the reg#.
229   assert(!(isDead && !isDef) && "Dead flag on non-def");
230   assert(!(isKill && isDef) && "Kill flag on def");
231   OpKind = MO_Register;
232   SmallContents.RegNo = Reg;
233   SubReg_TargetFlags = 0;
234   IsDef = isDef;
235   IsImp = isImp;
236   IsDeadOrKill = isKill | isDead;
237   IsRenamable = false;
238   IsUndef = isUndef;
239   IsInternalRead = false;
240   IsEarlyClobber = false;
241   IsDebug = isDebug;
242   // Ensure isOnRegUseList() returns false.
243   Contents.Reg.Prev = nullptr;
244   // Preserve the tie when the operand was already a register.
245   if (!WasReg)
246     TiedTo = 0;
247 
248   // If this operand is embedded in a function, add the operand to the
249   // register's use/def list.
250   if (RegInfo)
251     RegInfo->addRegOperandToUseList(this);
252 }
253 
254 /// isIdenticalTo - Return true if this operand is identical to the specified
255 /// operand. Note that this should stay in sync with the hash_value overload
256 /// below.
257 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
258   if (getType() != Other.getType() ||
259       getTargetFlags() != Other.getTargetFlags())
260     return false;
261 
262   switch (getType()) {
263   case MachineOperand::MO_Register:
264     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
265            getSubReg() == Other.getSubReg();
266   case MachineOperand::MO_Immediate:
267     return getImm() == Other.getImm();
268   case MachineOperand::MO_CImmediate:
269     return getCImm() == Other.getCImm();
270   case MachineOperand::MO_FPImmediate:
271     return getFPImm() == Other.getFPImm();
272   case MachineOperand::MO_MachineBasicBlock:
273     return getMBB() == Other.getMBB();
274   case MachineOperand::MO_FrameIndex:
275     return getIndex() == Other.getIndex();
276   case MachineOperand::MO_ConstantPoolIndex:
277   case MachineOperand::MO_TargetIndex:
278     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
279   case MachineOperand::MO_JumpTableIndex:
280     return getIndex() == Other.getIndex();
281   case MachineOperand::MO_GlobalAddress:
282     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
283   case MachineOperand::MO_ExternalSymbol:
284     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
285            getOffset() == Other.getOffset();
286   case MachineOperand::MO_BlockAddress:
287     return getBlockAddress() == Other.getBlockAddress() &&
288            getOffset() == Other.getOffset();
289   case MachineOperand::MO_RegisterMask:
290   case MachineOperand::MO_RegisterLiveOut: {
291     // Shallow compare of the two RegMasks
292     const uint32_t *RegMask = getRegMask();
293     const uint32_t *OtherRegMask = Other.getRegMask();
294     if (RegMask == OtherRegMask)
295       return true;
296 
297     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
298       // Calculate the size of the RegMask
299       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
300       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
301 
302       // Deep compare of the two RegMasks
303       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
304     }
305     // We don't know the size of the RegMask, so we can't deep compare the two
306     // reg masks.
307     return false;
308   }
309   case MachineOperand::MO_MCSymbol:
310     return getMCSymbol() == Other.getMCSymbol();
311   case MachineOperand::MO_CFIIndex:
312     return getCFIIndex() == Other.getCFIIndex();
313   case MachineOperand::MO_Metadata:
314     return getMetadata() == Other.getMetadata();
315   case MachineOperand::MO_IntrinsicID:
316     return getIntrinsicID() == Other.getIntrinsicID();
317   case MachineOperand::MO_Predicate:
318     return getPredicate() == Other.getPredicate();
319   }
320   llvm_unreachable("Invalid machine operand type");
321 }
322 
323 // Note: this must stay exactly in sync with isIdenticalTo above.
324 hash_code llvm::hash_value(const MachineOperand &MO) {
325   switch (MO.getType()) {
326   case MachineOperand::MO_Register:
327     // Register operands don't have target flags.
328     return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
329   case MachineOperand::MO_Immediate:
330     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
331   case MachineOperand::MO_CImmediate:
332     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
333   case MachineOperand::MO_FPImmediate:
334     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
335   case MachineOperand::MO_MachineBasicBlock:
336     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
337   case MachineOperand::MO_FrameIndex:
338     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
339   case MachineOperand::MO_ConstantPoolIndex:
340   case MachineOperand::MO_TargetIndex:
341     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
342                         MO.getOffset());
343   case MachineOperand::MO_JumpTableIndex:
344     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
345   case MachineOperand::MO_ExternalSymbol:
346     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
347                         MO.getSymbolName());
348   case MachineOperand::MO_GlobalAddress:
349     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
350                         MO.getOffset());
351   case MachineOperand::MO_BlockAddress:
352     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
353                         MO.getOffset());
354   case MachineOperand::MO_RegisterMask:
355   case MachineOperand::MO_RegisterLiveOut:
356     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
357   case MachineOperand::MO_Metadata:
358     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
359   case MachineOperand::MO_MCSymbol:
360     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
361   case MachineOperand::MO_CFIIndex:
362     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
363   case MachineOperand::MO_IntrinsicID:
364     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
365   case MachineOperand::MO_Predicate:
366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
367   }
368   llvm_unreachable("Invalid machine operand type");
369 }
370 
371 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
372 // it.
373 static void tryToGetTargetInfo(const MachineOperand &MO,
374                                const TargetRegisterInfo *&TRI,
375                                const TargetIntrinsicInfo *&IntrinsicInfo) {
376   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
377     TRI = MF->getSubtarget().getRegisterInfo();
378     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
379   }
380 }
381 
382 static void printOffset(raw_ostream &OS, int64_t Offset) {
383   if (Offset == 0)
384     return;
385   if (Offset < 0) {
386     OS << " - " << -Offset;
387     return;
388   }
389   OS << " + " << Offset;
390 }
391 
392 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
393   const auto *TII = MF.getSubtarget().getInstrInfo();
394   assert(TII && "expected instruction info");
395   auto Indices = TII->getSerializableTargetIndices();
396   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
397     return I.first == Index;
398   });
399   if (Found != Indices.end())
400     return Found->second;
401   return nullptr;
402 }
403 
404 void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
405                                     const TargetRegisterInfo *TRI) {
406   OS << "%subreg.";
407   if (TRI)
408     OS << TRI->getSubRegIndexName(Index);
409   else
410     OS << Index;
411 }
412 
413 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
414                            const TargetIntrinsicInfo *IntrinsicInfo) const {
415   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
416   ModuleSlotTracker DummyMST(nullptr);
417   print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
418         /*ShouldPrintRegisterTies=*/true,
419         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
420 }
421 
422 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
423                            LLT TypeToPrint, bool PrintDef,
424                            bool ShouldPrintRegisterTies,
425                            unsigned TiedOperandIdx,
426                            const TargetRegisterInfo *TRI,
427                            const TargetIntrinsicInfo *IntrinsicInfo) const {
428   switch (getType()) {
429   case MachineOperand::MO_Register: {
430     unsigned Reg = getReg();
431     if (isImplicit())
432       OS << (isDef() ? "implicit-def " : "implicit ");
433     else if (PrintDef && isDef())
434       // Print the 'def' flag only when the operand is defined after '='.
435       OS << "def ";
436     if (isInternalRead())
437       OS << "internal ";
438     if (isDead())
439       OS << "dead ";
440     if (isKill())
441       OS << "killed ";
442     if (isUndef())
443       OS << "undef ";
444     if (isEarlyClobber())
445       OS << "early-clobber ";
446     if (isDebug())
447       OS << "debug-use ";
448     if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
449       OS << "renamable ";
450     OS << printReg(Reg, TRI);
451     // Print the sub register.
452     if (unsigned SubReg = getSubReg()) {
453       if (TRI)
454         OS << '.' << TRI->getSubRegIndexName(SubReg);
455       else
456         OS << ".subreg" << SubReg;
457     }
458     // Print the register class / bank.
459     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
460       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
461         const MachineRegisterInfo &MRI = MF->getRegInfo();
462         if (!PrintDef || MRI.def_empty(Reg)) {
463           OS << ':';
464           OS << printRegClassOrBank(Reg, MRI, TRI);
465         }
466       }
467     }
468     // Print ties.
469     if (ShouldPrintRegisterTies && isTied() && !isDef())
470       OS << "(tied-def " << TiedOperandIdx << ")";
471     // Print types.
472     if (TypeToPrint.isValid())
473       OS << '(' << TypeToPrint << ')';
474     break;
475   }
476   case MachineOperand::MO_Immediate:
477     OS << getImm();
478     break;
479   case MachineOperand::MO_CImmediate:
480     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
481     break;
482   case MachineOperand::MO_FPImmediate:
483     if (getFPImm()->getType()->isFloatTy()) {
484       OS << getFPImm()->getValueAPF().convertToFloat();
485     } else if (getFPImm()->getType()->isHalfTy()) {
486       APFloat APF = getFPImm()->getValueAPF();
487       bool Unused;
488       APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
489       OS << "half " << APF.convertToFloat();
490     } else if (getFPImm()->getType()->isFP128Ty()) {
491       APFloat APF = getFPImm()->getValueAPF();
492       SmallString<16> Str;
493       getFPImm()->getValueAPF().toString(Str);
494       OS << "quad " << Str;
495     } else if (getFPImm()->getType()->isX86_FP80Ty()) {
496       APFloat APF = getFPImm()->getValueAPF();
497       OS << "x86_fp80 0xK";
498       APInt API = APF.bitcastToAPInt();
499       OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
500                                  /*Upper=*/true);
501       OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
502                                  /*Upper=*/true);
503     } else {
504       OS << getFPImm()->getValueAPF().convertToDouble();
505     }
506     break;
507   case MachineOperand::MO_MachineBasicBlock:
508     OS << printMBBReference(*getMBB());
509     break;
510   case MachineOperand::MO_FrameIndex:
511     OS << "<fi#" << getIndex() << '>';
512     break;
513   case MachineOperand::MO_ConstantPoolIndex:
514     OS << "%const." << getIndex();
515     printOffset(OS, getOffset());
516     break;
517   case MachineOperand::MO_TargetIndex: {
518     OS << "target-index(";
519     const char *Name = "<unknown>";
520     if (const MachineFunction *MF = getMFIfAvailable(*this))
521       if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
522         Name = TargetIndexName;
523     OS << Name << ')';
524     printOffset(OS, getOffset());
525     break;
526   }
527   case MachineOperand::MO_JumpTableIndex:
528     OS << printJumpTableEntryReference(getIndex());
529     break;
530   case MachineOperand::MO_GlobalAddress:
531     OS << "<ga:";
532     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
533     if (getOffset())
534       OS << "+" << getOffset();
535     OS << '>';
536     break;
537   case MachineOperand::MO_ExternalSymbol: {
538     StringRef Name = getSymbolName();
539     OS << '$';
540     if (Name.empty()) {
541       OS << "\"\"";
542     } else {
543       printLLVMNameWithoutPrefix(OS, Name);
544     }
545     printOffset(OS, getOffset());
546     break;
547   }
548   case MachineOperand::MO_BlockAddress:
549     OS << '<';
550     getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
551     if (getOffset())
552       OS << "+" << getOffset();
553     OS << '>';
554     break;
555   case MachineOperand::MO_RegisterMask: {
556     OS << "<regmask";
557     if (TRI) {
558       unsigned NumRegsInMask = 0;
559       unsigned NumRegsEmitted = 0;
560       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
561         unsigned MaskWord = i / 32;
562         unsigned MaskBit = i % 32;
563         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
564           if (PrintRegMaskNumRegs < 0 ||
565               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
566             OS << " " << printReg(i, TRI);
567             NumRegsEmitted++;
568           }
569           NumRegsInMask++;
570         }
571       }
572       if (NumRegsEmitted != NumRegsInMask)
573         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
574     } else {
575       OS << " ...";
576     }
577     OS << ">";
578     break;
579   }
580   case MachineOperand::MO_RegisterLiveOut:
581     OS << "<regliveout>";
582     break;
583   case MachineOperand::MO_Metadata:
584     OS << '<';
585     getMetadata()->printAsOperand(OS, MST);
586     OS << '>';
587     break;
588   case MachineOperand::MO_MCSymbol:
589     OS << "<MCSym=" << *getMCSymbol() << '>';
590     break;
591   case MachineOperand::MO_CFIIndex:
592     OS << "<call frame instruction>";
593     break;
594   case MachineOperand::MO_IntrinsicID: {
595     Intrinsic::ID ID = getIntrinsicID();
596     if (ID < Intrinsic::num_intrinsics)
597       OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
598     else if (IntrinsicInfo)
599       OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
600     else
601       OS << "<intrinsic:" << ID << '>';
602     break;
603   }
604   case MachineOperand::MO_Predicate: {
605     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
606     OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
607        << CmpInst::getPredicateName(Pred) << '>';
608     break;
609   }
610   }
611   if (unsigned TF = getTargetFlags())
612     OS << "[TF=" << TF << ']';
613 }
614 
615 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
616 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
617 #endif
618 
619 //===----------------------------------------------------------------------===//
620 // MachineMemOperand Implementation
621 //===----------------------------------------------------------------------===//
622 
623 /// getAddrSpace - Return the LLVM IR address space number that this pointer
624 /// points into.
625 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
626 
627 /// isDereferenceable - Return true if V is always dereferenceable for
628 /// Offset + Size byte.
629 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
630                                            const DataLayout &DL) const {
631   if (!V.is<const Value *>())
632     return false;
633 
634   const Value *BasePtr = V.get<const Value *>();
635   if (BasePtr == nullptr)
636     return false;
637 
638   return isDereferenceableAndAlignedPointer(
639       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
640 }
641 
642 /// getConstantPool - Return a MachinePointerInfo record that refers to the
643 /// constant pool.
644 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
645   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
646 }
647 
648 /// getFixedStack - Return a MachinePointerInfo record that refers to the
649 /// the specified FrameIndex.
650 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
651                                                      int FI, int64_t Offset) {
652   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
653 }
654 
655 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
656   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
657 }
658 
659 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
660   return MachinePointerInfo(MF.getPSVManager().getGOT());
661 }
662 
663 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
664                                                 int64_t Offset, uint8_t ID) {
665   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
666 }
667 
668 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
669   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
670 }
671 
672 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
673                                      uint64_t s, unsigned int a,
674                                      const AAMDNodes &AAInfo,
675                                      const MDNode *Ranges, SyncScope::ID SSID,
676                                      AtomicOrdering Ordering,
677                                      AtomicOrdering FailureOrdering)
678     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
679       AAInfo(AAInfo), Ranges(Ranges) {
680   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
681           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
682          "invalid pointer value");
683   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
684   assert((isLoad() || isStore()) && "Not a load/store!");
685 
686   AtomicInfo.SSID = static_cast<unsigned>(SSID);
687   assert(getSyncScopeID() == SSID && "Value truncated");
688   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
689   assert(getOrdering() == Ordering && "Value truncated");
690   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
691   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
692 }
693 
694 /// Profile - Gather unique data for the object.
695 ///
696 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
697   ID.AddInteger(getOffset());
698   ID.AddInteger(Size);
699   ID.AddPointer(getOpaqueValue());
700   ID.AddInteger(getFlags());
701   ID.AddInteger(getBaseAlignment());
702 }
703 
704 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
705   // The Value and Offset may differ due to CSE. But the flags and size
706   // should be the same.
707   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
708   assert(MMO->getSize() == getSize() && "Size mismatch!");
709 
710   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
711     // Update the alignment value.
712     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
713     // Also update the base and offset, because the new alignment may
714     // not be applicable with the old ones.
715     PtrInfo = MMO->PtrInfo;
716   }
717 }
718 
719 /// getAlignment - Return the minimum known alignment in bytes of the
720 /// actual memory reference.
721 uint64_t MachineMemOperand::getAlignment() const {
722   return MinAlign(getBaseAlignment(), getOffset());
723 }
724 
725 void MachineMemOperand::print(raw_ostream &OS) const {
726   ModuleSlotTracker DummyMST(nullptr);
727   print(OS, DummyMST);
728 }
729 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
730   assert((isLoad() || isStore()) && "SV has to be a load, store or both.");
731 
732   if (isVolatile())
733     OS << "Volatile ";
734 
735   if (isLoad())
736     OS << "LD";
737   if (isStore())
738     OS << "ST";
739   OS << getSize();
740 
741   // Print the address information.
742   OS << "[";
743   if (const Value *V = getValue())
744     V->printAsOperand(OS, /*PrintType=*/false, MST);
745   else if (const PseudoSourceValue *PSV = getPseudoValue())
746     PSV->printCustom(OS);
747   else
748     OS << "<unknown>";
749 
750   unsigned AS = getAddrSpace();
751   if (AS != 0)
752     OS << "(addrspace=" << AS << ')';
753 
754   // If the alignment of the memory reference itself differs from the alignment
755   // of the base pointer, print the base alignment explicitly, next to the base
756   // pointer.
757   if (getBaseAlignment() != getAlignment())
758     OS << "(align=" << getBaseAlignment() << ")";
759 
760   if (getOffset() != 0)
761     OS << "+" << getOffset();
762   OS << "]";
763 
764   // Print the alignment of the reference.
765   if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
766     OS << "(align=" << getAlignment() << ")";
767 
768   // Print TBAA info.
769   if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
770     OS << "(tbaa=";
771     if (TBAAInfo->getNumOperands() > 0)
772       TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
773     else
774       OS << "<unknown>";
775     OS << ")";
776   }
777 
778   // Print AA scope info.
779   if (const MDNode *ScopeInfo = getAAInfo().Scope) {
780     OS << "(alias.scope=";
781     if (ScopeInfo->getNumOperands() > 0)
782       for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
783         ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
784         if (i != ie - 1)
785           OS << ",";
786       }
787     else
788       OS << "<unknown>";
789     OS << ")";
790   }
791 
792   // Print AA noalias scope info.
793   if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
794     OS << "(noalias=";
795     if (NoAliasInfo->getNumOperands() > 0)
796       for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
797         NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
798         if (i != ie - 1)
799           OS << ",";
800       }
801     else
802       OS << "<unknown>";
803     OS << ")";
804   }
805 
806   if (const MDNode *Ranges = getRanges()) {
807     unsigned NumRanges = Ranges->getNumOperands();
808     if (NumRanges != 0) {
809       OS << "(ranges=";
810 
811       for (unsigned I = 0; I != NumRanges; ++I) {
812         Ranges->getOperand(I)->printAsOperand(OS, MST);
813         if (I != NumRanges - 1)
814           OS << ',';
815       }
816 
817       OS << ')';
818     }
819   }
820 
821   if (isNonTemporal())
822     OS << "(nontemporal)";
823   if (isDereferenceable())
824     OS << "(dereferenceable)";
825   if (isInvariant())
826     OS << "(invariant)";
827   if (getFlags() & MOTargetFlag1)
828     OS << "(flag1)";
829   if (getFlags() & MOTargetFlag2)
830     OS << "(flag2)";
831   if (getFlags() & MOTargetFlag3)
832     OS << "(flag3)";
833 }
834