1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MachineOperand.h"
15 #include "llvm/Analysis/Loads.h"
16 #include "llvm/CodeGen/MIRPrinter.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetRegisterInfo.h"
19 #include "llvm/IR/Constants.h"
20 #include "llvm/IR/ModuleSlotTracker.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 
24 using namespace llvm;
25 
26 static cl::opt<int>
27     PrintRegMaskNumRegs("print-regmask-num-regs",
28                         cl::desc("Number of registers to limit to when "
29                                  "printing regmask operands in IR dumps. "
30                                  "unlimited = -1"),
31                         cl::init(32), cl::Hidden);
32 
33 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
34   if (const MachineInstr *MI = MO.getParent())
35     if (const MachineBasicBlock *MBB = MI->getParent())
36       if (const MachineFunction *MF = MBB->getParent())
37         return MF;
38   return nullptr;
39 }
40 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
41   return const_cast<MachineFunction *>(
42       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
43 }
44 
45 void MachineOperand::setReg(unsigned Reg) {
46   if (getReg() == Reg)
47     return; // No change.
48 
49   // Otherwise, we have to change the register.  If this operand is embedded
50   // into a machine function, we need to update the old and new register's
51   // use/def lists.
52   if (MachineFunction *MF = getMFIfAvailable(*this)) {
53     MachineRegisterInfo &MRI = MF->getRegInfo();
54     MRI.removeRegOperandFromUseList(this);
55     SmallContents.RegNo = Reg;
56     MRI.addRegOperandToUseList(this);
57     return;
58   }
59 
60   // Otherwise, just change the register, no problem.  :)
61   SmallContents.RegNo = Reg;
62 }
63 
64 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
65                                   const TargetRegisterInfo &TRI) {
66   assert(TargetRegisterInfo::isVirtualRegister(Reg));
67   if (SubIdx && getSubReg())
68     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
69   setReg(Reg);
70   if (SubIdx)
71     setSubReg(SubIdx);
72 }
73 
74 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
75   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
76   if (getSubReg()) {
77     Reg = TRI.getSubReg(Reg, getSubReg());
78     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
79     // That won't happen in legal code.
80     setSubReg(0);
81     if (isDef())
82       setIsUndef(false);
83   }
84   setReg(Reg);
85 }
86 
87 /// Change a def to a use, or a use to a def.
88 void MachineOperand::setIsDef(bool Val) {
89   assert(isReg() && "Wrong MachineOperand accessor");
90   assert((!Val || !isDebug()) && "Marking a debug operation as def");
91   if (IsDef == Val)
92     return;
93   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
94   // MRI may keep uses and defs in different list positions.
95   if (MachineFunction *MF = getMFIfAvailable(*this)) {
96     MachineRegisterInfo &MRI = MF->getRegInfo();
97     MRI.removeRegOperandFromUseList(this);
98     IsDef = Val;
99     MRI.addRegOperandToUseList(this);
100     return;
101   }
102   IsDef = Val;
103 }
104 
105 bool MachineOperand::isRenamable() const {
106   assert(isReg() && "Wrong MachineOperand accessor");
107   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
108          "isRenamable should only be checked on physical registers");
109   return IsRenamable;
110 }
111 
112 void MachineOperand::setIsRenamable(bool Val) {
113   assert(isReg() && "Wrong MachineOperand accessor");
114   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
115          "setIsRenamable should only be called on physical registers");
116   if (const MachineInstr *MI = getParent())
117     if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
118         (isUse() && MI->hasExtraSrcRegAllocReq()))
119       assert(!Val && "isRenamable should be false for "
120                      "hasExtraDefRegAllocReq/hasExtraSrcRegAllocReq opcodes");
121   IsRenamable = Val;
122 }
123 
124 void MachineOperand::setIsRenamableIfNoExtraRegAllocReq() {
125   if (const MachineInstr *MI = getParent())
126     if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
127         (isUse() && MI->hasExtraSrcRegAllocReq()))
128       return;
129 
130   setIsRenamable(true);
131 }
132 
133 // If this operand is currently a register operand, and if this is in a
134 // function, deregister the operand from the register's use/def list.
135 void MachineOperand::removeRegFromUses() {
136   if (!isReg() || !isOnRegUseList())
137     return;
138 
139   if (MachineFunction *MF = getMFIfAvailable(*this))
140     MF->getRegInfo().removeRegOperandFromUseList(this);
141 }
142 
143 /// ChangeToImmediate - Replace this operand with a new immediate operand of
144 /// the specified value.  If an operand is known to be an immediate already,
145 /// the setImm method should be used.
146 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
147   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
148 
149   removeRegFromUses();
150 
151   OpKind = MO_Immediate;
152   Contents.ImmVal = ImmVal;
153 }
154 
155 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
156   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
157 
158   removeRegFromUses();
159 
160   OpKind = MO_FPImmediate;
161   Contents.CFP = FPImm;
162 }
163 
164 void MachineOperand::ChangeToES(const char *SymName,
165                                 unsigned char TargetFlags) {
166   assert((!isReg() || !isTied()) &&
167          "Cannot change a tied operand into an external symbol");
168 
169   removeRegFromUses();
170 
171   OpKind = MO_ExternalSymbol;
172   Contents.OffsetedInfo.Val.SymbolName = SymName;
173   setOffset(0); // Offset is always 0.
174   setTargetFlags(TargetFlags);
175 }
176 
177 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
178   assert((!isReg() || !isTied()) &&
179          "Cannot change a tied operand into an MCSymbol");
180 
181   removeRegFromUses();
182 
183   OpKind = MO_MCSymbol;
184   Contents.Sym = Sym;
185 }
186 
187 void MachineOperand::ChangeToFrameIndex(int Idx) {
188   assert((!isReg() || !isTied()) &&
189          "Cannot change a tied operand into a FrameIndex");
190 
191   removeRegFromUses();
192 
193   OpKind = MO_FrameIndex;
194   setIndex(Idx);
195 }
196 
197 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
198                                          unsigned char TargetFlags) {
199   assert((!isReg() || !isTied()) &&
200          "Cannot change a tied operand into a FrameIndex");
201 
202   removeRegFromUses();
203 
204   OpKind = MO_TargetIndex;
205   setIndex(Idx);
206   setOffset(Offset);
207   setTargetFlags(TargetFlags);
208 }
209 
210 /// ChangeToRegister - Replace this operand with a new register operand of
211 /// the specified value.  If an operand is known to be an register already,
212 /// the setReg method should be used.
213 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
214                                       bool isKill, bool isDead, bool isUndef,
215                                       bool isDebug) {
216   MachineRegisterInfo *RegInfo = nullptr;
217   if (MachineFunction *MF = getMFIfAvailable(*this))
218     RegInfo = &MF->getRegInfo();
219   // If this operand is already a register operand, remove it from the
220   // register's use/def lists.
221   bool WasReg = isReg();
222   if (RegInfo && WasReg)
223     RegInfo->removeRegOperandFromUseList(this);
224 
225   // Change this to a register and set the reg#.
226   assert(!(isDead && !isDef) && "Dead flag on non-def");
227   assert(!(isKill && isDef) && "Kill flag on def");
228   OpKind = MO_Register;
229   SmallContents.RegNo = Reg;
230   SubReg_TargetFlags = 0;
231   IsDef = isDef;
232   IsImp = isImp;
233   IsDeadOrKill = isKill | isDead;
234   IsRenamable = false;
235   IsUndef = isUndef;
236   IsInternalRead = false;
237   IsEarlyClobber = false;
238   IsDebug = isDebug;
239   // Ensure isOnRegUseList() returns false.
240   Contents.Reg.Prev = nullptr;
241   // Preserve the tie when the operand was already a register.
242   if (!WasReg)
243     TiedTo = 0;
244 
245   // If this operand is embedded in a function, add the operand to the
246   // register's use/def list.
247   if (RegInfo)
248     RegInfo->addRegOperandToUseList(this);
249 }
250 
251 /// isIdenticalTo - Return true if this operand is identical to the specified
252 /// operand. Note that this should stay in sync with the hash_value overload
253 /// below.
254 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
255   if (getType() != Other.getType() ||
256       getTargetFlags() != Other.getTargetFlags())
257     return false;
258 
259   switch (getType()) {
260   case MachineOperand::MO_Register:
261     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
262            getSubReg() == Other.getSubReg();
263   case MachineOperand::MO_Immediate:
264     return getImm() == Other.getImm();
265   case MachineOperand::MO_CImmediate:
266     return getCImm() == Other.getCImm();
267   case MachineOperand::MO_FPImmediate:
268     return getFPImm() == Other.getFPImm();
269   case MachineOperand::MO_MachineBasicBlock:
270     return getMBB() == Other.getMBB();
271   case MachineOperand::MO_FrameIndex:
272     return getIndex() == Other.getIndex();
273   case MachineOperand::MO_ConstantPoolIndex:
274   case MachineOperand::MO_TargetIndex:
275     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
276   case MachineOperand::MO_JumpTableIndex:
277     return getIndex() == Other.getIndex();
278   case MachineOperand::MO_GlobalAddress:
279     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
280   case MachineOperand::MO_ExternalSymbol:
281     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
282            getOffset() == Other.getOffset();
283   case MachineOperand::MO_BlockAddress:
284     return getBlockAddress() == Other.getBlockAddress() &&
285            getOffset() == Other.getOffset();
286   case MachineOperand::MO_RegisterMask:
287   case MachineOperand::MO_RegisterLiveOut: {
288     // Shallow compare of the two RegMasks
289     const uint32_t *RegMask = getRegMask();
290     const uint32_t *OtherRegMask = Other.getRegMask();
291     if (RegMask == OtherRegMask)
292       return true;
293 
294     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
295       // Calculate the size of the RegMask
296       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
297       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
298 
299       // Deep compare of the two RegMasks
300       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
301     }
302     // We don't know the size of the RegMask, so we can't deep compare the two
303     // reg masks.
304     return false;
305   }
306   case MachineOperand::MO_MCSymbol:
307     return getMCSymbol() == Other.getMCSymbol();
308   case MachineOperand::MO_CFIIndex:
309     return getCFIIndex() == Other.getCFIIndex();
310   case MachineOperand::MO_Metadata:
311     return getMetadata() == Other.getMetadata();
312   case MachineOperand::MO_IntrinsicID:
313     return getIntrinsicID() == Other.getIntrinsicID();
314   case MachineOperand::MO_Predicate:
315     return getPredicate() == Other.getPredicate();
316   }
317   llvm_unreachable("Invalid machine operand type");
318 }
319 
320 // Note: this must stay exactly in sync with isIdenticalTo above.
321 hash_code llvm::hash_value(const MachineOperand &MO) {
322   switch (MO.getType()) {
323   case MachineOperand::MO_Register:
324     // Register operands don't have target flags.
325     return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
326   case MachineOperand::MO_Immediate:
327     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
328   case MachineOperand::MO_CImmediate:
329     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
330   case MachineOperand::MO_FPImmediate:
331     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
332   case MachineOperand::MO_MachineBasicBlock:
333     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
334   case MachineOperand::MO_FrameIndex:
335     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
336   case MachineOperand::MO_ConstantPoolIndex:
337   case MachineOperand::MO_TargetIndex:
338     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
339                         MO.getOffset());
340   case MachineOperand::MO_JumpTableIndex:
341     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
342   case MachineOperand::MO_ExternalSymbol:
343     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
344                         MO.getSymbolName());
345   case MachineOperand::MO_GlobalAddress:
346     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
347                         MO.getOffset());
348   case MachineOperand::MO_BlockAddress:
349     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
350                         MO.getOffset());
351   case MachineOperand::MO_RegisterMask:
352   case MachineOperand::MO_RegisterLiveOut:
353     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
354   case MachineOperand::MO_Metadata:
355     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
356   case MachineOperand::MO_MCSymbol:
357     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
358   case MachineOperand::MO_CFIIndex:
359     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
360   case MachineOperand::MO_IntrinsicID:
361     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
362   case MachineOperand::MO_Predicate:
363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
364   }
365   llvm_unreachable("Invalid machine operand type");
366 }
367 
368 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
369 // it.
370 static void tryToGetTargetInfo(const MachineOperand &MO,
371                                const TargetRegisterInfo *&TRI,
372                                const TargetIntrinsicInfo *&IntrinsicInfo) {
373   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
374     TRI = MF->getSubtarget().getRegisterInfo();
375     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
376   }
377 }
378 
379 void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
380                                     const TargetRegisterInfo *TRI) {
381   OS << "%subreg.";
382   if (TRI)
383     OS << TRI->getSubRegIndexName(Index);
384   else
385     OS << Index;
386 }
387 
388 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
389                            const TargetIntrinsicInfo *IntrinsicInfo) const {
390   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
391   ModuleSlotTracker DummyMST(nullptr);
392   print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
393         /*ShouldPrintRegisterTies=*/true,
394         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
395 }
396 
397 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
398                            LLT TypeToPrint, bool PrintDef,
399                            bool ShouldPrintRegisterTies,
400                            unsigned TiedOperandIdx,
401                            const TargetRegisterInfo *TRI,
402                            const TargetIntrinsicInfo *IntrinsicInfo) const {
403   switch (getType()) {
404   case MachineOperand::MO_Register: {
405     unsigned Reg = getReg();
406     if (isImplicit())
407       OS << (isDef() ? "implicit-def " : "implicit ");
408     else if (PrintDef && isDef())
409       // Print the 'def' flag only when the operand is defined after '='.
410       OS << "def ";
411     if (isInternalRead())
412       OS << "internal ";
413     if (isDead())
414       OS << "dead ";
415     if (isKill())
416       OS << "killed ";
417     if (isUndef())
418       OS << "undef ";
419     if (isEarlyClobber())
420       OS << "early-clobber ";
421     if (isDebug())
422       OS << "debug-use ";
423     if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
424       OS << "renamable ";
425     OS << printReg(Reg, TRI);
426     // Print the sub register.
427     if (unsigned SubReg = getSubReg()) {
428       if (TRI)
429         OS << '.' << TRI->getSubRegIndexName(SubReg);
430       else
431         OS << ".subreg" << SubReg;
432     }
433     // Print the register class / bank.
434     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
435       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
436         const MachineRegisterInfo &MRI = MF->getRegInfo();
437         if (!PrintDef || MRI.def_empty(Reg)) {
438           OS << ':';
439           OS << printRegClassOrBank(Reg, MRI, TRI);
440         }
441       }
442     }
443     // Print ties.
444     if (ShouldPrintRegisterTies && isTied() && !isDef())
445       OS << "(tied-def " << TiedOperandIdx << ")";
446     // Print types.
447     if (TypeToPrint.isValid())
448       OS << '(' << TypeToPrint << ')';
449     break;
450   }
451   case MachineOperand::MO_Immediate:
452     OS << getImm();
453     break;
454   case MachineOperand::MO_CImmediate:
455     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
456     break;
457   case MachineOperand::MO_FPImmediate:
458     if (getFPImm()->getType()->isFloatTy()) {
459       OS << getFPImm()->getValueAPF().convertToFloat();
460     } else if (getFPImm()->getType()->isHalfTy()) {
461       APFloat APF = getFPImm()->getValueAPF();
462       bool Unused;
463       APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
464       OS << "half " << APF.convertToFloat();
465     } else if (getFPImm()->getType()->isFP128Ty()) {
466       APFloat APF = getFPImm()->getValueAPF();
467       SmallString<16> Str;
468       getFPImm()->getValueAPF().toString(Str);
469       OS << "quad " << Str;
470     } else if (getFPImm()->getType()->isX86_FP80Ty()) {
471       APFloat APF = getFPImm()->getValueAPF();
472       OS << "x86_fp80 0xK";
473       APInt API = APF.bitcastToAPInt();
474       OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
475                                  /*Upper=*/true);
476       OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
477                                  /*Upper=*/true);
478     } else {
479       OS << getFPImm()->getValueAPF().convertToDouble();
480     }
481     break;
482   case MachineOperand::MO_MachineBasicBlock:
483     OS << printMBBReference(*getMBB());
484     break;
485   case MachineOperand::MO_FrameIndex:
486     OS << "<fi#" << getIndex() << '>';
487     break;
488   case MachineOperand::MO_ConstantPoolIndex:
489     OS << "<cp#" << getIndex();
490     if (getOffset())
491       OS << "+" << getOffset();
492     OS << '>';
493     break;
494   case MachineOperand::MO_TargetIndex:
495     OS << "<ti#" << getIndex();
496     if (getOffset())
497       OS << "+" << getOffset();
498     OS << '>';
499     break;
500   case MachineOperand::MO_JumpTableIndex:
501     OS << "<jt#" << getIndex() << '>';
502     break;
503   case MachineOperand::MO_GlobalAddress:
504     OS << "<ga:";
505     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
506     if (getOffset())
507       OS << "+" << getOffset();
508     OS << '>';
509     break;
510   case MachineOperand::MO_ExternalSymbol:
511     OS << "<es:" << getSymbolName();
512     if (getOffset())
513       OS << "+" << getOffset();
514     OS << '>';
515     break;
516   case MachineOperand::MO_BlockAddress:
517     OS << '<';
518     getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
519     if (getOffset())
520       OS << "+" << getOffset();
521     OS << '>';
522     break;
523   case MachineOperand::MO_RegisterMask: {
524     OS << "<regmask";
525     if (TRI) {
526       unsigned NumRegsInMask = 0;
527       unsigned NumRegsEmitted = 0;
528       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
529         unsigned MaskWord = i / 32;
530         unsigned MaskBit = i % 32;
531         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
532           if (PrintRegMaskNumRegs < 0 ||
533               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
534             OS << " " << printReg(i, TRI);
535             NumRegsEmitted++;
536           }
537           NumRegsInMask++;
538         }
539       }
540       if (NumRegsEmitted != NumRegsInMask)
541         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
542     } else {
543       OS << " ...";
544     }
545     OS << ">";
546     break;
547   }
548   case MachineOperand::MO_RegisterLiveOut:
549     OS << "<regliveout>";
550     break;
551   case MachineOperand::MO_Metadata:
552     OS << '<';
553     getMetadata()->printAsOperand(OS, MST);
554     OS << '>';
555     break;
556   case MachineOperand::MO_MCSymbol:
557     OS << "<MCSym=" << *getMCSymbol() << '>';
558     break;
559   case MachineOperand::MO_CFIIndex:
560     OS << "<call frame instruction>";
561     break;
562   case MachineOperand::MO_IntrinsicID: {
563     Intrinsic::ID ID = getIntrinsicID();
564     if (ID < Intrinsic::num_intrinsics)
565       OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
566     else if (IntrinsicInfo)
567       OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
568     else
569       OS << "<intrinsic:" << ID << '>';
570     break;
571   }
572   case MachineOperand::MO_Predicate: {
573     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
574     OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
575        << CmpInst::getPredicateName(Pred) << '>';
576     break;
577   }
578   }
579   if (unsigned TF = getTargetFlags())
580     OS << "[TF=" << TF << ']';
581 }
582 
583 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
584 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
585 #endif
586 
587 //===----------------------------------------------------------------------===//
588 // MachineMemOperand Implementation
589 //===----------------------------------------------------------------------===//
590 
591 /// getAddrSpace - Return the LLVM IR address space number that this pointer
592 /// points into.
593 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
594 
595 /// isDereferenceable - Return true if V is always dereferenceable for
596 /// Offset + Size byte.
597 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
598                                            const DataLayout &DL) const {
599   if (!V.is<const Value *>())
600     return false;
601 
602   const Value *BasePtr = V.get<const Value *>();
603   if (BasePtr == nullptr)
604     return false;
605 
606   return isDereferenceableAndAlignedPointer(
607       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
608 }
609 
610 /// getConstantPool - Return a MachinePointerInfo record that refers to the
611 /// constant pool.
612 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
613   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
614 }
615 
616 /// getFixedStack - Return a MachinePointerInfo record that refers to the
617 /// the specified FrameIndex.
618 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
619                                                      int FI, int64_t Offset) {
620   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
621 }
622 
623 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
624   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
625 }
626 
627 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
628   return MachinePointerInfo(MF.getPSVManager().getGOT());
629 }
630 
631 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
632                                                 int64_t Offset, uint8_t ID) {
633   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
634 }
635 
636 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
637   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
638 }
639 
640 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
641                                      uint64_t s, unsigned int a,
642                                      const AAMDNodes &AAInfo,
643                                      const MDNode *Ranges, SyncScope::ID SSID,
644                                      AtomicOrdering Ordering,
645                                      AtomicOrdering FailureOrdering)
646     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
647       AAInfo(AAInfo), Ranges(Ranges) {
648   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
649           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
650          "invalid pointer value");
651   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
652   assert((isLoad() || isStore()) && "Not a load/store!");
653 
654   AtomicInfo.SSID = static_cast<unsigned>(SSID);
655   assert(getSyncScopeID() == SSID && "Value truncated");
656   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
657   assert(getOrdering() == Ordering && "Value truncated");
658   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
659   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
660 }
661 
662 /// Profile - Gather unique data for the object.
663 ///
664 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
665   ID.AddInteger(getOffset());
666   ID.AddInteger(Size);
667   ID.AddPointer(getOpaqueValue());
668   ID.AddInteger(getFlags());
669   ID.AddInteger(getBaseAlignment());
670 }
671 
672 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
673   // The Value and Offset may differ due to CSE. But the flags and size
674   // should be the same.
675   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
676   assert(MMO->getSize() == getSize() && "Size mismatch!");
677 
678   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
679     // Update the alignment value.
680     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
681     // Also update the base and offset, because the new alignment may
682     // not be applicable with the old ones.
683     PtrInfo = MMO->PtrInfo;
684   }
685 }
686 
687 /// getAlignment - Return the minimum known alignment in bytes of the
688 /// actual memory reference.
689 uint64_t MachineMemOperand::getAlignment() const {
690   return MinAlign(getBaseAlignment(), getOffset());
691 }
692 
693 void MachineMemOperand::print(raw_ostream &OS) const {
694   ModuleSlotTracker DummyMST(nullptr);
695   print(OS, DummyMST);
696 }
697 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
698   assert((isLoad() || isStore()) && "SV has to be a load, store or both.");
699 
700   if (isVolatile())
701     OS << "Volatile ";
702 
703   if (isLoad())
704     OS << "LD";
705   if (isStore())
706     OS << "ST";
707   OS << getSize();
708 
709   // Print the address information.
710   OS << "[";
711   if (const Value *V = getValue())
712     V->printAsOperand(OS, /*PrintType=*/false, MST);
713   else if (const PseudoSourceValue *PSV = getPseudoValue())
714     PSV->printCustom(OS);
715   else
716     OS << "<unknown>";
717 
718   unsigned AS = getAddrSpace();
719   if (AS != 0)
720     OS << "(addrspace=" << AS << ')';
721 
722   // If the alignment of the memory reference itself differs from the alignment
723   // of the base pointer, print the base alignment explicitly, next to the base
724   // pointer.
725   if (getBaseAlignment() != getAlignment())
726     OS << "(align=" << getBaseAlignment() << ")";
727 
728   if (getOffset() != 0)
729     OS << "+" << getOffset();
730   OS << "]";
731 
732   // Print the alignment of the reference.
733   if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
734     OS << "(align=" << getAlignment() << ")";
735 
736   // Print TBAA info.
737   if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
738     OS << "(tbaa=";
739     if (TBAAInfo->getNumOperands() > 0)
740       TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
741     else
742       OS << "<unknown>";
743     OS << ")";
744   }
745 
746   // Print AA scope info.
747   if (const MDNode *ScopeInfo = getAAInfo().Scope) {
748     OS << "(alias.scope=";
749     if (ScopeInfo->getNumOperands() > 0)
750       for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
751         ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
752         if (i != ie - 1)
753           OS << ",";
754       }
755     else
756       OS << "<unknown>";
757     OS << ")";
758   }
759 
760   // Print AA noalias scope info.
761   if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
762     OS << "(noalias=";
763     if (NoAliasInfo->getNumOperands() > 0)
764       for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
765         NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
766         if (i != ie - 1)
767           OS << ",";
768       }
769     else
770       OS << "<unknown>";
771     OS << ")";
772   }
773 
774   if (const MDNode *Ranges = getRanges()) {
775     unsigned NumRanges = Ranges->getNumOperands();
776     if (NumRanges != 0) {
777       OS << "(ranges=";
778 
779       for (unsigned I = 0; I != NumRanges; ++I) {
780         Ranges->getOperand(I)->printAsOperand(OS, MST);
781         if (I != NumRanges - 1)
782           OS << ',';
783       }
784 
785       OS << ')';
786     }
787   }
788 
789   if (isNonTemporal())
790     OS << "(nontemporal)";
791   if (isDereferenceable())
792     OS << "(dereferenceable)";
793   if (isInvariant())
794     OS << "(invariant)";
795   if (getFlags() & MOTargetFlag1)
796     OS << "(flag1)";
797   if (getFlags() & MOTargetFlag2)
798     OS << "(flag2)";
799   if (getFlags() & MOTargetFlag3)
800     OS << "(flag3)";
801 }
802