1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MachineOperand.h"
15 #include "llvm/Analysis/Loads.h"
16 #include "llvm/CodeGen/MIRPrinter.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetRegisterInfo.h"
19 #include "llvm/IR/Constants.h"
20 #include "llvm/IR/ModuleSlotTracker.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 
24 using namespace llvm;
25 
26 static cl::opt<int>
27     PrintRegMaskNumRegs("print-regmask-num-regs",
28                         cl::desc("Number of registers to limit to when "
29                                  "printing regmask operands in IR dumps. "
30                                  "unlimited = -1"),
31                         cl::init(32), cl::Hidden);
32 
33 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
34   if (const MachineInstr *MI = MO.getParent())
35     if (const MachineBasicBlock *MBB = MI->getParent())
36       if (const MachineFunction *MF = MBB->getParent())
37         return MF;
38   return nullptr;
39 }
40 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
41   return const_cast<MachineFunction *>(
42       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
43 }
44 
45 void MachineOperand::setReg(unsigned Reg) {
46   if (getReg() == Reg)
47     return; // No change.
48 
49   // Otherwise, we have to change the register.  If this operand is embedded
50   // into a machine function, we need to update the old and new register's
51   // use/def lists.
52   if (MachineFunction *MF = getMFIfAvailable(*this)) {
53     MachineRegisterInfo &MRI = MF->getRegInfo();
54     MRI.removeRegOperandFromUseList(this);
55     SmallContents.RegNo = Reg;
56     MRI.addRegOperandToUseList(this);
57     return;
58   }
59 
60   // Otherwise, just change the register, no problem.  :)
61   SmallContents.RegNo = Reg;
62 }
63 
64 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
65                                   const TargetRegisterInfo &TRI) {
66   assert(TargetRegisterInfo::isVirtualRegister(Reg));
67   if (SubIdx && getSubReg())
68     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
69   setReg(Reg);
70   if (SubIdx)
71     setSubReg(SubIdx);
72 }
73 
74 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
75   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
76   if (getSubReg()) {
77     Reg = TRI.getSubReg(Reg, getSubReg());
78     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
79     // That won't happen in legal code.
80     setSubReg(0);
81     if (isDef())
82       setIsUndef(false);
83   }
84   setReg(Reg);
85 }
86 
87 /// Change a def to a use, or a use to a def.
88 void MachineOperand::setIsDef(bool Val) {
89   assert(isReg() && "Wrong MachineOperand accessor");
90   assert((!Val || !isDebug()) && "Marking a debug operation as def");
91   if (IsDef == Val)
92     return;
93   // MRI may keep uses and defs in different list positions.
94   if (MachineFunction *MF = getMFIfAvailable(*this)) {
95     MachineRegisterInfo &MRI = MF->getRegInfo();
96     MRI.removeRegOperandFromUseList(this);
97     IsDef = Val;
98     MRI.addRegOperandToUseList(this);
99     return;
100   }
101   IsDef = Val;
102 }
103 
104 // If this operand is currently a register operand, and if this is in a
105 // function, deregister the operand from the register's use/def list.
106 void MachineOperand::removeRegFromUses() {
107   if (!isReg() || !isOnRegUseList())
108     return;
109 
110   if (MachineFunction *MF = getMFIfAvailable(*this))
111     MF->getRegInfo().removeRegOperandFromUseList(this);
112 }
113 
114 /// ChangeToImmediate - Replace this operand with a new immediate operand of
115 /// the specified value.  If an operand is known to be an immediate already,
116 /// the setImm method should be used.
117 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
118   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
119 
120   removeRegFromUses();
121 
122   OpKind = MO_Immediate;
123   Contents.ImmVal = ImmVal;
124 }
125 
126 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
127   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
128 
129   removeRegFromUses();
130 
131   OpKind = MO_FPImmediate;
132   Contents.CFP = FPImm;
133 }
134 
135 void MachineOperand::ChangeToES(const char *SymName,
136                                 unsigned char TargetFlags) {
137   assert((!isReg() || !isTied()) &&
138          "Cannot change a tied operand into an external symbol");
139 
140   removeRegFromUses();
141 
142   OpKind = MO_ExternalSymbol;
143   Contents.OffsetedInfo.Val.SymbolName = SymName;
144   setOffset(0); // Offset is always 0.
145   setTargetFlags(TargetFlags);
146 }
147 
148 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
149   assert((!isReg() || !isTied()) &&
150          "Cannot change a tied operand into an MCSymbol");
151 
152   removeRegFromUses();
153 
154   OpKind = MO_MCSymbol;
155   Contents.Sym = Sym;
156 }
157 
158 void MachineOperand::ChangeToFrameIndex(int Idx) {
159   assert((!isReg() || !isTied()) &&
160          "Cannot change a tied operand into a FrameIndex");
161 
162   removeRegFromUses();
163 
164   OpKind = MO_FrameIndex;
165   setIndex(Idx);
166 }
167 
168 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
169                                          unsigned char TargetFlags) {
170   assert((!isReg() || !isTied()) &&
171          "Cannot change a tied operand into a FrameIndex");
172 
173   removeRegFromUses();
174 
175   OpKind = MO_TargetIndex;
176   setIndex(Idx);
177   setOffset(Offset);
178   setTargetFlags(TargetFlags);
179 }
180 
181 /// ChangeToRegister - Replace this operand with a new register operand of
182 /// the specified value.  If an operand is known to be an register already,
183 /// the setReg method should be used.
184 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
185                                       bool isKill, bool isDead, bool isUndef,
186                                       bool isDebug) {
187   MachineRegisterInfo *RegInfo = nullptr;
188   if (MachineFunction *MF = getMFIfAvailable(*this))
189     RegInfo = &MF->getRegInfo();
190   // If this operand is already a register operand, remove it from the
191   // register's use/def lists.
192   bool WasReg = isReg();
193   if (RegInfo && WasReg)
194     RegInfo->removeRegOperandFromUseList(this);
195 
196   // Change this to a register and set the reg#.
197   OpKind = MO_Register;
198   SmallContents.RegNo = Reg;
199   SubReg_TargetFlags = 0;
200   IsDef = isDef;
201   IsImp = isImp;
202   IsKill = isKill;
203   IsDead = isDead;
204   IsUndef = isUndef;
205   IsInternalRead = false;
206   IsEarlyClobber = false;
207   IsDebug = isDebug;
208   // Ensure isOnRegUseList() returns false.
209   Contents.Reg.Prev = nullptr;
210   // Preserve the tie when the operand was already a register.
211   if (!WasReg)
212     TiedTo = 0;
213 
214   // If this operand is embedded in a function, add the operand to the
215   // register's use/def list.
216   if (RegInfo)
217     RegInfo->addRegOperandToUseList(this);
218 }
219 
220 /// isIdenticalTo - Return true if this operand is identical to the specified
221 /// operand. Note that this should stay in sync with the hash_value overload
222 /// below.
223 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
224   if (getType() != Other.getType() ||
225       getTargetFlags() != Other.getTargetFlags())
226     return false;
227 
228   switch (getType()) {
229   case MachineOperand::MO_Register:
230     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
231            getSubReg() == Other.getSubReg();
232   case MachineOperand::MO_Immediate:
233     return getImm() == Other.getImm();
234   case MachineOperand::MO_CImmediate:
235     return getCImm() == Other.getCImm();
236   case MachineOperand::MO_FPImmediate:
237     return getFPImm() == Other.getFPImm();
238   case MachineOperand::MO_MachineBasicBlock:
239     return getMBB() == Other.getMBB();
240   case MachineOperand::MO_FrameIndex:
241     return getIndex() == Other.getIndex();
242   case MachineOperand::MO_ConstantPoolIndex:
243   case MachineOperand::MO_TargetIndex:
244     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
245   case MachineOperand::MO_JumpTableIndex:
246     return getIndex() == Other.getIndex();
247   case MachineOperand::MO_GlobalAddress:
248     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
249   case MachineOperand::MO_ExternalSymbol:
250     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
251            getOffset() == Other.getOffset();
252   case MachineOperand::MO_BlockAddress:
253     return getBlockAddress() == Other.getBlockAddress() &&
254            getOffset() == Other.getOffset();
255   case MachineOperand::MO_RegisterMask:
256   case MachineOperand::MO_RegisterLiveOut: {
257     // Shallow compare of the two RegMasks
258     const uint32_t *RegMask = getRegMask();
259     const uint32_t *OtherRegMask = Other.getRegMask();
260     if (RegMask == OtherRegMask)
261       return true;
262 
263     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
264       // Calculate the size of the RegMask
265       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
266       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
267 
268       // Deep compare of the two RegMasks
269       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
270     }
271     // We don't know the size of the RegMask, so we can't deep compare the two
272     // reg masks.
273     return false;
274   }
275   case MachineOperand::MO_MCSymbol:
276     return getMCSymbol() == Other.getMCSymbol();
277   case MachineOperand::MO_CFIIndex:
278     return getCFIIndex() == Other.getCFIIndex();
279   case MachineOperand::MO_Metadata:
280     return getMetadata() == Other.getMetadata();
281   case MachineOperand::MO_IntrinsicID:
282     return getIntrinsicID() == Other.getIntrinsicID();
283   case MachineOperand::MO_Predicate:
284     return getPredicate() == Other.getPredicate();
285   }
286   llvm_unreachable("Invalid machine operand type");
287 }
288 
289 // Note: this must stay exactly in sync with isIdenticalTo above.
290 hash_code llvm::hash_value(const MachineOperand &MO) {
291   switch (MO.getType()) {
292   case MachineOperand::MO_Register:
293     // Register operands don't have target flags.
294     return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
295   case MachineOperand::MO_Immediate:
296     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
297   case MachineOperand::MO_CImmediate:
298     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
299   case MachineOperand::MO_FPImmediate:
300     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
301   case MachineOperand::MO_MachineBasicBlock:
302     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
303   case MachineOperand::MO_FrameIndex:
304     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
305   case MachineOperand::MO_ConstantPoolIndex:
306   case MachineOperand::MO_TargetIndex:
307     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
308                         MO.getOffset());
309   case MachineOperand::MO_JumpTableIndex:
310     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
311   case MachineOperand::MO_ExternalSymbol:
312     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
313                         MO.getSymbolName());
314   case MachineOperand::MO_GlobalAddress:
315     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
316                         MO.getOffset());
317   case MachineOperand::MO_BlockAddress:
318     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
319                         MO.getOffset());
320   case MachineOperand::MO_RegisterMask:
321   case MachineOperand::MO_RegisterLiveOut:
322     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
323   case MachineOperand::MO_Metadata:
324     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
325   case MachineOperand::MO_MCSymbol:
326     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
327   case MachineOperand::MO_CFIIndex:
328     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
329   case MachineOperand::MO_IntrinsicID:
330     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
331   case MachineOperand::MO_Predicate:
332     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
333   }
334   llvm_unreachable("Invalid machine operand type");
335 }
336 
337 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
338 // it.
339 static void tryToGetTargetInfo(const MachineOperand &MO,
340                                const TargetRegisterInfo *&TRI,
341                                const TargetIntrinsicInfo *&IntrinsicInfo) {
342   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
343     TRI = MF->getSubtarget().getRegisterInfo();
344     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
345   }
346 }
347 
348 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
349                            const TargetIntrinsicInfo *IntrinsicInfo) const {
350   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
351   ModuleSlotTracker DummyMST(nullptr);
352   print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
353         /*ShouldPrintRegisterTies=*/true,
354         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
355 }
356 
357 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
358                            LLT TypeToPrint, bool PrintDef,
359                            bool ShouldPrintRegisterTies,
360                            unsigned TiedOperandIdx,
361                            const TargetRegisterInfo *TRI,
362                            const TargetIntrinsicInfo *IntrinsicInfo) const {
363   switch (getType()) {
364   case MachineOperand::MO_Register: {
365     unsigned Reg = getReg();
366     if (isImplicit())
367       OS << (isDef() ? "implicit-def " : "implicit ");
368     else if (PrintDef && isDef())
369       // Print the 'def' flag only when the operand is defined after '='.
370       OS << "def ";
371     if (isInternalRead())
372       OS << "internal ";
373     if (isDead())
374       OS << "dead ";
375     if (isKill())
376       OS << "killed ";
377     if (isUndef())
378       OS << "undef ";
379     if (isEarlyClobber())
380       OS << "early-clobber ";
381     if (isDebug())
382       OS << "debug-use ";
383     OS << printReg(Reg, TRI);
384     // Print the sub register.
385     if (unsigned SubReg = getSubReg()) {
386       if (TRI)
387         OS << '.' << TRI->getSubRegIndexName(SubReg);
388       else
389         OS << ".subreg" << SubReg;
390     }
391     // Print the register class / bank.
392     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
393       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
394         const MachineRegisterInfo &MRI = MF->getRegInfo();
395         if (!PrintDef || MRI.def_empty(Reg)) {
396           OS << ':';
397           OS << printRegClassOrBank(Reg, MRI, TRI);
398         }
399       }
400     }
401     // Print ties.
402     if (ShouldPrintRegisterTies && isTied() && !isDef())
403       OS << "(tied-def " << TiedOperandIdx << ")";
404     // Print types.
405     if (TypeToPrint.isValid())
406       OS << '(' << TypeToPrint << ')';
407     break;
408   }
409   case MachineOperand::MO_Immediate:
410     OS << getImm();
411     break;
412   case MachineOperand::MO_CImmediate:
413     getCImm()->getValue().print(OS, false);
414     break;
415   case MachineOperand::MO_FPImmediate:
416     if (getFPImm()->getType()->isFloatTy()) {
417       OS << getFPImm()->getValueAPF().convertToFloat();
418     } else if (getFPImm()->getType()->isHalfTy()) {
419       APFloat APF = getFPImm()->getValueAPF();
420       bool Unused;
421       APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
422       OS << "half " << APF.convertToFloat();
423     } else if (getFPImm()->getType()->isFP128Ty()) {
424       APFloat APF = getFPImm()->getValueAPF();
425       SmallString<16> Str;
426       getFPImm()->getValueAPF().toString(Str);
427       OS << "quad " << Str;
428     } else if (getFPImm()->getType()->isX86_FP80Ty()) {
429       APFloat APF = getFPImm()->getValueAPF();
430       OS << "x86_fp80 0xK";
431       APInt API = APF.bitcastToAPInt();
432       OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
433                                  /*Upper=*/true);
434       OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
435                                  /*Upper=*/true);
436     } else {
437       OS << getFPImm()->getValueAPF().convertToDouble();
438     }
439     break;
440   case MachineOperand::MO_MachineBasicBlock:
441     OS << printMBBReference(*getMBB());
442     break;
443   case MachineOperand::MO_FrameIndex:
444     OS << "<fi#" << getIndex() << '>';
445     break;
446   case MachineOperand::MO_ConstantPoolIndex:
447     OS << "<cp#" << getIndex();
448     if (getOffset())
449       OS << "+" << getOffset();
450     OS << '>';
451     break;
452   case MachineOperand::MO_TargetIndex:
453     OS << "<ti#" << getIndex();
454     if (getOffset())
455       OS << "+" << getOffset();
456     OS << '>';
457     break;
458   case MachineOperand::MO_JumpTableIndex:
459     OS << "<jt#" << getIndex() << '>';
460     break;
461   case MachineOperand::MO_GlobalAddress:
462     OS << "<ga:";
463     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
464     if (getOffset())
465       OS << "+" << getOffset();
466     OS << '>';
467     break;
468   case MachineOperand::MO_ExternalSymbol:
469     OS << "<es:" << getSymbolName();
470     if (getOffset())
471       OS << "+" << getOffset();
472     OS << '>';
473     break;
474   case MachineOperand::MO_BlockAddress:
475     OS << '<';
476     getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
477     if (getOffset())
478       OS << "+" << getOffset();
479     OS << '>';
480     break;
481   case MachineOperand::MO_RegisterMask: {
482     OS << "<regmask";
483     if (TRI) {
484       unsigned NumRegsInMask = 0;
485       unsigned NumRegsEmitted = 0;
486       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
487         unsigned MaskWord = i / 32;
488         unsigned MaskBit = i % 32;
489         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
490           if (PrintRegMaskNumRegs < 0 ||
491               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
492             OS << " " << printReg(i, TRI);
493             NumRegsEmitted++;
494           }
495           NumRegsInMask++;
496         }
497       }
498       if (NumRegsEmitted != NumRegsInMask)
499         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
500     } else {
501       OS << " ...";
502     }
503     OS << ">";
504     break;
505   }
506   case MachineOperand::MO_RegisterLiveOut:
507     OS << "<regliveout>";
508     break;
509   case MachineOperand::MO_Metadata:
510     OS << '<';
511     getMetadata()->printAsOperand(OS, MST);
512     OS << '>';
513     break;
514   case MachineOperand::MO_MCSymbol:
515     OS << "<MCSym=" << *getMCSymbol() << '>';
516     break;
517   case MachineOperand::MO_CFIIndex:
518     OS << "<call frame instruction>";
519     break;
520   case MachineOperand::MO_IntrinsicID: {
521     Intrinsic::ID ID = getIntrinsicID();
522     if (ID < Intrinsic::num_intrinsics)
523       OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
524     else if (IntrinsicInfo)
525       OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
526     else
527       OS << "<intrinsic:" << ID << '>';
528     break;
529   }
530   case MachineOperand::MO_Predicate: {
531     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
532     OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
533        << CmpInst::getPredicateName(Pred) << '>';
534     break;
535   }
536   }
537   if (unsigned TF = getTargetFlags())
538     OS << "[TF=" << TF << ']';
539 }
540 
541 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
542 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
543 #endif
544 
545 //===----------------------------------------------------------------------===//
546 // MachineMemOperand Implementation
547 //===----------------------------------------------------------------------===//
548 
549 /// getAddrSpace - Return the LLVM IR address space number that this pointer
550 /// points into.
551 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
552 
553 /// isDereferenceable - Return true if V is always dereferenceable for
554 /// Offset + Size byte.
555 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
556                                            const DataLayout &DL) const {
557   if (!V.is<const Value *>())
558     return false;
559 
560   const Value *BasePtr = V.get<const Value *>();
561   if (BasePtr == nullptr)
562     return false;
563 
564   return isDereferenceableAndAlignedPointer(
565       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
566 }
567 
568 /// getConstantPool - Return a MachinePointerInfo record that refers to the
569 /// constant pool.
570 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
571   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
572 }
573 
574 /// getFixedStack - Return a MachinePointerInfo record that refers to the
575 /// the specified FrameIndex.
576 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
577                                                      int FI, int64_t Offset) {
578   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
579 }
580 
581 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
582   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
583 }
584 
585 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
586   return MachinePointerInfo(MF.getPSVManager().getGOT());
587 }
588 
589 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
590                                                 int64_t Offset, uint8_t ID) {
591   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
592 }
593 
594 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
595   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
596 }
597 
598 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
599                                      uint64_t s, unsigned int a,
600                                      const AAMDNodes &AAInfo,
601                                      const MDNode *Ranges, SyncScope::ID SSID,
602                                      AtomicOrdering Ordering,
603                                      AtomicOrdering FailureOrdering)
604     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
605       AAInfo(AAInfo), Ranges(Ranges) {
606   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
607           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
608          "invalid pointer value");
609   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
610   assert((isLoad() || isStore()) && "Not a load/store!");
611 
612   AtomicInfo.SSID = static_cast<unsigned>(SSID);
613   assert(getSyncScopeID() == SSID && "Value truncated");
614   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
615   assert(getOrdering() == Ordering && "Value truncated");
616   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
617   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
618 }
619 
620 /// Profile - Gather unique data for the object.
621 ///
622 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
623   ID.AddInteger(getOffset());
624   ID.AddInteger(Size);
625   ID.AddPointer(getOpaqueValue());
626   ID.AddInteger(getFlags());
627   ID.AddInteger(getBaseAlignment());
628 }
629 
630 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
631   // The Value and Offset may differ due to CSE. But the flags and size
632   // should be the same.
633   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
634   assert(MMO->getSize() == getSize() && "Size mismatch!");
635 
636   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
637     // Update the alignment value.
638     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
639     // Also update the base and offset, because the new alignment may
640     // not be applicable with the old ones.
641     PtrInfo = MMO->PtrInfo;
642   }
643 }
644 
645 /// getAlignment - Return the minimum known alignment in bytes of the
646 /// actual memory reference.
647 uint64_t MachineMemOperand::getAlignment() const {
648   return MinAlign(getBaseAlignment(), getOffset());
649 }
650 
651 void MachineMemOperand::print(raw_ostream &OS) const {
652   ModuleSlotTracker DummyMST(nullptr);
653   print(OS, DummyMST);
654 }
655 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
656   assert((isLoad() || isStore()) && "SV has to be a load, store or both.");
657 
658   if (isVolatile())
659     OS << "Volatile ";
660 
661   if (isLoad())
662     OS << "LD";
663   if (isStore())
664     OS << "ST";
665   OS << getSize();
666 
667   // Print the address information.
668   OS << "[";
669   if (const Value *V = getValue())
670     V->printAsOperand(OS, /*PrintType=*/false, MST);
671   else if (const PseudoSourceValue *PSV = getPseudoValue())
672     PSV->printCustom(OS);
673   else
674     OS << "<unknown>";
675 
676   unsigned AS = getAddrSpace();
677   if (AS != 0)
678     OS << "(addrspace=" << AS << ')';
679 
680   // If the alignment of the memory reference itself differs from the alignment
681   // of the base pointer, print the base alignment explicitly, next to the base
682   // pointer.
683   if (getBaseAlignment() != getAlignment())
684     OS << "(align=" << getBaseAlignment() << ")";
685 
686   if (getOffset() != 0)
687     OS << "+" << getOffset();
688   OS << "]";
689 
690   // Print the alignment of the reference.
691   if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
692     OS << "(align=" << getAlignment() << ")";
693 
694   // Print TBAA info.
695   if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
696     OS << "(tbaa=";
697     if (TBAAInfo->getNumOperands() > 0)
698       TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
699     else
700       OS << "<unknown>";
701     OS << ")";
702   }
703 
704   // Print AA scope info.
705   if (const MDNode *ScopeInfo = getAAInfo().Scope) {
706     OS << "(alias.scope=";
707     if (ScopeInfo->getNumOperands() > 0)
708       for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
709         ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
710         if (i != ie - 1)
711           OS << ",";
712       }
713     else
714       OS << "<unknown>";
715     OS << ")";
716   }
717 
718   // Print AA noalias scope info.
719   if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
720     OS << "(noalias=";
721     if (NoAliasInfo->getNumOperands() > 0)
722       for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
723         NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
724         if (i != ie - 1)
725           OS << ",";
726       }
727     else
728       OS << "<unknown>";
729     OS << ")";
730   }
731 
732   if (const MDNode *Ranges = getRanges()) {
733     unsigned NumRanges = Ranges->getNumOperands();
734     if (NumRanges != 0) {
735       OS << "(ranges=";
736 
737       for (unsigned I = 0; I != NumRanges; ++I) {
738         Ranges->getOperand(I)->printAsOperand(OS, MST);
739         if (I != NumRanges - 1)
740           OS << ',';
741       }
742 
743       OS << ')';
744     }
745   }
746 
747   if (isNonTemporal())
748     OS << "(nontemporal)";
749   if (isDereferenceable())
750     OS << "(dereferenceable)";
751   if (isInvariant())
752     OS << "(invariant)";
753   if (getFlags() & MOTargetFlag1)
754     OS << "(flag1)";
755   if (getFlags() & MOTargetFlag2)
756     OS << "(flag2)";
757   if (getFlags() & MOTargetFlag3)
758     OS << "(flag3)";
759 }
760