1 //===---------- MIRVRegNamerUtils.cpp - MIR VReg Renaming Utilities -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MIRVRegNamerUtils.h"
10 #include "llvm/Support/Debug.h"
11 
12 using namespace llvm;
13 
14 #define DEBUG_TYPE "mir-vregnamer-utils"
15 
16 using VRegRenameMap = std::map<unsigned, unsigned>;
17 
18 bool VRegRenamer::doVRegRenaming(const VRegRenameMap &VRM) {
19   bool Changed = false;
20 
21   for (const auto &E : VRM) {
22     Changed = Changed || !MRI.reg_empty(E.first);
23     MRI.replaceRegWith(E.first, E.second);
24   }
25 
26   return Changed;
27 }
28 
29 VRegRenameMap
30 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) {
31 
32   StringMap<unsigned> VRegNameCollisionMap;
33 
34   auto GetUniqueVRegName = [&VRegNameCollisionMap](const NamedVReg &Reg) {
35     if (VRegNameCollisionMap.find(Reg.getName()) == VRegNameCollisionMap.end())
36       VRegNameCollisionMap[Reg.getName()] = 0;
37     const unsigned Counter = ++VRegNameCollisionMap[Reg.getName()];
38     return Reg.getName() + "__" + std::to_string(Counter);
39   };
40 
41   VRegRenameMap VRM;
42   for (const auto &VReg : VRegs) {
43     const unsigned Reg = VReg.getReg();
44     VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg));
45   }
46   return VRM;
47 }
48 
49 std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
50   std::string S;
51   raw_string_ostream OS(S);
52 
53   // Gets a hashable artifact from a given MachineOperand (ie an unsigned).
54   auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
55     switch (MO.getType()) {
56     case MachineOperand::MO_CImmediate:
57       return hash_combine(MO.getType(), MO.getTargetFlags(),
58                           MO.getCImm()->getZExtValue());
59     case MachineOperand::MO_FPImmediate:
60       return hash_combine(
61           MO.getType(), MO.getTargetFlags(),
62           MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
63     case MachineOperand::MO_Register:
64       if (Register::isVirtualRegister(MO.getReg()))
65         return MRI.getVRegDef(MO.getReg())->getOpcode();
66       return MO.getReg();
67     case MachineOperand::MO_Immediate:
68       return MO.getImm();
69     case MachineOperand::MO_TargetIndex:
70       return MO.getOffset() | (MO.getTargetFlags() << 16);
71 
72     // We could explicitly handle all the types of the MachineOperand,
73     // here but we can just return a common number until we find a
74     // compelling test case where this is bad. The only side effect here
75     // is contributing to a hash collision but there's enough information
76     // (Opcodes,other registers etc) that this will likely not be a problem.
77 
78     // TODO: Handle the following Index/ID/Predicate cases. They can
79     // be hashed on in a stable manner.
80     case MachineOperand::MO_FrameIndex:
81     case MachineOperand::MO_ConstantPoolIndex:
82     case MachineOperand::MO_JumpTableIndex:
83     case MachineOperand::MO_CFIIndex:
84     case MachineOperand::MO_IntrinsicID:
85     case MachineOperand::MO_Predicate:
86 
87     // In the cases below we havn't found a way to produce an artifact that will
88     // result in a stable hash, in most cases because they are pointers. We want
89     // stable hashes because we want the hash to be the same run to run.
90     case MachineOperand::MO_MachineBasicBlock:
91     case MachineOperand::MO_ExternalSymbol:
92     case MachineOperand::MO_GlobalAddress:
93     case MachineOperand::MO_BlockAddress:
94     case MachineOperand::MO_RegisterMask:
95     case MachineOperand::MO_RegisterLiveOut:
96     case MachineOperand::MO_Metadata:
97     case MachineOperand::MO_MCSymbol:
98     case MachineOperand::MO_ShuffleMask:
99       return 0;
100     }
101     llvm_unreachable("Unexpected MachineOperandType.");
102   };
103 
104   SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};
105   llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO);
106 
107   for (const auto *Op : MI.memoperands()) {
108     MIOperands.push_back((unsigned)Op->getSize());
109     MIOperands.push_back((unsigned)Op->getFlags());
110     MIOperands.push_back((unsigned)Op->getOffset());
111     MIOperands.push_back((unsigned)Op->getOrdering());
112     MIOperands.push_back((unsigned)Op->getAddrSpace());
113     MIOperands.push_back((unsigned)Op->getSyncScopeID());
114     MIOperands.push_back((unsigned)Op->getBaseAlignment());
115     MIOperands.push_back((unsigned)Op->getFailureOrdering());
116   }
117 
118   auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());
119   return std::to_string(HashMI).substr(0, 5);
120 }
121 
122 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
123   assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers");
124   std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
125   return createVirtualRegisterWithLowerName(VReg, Name);
126 }
127 
128 bool VRegRenamer::renameInstsInMBB(MachineBasicBlock *MBB) {
129   std::vector<NamedVReg> VRegs;
130   std::string Prefix = "bb" + std::to_string(CurrentBBNumber) + "_";
131   for (MachineInstr &Candidate : *MBB) {
132     // Don't rename stores/branches.
133     if (Candidate.mayStore() || Candidate.isBranch())
134       continue;
135     if (!Candidate.getNumOperands())
136       continue;
137     // Look for instructions that define VRegs in operand 0.
138     MachineOperand &MO = Candidate.getOperand(0);
139     // Avoid non regs, instructions defining physical regs.
140     if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
141       continue;
142     VRegs.push_back(
143         NamedVReg(MO.getReg(), Prefix + getInstructionOpcodeHash(Candidate)));
144   }
145 
146   return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false;
147 }
148 
149 unsigned VRegRenamer::createVirtualRegisterWithLowerName(unsigned VReg,
150                                                          StringRef Name) {
151   std::string LowerName = Name.lower();
152   const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
153   return RC ? MRI.createVirtualRegister(RC, LowerName)
154             : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName);
155 }
156