1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/MIRYamlMapping.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCContext.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132 
133 private:
134   void initRegisterMaskIds(const MachineFunction &MF);
135 };
136 
137 /// This class prints out the machine instructions using the MIR serialization
138 /// format.
139 class MIPrinter {
140   raw_ostream &OS;
141   ModuleSlotTracker &MST;
142   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144   /// Synchronization scope names registered with LLVMContext.
145   SmallVector<StringRef, 8> SSNs;
146 
147   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
149 
150 public:
151   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155         StackObjectOperandMapping(StackObjectOperandMapping) {}
156 
157   void print(const MachineBasicBlock &MBB);
158 
159   void print(const MachineInstr &MI);
160   void printStackObjectReference(int FrameIndex);
161   void print(const MachineInstr &MI, unsigned OpIdx,
162              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
163              LLT TypeToPrint, bool PrintDef = true);
164 };
165 
166 } // end namespace llvm
167 
168 namespace llvm {
169 namespace yaml {
170 
171 /// This struct serializes the LLVM IR module.
172 template <> struct BlockScalarTraits<Module> {
173   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
174     Mod.print(OS, nullptr);
175   }
176 
177   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
178     llvm_unreachable("LLVM Module is supposed to be parsed separately");
179     return "";
180   }
181 };
182 
183 } // end namespace yaml
184 } // end namespace llvm
185 
186 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
187                         const TargetRegisterInfo *TRI) {
188   raw_string_ostream OS(Dest.Value);
189   OS << printReg(Reg, TRI);
190 }
191 
192 void MIRPrinter::print(const MachineFunction &MF) {
193   initRegisterMaskIds(MF);
194 
195   yaml::MachineFunction YamlMF;
196   YamlMF.Name = MF.getName();
197   YamlMF.Alignment = MF.getAlignment();
198   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
199 
200   YamlMF.Legalized = MF.getProperties().hasProperty(
201       MachineFunctionProperties::Property::Legalized);
202   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
203       MachineFunctionProperties::Property::RegBankSelected);
204   YamlMF.Selected = MF.getProperties().hasProperty(
205       MachineFunctionProperties::Property::Selected);
206   YamlMF.FailedISel = MF.getProperties().hasProperty(
207       MachineFunctionProperties::Property::FailedISel);
208 
209   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
210   ModuleSlotTracker MST(MF.getFunction().getParent());
211   MST.incorporateFunction(MF.getFunction());
212   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
213   convertStackObjects(YamlMF, MF, MST);
214   if (const auto *ConstantPool = MF.getConstantPool())
215     convert(YamlMF, *ConstantPool);
216   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
217     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
218   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
219   bool IsNewlineNeeded = false;
220   for (const auto &MBB : MF) {
221     if (IsNewlineNeeded)
222       StrOS << "\n";
223     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
224         .print(MBB);
225     IsNewlineNeeded = true;
226   }
227   StrOS.flush();
228   yaml::Output Out(OS);
229   if (!SimplifyMIR)
230       Out.setWriteDefaultValues(true);
231   Out << YamlMF;
232 }
233 
234 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
235                                const TargetRegisterInfo *TRI) {
236   assert(RegMask && "Can't print an empty register mask");
237   OS << StringRef("CustomRegMask(");
238 
239   bool IsRegInRegMaskFound = false;
240   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
241     // Check whether the register is asserted in regmask.
242     if (RegMask[I / 32] & (1u << (I % 32))) {
243       if (IsRegInRegMaskFound)
244         OS << ',';
245       OS << printReg(I, TRI);
246       IsRegInRegMaskFound = true;
247     }
248   }
249 
250   OS << ')';
251 }
252 
253 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
254                                 const MachineRegisterInfo &RegInfo,
255                                 const TargetRegisterInfo *TRI) {
256   raw_string_ostream OS(Dest.Value);
257   OS << printRegClassOrBank(Reg, RegInfo, TRI);
258 }
259 
260 template <typename T>
261 static void
262 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
263                         T &Object, ModuleSlotTracker &MST) {
264   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
265                                         &Object.DebugExpr.Value,
266                                         &Object.DebugLoc.Value}};
267   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
268                                         DebugVar.Expr,
269                                         DebugVar.Loc}};
270   for (unsigned i = 0; i < 3; ++i) {
271     raw_string_ostream StrOS(*Outputs[i]);
272     Metas[i]->printAsOperand(StrOS, MST);
273   }
274 }
275 
276 void MIRPrinter::convert(yaml::MachineFunction &MF,
277                          const MachineRegisterInfo &RegInfo,
278                          const TargetRegisterInfo *TRI) {
279   MF.TracksRegLiveness = RegInfo.tracksLiveness();
280 
281   // Print the virtual register definitions.
282   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
283     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
284     yaml::VirtualRegisterDefinition VReg;
285     VReg.ID = I;
286     if (RegInfo.getVRegName(Reg) != "")
287       continue;
288     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
289     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
290     if (PreferredReg)
291       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
292     MF.VirtualRegisters.push_back(VReg);
293   }
294 
295   // Print the live ins.
296   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
297     yaml::MachineFunctionLiveIn LiveIn;
298     printRegMIR(LI.first, LiveIn.Register, TRI);
299     if (LI.second)
300       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
301     MF.LiveIns.push_back(LiveIn);
302   }
303 
304   // Prints the callee saved registers.
305   if (RegInfo.isUpdatedCSRsInitialized()) {
306     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
307     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
308     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
309       yaml::FlowStringValue Reg;
310       printRegMIR(*I, Reg, TRI);
311       CalleeSavedRegisters.push_back(Reg);
312     }
313     MF.CalleeSavedRegisters = CalleeSavedRegisters;
314   }
315 }
316 
317 void MIRPrinter::convert(ModuleSlotTracker &MST,
318                          yaml::MachineFrameInfo &YamlMFI,
319                          const MachineFrameInfo &MFI) {
320   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
321   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
322   YamlMFI.HasStackMap = MFI.hasStackMap();
323   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
324   YamlMFI.StackSize = MFI.getStackSize();
325   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
326   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
327   YamlMFI.AdjustsStack = MFI.adjustsStack();
328   YamlMFI.HasCalls = MFI.hasCalls();
329   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
330     ? MFI.getMaxCallFrameSize() : ~0u;
331   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
332   YamlMFI.HasVAStart = MFI.hasVAStart();
333   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
334   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
335   if (MFI.getSavePoint()) {
336     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
337     StrOS << printMBBReference(*MFI.getSavePoint());
338   }
339   if (MFI.getRestorePoint()) {
340     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
341     StrOS << printMBBReference(*MFI.getRestorePoint());
342   }
343 }
344 
345 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
346                                      const MachineFunction &MF,
347                                      ModuleSlotTracker &MST) {
348   const MachineFrameInfo &MFI = MF.getFrameInfo();
349   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
350   // Process fixed stack objects.
351   unsigned ID = 0;
352   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
353     if (MFI.isDeadObjectIndex(I))
354       continue;
355 
356     yaml::FixedMachineStackObject YamlObject;
357     YamlObject.ID = ID;
358     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
359                           ? yaml::FixedMachineStackObject::SpillSlot
360                           : yaml::FixedMachineStackObject::DefaultType;
361     YamlObject.Offset = MFI.getObjectOffset(I);
362     YamlObject.Size = MFI.getObjectSize(I);
363     YamlObject.Alignment = MFI.getObjectAlignment(I);
364     YamlObject.StackID = MFI.getStackID(I);
365     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
366     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
367     YMF.FixedStackObjects.push_back(YamlObject);
368     StackObjectOperandMapping.insert(
369         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
370   }
371 
372   // Process ordinary stack objects.
373   ID = 0;
374   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
375     if (MFI.isDeadObjectIndex(I))
376       continue;
377 
378     yaml::MachineStackObject YamlObject;
379     YamlObject.ID = ID;
380     if (const auto *Alloca = MFI.getObjectAllocation(I))
381       YamlObject.Name.Value =
382           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
383     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
384                           ? yaml::MachineStackObject::SpillSlot
385                           : MFI.isVariableSizedObjectIndex(I)
386                                 ? yaml::MachineStackObject::VariableSized
387                                 : yaml::MachineStackObject::DefaultType;
388     YamlObject.Offset = MFI.getObjectOffset(I);
389     YamlObject.Size = MFI.getObjectSize(I);
390     YamlObject.Alignment = MFI.getObjectAlignment(I);
391     YamlObject.StackID = MFI.getStackID(I);
392 
393     YMF.StackObjects.push_back(YamlObject);
394     StackObjectOperandMapping.insert(std::make_pair(
395         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
396   }
397 
398   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
399     yaml::StringValue Reg;
400     printRegMIR(CSInfo.getReg(), Reg, TRI);
401     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
402     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
403            "Invalid stack object index");
404     const FrameIndexOperand &StackObject = StackObjectInfo->second;
405     if (StackObject.IsFixed) {
406       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
407       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
408         CSInfo.isRestored();
409     } else {
410       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
411       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
412         CSInfo.isRestored();
413     }
414   }
415   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
416     auto LocalObject = MFI.getLocalFrameObjectMap(I);
417     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
418     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
419            "Invalid stack object index");
420     const FrameIndexOperand &StackObject = StackObjectInfo->second;
421     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
422     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
423   }
424 
425   // Print the stack object references in the frame information class after
426   // converting the stack objects.
427   if (MFI.hasStackProtectorIndex()) {
428     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
429     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
430         .printStackObjectReference(MFI.getStackProtectorIndex());
431   }
432 
433   // Print the debug variable information.
434   for (const MachineFunction::VariableDbgInfo &DebugVar :
435        MF.getVariableDbgInfo()) {
436     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
437     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
438            "Invalid stack object index");
439     const FrameIndexOperand &StackObject = StackObjectInfo->second;
440     if (StackObject.IsFixed) {
441       auto &Object = YMF.FixedStackObjects[StackObject.ID];
442       printStackObjectDbgInfo(DebugVar, Object, MST);
443     } else {
444       auto &Object = YMF.StackObjects[StackObject.ID];
445       printStackObjectDbgInfo(DebugVar, Object, MST);
446     }
447   }
448 }
449 
450 void MIRPrinter::convert(yaml::MachineFunction &MF,
451                          const MachineConstantPool &ConstantPool) {
452   unsigned ID = 0;
453   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
454     std::string Str;
455     raw_string_ostream StrOS(Str);
456     if (Constant.isMachineConstantPoolEntry()) {
457       Constant.Val.MachineCPVal->print(StrOS);
458     } else {
459       Constant.Val.ConstVal->printAsOperand(StrOS);
460     }
461 
462     yaml::MachineConstantPoolValue YamlConstant;
463     YamlConstant.ID = ID++;
464     YamlConstant.Value = StrOS.str();
465     YamlConstant.Alignment = Constant.getAlignment();
466     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
467 
468     MF.Constants.push_back(YamlConstant);
469   }
470 }
471 
472 void MIRPrinter::convert(ModuleSlotTracker &MST,
473                          yaml::MachineJumpTable &YamlJTI,
474                          const MachineJumpTableInfo &JTI) {
475   YamlJTI.Kind = JTI.getEntryKind();
476   unsigned ID = 0;
477   for (const auto &Table : JTI.getJumpTables()) {
478     std::string Str;
479     yaml::MachineJumpTable::Entry Entry;
480     Entry.ID = ID++;
481     for (const auto *MBB : Table.MBBs) {
482       raw_string_ostream StrOS(Str);
483       StrOS << printMBBReference(*MBB);
484       Entry.Blocks.push_back(StrOS.str());
485       Str.clear();
486     }
487     YamlJTI.Entries.push_back(Entry);
488   }
489 }
490 
491 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
492   const auto *TRI = MF.getSubtarget().getRegisterInfo();
493   unsigned I = 0;
494   for (const uint32_t *Mask : TRI->getRegMasks())
495     RegisterMaskIds.insert(std::make_pair(Mask, I++));
496 }
497 
498 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
499                            SmallVectorImpl<MachineBasicBlock*> &Result,
500                            bool &IsFallthrough) {
501   SmallPtrSet<MachineBasicBlock*,8> Seen;
502 
503   for (const MachineInstr &MI : MBB) {
504     if (MI.isPHI())
505       continue;
506     for (const MachineOperand &MO : MI.operands()) {
507       if (!MO.isMBB())
508         continue;
509       MachineBasicBlock *Succ = MO.getMBB();
510       auto RP = Seen.insert(Succ);
511       if (RP.second)
512         Result.push_back(Succ);
513     }
514   }
515   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
516   IsFallthrough = I == MBB.end() || !I->isBarrier();
517 }
518 
519 bool
520 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
521   if (MBB.succ_size() <= 1)
522     return true;
523   if (!MBB.hasSuccessorProbabilities())
524     return true;
525 
526   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
527                                               MBB.Probs.end());
528   BranchProbability::normalizeProbabilities(Normalized.begin(),
529                                             Normalized.end());
530   SmallVector<BranchProbability,8> Equal(Normalized.size());
531   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
532 
533   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
534 }
535 
536 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
537   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
538   bool GuessedFallthrough;
539   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
540   if (GuessedFallthrough) {
541     const MachineFunction &MF = *MBB.getParent();
542     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
543     if (NextI != MF.end()) {
544       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
545       if (!is_contained(GuessedSuccs, Next))
546         GuessedSuccs.push_back(Next);
547     }
548   }
549   if (GuessedSuccs.size() != MBB.succ_size())
550     return false;
551   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
552 }
553 
554 void MIPrinter::print(const MachineBasicBlock &MBB) {
555   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
556   OS << "bb." << MBB.getNumber();
557   bool HasAttributes = false;
558   if (const auto *BB = MBB.getBasicBlock()) {
559     if (BB->hasName()) {
560       OS << "." << BB->getName();
561     } else {
562       HasAttributes = true;
563       OS << " (";
564       int Slot = MST.getLocalSlot(BB);
565       if (Slot == -1)
566         OS << "<ir-block badref>";
567       else
568         OS << (Twine("%ir-block.") + Twine(Slot)).str();
569     }
570   }
571   if (MBB.hasAddressTaken()) {
572     OS << (HasAttributes ? ", " : " (");
573     OS << "address-taken";
574     HasAttributes = true;
575   }
576   if (MBB.isEHPad()) {
577     OS << (HasAttributes ? ", " : " (");
578     OS << "landing-pad";
579     HasAttributes = true;
580   }
581   if (MBB.getAlignment()) {
582     OS << (HasAttributes ? ", " : " (");
583     OS << "align " << MBB.getAlignment();
584     HasAttributes = true;
585   }
586   if (HasAttributes)
587     OS << ")";
588   OS << ":\n";
589 
590   bool HasLineAttributes = false;
591   // Print the successors
592   bool canPredictProbs = canPredictBranchProbabilities(MBB);
593   // Even if the list of successors is empty, if we cannot guess it,
594   // we need to print it to tell the parser that the list is empty.
595   // This is needed, because MI model unreachable as empty blocks
596   // with an empty successor list. If the parser would see that
597   // without the successor list, it would guess the code would
598   // fallthrough.
599   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
600       !canPredictSuccessors(MBB)) {
601     OS.indent(2) << "successors: ";
602     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
603       if (I != MBB.succ_begin())
604         OS << ", ";
605       OS << printMBBReference(**I);
606       if (!SimplifyMIR || !canPredictProbs)
607         OS << '('
608            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
609            << ')';
610     }
611     OS << "\n";
612     HasLineAttributes = true;
613   }
614 
615   // Print the live in registers.
616   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
617   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
618     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
619     OS.indent(2) << "liveins: ";
620     bool First = true;
621     for (const auto &LI : MBB.liveins()) {
622       if (!First)
623         OS << ", ";
624       First = false;
625       OS << printReg(LI.PhysReg, &TRI);
626       if (!LI.LaneMask.all())
627         OS << ":0x" << PrintLaneMask(LI.LaneMask);
628     }
629     OS << "\n";
630     HasLineAttributes = true;
631   }
632 
633   if (HasLineAttributes)
634     OS << "\n";
635   bool IsInBundle = false;
636   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
637     const MachineInstr &MI = *I;
638     if (IsInBundle && !MI.isInsideBundle()) {
639       OS.indent(2) << "}\n";
640       IsInBundle = false;
641     }
642     OS.indent(IsInBundle ? 4 : 2);
643     print(MI);
644     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
645       OS << " {";
646       IsInBundle = true;
647     }
648     OS << "\n";
649   }
650   if (IsInBundle)
651     OS.indent(2) << "}\n";
652 }
653 
654 void MIPrinter::print(const MachineInstr &MI) {
655   const auto *MF = MI.getMF();
656   const auto &MRI = MF->getRegInfo();
657   const auto &SubTarget = MF->getSubtarget();
658   const auto *TRI = SubTarget.getRegisterInfo();
659   assert(TRI && "Expected target register info");
660   const auto *TII = SubTarget.getInstrInfo();
661   assert(TII && "Expected target instruction info");
662   if (MI.isCFIInstruction())
663     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
664 
665   SmallBitVector PrintedTypes(8);
666   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
667   unsigned I = 0, E = MI.getNumOperands();
668   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
669          !MI.getOperand(I).isImplicit();
670        ++I) {
671     if (I)
672       OS << ", ";
673     print(MI, I, TRI, ShouldPrintRegisterTies,
674           MI.getTypeToPrint(I, PrintedTypes, MRI),
675           /*PrintDef=*/false);
676   }
677 
678   if (I)
679     OS << " = ";
680   if (MI.getFlag(MachineInstr::FrameSetup))
681     OS << "frame-setup ";
682   if (MI.getFlag(MachineInstr::FrameDestroy))
683     OS << "frame-destroy ";
684   if (MI.getFlag(MachineInstr::FmNoNans))
685     OS << "nnan ";
686   if (MI.getFlag(MachineInstr::FmNoInfs))
687     OS << "ninf ";
688   if (MI.getFlag(MachineInstr::FmNsz))
689     OS << "nsz ";
690   if (MI.getFlag(MachineInstr::FmArcp))
691     OS << "arcp ";
692   if (MI.getFlag(MachineInstr::FmContract))
693     OS << "contract ";
694   if (MI.getFlag(MachineInstr::FmAfn))
695     OS << "afn ";
696   if (MI.getFlag(MachineInstr::FmReassoc))
697     OS << "reassoc ";
698   if (MI.getFlag(MachineInstr::NoUWrap))
699     OS << "nuw ";
700   if (MI.getFlag(MachineInstr::NoSWrap))
701     OS << "nsw ";
702   if (MI.getFlag(MachineInstr::IsExact))
703     OS << "exact ";
704 
705   OS << TII->getName(MI.getOpcode());
706   if (I < E)
707     OS << ' ';
708 
709   bool NeedComma = false;
710   for (; I < E; ++I) {
711     if (NeedComma)
712       OS << ", ";
713     print(MI, I, TRI, ShouldPrintRegisterTies,
714           MI.getTypeToPrint(I, PrintedTypes, MRI));
715     NeedComma = true;
716   }
717 
718   // Print any optional symbols attached to this instruction as-if they were
719   // operands.
720   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
721     if (NeedComma)
722       OS << ',';
723     OS << " pre-instr-symbol ";
724     MachineOperand::printSymbol(OS, *PreInstrSymbol);
725     NeedComma = true;
726   }
727   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
728     if (NeedComma)
729       OS << ',';
730     OS << " post-instr-symbol ";
731     MachineOperand::printSymbol(OS, *PostInstrSymbol);
732     NeedComma = true;
733   }
734 
735   if (const DebugLoc &DL = MI.getDebugLoc()) {
736     if (NeedComma)
737       OS << ',';
738     OS << " debug-location ";
739     DL->printAsOperand(OS, MST);
740   }
741 
742   if (!MI.memoperands_empty()) {
743     OS << " :: ";
744     const LLVMContext &Context = MF->getFunction().getContext();
745     const MachineFrameInfo &MFI = MF->getFrameInfo();
746     bool NeedComma = false;
747     for (const auto *Op : MI.memoperands()) {
748       if (NeedComma)
749         OS << ", ";
750       Op->print(OS, MST, SSNs, Context, &MFI, TII);
751       NeedComma = true;
752     }
753   }
754 }
755 
756 void MIPrinter::printStackObjectReference(int FrameIndex) {
757   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
758   assert(ObjectInfo != StackObjectOperandMapping.end() &&
759          "Invalid frame index");
760   const FrameIndexOperand &Operand = ObjectInfo->second;
761   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
762                                             Operand.Name);
763 }
764 
765 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
766                       const TargetRegisterInfo *TRI,
767                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
768                       bool PrintDef) {
769   const MachineOperand &Op = MI.getOperand(OpIdx);
770   switch (Op.getType()) {
771   case MachineOperand::MO_Immediate:
772     if (MI.isOperandSubregIdx(OpIdx)) {
773       MachineOperand::printTargetFlags(OS, Op);
774       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
775       break;
776     }
777     LLVM_FALLTHROUGH;
778   case MachineOperand::MO_Register:
779   case MachineOperand::MO_CImmediate:
780   case MachineOperand::MO_FPImmediate:
781   case MachineOperand::MO_MachineBasicBlock:
782   case MachineOperand::MO_ConstantPoolIndex:
783   case MachineOperand::MO_TargetIndex:
784   case MachineOperand::MO_JumpTableIndex:
785   case MachineOperand::MO_ExternalSymbol:
786   case MachineOperand::MO_GlobalAddress:
787   case MachineOperand::MO_RegisterLiveOut:
788   case MachineOperand::MO_Metadata:
789   case MachineOperand::MO_MCSymbol:
790   case MachineOperand::MO_CFIIndex:
791   case MachineOperand::MO_IntrinsicID:
792   case MachineOperand::MO_Predicate:
793   case MachineOperand::MO_BlockAddress: {
794     unsigned TiedOperandIdx = 0;
795     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
796       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
797     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
798     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
799              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
800     break;
801   }
802   case MachineOperand::MO_FrameIndex:
803     printStackObjectReference(Op.getIndex());
804     break;
805   case MachineOperand::MO_RegisterMask: {
806     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
807     if (RegMaskInfo != RegisterMaskIds.end())
808       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
809     else
810       printCustomRegMask(Op.getRegMask(), OS, TRI);
811     break;
812   }
813   }
814 }
815 
816 void llvm::printMIR(raw_ostream &OS, const Module &M) {
817   yaml::Output Out(OS);
818   Out << const_cast<Module &>(M);
819 }
820 
821 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
822   MIRPrinter Printer(OS);
823   Printer.print(MF);
824 }
825