1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 
34 /// This class prints out the machine functions using the MIR serialization
35 /// format.
36 class MIRPrinter {
37   raw_ostream &OS;
38   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
39 
40 public:
41   MIRPrinter(raw_ostream &OS) : OS(OS) {}
42 
43   void print(const MachineFunction &MF);
44 
45   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
46                const TargetRegisterInfo *TRI);
47   void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
48   void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
49                const MachineBasicBlock &MBB);
50   void convertStackObjects(yaml::MachineFunction &MF,
51                            const MachineFrameInfo &MFI);
52 
53 private:
54   void initRegisterMaskIds(const MachineFunction &MF);
55 };
56 
57 /// This class prints out the machine instructions using the MIR serialization
58 /// format.
59 class MIPrinter {
60   raw_ostream &OS;
61   ModuleSlotTracker &MST;
62   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
63 
64 public:
65   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
66             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
67       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
68 
69   void print(const MachineInstr &MI);
70   void printMBBReference(const MachineBasicBlock &MBB);
71   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
72 };
73 
74 } // end anonymous namespace
75 
76 namespace llvm {
77 namespace yaml {
78 
79 /// This struct serializes the LLVM IR module.
80 template <> struct BlockScalarTraits<Module> {
81   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
82     Mod.print(OS, nullptr);
83   }
84   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
85     llvm_unreachable("LLVM Module is supposed to be parsed separately");
86     return "";
87   }
88 };
89 
90 } // end namespace yaml
91 } // end namespace llvm
92 
93 void MIRPrinter::print(const MachineFunction &MF) {
94   initRegisterMaskIds(MF);
95 
96   yaml::MachineFunction YamlMF;
97   YamlMF.Name = MF.getName();
98   YamlMF.Alignment = MF.getAlignment();
99   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
100   YamlMF.HasInlineAsm = MF.hasInlineAsm();
101   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
102   convert(YamlMF.FrameInfo, *MF.getFrameInfo());
103   convertStackObjects(YamlMF, *MF.getFrameInfo());
104 
105   int I = 0;
106   ModuleSlotTracker MST(MF.getFunction()->getParent());
107   for (const auto &MBB : MF) {
108     // TODO: Allow printing of non sequentially numbered MBBs.
109     // This is currently needed as the basic block references get their index
110     // from MBB.getNumber(), thus it should be sequential so that the parser can
111     // map back to the correct MBBs when parsing the output.
112     assert(MBB.getNumber() == I++ &&
113            "Can't print MBBs that aren't sequentially numbered");
114     (void)I;
115     yaml::MachineBasicBlock YamlMBB;
116     convert(MST, YamlMBB, MBB);
117     YamlMF.BasicBlocks.push_back(YamlMBB);
118   }
119   yaml::Output Out(OS);
120   Out << YamlMF;
121 }
122 
123 void MIRPrinter::convert(yaml::MachineFunction &MF,
124                          const MachineRegisterInfo &RegInfo,
125                          const TargetRegisterInfo *TRI) {
126   MF.IsSSA = RegInfo.isSSA();
127   MF.TracksRegLiveness = RegInfo.tracksLiveness();
128   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
129 
130   // Print the virtual register definitions.
131   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
132     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
133     yaml::VirtualRegisterDefinition VReg;
134     VReg.ID = I;
135     VReg.Class =
136         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
137     MF.VirtualRegisters.push_back(VReg);
138   }
139 }
140 
141 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
142                          const MachineFrameInfo &MFI) {
143   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
144   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
145   YamlMFI.HasStackMap = MFI.hasStackMap();
146   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
147   YamlMFI.StackSize = MFI.getStackSize();
148   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
149   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
150   YamlMFI.AdjustsStack = MFI.adjustsStack();
151   YamlMFI.HasCalls = MFI.hasCalls();
152   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
153   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
154   YamlMFI.HasVAStart = MFI.hasVAStart();
155   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
156 }
157 
158 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
159                                      const MachineFrameInfo &MFI) {
160   // Process fixed stack objects.
161   unsigned ID = 0;
162   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
163     if (MFI.isDeadObjectIndex(I))
164       continue;
165 
166     yaml::FixedMachineStackObject YamlObject;
167     YamlObject.ID = ID++;
168     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
169                           ? yaml::FixedMachineStackObject::SpillSlot
170                           : yaml::FixedMachineStackObject::DefaultType;
171     YamlObject.Offset = MFI.getObjectOffset(I);
172     YamlObject.Size = MFI.getObjectSize(I);
173     YamlObject.Alignment = MFI.getObjectAlignment(I);
174     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
175     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
176     MF.FixedStackObjects.push_back(YamlObject);
177     // TODO: Store the mapping between fixed object IDs and object indices to
178     // print the fixed stack object references correctly.
179   }
180 
181   // Process ordinary stack objects.
182   ID = 0;
183   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
184     if (MFI.isDeadObjectIndex(I))
185       continue;
186 
187     yaml::MachineStackObject YamlObject;
188     YamlObject.ID = ID++;
189     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
190                           ? yaml::MachineStackObject::SpillSlot
191                           : yaml::MachineStackObject::DefaultType;
192     YamlObject.Offset = MFI.getObjectOffset(I);
193     YamlObject.Size = MFI.getObjectSize(I);
194     YamlObject.Alignment = MFI.getObjectAlignment(I);
195 
196     MF.StackObjects.push_back(YamlObject);
197     // TODO: Store the mapping between object IDs and object indices to print
198     // the stack object references correctly.
199   }
200 }
201 
202 void MIRPrinter::convert(ModuleSlotTracker &MST,
203                          yaml::MachineBasicBlock &YamlMBB,
204                          const MachineBasicBlock &MBB) {
205   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
206   YamlMBB.ID = (unsigned)MBB.getNumber();
207   // TODO: Serialize unnamed BB references.
208   if (const auto *BB = MBB.getBasicBlock())
209     YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
210   else
211     YamlMBB.Name.Value = "";
212   YamlMBB.Alignment = MBB.getAlignment();
213   YamlMBB.AddressTaken = MBB.hasAddressTaken();
214   YamlMBB.IsLandingPad = MBB.isLandingPad();
215   for (const auto *SuccMBB : MBB.successors()) {
216     std::string Str;
217     raw_string_ostream StrOS(Str);
218     MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
219     YamlMBB.Successors.push_back(StrOS.str());
220   }
221 
222   // Print the machine instructions.
223   YamlMBB.Instructions.reserve(MBB.size());
224   std::string Str;
225   for (const auto &MI : MBB) {
226     raw_string_ostream StrOS(Str);
227     MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
228     YamlMBB.Instructions.push_back(StrOS.str());
229     Str.clear();
230   }
231 }
232 
233 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
234   const auto *TRI = MF.getSubtarget().getRegisterInfo();
235   unsigned I = 0;
236   for (const uint32_t *Mask : TRI->getRegMasks())
237     RegisterMaskIds.insert(std::make_pair(Mask, I++));
238 }
239 
240 void MIPrinter::print(const MachineInstr &MI) {
241   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
242   const auto *TRI = SubTarget.getRegisterInfo();
243   assert(TRI && "Expected target register info");
244   const auto *TII = SubTarget.getInstrInfo();
245   assert(TII && "Expected target instruction info");
246 
247   unsigned I = 0, E = MI.getNumOperands();
248   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
249          !MI.getOperand(I).isImplicit();
250        ++I) {
251     if (I)
252       OS << ", ";
253     print(MI.getOperand(I), TRI);
254   }
255 
256   if (I)
257     OS << " = ";
258   OS << TII->getName(MI.getOpcode());
259   // TODO: Print the instruction flags, machine mem operands.
260   if (I < E)
261     OS << ' ';
262 
263   bool NeedComma = false;
264   for (; I < E; ++I) {
265     if (NeedComma)
266       OS << ", ";
267     print(MI.getOperand(I), TRI);
268     NeedComma = true;
269   }
270 }
271 
272 static void printReg(unsigned Reg, raw_ostream &OS,
273                      const TargetRegisterInfo *TRI) {
274   // TODO: Print Stack Slots.
275   if (!Reg)
276     OS << '_';
277   else if (TargetRegisterInfo::isVirtualRegister(Reg))
278     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
279   else if (Reg < TRI->getNumRegs())
280     OS << '%' << StringRef(TRI->getName(Reg)).lower();
281   else
282     llvm_unreachable("Can't print this kind of register yet");
283 }
284 
285 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
286   OS << "%bb." << MBB.getNumber();
287   if (const auto *BB = MBB.getBasicBlock()) {
288     if (BB->hasName())
289       OS << '.' << BB->getName();
290   }
291 }
292 
293 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
294   switch (Op.getType()) {
295   case MachineOperand::MO_Register:
296     // TODO: Print the other register flags.
297     if (Op.isImplicit())
298       OS << (Op.isDef() ? "implicit-def " : "implicit ");
299     if (Op.isDead())
300       OS << "dead ";
301     if (Op.isKill())
302       OS << "killed ";
303     if (Op.isUndef())
304       OS << "undef ";
305     printReg(Op.getReg(), OS, TRI);
306     // TODO: Print sub register.
307     break;
308   case MachineOperand::MO_Immediate:
309     OS << Op.getImm();
310     break;
311   case MachineOperand::MO_MachineBasicBlock:
312     printMBBReference(*Op.getMBB());
313     break;
314   case MachineOperand::MO_GlobalAddress:
315     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
316     // TODO: Print offset and target flags.
317     break;
318   case MachineOperand::MO_RegisterMask: {
319     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
320     if (RegMaskInfo != RegisterMaskIds.end())
321       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
322     else
323       llvm_unreachable("Can't print this machine register mask yet.");
324     break;
325   }
326   default:
327     // TODO: Print the other machine operands.
328     llvm_unreachable("Can't print this machine operand at the moment");
329   }
330 }
331 
332 void llvm::printMIR(raw_ostream &OS, const Module &M) {
333   yaml::Output Out(OS);
334   Out << const_cast<Module &>(M);
335 }
336 
337 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
338   MIRPrinter Printer(OS);
339   Printer.print(MF);
340 }
341