1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/Support/MemoryBuffer.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/YAMLTraits.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
35 
36 using namespace llvm;
37 
38 namespace {
39 
40 /// This structure describes how to print out stack object references.
41 struct FrameIndexOperand {
42   std::string Name;
43   unsigned ID;
44   bool IsFixed;
45 
46   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
47       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
48 
49   /// Return an ordinary stack object reference.
50   static FrameIndexOperand create(StringRef Name, unsigned ID) {
51     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
52   }
53 
54   /// Return a fixed stack object reference.
55   static FrameIndexOperand createFixed(unsigned ID) {
56     return FrameIndexOperand("", ID, /*IsFixed=*/true);
57   }
58 };
59 
60 } // end anonymous namespace
61 
62 namespace llvm {
63 
64 /// This class prints out the machine functions using the MIR serialization
65 /// format.
66 class MIRPrinter {
67   raw_ostream &OS;
68   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
69   /// Maps from stack object indices to operand indices which will be used when
70   /// printing frame index machine operands.
71   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
72 
73 public:
74   MIRPrinter(raw_ostream &OS) : OS(OS) {}
75 
76   void print(const MachineFunction &MF);
77 
78   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
79                const TargetRegisterInfo *TRI);
80   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
81                const MachineFrameInfo &MFI);
82   void convert(yaml::MachineFunction &MF,
83                const MachineConstantPool &ConstantPool);
84   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
85                const MachineJumpTableInfo &JTI);
86   void convertStackObjects(yaml::MachineFunction &MF,
87                            const MachineFrameInfo &MFI,
88                            const TargetRegisterInfo *TRI);
89 
90 private:
91   void initRegisterMaskIds(const MachineFunction &MF);
92 };
93 
94 /// This class prints out the machine instructions using the MIR serialization
95 /// format.
96 class MIPrinter {
97   raw_ostream &OS;
98   ModuleSlotTracker &MST;
99   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
100   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
101 
102 public:
103   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
104             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
105             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
106       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
107         StackObjectOperandMapping(StackObjectOperandMapping) {}
108 
109   void print(const MachineBasicBlock &MBB);
110 
111   void print(const MachineInstr &MI);
112   void printMBBReference(const MachineBasicBlock &MBB);
113   void printIRBlockReference(const BasicBlock &BB);
114   void printIRValueReference(const Value &V);
115   void printStackObjectReference(int FrameIndex);
116   void printOffset(int64_t Offset);
117   void printTargetFlags(const MachineOperand &Op);
118   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
119   void print(const MachineMemOperand &Op);
120 
121   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
122 };
123 
124 } // end namespace llvm
125 
126 namespace llvm {
127 namespace yaml {
128 
129 /// This struct serializes the LLVM IR module.
130 template <> struct BlockScalarTraits<Module> {
131   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
132     Mod.print(OS, nullptr);
133   }
134   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
135     llvm_unreachable("LLVM Module is supposed to be parsed separately");
136     return "";
137   }
138 };
139 
140 } // end namespace yaml
141 } // end namespace llvm
142 
143 static void printReg(unsigned Reg, raw_ostream &OS,
144                      const TargetRegisterInfo *TRI) {
145   // TODO: Print Stack Slots.
146   if (!Reg)
147     OS << '_';
148   else if (TargetRegisterInfo::isVirtualRegister(Reg))
149     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
150   else if (Reg < TRI->getNumRegs())
151     OS << '%' << StringRef(TRI->getName(Reg)).lower();
152   else
153     llvm_unreachable("Can't print this kind of register yet");
154 }
155 
156 static void printReg(unsigned Reg, yaml::StringValue &Dest,
157                      const TargetRegisterInfo *TRI) {
158   raw_string_ostream OS(Dest.Value);
159   printReg(Reg, OS, TRI);
160 }
161 
162 void MIRPrinter::print(const MachineFunction &MF) {
163   initRegisterMaskIds(MF);
164 
165   yaml::MachineFunction YamlMF;
166   YamlMF.Name = MF.getName();
167   YamlMF.Alignment = MF.getAlignment();
168   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
169   YamlMF.HasInlineAsm = MF.hasInlineAsm();
170   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
171   ModuleSlotTracker MST(MF.getFunction()->getParent());
172   MST.incorporateFunction(*MF.getFunction());
173   convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
174   convertStackObjects(YamlMF, *MF.getFrameInfo(),
175                       MF.getSubtarget().getRegisterInfo());
176   if (const auto *ConstantPool = MF.getConstantPool())
177     convert(YamlMF, *ConstantPool);
178   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
179     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
180   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
181   bool IsNewlineNeeded = false;
182   for (const auto &MBB : MF) {
183     if (IsNewlineNeeded)
184       StrOS << "\n";
185     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
186         .print(MBB);
187     IsNewlineNeeded = true;
188   }
189   StrOS.flush();
190   yaml::Output Out(OS);
191   Out << YamlMF;
192 }
193 
194 void MIRPrinter::convert(yaml::MachineFunction &MF,
195                          const MachineRegisterInfo &RegInfo,
196                          const TargetRegisterInfo *TRI) {
197   MF.IsSSA = RegInfo.isSSA();
198   MF.TracksRegLiveness = RegInfo.tracksLiveness();
199   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
200 
201   // Print the virtual register definitions.
202   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
203     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
204     yaml::VirtualRegisterDefinition VReg;
205     VReg.ID = I;
206     VReg.Class =
207         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
208     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
209     if (PreferredReg)
210       printReg(PreferredReg, VReg.PreferredRegister, TRI);
211     MF.VirtualRegisters.push_back(VReg);
212   }
213 
214   // Print the live ins.
215   for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
216     yaml::MachineFunctionLiveIn LiveIn;
217     printReg(I->first, LiveIn.Register, TRI);
218     if (I->second)
219       printReg(I->second, LiveIn.VirtualRegister, TRI);
220     MF.LiveIns.push_back(LiveIn);
221   }
222   // The used physical register mask is printed as an inverted callee saved
223   // register mask.
224   const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
225   if (UsedPhysRegMask.none())
226     return;
227   std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
228   for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
229     if (!UsedPhysRegMask[I]) {
230       yaml::FlowStringValue Reg;
231       printReg(I, Reg, TRI);
232       CalleeSavedRegisters.push_back(Reg);
233     }
234   }
235   MF.CalleeSavedRegisters = CalleeSavedRegisters;
236 }
237 
238 void MIRPrinter::convert(ModuleSlotTracker &MST,
239                          yaml::MachineFrameInfo &YamlMFI,
240                          const MachineFrameInfo &MFI) {
241   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
242   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
243   YamlMFI.HasStackMap = MFI.hasStackMap();
244   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
245   YamlMFI.StackSize = MFI.getStackSize();
246   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
247   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
248   YamlMFI.AdjustsStack = MFI.adjustsStack();
249   YamlMFI.HasCalls = MFI.hasCalls();
250   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
251   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
252   YamlMFI.HasVAStart = MFI.hasVAStart();
253   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
254   if (MFI.getSavePoint()) {
255     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
256     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
257         .printMBBReference(*MFI.getSavePoint());
258   }
259   if (MFI.getRestorePoint()) {
260     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
261     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
262         .printMBBReference(*MFI.getRestorePoint());
263   }
264 }
265 
266 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
267                                      const MachineFrameInfo &MFI,
268                                      const TargetRegisterInfo *TRI) {
269   // Process fixed stack objects.
270   unsigned ID = 0;
271   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
272     if (MFI.isDeadObjectIndex(I))
273       continue;
274 
275     yaml::FixedMachineStackObject YamlObject;
276     YamlObject.ID = ID;
277     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
278                           ? yaml::FixedMachineStackObject::SpillSlot
279                           : yaml::FixedMachineStackObject::DefaultType;
280     YamlObject.Offset = MFI.getObjectOffset(I);
281     YamlObject.Size = MFI.getObjectSize(I);
282     YamlObject.Alignment = MFI.getObjectAlignment(I);
283     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
284     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
285     MF.FixedStackObjects.push_back(YamlObject);
286     StackObjectOperandMapping.insert(
287         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
288   }
289 
290   // Process ordinary stack objects.
291   ID = 0;
292   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
293     if (MFI.isDeadObjectIndex(I))
294       continue;
295 
296     yaml::MachineStackObject YamlObject;
297     YamlObject.ID = ID;
298     if (const auto *Alloca = MFI.getObjectAllocation(I))
299       YamlObject.Name.Value =
300           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
301     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
302                           ? yaml::MachineStackObject::SpillSlot
303                           : MFI.isVariableSizedObjectIndex(I)
304                                 ? yaml::MachineStackObject::VariableSized
305                                 : yaml::MachineStackObject::DefaultType;
306     YamlObject.Offset = MFI.getObjectOffset(I);
307     YamlObject.Size = MFI.getObjectSize(I);
308     YamlObject.Alignment = MFI.getObjectAlignment(I);
309 
310     MF.StackObjects.push_back(YamlObject);
311     StackObjectOperandMapping.insert(std::make_pair(
312         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
313   }
314 
315   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
316     yaml::StringValue Reg;
317     printReg(CSInfo.getReg(), Reg, TRI);
318     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
319     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
320            "Invalid stack object index");
321     const FrameIndexOperand &StackObject = StackObjectInfo->second;
322     if (StackObject.IsFixed)
323       MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
324     else
325       MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
326   }
327 }
328 
329 void MIRPrinter::convert(yaml::MachineFunction &MF,
330                          const MachineConstantPool &ConstantPool) {
331   unsigned ID = 0;
332   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
333     // TODO: Serialize target specific constant pool entries.
334     if (Constant.isMachineConstantPoolEntry())
335       llvm_unreachable("Can't print target specific constant pool entries yet");
336 
337     yaml::MachineConstantPoolValue YamlConstant;
338     std::string Str;
339     raw_string_ostream StrOS(Str);
340     Constant.Val.ConstVal->printAsOperand(StrOS);
341     YamlConstant.ID = ID++;
342     YamlConstant.Value = StrOS.str();
343     YamlConstant.Alignment = Constant.getAlignment();
344     MF.Constants.push_back(YamlConstant);
345   }
346 }
347 
348 void MIRPrinter::convert(ModuleSlotTracker &MST,
349                          yaml::MachineJumpTable &YamlJTI,
350                          const MachineJumpTableInfo &JTI) {
351   YamlJTI.Kind = JTI.getEntryKind();
352   unsigned ID = 0;
353   for (const auto &Table : JTI.getJumpTables()) {
354     std::string Str;
355     yaml::MachineJumpTable::Entry Entry;
356     Entry.ID = ID++;
357     for (const auto *MBB : Table.MBBs) {
358       raw_string_ostream StrOS(Str);
359       MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
360           .printMBBReference(*MBB);
361       Entry.Blocks.push_back(StrOS.str());
362       Str.clear();
363     }
364     YamlJTI.Entries.push_back(Entry);
365   }
366 }
367 
368 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
369   const auto *TRI = MF.getSubtarget().getRegisterInfo();
370   unsigned I = 0;
371   for (const uint32_t *Mask : TRI->getRegMasks())
372     RegisterMaskIds.insert(std::make_pair(Mask, I++));
373 }
374 
375 void MIPrinter::print(const MachineBasicBlock &MBB) {
376   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
377   OS << "bb." << MBB.getNumber();
378   bool HasAttributes = false;
379   if (const auto *BB = MBB.getBasicBlock()) {
380     if (BB->hasName()) {
381       OS << "." << BB->getName();
382     } else {
383       HasAttributes = true;
384       OS << " (";
385       int Slot = MST.getLocalSlot(BB);
386       if (Slot == -1)
387         OS << "<ir-block badref>";
388       else
389         OS << (Twine("%ir-block.") + Twine(Slot)).str();
390     }
391   }
392   if (MBB.hasAddressTaken()) {
393     OS << (HasAttributes ? ", " : " (");
394     OS << "address-taken";
395     HasAttributes = true;
396   }
397   if (MBB.isLandingPad()) {
398     OS << (HasAttributes ? ", " : " (");
399     OS << "landing-pad";
400     HasAttributes = true;
401   }
402   if (MBB.getAlignment()) {
403     OS << (HasAttributes ? ", " : " (");
404     OS << "align " << MBB.getAlignment();
405     HasAttributes = true;
406   }
407   if (HasAttributes)
408     OS << ")";
409   OS << ":\n";
410 
411   bool HasLineAttributes = false;
412   // Print the successors
413   if (!MBB.succ_empty()) {
414     OS.indent(2) << "successors: ";
415     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
416       if (I != MBB.succ_begin())
417         OS << ", ";
418       printMBBReference(**I);
419       if (MBB.hasSuccessorWeights())
420         OS << '(' << MBB.getSuccWeight(I) << ')';
421     }
422     OS << "\n";
423     HasLineAttributes = true;
424   }
425 
426   // Print the live in registers.
427   const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
428   assert(TRI && "Expected target register info");
429   if (!MBB.livein_empty()) {
430     OS.indent(2) << "liveins: ";
431     for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
432       if (I != MBB.livein_begin())
433         OS << ", ";
434       printReg(*I, OS, TRI);
435     }
436     OS << "\n";
437     HasLineAttributes = true;
438   }
439 
440   if (HasLineAttributes)
441     OS << "\n";
442   for (const auto &MI : MBB) {
443     OS.indent(2);
444     print(MI);
445     OS << "\n";
446   }
447 }
448 
449 void MIPrinter::print(const MachineInstr &MI) {
450   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
451   const auto *TRI = SubTarget.getRegisterInfo();
452   assert(TRI && "Expected target register info");
453   const auto *TII = SubTarget.getInstrInfo();
454   assert(TII && "Expected target instruction info");
455   if (MI.isCFIInstruction())
456     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
457 
458   unsigned I = 0, E = MI.getNumOperands();
459   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
460          !MI.getOperand(I).isImplicit();
461        ++I) {
462     if (I)
463       OS << ", ";
464     print(MI.getOperand(I), TRI);
465   }
466 
467   if (I)
468     OS << " = ";
469   if (MI.getFlag(MachineInstr::FrameSetup))
470     OS << "frame-setup ";
471   OS << TII->getName(MI.getOpcode());
472   // TODO: Print the bundling instruction flags.
473   if (I < E)
474     OS << ' ';
475 
476   bool NeedComma = false;
477   for (; I < E; ++I) {
478     if (NeedComma)
479       OS << ", ";
480     print(MI.getOperand(I), TRI);
481     NeedComma = true;
482   }
483 
484   if (MI.getDebugLoc()) {
485     if (NeedComma)
486       OS << ',';
487     OS << " debug-location ";
488     MI.getDebugLoc()->printAsOperand(OS, MST);
489   }
490 
491   if (!MI.memoperands_empty()) {
492     OS << " :: ";
493     bool NeedComma = false;
494     for (const auto *Op : MI.memoperands()) {
495       if (NeedComma)
496         OS << ", ";
497       print(*Op);
498       NeedComma = true;
499     }
500   }
501 }
502 
503 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
504   OS << "%bb." << MBB.getNumber();
505   if (const auto *BB = MBB.getBasicBlock()) {
506     if (BB->hasName())
507       OS << '.' << BB->getName();
508   }
509 }
510 
511 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
512   OS << "%ir-block.";
513   if (BB.hasName()) {
514     printLLVMNameWithoutPrefix(OS, BB.getName());
515     return;
516   }
517   const Function *F = BB.getParent();
518   int Slot;
519   if (F == MST.getCurrentFunction()) {
520     Slot = MST.getLocalSlot(&BB);
521   } else {
522     ModuleSlotTracker CustomMST(F->getParent(),
523                                 /*ShouldInitializeAllMetadata=*/false);
524     CustomMST.incorporateFunction(*F);
525     Slot = CustomMST.getLocalSlot(&BB);
526   }
527   if (Slot == -1)
528     OS << "<badref>";
529   else
530     OS << Slot;
531 }
532 
533 void MIPrinter::printIRValueReference(const Value &V) {
534   OS << "%ir.";
535   if (V.hasName()) {
536     printLLVMNameWithoutPrefix(OS, V.getName());
537     return;
538   }
539   // TODO: Serialize the unnamed IR value references.
540   OS << "<unserializable ir value>";
541 }
542 
543 void MIPrinter::printStackObjectReference(int FrameIndex) {
544   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
545   assert(ObjectInfo != StackObjectOperandMapping.end() &&
546          "Invalid frame index");
547   const FrameIndexOperand &Operand = ObjectInfo->second;
548   if (Operand.IsFixed) {
549     OS << "%fixed-stack." << Operand.ID;
550     return;
551   }
552   OS << "%stack." << Operand.ID;
553   if (!Operand.Name.empty())
554     OS << '.' << Operand.Name;
555 }
556 
557 void MIPrinter::printOffset(int64_t Offset) {
558   if (Offset == 0)
559     return;
560   if (Offset < 0) {
561     OS << " - " << -Offset;
562     return;
563   }
564   OS << " + " << Offset;
565 }
566 
567 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
568   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
569   for (const auto &I : Flags) {
570     if (I.first == TF) {
571       return I.second;
572     }
573   }
574   return nullptr;
575 }
576 
577 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
578   if (!Op.getTargetFlags())
579     return;
580   const auto *TII =
581       Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
582   assert(TII && "expected instruction info");
583   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
584   OS << "target-flags(";
585   if (const auto *Name = getTargetFlagName(TII, Flags.first))
586     OS << Name;
587   else
588     OS << "<unknown target flag>";
589   // TODO: Print the target's bit flags.
590   OS << ") ";
591 }
592 
593 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
594   const auto *TII = MF.getSubtarget().getInstrInfo();
595   assert(TII && "expected instruction info");
596   auto Indices = TII->getSerializableTargetIndices();
597   for (const auto &I : Indices) {
598     if (I.first == Index) {
599       return I.second;
600     }
601   }
602   return nullptr;
603 }
604 
605 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
606   printTargetFlags(Op);
607   switch (Op.getType()) {
608   case MachineOperand::MO_Register:
609     // TODO: Print the other register flags.
610     if (Op.isImplicit())
611       OS << (Op.isDef() ? "implicit-def " : "implicit ");
612     if (Op.isDead())
613       OS << "dead ";
614     if (Op.isKill())
615       OS << "killed ";
616     if (Op.isUndef())
617       OS << "undef ";
618     if (Op.isEarlyClobber())
619       OS << "early-clobber ";
620     if (Op.isDebug())
621       OS << "debug-use ";
622     printReg(Op.getReg(), OS, TRI);
623     // Print the sub register.
624     if (Op.getSubReg() != 0)
625       OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
626     break;
627   case MachineOperand::MO_Immediate:
628     OS << Op.getImm();
629     break;
630   case MachineOperand::MO_CImmediate:
631     Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
632     break;
633   case MachineOperand::MO_FPImmediate:
634     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
635     break;
636   case MachineOperand::MO_MachineBasicBlock:
637     printMBBReference(*Op.getMBB());
638     break;
639   case MachineOperand::MO_FrameIndex:
640     printStackObjectReference(Op.getIndex());
641     break;
642   case MachineOperand::MO_ConstantPoolIndex:
643     OS << "%const." << Op.getIndex();
644     printOffset(Op.getOffset());
645     break;
646   case MachineOperand::MO_TargetIndex: {
647     OS << "target-index(";
648     if (const auto *Name = getTargetIndexName(
649             *Op.getParent()->getParent()->getParent(), Op.getIndex()))
650       OS << Name;
651     else
652       OS << "<unknown>";
653     OS << ')';
654     printOffset(Op.getOffset());
655     break;
656   }
657   case MachineOperand::MO_JumpTableIndex:
658     OS << "%jump-table." << Op.getIndex();
659     break;
660   case MachineOperand::MO_ExternalSymbol:
661     OS << '$';
662     printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
663     printOffset(Op.getOffset());
664     break;
665   case MachineOperand::MO_GlobalAddress:
666     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
667     printOffset(Op.getOffset());
668     break;
669   case MachineOperand::MO_BlockAddress:
670     OS << "blockaddress(";
671     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
672                                                         MST);
673     OS << ", ";
674     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
675     OS << ')';
676     printOffset(Op.getOffset());
677     break;
678   case MachineOperand::MO_RegisterMask: {
679     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
680     if (RegMaskInfo != RegisterMaskIds.end())
681       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
682     else
683       llvm_unreachable("Can't print this machine register mask yet.");
684     break;
685   }
686   case MachineOperand::MO_RegisterLiveOut: {
687     const uint32_t *RegMask = Op.getRegLiveOut();
688     OS << "liveout(";
689     bool IsCommaNeeded = false;
690     for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
691       if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
692         if (IsCommaNeeded)
693           OS << ", ";
694         printReg(Reg, OS, TRI);
695         IsCommaNeeded = true;
696       }
697     }
698     OS << ")";
699     break;
700   }
701   case MachineOperand::MO_Metadata:
702     Op.getMetadata()->printAsOperand(OS, MST);
703     break;
704   case MachineOperand::MO_CFIIndex: {
705     const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
706     print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
707     break;
708   }
709   default:
710     // TODO: Print the other machine operands.
711     llvm_unreachable("Can't print this machine operand at the moment");
712   }
713 }
714 
715 void MIPrinter::print(const MachineMemOperand &Op) {
716   OS << '(';
717   // TODO: Print operand's target specific flags.
718   if (Op.isVolatile())
719     OS << "volatile ";
720   if (Op.isNonTemporal())
721     OS << "non-temporal ";
722   if (Op.isInvariant())
723     OS << "invariant ";
724   if (Op.isLoad())
725     OS << "load ";
726   else {
727     assert(Op.isStore() && "Non load machine operand must be a store");
728     OS << "store ";
729   }
730   OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
731   if (const Value *Val = Op.getValue()) {
732     printIRValueReference(*Val);
733   } else {
734     const PseudoSourceValue *PVal = Op.getPseudoValue();
735     assert(PVal && "Expected a pseudo source value");
736     switch (PVal->kind()) {
737     case PseudoSourceValue::Stack:
738       OS << "stack";
739       break;
740     case PseudoSourceValue::GOT:
741       OS << "got";
742       break;
743     case PseudoSourceValue::JumpTable:
744       OS << "jump-table";
745       break;
746     case PseudoSourceValue::ConstantPool:
747       OS << "constant-pool";
748       break;
749     case PseudoSourceValue::FixedStack:
750       printStackObjectReference(
751           cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
752       break;
753     default:
754       // TODO: Print the other pseudo source values.
755       OS << "<unserializable pseudo value>";
756       break;
757     }
758   }
759   printOffset(Op.getOffset());
760   if (Op.getBaseAlignment() != Op.getSize())
761     OS << ", align " << Op.getBaseAlignment();
762   // TODO: Print the metadata attributes.
763   OS << ')';
764 }
765 
766 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
767                              const TargetRegisterInfo *TRI) {
768   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
769   if (Reg == -1) {
770     OS << "<badreg>";
771     return;
772   }
773   printReg(Reg, OS, TRI);
774 }
775 
776 void MIPrinter::print(const MCCFIInstruction &CFI,
777                       const TargetRegisterInfo *TRI) {
778   switch (CFI.getOperation()) {
779   case MCCFIInstruction::OpOffset:
780     OS << ".cfi_offset ";
781     if (CFI.getLabel())
782       OS << "<mcsymbol> ";
783     printCFIRegister(CFI.getRegister(), OS, TRI);
784     OS << ", " << CFI.getOffset();
785     break;
786   case MCCFIInstruction::OpDefCfaRegister:
787     OS << ".cfi_def_cfa_register ";
788     if (CFI.getLabel())
789       OS << "<mcsymbol> ";
790     printCFIRegister(CFI.getRegister(), OS, TRI);
791     break;
792   case MCCFIInstruction::OpDefCfaOffset:
793     OS << ".cfi_def_cfa_offset ";
794     if (CFI.getLabel())
795       OS << "<mcsymbol> ";
796     OS << CFI.getOffset();
797     break;
798   case MCCFIInstruction::OpDefCfa:
799     OS << ".cfi_def_cfa ";
800     if (CFI.getLabel())
801       OS << "<mcsymbol> ";
802     printCFIRegister(CFI.getRegister(), OS, TRI);
803     OS << ", " << CFI.getOffset();
804     break;
805   default:
806     // TODO: Print the other CFI Operations.
807     OS << "<unserializable cfi operation>";
808     break;
809   }
810 }
811 
812 void llvm::printMIR(raw_ostream &OS, const Module &M) {
813   yaml::Output Out(OS);
814   Out << const_cast<Module &>(M);
815 }
816 
817 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
818   MIRPrinter Printer(OS);
819   Printer.print(MF);
820 }
821