1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/MIRYamlMapping.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCContext.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132 
133 private:
134   void initRegisterMaskIds(const MachineFunction &MF);
135 };
136 
137 /// This class prints out the machine instructions using the MIR serialization
138 /// format.
139 class MIPrinter {
140   raw_ostream &OS;
141   ModuleSlotTracker &MST;
142   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144   /// Synchronization scope names registered with LLVMContext.
145   SmallVector<StringRef, 8> SSNs;
146 
147   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
149 
150 public:
151   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155         StackObjectOperandMapping(StackObjectOperandMapping) {}
156 
157   void print(const MachineBasicBlock &MBB);
158 
159   void print(const MachineInstr &MI);
160   void printStackObjectReference(int FrameIndex);
161   void print(const MachineInstr &MI, unsigned OpIdx,
162              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
163              LLT TypeToPrint, bool PrintDef = true);
164 };
165 
166 } // end namespace llvm
167 
168 namespace llvm {
169 namespace yaml {
170 
171 /// This struct serializes the LLVM IR module.
172 template <> struct BlockScalarTraits<Module> {
173   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
174     Mod.print(OS, nullptr);
175   }
176 
177   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
178     llvm_unreachable("LLVM Module is supposed to be parsed separately");
179     return "";
180   }
181 };
182 
183 } // end namespace yaml
184 } // end namespace llvm
185 
186 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
187                         const TargetRegisterInfo *TRI) {
188   raw_string_ostream OS(Dest.Value);
189   OS << printReg(Reg, TRI);
190 }
191 
192 void MIRPrinter::print(const MachineFunction &MF) {
193   initRegisterMaskIds(MF);
194 
195   yaml::MachineFunction YamlMF;
196   YamlMF.Name = MF.getName();
197   YamlMF.Alignment = MF.getAlignment();
198   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
199 
200   YamlMF.Legalized = MF.getProperties().hasProperty(
201       MachineFunctionProperties::Property::Legalized);
202   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
203       MachineFunctionProperties::Property::RegBankSelected);
204   YamlMF.Selected = MF.getProperties().hasProperty(
205       MachineFunctionProperties::Property::Selected);
206   YamlMF.FailedISel = MF.getProperties().hasProperty(
207       MachineFunctionProperties::Property::FailedISel);
208 
209   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
210   ModuleSlotTracker MST(MF.getFunction().getParent());
211   MST.incorporateFunction(MF.getFunction());
212   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
213   convertStackObjects(YamlMF, MF, MST);
214   if (const auto *ConstantPool = MF.getConstantPool())
215     convert(YamlMF, *ConstantPool);
216   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
217     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
218   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
219   bool IsNewlineNeeded = false;
220   for (const auto &MBB : MF) {
221     if (IsNewlineNeeded)
222       StrOS << "\n";
223     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
224         .print(MBB);
225     IsNewlineNeeded = true;
226   }
227   StrOS.flush();
228   yaml::Output Out(OS);
229   if (!SimplifyMIR)
230       Out.setWriteDefaultValues(true);
231   Out << YamlMF;
232 }
233 
234 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
235                                const TargetRegisterInfo *TRI) {
236   assert(RegMask && "Can't print an empty register mask");
237   OS << StringRef("CustomRegMask(");
238 
239   bool IsRegInRegMaskFound = false;
240   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
241     // Check whether the register is asserted in regmask.
242     if (RegMask[I / 32] & (1u << (I % 32))) {
243       if (IsRegInRegMaskFound)
244         OS << ',';
245       OS << printReg(I, TRI);
246       IsRegInRegMaskFound = true;
247     }
248   }
249 
250   OS << ')';
251 }
252 
253 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
254                                 const MachineRegisterInfo &RegInfo,
255                                 const TargetRegisterInfo *TRI) {
256   raw_string_ostream OS(Dest.Value);
257   OS << printRegClassOrBank(Reg, RegInfo, TRI);
258 }
259 
260 template <typename T>
261 static void
262 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
263                         T &Object, ModuleSlotTracker &MST) {
264   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
265                                         &Object.DebugExpr.Value,
266                                         &Object.DebugLoc.Value}};
267   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
268                                         DebugVar.Expr,
269                                         DebugVar.Loc}};
270   for (unsigned i = 0; i < 3; ++i) {
271     raw_string_ostream StrOS(*Outputs[i]);
272     Metas[i]->printAsOperand(StrOS, MST);
273   }
274 }
275 
276 void MIRPrinter::convert(yaml::MachineFunction &MF,
277                          const MachineRegisterInfo &RegInfo,
278                          const TargetRegisterInfo *TRI) {
279   MF.TracksRegLiveness = RegInfo.tracksLiveness();
280 
281   // Print the virtual register definitions.
282   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
283     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
284     yaml::VirtualRegisterDefinition VReg;
285     VReg.ID = I;
286     if (RegInfo.getVRegName(Reg) != "")
287       continue;
288     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
289     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
290     if (PreferredReg)
291       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
292     MF.VirtualRegisters.push_back(VReg);
293   }
294 
295   // Print the live ins.
296   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
297     yaml::MachineFunctionLiveIn LiveIn;
298     printRegMIR(LI.first, LiveIn.Register, TRI);
299     if (LI.second)
300       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
301     MF.LiveIns.push_back(LiveIn);
302   }
303 
304   // Prints the callee saved registers.
305   if (RegInfo.isUpdatedCSRsInitialized()) {
306     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
307     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
308     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
309       yaml::FlowStringValue Reg;
310       printRegMIR(*I, Reg, TRI);
311       CalleeSavedRegisters.push_back(Reg);
312     }
313     MF.CalleeSavedRegisters = CalleeSavedRegisters;
314   }
315 }
316 
317 void MIRPrinter::convert(ModuleSlotTracker &MST,
318                          yaml::MachineFrameInfo &YamlMFI,
319                          const MachineFrameInfo &MFI) {
320   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
321   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
322   YamlMFI.HasStackMap = MFI.hasStackMap();
323   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
324   YamlMFI.StackSize = MFI.getStackSize();
325   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
326   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
327   YamlMFI.AdjustsStack = MFI.adjustsStack();
328   YamlMFI.HasCalls = MFI.hasCalls();
329   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
330     ? MFI.getMaxCallFrameSize() : ~0u;
331   YamlMFI.CVBytesOfCalleeSavedRegisters =
332       MFI.getCVBytesOfCalleeSavedRegisters();
333   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
334   YamlMFI.HasVAStart = MFI.hasVAStart();
335   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
336   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
337   if (MFI.getSavePoint()) {
338     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
339     StrOS << printMBBReference(*MFI.getSavePoint());
340   }
341   if (MFI.getRestorePoint()) {
342     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
343     StrOS << printMBBReference(*MFI.getRestorePoint());
344   }
345 }
346 
347 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
348                                      const MachineFunction &MF,
349                                      ModuleSlotTracker &MST) {
350   const MachineFrameInfo &MFI = MF.getFrameInfo();
351   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
352   // Process fixed stack objects.
353   unsigned ID = 0;
354   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
355     if (MFI.isDeadObjectIndex(I))
356       continue;
357 
358     yaml::FixedMachineStackObject YamlObject;
359     YamlObject.ID = ID;
360     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
361                           ? yaml::FixedMachineStackObject::SpillSlot
362                           : yaml::FixedMachineStackObject::DefaultType;
363     YamlObject.Offset = MFI.getObjectOffset(I);
364     YamlObject.Size = MFI.getObjectSize(I);
365     YamlObject.Alignment = MFI.getObjectAlignment(I);
366     YamlObject.StackID = MFI.getStackID(I);
367     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
368     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
369     YMF.FixedStackObjects.push_back(YamlObject);
370     StackObjectOperandMapping.insert(
371         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
372   }
373 
374   // Process ordinary stack objects.
375   ID = 0;
376   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
377     if (MFI.isDeadObjectIndex(I))
378       continue;
379 
380     yaml::MachineStackObject YamlObject;
381     YamlObject.ID = ID;
382     if (const auto *Alloca = MFI.getObjectAllocation(I))
383       YamlObject.Name.Value =
384           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
385     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
386                           ? yaml::MachineStackObject::SpillSlot
387                           : MFI.isVariableSizedObjectIndex(I)
388                                 ? yaml::MachineStackObject::VariableSized
389                                 : yaml::MachineStackObject::DefaultType;
390     YamlObject.Offset = MFI.getObjectOffset(I);
391     YamlObject.Size = MFI.getObjectSize(I);
392     YamlObject.Alignment = MFI.getObjectAlignment(I);
393     YamlObject.StackID = MFI.getStackID(I);
394 
395     YMF.StackObjects.push_back(YamlObject);
396     StackObjectOperandMapping.insert(std::make_pair(
397         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
398   }
399 
400   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
401     yaml::StringValue Reg;
402     printRegMIR(CSInfo.getReg(), Reg, TRI);
403     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
404     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
405            "Invalid stack object index");
406     const FrameIndexOperand &StackObject = StackObjectInfo->second;
407     if (StackObject.IsFixed) {
408       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
409       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
410         CSInfo.isRestored();
411     } else {
412       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
413       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
414         CSInfo.isRestored();
415     }
416   }
417   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
418     auto LocalObject = MFI.getLocalFrameObjectMap(I);
419     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
420     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
421            "Invalid stack object index");
422     const FrameIndexOperand &StackObject = StackObjectInfo->second;
423     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
424     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
425   }
426 
427   // Print the stack object references in the frame information class after
428   // converting the stack objects.
429   if (MFI.hasStackProtectorIndex()) {
430     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
431     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
432         .printStackObjectReference(MFI.getStackProtectorIndex());
433   }
434 
435   // Print the debug variable information.
436   for (const MachineFunction::VariableDbgInfo &DebugVar :
437        MF.getVariableDbgInfo()) {
438     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
439     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
440            "Invalid stack object index");
441     const FrameIndexOperand &StackObject = StackObjectInfo->second;
442     if (StackObject.IsFixed) {
443       auto &Object = YMF.FixedStackObjects[StackObject.ID];
444       printStackObjectDbgInfo(DebugVar, Object, MST);
445     } else {
446       auto &Object = YMF.StackObjects[StackObject.ID];
447       printStackObjectDbgInfo(DebugVar, Object, MST);
448     }
449   }
450 }
451 
452 void MIRPrinter::convert(yaml::MachineFunction &MF,
453                          const MachineConstantPool &ConstantPool) {
454   unsigned ID = 0;
455   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
456     std::string Str;
457     raw_string_ostream StrOS(Str);
458     if (Constant.isMachineConstantPoolEntry()) {
459       Constant.Val.MachineCPVal->print(StrOS);
460     } else {
461       Constant.Val.ConstVal->printAsOperand(StrOS);
462     }
463 
464     yaml::MachineConstantPoolValue YamlConstant;
465     YamlConstant.ID = ID++;
466     YamlConstant.Value = StrOS.str();
467     YamlConstant.Alignment = Constant.getAlignment();
468     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
469 
470     MF.Constants.push_back(YamlConstant);
471   }
472 }
473 
474 void MIRPrinter::convert(ModuleSlotTracker &MST,
475                          yaml::MachineJumpTable &YamlJTI,
476                          const MachineJumpTableInfo &JTI) {
477   YamlJTI.Kind = JTI.getEntryKind();
478   unsigned ID = 0;
479   for (const auto &Table : JTI.getJumpTables()) {
480     std::string Str;
481     yaml::MachineJumpTable::Entry Entry;
482     Entry.ID = ID++;
483     for (const auto *MBB : Table.MBBs) {
484       raw_string_ostream StrOS(Str);
485       StrOS << printMBBReference(*MBB);
486       Entry.Blocks.push_back(StrOS.str());
487       Str.clear();
488     }
489     YamlJTI.Entries.push_back(Entry);
490   }
491 }
492 
493 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
494   const auto *TRI = MF.getSubtarget().getRegisterInfo();
495   unsigned I = 0;
496   for (const uint32_t *Mask : TRI->getRegMasks())
497     RegisterMaskIds.insert(std::make_pair(Mask, I++));
498 }
499 
500 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
501                            SmallVectorImpl<MachineBasicBlock*> &Result,
502                            bool &IsFallthrough) {
503   SmallPtrSet<MachineBasicBlock*,8> Seen;
504 
505   for (const MachineInstr &MI : MBB) {
506     if (MI.isPHI())
507       continue;
508     for (const MachineOperand &MO : MI.operands()) {
509       if (!MO.isMBB())
510         continue;
511       MachineBasicBlock *Succ = MO.getMBB();
512       auto RP = Seen.insert(Succ);
513       if (RP.second)
514         Result.push_back(Succ);
515     }
516   }
517   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
518   IsFallthrough = I == MBB.end() || !I->isBarrier();
519 }
520 
521 bool
522 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
523   if (MBB.succ_size() <= 1)
524     return true;
525   if (!MBB.hasSuccessorProbabilities())
526     return true;
527 
528   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
529                                               MBB.Probs.end());
530   BranchProbability::normalizeProbabilities(Normalized.begin(),
531                                             Normalized.end());
532   SmallVector<BranchProbability,8> Equal(Normalized.size());
533   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
534 
535   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
536 }
537 
538 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
539   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
540   bool GuessedFallthrough;
541   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
542   if (GuessedFallthrough) {
543     const MachineFunction &MF = *MBB.getParent();
544     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
545     if (NextI != MF.end()) {
546       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
547       if (!is_contained(GuessedSuccs, Next))
548         GuessedSuccs.push_back(Next);
549     }
550   }
551   if (GuessedSuccs.size() != MBB.succ_size())
552     return false;
553   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
554 }
555 
556 void MIPrinter::print(const MachineBasicBlock &MBB) {
557   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
558   OS << "bb." << MBB.getNumber();
559   bool HasAttributes = false;
560   if (const auto *BB = MBB.getBasicBlock()) {
561     if (BB->hasName()) {
562       OS << "." << BB->getName();
563     } else {
564       HasAttributes = true;
565       OS << " (";
566       int Slot = MST.getLocalSlot(BB);
567       if (Slot == -1)
568         OS << "<ir-block badref>";
569       else
570         OS << (Twine("%ir-block.") + Twine(Slot)).str();
571     }
572   }
573   if (MBB.hasAddressTaken()) {
574     OS << (HasAttributes ? ", " : " (");
575     OS << "address-taken";
576     HasAttributes = true;
577   }
578   if (MBB.isEHPad()) {
579     OS << (HasAttributes ? ", " : " (");
580     OS << "landing-pad";
581     HasAttributes = true;
582   }
583   if (MBB.getAlignment()) {
584     OS << (HasAttributes ? ", " : " (");
585     OS << "align " << MBB.getAlignment();
586     HasAttributes = true;
587   }
588   if (HasAttributes)
589     OS << ")";
590   OS << ":\n";
591 
592   bool HasLineAttributes = false;
593   // Print the successors
594   bool canPredictProbs = canPredictBranchProbabilities(MBB);
595   // Even if the list of successors is empty, if we cannot guess it,
596   // we need to print it to tell the parser that the list is empty.
597   // This is needed, because MI model unreachable as empty blocks
598   // with an empty successor list. If the parser would see that
599   // without the successor list, it would guess the code would
600   // fallthrough.
601   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
602       !canPredictSuccessors(MBB)) {
603     OS.indent(2) << "successors: ";
604     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
605       if (I != MBB.succ_begin())
606         OS << ", ";
607       OS << printMBBReference(**I);
608       if (!SimplifyMIR || !canPredictProbs)
609         OS << '('
610            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
611            << ')';
612     }
613     OS << "\n";
614     HasLineAttributes = true;
615   }
616 
617   // Print the live in registers.
618   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
619   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
620     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
621     OS.indent(2) << "liveins: ";
622     bool First = true;
623     for (const auto &LI : MBB.liveins()) {
624       if (!First)
625         OS << ", ";
626       First = false;
627       OS << printReg(LI.PhysReg, &TRI);
628       if (!LI.LaneMask.all())
629         OS << ":0x" << PrintLaneMask(LI.LaneMask);
630     }
631     OS << "\n";
632     HasLineAttributes = true;
633   }
634 
635   if (HasLineAttributes)
636     OS << "\n";
637   bool IsInBundle = false;
638   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
639     const MachineInstr &MI = *I;
640     if (IsInBundle && !MI.isInsideBundle()) {
641       OS.indent(2) << "}\n";
642       IsInBundle = false;
643     }
644     OS.indent(IsInBundle ? 4 : 2);
645     print(MI);
646     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
647       OS << " {";
648       IsInBundle = true;
649     }
650     OS << "\n";
651   }
652   if (IsInBundle)
653     OS.indent(2) << "}\n";
654 }
655 
656 void MIPrinter::print(const MachineInstr &MI) {
657   const auto *MF = MI.getMF();
658   const auto &MRI = MF->getRegInfo();
659   const auto &SubTarget = MF->getSubtarget();
660   const auto *TRI = SubTarget.getRegisterInfo();
661   assert(TRI && "Expected target register info");
662   const auto *TII = SubTarget.getInstrInfo();
663   assert(TII && "Expected target instruction info");
664   if (MI.isCFIInstruction())
665     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
666 
667   SmallBitVector PrintedTypes(8);
668   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
669   unsigned I = 0, E = MI.getNumOperands();
670   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
671          !MI.getOperand(I).isImplicit();
672        ++I) {
673     if (I)
674       OS << ", ";
675     print(MI, I, TRI, ShouldPrintRegisterTies,
676           MI.getTypeToPrint(I, PrintedTypes, MRI),
677           /*PrintDef=*/false);
678   }
679 
680   if (I)
681     OS << " = ";
682   if (MI.getFlag(MachineInstr::FrameSetup))
683     OS << "frame-setup ";
684   if (MI.getFlag(MachineInstr::FrameDestroy))
685     OS << "frame-destroy ";
686   if (MI.getFlag(MachineInstr::FmNoNans))
687     OS << "nnan ";
688   if (MI.getFlag(MachineInstr::FmNoInfs))
689     OS << "ninf ";
690   if (MI.getFlag(MachineInstr::FmNsz))
691     OS << "nsz ";
692   if (MI.getFlag(MachineInstr::FmArcp))
693     OS << "arcp ";
694   if (MI.getFlag(MachineInstr::FmContract))
695     OS << "contract ";
696   if (MI.getFlag(MachineInstr::FmAfn))
697     OS << "afn ";
698   if (MI.getFlag(MachineInstr::FmReassoc))
699     OS << "reassoc ";
700   if (MI.getFlag(MachineInstr::NoUWrap))
701     OS << "nuw ";
702   if (MI.getFlag(MachineInstr::NoSWrap))
703     OS << "nsw ";
704   if (MI.getFlag(MachineInstr::IsExact))
705     OS << "exact ";
706 
707   OS << TII->getName(MI.getOpcode());
708   if (I < E)
709     OS << ' ';
710 
711   bool NeedComma = false;
712   for (; I < E; ++I) {
713     if (NeedComma)
714       OS << ", ";
715     print(MI, I, TRI, ShouldPrintRegisterTies,
716           MI.getTypeToPrint(I, PrintedTypes, MRI));
717     NeedComma = true;
718   }
719 
720   // Print any optional symbols attached to this instruction as-if they were
721   // operands.
722   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
723     if (NeedComma)
724       OS << ',';
725     OS << " pre-instr-symbol ";
726     MachineOperand::printSymbol(OS, *PreInstrSymbol);
727     NeedComma = true;
728   }
729   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
730     if (NeedComma)
731       OS << ',';
732     OS << " post-instr-symbol ";
733     MachineOperand::printSymbol(OS, *PostInstrSymbol);
734     NeedComma = true;
735   }
736 
737   if (const DebugLoc &DL = MI.getDebugLoc()) {
738     if (NeedComma)
739       OS << ',';
740     OS << " debug-location ";
741     DL->printAsOperand(OS, MST);
742   }
743 
744   if (!MI.memoperands_empty()) {
745     OS << " :: ";
746     const LLVMContext &Context = MF->getFunction().getContext();
747     const MachineFrameInfo &MFI = MF->getFrameInfo();
748     bool NeedComma = false;
749     for (const auto *Op : MI.memoperands()) {
750       if (NeedComma)
751         OS << ", ";
752       Op->print(OS, MST, SSNs, Context, &MFI, TII);
753       NeedComma = true;
754     }
755   }
756 }
757 
758 void MIPrinter::printStackObjectReference(int FrameIndex) {
759   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
760   assert(ObjectInfo != StackObjectOperandMapping.end() &&
761          "Invalid frame index");
762   const FrameIndexOperand &Operand = ObjectInfo->second;
763   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
764                                             Operand.Name);
765 }
766 
767 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
768                       const TargetRegisterInfo *TRI,
769                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
770                       bool PrintDef) {
771   const MachineOperand &Op = MI.getOperand(OpIdx);
772   switch (Op.getType()) {
773   case MachineOperand::MO_Immediate:
774     if (MI.isOperandSubregIdx(OpIdx)) {
775       MachineOperand::printTargetFlags(OS, Op);
776       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
777       break;
778     }
779     LLVM_FALLTHROUGH;
780   case MachineOperand::MO_Register:
781   case MachineOperand::MO_CImmediate:
782   case MachineOperand::MO_FPImmediate:
783   case MachineOperand::MO_MachineBasicBlock:
784   case MachineOperand::MO_ConstantPoolIndex:
785   case MachineOperand::MO_TargetIndex:
786   case MachineOperand::MO_JumpTableIndex:
787   case MachineOperand::MO_ExternalSymbol:
788   case MachineOperand::MO_GlobalAddress:
789   case MachineOperand::MO_RegisterLiveOut:
790   case MachineOperand::MO_Metadata:
791   case MachineOperand::MO_MCSymbol:
792   case MachineOperand::MO_CFIIndex:
793   case MachineOperand::MO_IntrinsicID:
794   case MachineOperand::MO_Predicate:
795   case MachineOperand::MO_BlockAddress: {
796     unsigned TiedOperandIdx = 0;
797     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
798       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
799     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
800     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
801              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
802     break;
803   }
804   case MachineOperand::MO_FrameIndex:
805     printStackObjectReference(Op.getIndex());
806     break;
807   case MachineOperand::MO_RegisterMask: {
808     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
809     if (RegMaskInfo != RegisterMaskIds.end())
810       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
811     else
812       printCustomRegMask(Op.getRegMask(), OS, TRI);
813     break;
814   }
815   }
816 }
817 
818 void llvm::printMIR(raw_ostream &OS, const Module &M) {
819   yaml::Output Out(OS);
820   Out << const_cast<Module &>(M);
821 }
822 
823 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
824   MIRPrinter Printer(OS);
825   Printer.print(MF);
826 }
827