1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/MIRYamlMapping.h"
23 #include "llvm/IR/BasicBlock.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Instructions.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Module.h"
28 #include "llvm/IR/ModuleSlotTracker.h"
29 #include "llvm/Support/MemoryBuffer.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Support/YAMLTraits.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
34 
35 using namespace llvm;
36 
37 namespace {
38 
39 /// This structure describes how to print out stack object references.
40 struct FrameIndexOperand {
41   std::string Name;
42   unsigned ID;
43   bool IsFixed;
44 
45   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
46       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
47 
48   /// Return an ordinary stack object reference.
49   static FrameIndexOperand create(StringRef Name, unsigned ID) {
50     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
51   }
52 
53   /// Return a fixed stack object reference.
54   static FrameIndexOperand createFixed(unsigned ID) {
55     return FrameIndexOperand("", ID, /*IsFixed=*/true);
56   }
57 };
58 
59 } // end anonymous namespace
60 
61 namespace llvm {
62 
63 /// This class prints out the machine functions using the MIR serialization
64 /// format.
65 class MIRPrinter {
66   raw_ostream &OS;
67   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
68   /// Maps from stack object indices to operand indices which will be used when
69   /// printing frame index machine operands.
70   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
71 
72 public:
73   MIRPrinter(raw_ostream &OS) : OS(OS) {}
74 
75   void print(const MachineFunction &MF);
76 
77   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
78                const TargetRegisterInfo *TRI);
79   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
80                const MachineFrameInfo &MFI);
81   void convert(yaml::MachineFunction &MF,
82                const MachineConstantPool &ConstantPool);
83   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
84                const MachineJumpTableInfo &JTI);
85   void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
86                const MachineBasicBlock &MBB);
87   void convertStackObjects(yaml::MachineFunction &MF,
88                            const MachineFrameInfo &MFI,
89                            const TargetRegisterInfo *TRI);
90 
91 private:
92   void initRegisterMaskIds(const MachineFunction &MF);
93 };
94 
95 } // end namespace llvm
96 
97 namespace {
98 
99 /// This class prints out the machine instructions using the MIR serialization
100 /// format.
101 class MIPrinter {
102   raw_ostream &OS;
103   ModuleSlotTracker &MST;
104   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
105   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
106 
107 public:
108   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
109             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
110             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
111       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
112         StackObjectOperandMapping(StackObjectOperandMapping) {}
113 
114   void print(const MachineInstr &MI);
115   void printMBBReference(const MachineBasicBlock &MBB);
116   void printIRBlockReference(const BasicBlock &BB);
117   void printStackObjectReference(int FrameIndex);
118   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
119 
120   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
121 };
122 
123 } // end anonymous namespace
124 
125 namespace llvm {
126 namespace yaml {
127 
128 /// This struct serializes the LLVM IR module.
129 template <> struct BlockScalarTraits<Module> {
130   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
131     Mod.print(OS, nullptr);
132   }
133   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
134     llvm_unreachable("LLVM Module is supposed to be parsed separately");
135     return "";
136   }
137 };
138 
139 } // end namespace yaml
140 } // end namespace llvm
141 
142 static void printReg(unsigned Reg, raw_ostream &OS,
143                      const TargetRegisterInfo *TRI) {
144   // TODO: Print Stack Slots.
145   if (!Reg)
146     OS << '_';
147   else if (TargetRegisterInfo::isVirtualRegister(Reg))
148     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
149   else if (Reg < TRI->getNumRegs())
150     OS << '%' << StringRef(TRI->getName(Reg)).lower();
151   else
152     llvm_unreachable("Can't print this kind of register yet");
153 }
154 
155 static void printReg(unsigned Reg, yaml::StringValue &Dest,
156                      const TargetRegisterInfo *TRI) {
157   raw_string_ostream OS(Dest.Value);
158   printReg(Reg, OS, TRI);
159 }
160 
161 void MIRPrinter::print(const MachineFunction &MF) {
162   initRegisterMaskIds(MF);
163 
164   yaml::MachineFunction YamlMF;
165   YamlMF.Name = MF.getName();
166   YamlMF.Alignment = MF.getAlignment();
167   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
168   YamlMF.HasInlineAsm = MF.hasInlineAsm();
169   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
170   ModuleSlotTracker MST(MF.getFunction()->getParent());
171   MST.incorporateFunction(*MF.getFunction());
172   convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
173   convertStackObjects(YamlMF, *MF.getFrameInfo(),
174                       MF.getSubtarget().getRegisterInfo());
175   if (const auto *ConstantPool = MF.getConstantPool())
176     convert(YamlMF, *ConstantPool);
177   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
178     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
179   for (const auto &MBB : MF) {
180     yaml::MachineBasicBlock YamlMBB;
181     convert(MST, YamlMBB, MBB);
182     YamlMF.BasicBlocks.push_back(YamlMBB);
183   }
184   yaml::Output Out(OS);
185   Out << YamlMF;
186 }
187 
188 void MIRPrinter::convert(yaml::MachineFunction &MF,
189                          const MachineRegisterInfo &RegInfo,
190                          const TargetRegisterInfo *TRI) {
191   MF.IsSSA = RegInfo.isSSA();
192   MF.TracksRegLiveness = RegInfo.tracksLiveness();
193   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
194 
195   // Print the virtual register definitions.
196   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
197     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
198     yaml::VirtualRegisterDefinition VReg;
199     VReg.ID = I;
200     VReg.Class =
201         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
202     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
203     if (PreferredReg)
204       printReg(PreferredReg, VReg.PreferredRegister, TRI);
205     MF.VirtualRegisters.push_back(VReg);
206   }
207 
208   // Print the live ins.
209   for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
210     yaml::MachineFunctionLiveIn LiveIn;
211     printReg(I->first, LiveIn.Register, TRI);
212     if (I->second)
213       printReg(I->second, LiveIn.VirtualRegister, TRI);
214     MF.LiveIns.push_back(LiveIn);
215   }
216 }
217 
218 void MIRPrinter::convert(ModuleSlotTracker &MST,
219                          yaml::MachineFrameInfo &YamlMFI,
220                          const MachineFrameInfo &MFI) {
221   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
222   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
223   YamlMFI.HasStackMap = MFI.hasStackMap();
224   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
225   YamlMFI.StackSize = MFI.getStackSize();
226   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
227   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
228   YamlMFI.AdjustsStack = MFI.adjustsStack();
229   YamlMFI.HasCalls = MFI.hasCalls();
230   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
231   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
232   YamlMFI.HasVAStart = MFI.hasVAStart();
233   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
234   if (MFI.getSavePoint()) {
235     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
236     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
237         .printMBBReference(*MFI.getSavePoint());
238   }
239   if (MFI.getRestorePoint()) {
240     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
241     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
242         .printMBBReference(*MFI.getRestorePoint());
243   }
244 }
245 
246 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
247                                      const MachineFrameInfo &MFI,
248                                      const TargetRegisterInfo *TRI) {
249   // Process fixed stack objects.
250   unsigned ID = 0;
251   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
252     if (MFI.isDeadObjectIndex(I))
253       continue;
254 
255     yaml::FixedMachineStackObject YamlObject;
256     YamlObject.ID = ID;
257     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
258                           ? yaml::FixedMachineStackObject::SpillSlot
259                           : yaml::FixedMachineStackObject::DefaultType;
260     YamlObject.Offset = MFI.getObjectOffset(I);
261     YamlObject.Size = MFI.getObjectSize(I);
262     YamlObject.Alignment = MFI.getObjectAlignment(I);
263     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
264     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
265     MF.FixedStackObjects.push_back(YamlObject);
266     StackObjectOperandMapping.insert(
267         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
268   }
269 
270   // Process ordinary stack objects.
271   ID = 0;
272   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
273     if (MFI.isDeadObjectIndex(I))
274       continue;
275 
276     yaml::MachineStackObject YamlObject;
277     YamlObject.ID = ID;
278     if (const auto *Alloca = MFI.getObjectAllocation(I))
279       YamlObject.Name.Value =
280           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
281     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
282                           ? yaml::MachineStackObject::SpillSlot
283                           : MFI.isVariableSizedObjectIndex(I)
284                                 ? yaml::MachineStackObject::VariableSized
285                                 : yaml::MachineStackObject::DefaultType;
286     YamlObject.Offset = MFI.getObjectOffset(I);
287     YamlObject.Size = MFI.getObjectSize(I);
288     YamlObject.Alignment = MFI.getObjectAlignment(I);
289 
290     MF.StackObjects.push_back(YamlObject);
291     StackObjectOperandMapping.insert(std::make_pair(
292         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
293   }
294 
295   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
296     yaml::StringValue Reg;
297     printReg(CSInfo.getReg(), Reg, TRI);
298     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
299     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
300            "Invalid stack object index");
301     const FrameIndexOperand &StackObject = StackObjectInfo->second;
302     if (StackObject.IsFixed)
303       MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
304     else
305       MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
306   }
307 }
308 
309 void MIRPrinter::convert(yaml::MachineFunction &MF,
310                          const MachineConstantPool &ConstantPool) {
311   unsigned ID = 0;
312   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
313     // TODO: Serialize target specific constant pool entries.
314     if (Constant.isMachineConstantPoolEntry())
315       llvm_unreachable("Can't print target specific constant pool entries yet");
316 
317     yaml::MachineConstantPoolValue YamlConstant;
318     std::string Str;
319     raw_string_ostream StrOS(Str);
320     Constant.Val.ConstVal->printAsOperand(StrOS);
321     YamlConstant.ID = ID++;
322     YamlConstant.Value = StrOS.str();
323     YamlConstant.Alignment = Constant.getAlignment();
324     MF.Constants.push_back(YamlConstant);
325   }
326 }
327 
328 void MIRPrinter::convert(ModuleSlotTracker &MST,
329                          yaml::MachineJumpTable &YamlJTI,
330                          const MachineJumpTableInfo &JTI) {
331   YamlJTI.Kind = JTI.getEntryKind();
332   unsigned ID = 0;
333   for (const auto &Table : JTI.getJumpTables()) {
334     std::string Str;
335     yaml::MachineJumpTable::Entry Entry;
336     Entry.ID = ID++;
337     for (const auto *MBB : Table.MBBs) {
338       raw_string_ostream StrOS(Str);
339       MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
340           .printMBBReference(*MBB);
341       Entry.Blocks.push_back(StrOS.str());
342       Str.clear();
343     }
344     YamlJTI.Entries.push_back(Entry);
345   }
346 }
347 
348 void MIRPrinter::convert(ModuleSlotTracker &MST,
349                          yaml::MachineBasicBlock &YamlMBB,
350                          const MachineBasicBlock &MBB) {
351   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
352   YamlMBB.ID = (unsigned)MBB.getNumber();
353   if (const auto *BB = MBB.getBasicBlock()) {
354     if (BB->hasName()) {
355       YamlMBB.Name.Value = BB->getName();
356     } else {
357       int Slot = MST.getLocalSlot(BB);
358       if (Slot == -1)
359         YamlMBB.IRBlock.Value = "<badref>";
360       else
361         YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();
362     }
363   }
364   YamlMBB.Alignment = MBB.getAlignment();
365   YamlMBB.AddressTaken = MBB.hasAddressTaken();
366   YamlMBB.IsLandingPad = MBB.isLandingPad();
367   for (const auto *SuccMBB : MBB.successors()) {
368     std::string Str;
369     raw_string_ostream StrOS(Str);
370     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
371         .printMBBReference(*SuccMBB);
372     YamlMBB.Successors.push_back(StrOS.str());
373   }
374   if (MBB.hasSuccessorWeights()) {
375     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I)
376       YamlMBB.SuccessorWeights.push_back(
377           yaml::UnsignedValue(MBB.getSuccWeight(I)));
378   }
379   // Print the live in registers.
380   const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
381   assert(TRI && "Expected target register info");
382   for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
383     std::string Str;
384     raw_string_ostream StrOS(Str);
385     printReg(*I, StrOS, TRI);
386     YamlMBB.LiveIns.push_back(StrOS.str());
387   }
388   // Print the machine instructions.
389   YamlMBB.Instructions.reserve(MBB.size());
390   std::string Str;
391   for (const auto &MI : MBB) {
392     raw_string_ostream StrOS(Str);
393     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
394     YamlMBB.Instructions.push_back(StrOS.str());
395     Str.clear();
396   }
397 }
398 
399 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
400   const auto *TRI = MF.getSubtarget().getRegisterInfo();
401   unsigned I = 0;
402   for (const uint32_t *Mask : TRI->getRegMasks())
403     RegisterMaskIds.insert(std::make_pair(Mask, I++));
404 }
405 
406 void MIPrinter::print(const MachineInstr &MI) {
407   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
408   const auto *TRI = SubTarget.getRegisterInfo();
409   assert(TRI && "Expected target register info");
410   const auto *TII = SubTarget.getInstrInfo();
411   assert(TII && "Expected target instruction info");
412   if (MI.isCFIInstruction())
413     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
414 
415   unsigned I = 0, E = MI.getNumOperands();
416   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
417          !MI.getOperand(I).isImplicit();
418        ++I) {
419     if (I)
420       OS << ", ";
421     print(MI.getOperand(I), TRI);
422   }
423 
424   if (I)
425     OS << " = ";
426   if (MI.getFlag(MachineInstr::FrameSetup))
427     OS << "frame-setup ";
428   OS << TII->getName(MI.getOpcode());
429   // TODO: Print the bundling instruction flags, machine mem operands.
430   if (I < E)
431     OS << ' ';
432 
433   bool NeedComma = false;
434   for (; I < E; ++I) {
435     if (NeedComma)
436       OS << ", ";
437     print(MI.getOperand(I), TRI);
438     NeedComma = true;
439   }
440 
441   if (MI.getDebugLoc()) {
442     if (NeedComma)
443       OS << ',';
444     OS << " debug-location ";
445     MI.getDebugLoc()->printAsOperand(OS, MST);
446   }
447 }
448 
449 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
450   OS << "%bb." << MBB.getNumber();
451   if (const auto *BB = MBB.getBasicBlock()) {
452     if (BB->hasName())
453       OS << '.' << BB->getName();
454   }
455 }
456 
457 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
458   OS << "%ir-block.";
459   if (BB.hasName()) {
460     printLLVMNameWithoutPrefix(OS, BB.getName());
461     return;
462   }
463   int Slot = MST.getLocalSlot(&BB);
464   if (Slot == -1)
465     OS << "<badref>";
466   else
467     OS << Slot;
468 }
469 
470 void MIPrinter::printStackObjectReference(int FrameIndex) {
471   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
472   assert(ObjectInfo != StackObjectOperandMapping.end() &&
473          "Invalid frame index");
474   const FrameIndexOperand &Operand = ObjectInfo->second;
475   if (Operand.IsFixed) {
476     OS << "%fixed-stack." << Operand.ID;
477     return;
478   }
479   OS << "%stack." << Operand.ID;
480   if (!Operand.Name.empty())
481     OS << '.' << Operand.Name;
482 }
483 
484 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
485   const auto *TII = MF.getSubtarget().getInstrInfo();
486   assert(TII && "expected instruction info");
487   auto Indices = TII->getSerializableTargetIndices();
488   for (const auto &I : Indices) {
489     if (I.first == Index) {
490       return I.second;
491     }
492   }
493   return nullptr;
494 }
495 
496 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
497   switch (Op.getType()) {
498   case MachineOperand::MO_Register:
499     // TODO: Print the other register flags.
500     if (Op.isImplicit())
501       OS << (Op.isDef() ? "implicit-def " : "implicit ");
502     if (Op.isDead())
503       OS << "dead ";
504     if (Op.isKill())
505       OS << "killed ";
506     if (Op.isUndef())
507       OS << "undef ";
508     printReg(Op.getReg(), OS, TRI);
509     // Print the sub register.
510     if (Op.getSubReg() != 0)
511       OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
512     break;
513   case MachineOperand::MO_Immediate:
514     OS << Op.getImm();
515     break;
516   case MachineOperand::MO_MachineBasicBlock:
517     printMBBReference(*Op.getMBB());
518     break;
519   case MachineOperand::MO_FrameIndex:
520     printStackObjectReference(Op.getIndex());
521     break;
522   case MachineOperand::MO_ConstantPoolIndex:
523     OS << "%const." << Op.getIndex();
524     // TODO: Print offset and target flags.
525     break;
526   case MachineOperand::MO_TargetIndex: {
527     OS << "target-index(";
528     if (const auto *Name = getTargetIndexName(
529             *Op.getParent()->getParent()->getParent(), Op.getIndex()))
530       OS << Name;
531     else
532       OS << "<unknown>";
533     OS << ')';
534     // TODO: Print the offset and target flags.
535     break;
536   }
537   case MachineOperand::MO_JumpTableIndex:
538     OS << "%jump-table." << Op.getIndex();
539     // TODO: Print target flags.
540     break;
541   case MachineOperand::MO_ExternalSymbol:
542     OS << '$';
543     printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
544     // TODO: Print the target flags.
545     break;
546   case MachineOperand::MO_GlobalAddress:
547     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
548     // TODO: Print offset and target flags.
549     break;
550   case MachineOperand::MO_BlockAddress:
551     OS << "blockaddress(";
552     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
553                                                         MST);
554     OS << ", ";
555     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
556     OS << ')';
557     // TODO: Print offset and target flags.
558     break;
559   case MachineOperand::MO_RegisterMask: {
560     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
561     if (RegMaskInfo != RegisterMaskIds.end())
562       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
563     else
564       llvm_unreachable("Can't print this machine register mask yet.");
565     break;
566   }
567   case MachineOperand::MO_Metadata:
568     Op.getMetadata()->printAsOperand(OS, MST);
569     break;
570   case MachineOperand::MO_CFIIndex: {
571     const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
572     print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
573     break;
574   }
575   default:
576     // TODO: Print the other machine operands.
577     llvm_unreachable("Can't print this machine operand at the moment");
578   }
579 }
580 
581 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
582                              const TargetRegisterInfo *TRI) {
583   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
584   if (Reg == -1) {
585     OS << "<badreg>";
586     return;
587   }
588   printReg(Reg, OS, TRI);
589 }
590 
591 void MIPrinter::print(const MCCFIInstruction &CFI,
592                       const TargetRegisterInfo *TRI) {
593   switch (CFI.getOperation()) {
594   case MCCFIInstruction::OpOffset:
595     OS << ".cfi_offset ";
596     if (CFI.getLabel())
597       OS << "<mcsymbol> ";
598     printCFIRegister(CFI.getRegister(), OS, TRI);
599     OS << ", " << CFI.getOffset();
600     break;
601   case MCCFIInstruction::OpDefCfaRegister:
602     OS << ".cfi_def_cfa_register ";
603     if (CFI.getLabel())
604       OS << "<mcsymbol> ";
605     printCFIRegister(CFI.getRegister(), OS, TRI);
606     break;
607   case MCCFIInstruction::OpDefCfaOffset:
608     OS << ".cfi_def_cfa_offset ";
609     if (CFI.getLabel())
610       OS << "<mcsymbol> ";
611     OS << CFI.getOffset();
612     break;
613   case MCCFIInstruction::OpDefCfa:
614     OS << ".cfi_def_cfa ";
615     if (CFI.getLabel())
616       OS << "<mcsymbol> ";
617     printCFIRegister(CFI.getRegister(), OS, TRI);
618     OS << ", " << CFI.getOffset();
619     break;
620   default:
621     // TODO: Print the other CFI Operations.
622     OS << "<unserializable cfi operation>";
623     break;
624   }
625 }
626 
627 void llvm::printMIR(raw_ostream &OS, const Module &M) {
628   yaml::Output Out(OS);
629   Out << const_cast<Module &>(M);
630 }
631 
632 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
633   MIRPrinter Printer(OS);
634   Printer.print(MF);
635 }
636