1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/MIRYamlMapping.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/MemoryBuffer.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/YAMLTraits.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetSubtargetInfo.h"
27 
28 using namespace llvm;
29 
30 namespace {
31 
32 /// This class prints out the machine functions using the MIR serialization
33 /// format.
34 class MIRPrinter {
35   raw_ostream &OS;
36   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
37 
38 public:
39   MIRPrinter(raw_ostream &OS) : OS(OS) {}
40 
41   void print(const MachineFunction &MF);
42 
43   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
44   void convert(const Module &M, yaml::MachineBasicBlock &YamlMBB,
45                const MachineBasicBlock &MBB);
46 
47 private:
48   void initRegisterMaskIds(const MachineFunction &MF);
49 };
50 
51 /// This class prints out the machine instructions using the MIR serialization
52 /// format.
53 class MIPrinter {
54   const Module &M;
55   raw_ostream &OS;
56   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
57 
58 public:
59   MIPrinter(const Module &M, raw_ostream &OS,
60             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
61       : M(M), OS(OS), RegisterMaskIds(RegisterMaskIds) {}
62 
63   void print(const MachineInstr &MI);
64   void printMBBReference(const MachineBasicBlock &MBB);
65   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
66 };
67 
68 } // end anonymous namespace
69 
70 namespace llvm {
71 namespace yaml {
72 
73 /// This struct serializes the LLVM IR module.
74 template <> struct BlockScalarTraits<Module> {
75   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
76     Mod.print(OS, nullptr);
77   }
78   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
79     llvm_unreachable("LLVM Module is supposed to be parsed separately");
80     return "";
81   }
82 };
83 
84 } // end namespace yaml
85 } // end namespace llvm
86 
87 void MIRPrinter::print(const MachineFunction &MF) {
88   initRegisterMaskIds(MF);
89 
90   yaml::MachineFunction YamlMF;
91   YamlMF.Name = MF.getName();
92   YamlMF.Alignment = MF.getAlignment();
93   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
94   YamlMF.HasInlineAsm = MF.hasInlineAsm();
95   convert(YamlMF, MF.getRegInfo());
96 
97   int I = 0;
98   const auto &M = *MF.getFunction()->getParent();
99   for (const auto &MBB : MF) {
100     // TODO: Allow printing of non sequentially numbered MBBs.
101     // This is currently needed as the basic block references get their index
102     // from MBB.getNumber(), thus it should be sequential so that the parser can
103     // map back to the correct MBBs when parsing the output.
104     assert(MBB.getNumber() == I++ &&
105            "Can't print MBBs that aren't sequentially numbered");
106     (void)I;
107     yaml::MachineBasicBlock YamlMBB;
108     convert(M, YamlMBB, MBB);
109     YamlMF.BasicBlocks.push_back(YamlMBB);
110   }
111   yaml::Output Out(OS);
112   Out << YamlMF;
113 }
114 
115 void MIRPrinter::convert(yaml::MachineFunction &MF,
116                          const MachineRegisterInfo &RegInfo) {
117   MF.IsSSA = RegInfo.isSSA();
118   MF.TracksRegLiveness = RegInfo.tracksLiveness();
119   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
120 }
121 
122 void MIRPrinter::convert(const Module &M, yaml::MachineBasicBlock &YamlMBB,
123                          const MachineBasicBlock &MBB) {
124   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
125   YamlMBB.ID = (unsigned)MBB.getNumber();
126   // TODO: Serialize unnamed BB references.
127   if (const auto *BB = MBB.getBasicBlock())
128     YamlMBB.Name = BB->hasName() ? BB->getName() : "<unnamed bb>";
129   else
130     YamlMBB.Name = "";
131   YamlMBB.Alignment = MBB.getAlignment();
132   YamlMBB.AddressTaken = MBB.hasAddressTaken();
133   YamlMBB.IsLandingPad = MBB.isLandingPad();
134   for (const auto *SuccMBB : MBB.successors()) {
135     std::string Str;
136     raw_string_ostream StrOS(Str);
137     MIPrinter(M, StrOS, RegisterMaskIds).printMBBReference(*SuccMBB);
138     YamlMBB.Successors.push_back(StrOS.str());
139   }
140 
141   // Print the machine instructions.
142   YamlMBB.Instructions.reserve(MBB.size());
143   std::string Str;
144   for (const auto &MI : MBB) {
145     raw_string_ostream StrOS(Str);
146     MIPrinter(M, StrOS, RegisterMaskIds).print(MI);
147     YamlMBB.Instructions.push_back(StrOS.str());
148     Str.clear();
149   }
150 }
151 
152 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
153   const auto *TRI = MF.getSubtarget().getRegisterInfo();
154   unsigned I = 0;
155   for (const uint32_t *Mask : TRI->getRegMasks())
156     RegisterMaskIds.insert(std::make_pair(Mask, I++));
157 }
158 
159 void MIPrinter::print(const MachineInstr &MI) {
160   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
161   const auto *TRI = SubTarget.getRegisterInfo();
162   assert(TRI && "Expected target register info");
163   const auto *TII = SubTarget.getInstrInfo();
164   assert(TII && "Expected target instruction info");
165 
166   unsigned I = 0, E = MI.getNumOperands();
167   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
168          !MI.getOperand(I).isImplicit();
169        ++I) {
170     if (I)
171       OS << ", ";
172     print(MI.getOperand(I), TRI);
173   }
174 
175   if (I)
176     OS << " = ";
177   OS << TII->getName(MI.getOpcode());
178   // TODO: Print the instruction flags, machine mem operands.
179   if (I < E)
180     OS << ' ';
181 
182   bool NeedComma = false;
183   for (; I < E; ++I) {
184     if (NeedComma)
185       OS << ", ";
186     print(MI.getOperand(I), TRI);
187     NeedComma = true;
188   }
189 }
190 
191 static void printReg(unsigned Reg, raw_ostream &OS,
192                      const TargetRegisterInfo *TRI) {
193   // TODO: Print Stack Slots.
194   // TODO: Print virtual registers.
195   if (!Reg)
196     OS << '_';
197   else if (Reg < TRI->getNumRegs())
198     OS << '%' << StringRef(TRI->getName(Reg)).lower();
199   else
200     llvm_unreachable("Can't print this kind of register yet");
201 }
202 
203 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
204   OS << "%bb." << MBB.getNumber();
205   if (const auto *BB = MBB.getBasicBlock()) {
206     if (BB->hasName())
207       OS << '.' << BB->getName();
208   }
209 }
210 
211 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
212   switch (Op.getType()) {
213   case MachineOperand::MO_Register:
214     // TODO: Print register flags.
215     printReg(Op.getReg(), OS, TRI);
216     // TODO: Print sub register.
217     break;
218   case MachineOperand::MO_Immediate:
219     OS << Op.getImm();
220     break;
221   case MachineOperand::MO_MachineBasicBlock:
222     printMBBReference(*Op.getMBB());
223     break;
224   case MachineOperand::MO_GlobalAddress:
225     // FIXME: Make this faster - print as operand will create a slot tracker to
226     // print unnamed values for the whole module every time it's called, which
227     // is inefficient.
228     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, &M);
229     // TODO: Print offset and target flags.
230     break;
231   case MachineOperand::MO_RegisterMask: {
232     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
233     if (RegMaskInfo != RegisterMaskIds.end())
234       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
235     else
236       llvm_unreachable("Can't print this machine register mask yet.");
237     break;
238   }
239   default:
240     // TODO: Print the other machine operands.
241     llvm_unreachable("Can't print this machine operand at the moment");
242   }
243 }
244 
245 void llvm::printMIR(raw_ostream &OS, const Module &M) {
246   yaml::Output Out(OS);
247   Out << const_cast<Module &>(M);
248 }
249 
250 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
251   MIRPrinter Printer(OS);
252   Printer.print(MF);
253 }
254