1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/MIRYamlMapping.h"
23 #include "llvm/IR/BasicBlock.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Instructions.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Module.h"
28 #include "llvm/IR/ModuleSlotTracker.h"
29 #include "llvm/Support/MemoryBuffer.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Support/YAMLTraits.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
34 
35 using namespace llvm;
36 
37 namespace {
38 
39 /// This structure describes how to print out stack object references.
40 struct FrameIndexOperand {
41   std::string Name;
42   unsigned ID;
43   bool IsFixed;
44 
45   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
46       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
47 
48   /// Return an ordinary stack object reference.
49   static FrameIndexOperand create(StringRef Name, unsigned ID) {
50     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
51   }
52 
53   /// Return a fixed stack object reference.
54   static FrameIndexOperand createFixed(unsigned ID) {
55     return FrameIndexOperand("", ID, /*IsFixed=*/true);
56   }
57 };
58 
59 /// This class prints out the machine functions using the MIR serialization
60 /// format.
61 class MIRPrinter {
62   raw_ostream &OS;
63   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
64   /// Maps from stack object indices to operand indices which will be used when
65   /// printing frame index machine operands.
66   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
67 
68 public:
69   MIRPrinter(raw_ostream &OS) : OS(OS) {}
70 
71   void print(const MachineFunction &MF);
72 
73   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
74                const TargetRegisterInfo *TRI);
75   void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
76   void convert(yaml::MachineFunction &MF,
77                const MachineConstantPool &ConstantPool);
78   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
79                const MachineJumpTableInfo &JTI);
80   void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
81                const MachineBasicBlock &MBB);
82   void convertStackObjects(yaml::MachineFunction &MF,
83                            const MachineFrameInfo &MFI,
84                            const TargetRegisterInfo *TRI);
85 
86 private:
87   void initRegisterMaskIds(const MachineFunction &MF);
88 };
89 
90 /// This class prints out the machine instructions using the MIR serialization
91 /// format.
92 class MIPrinter {
93   raw_ostream &OS;
94   ModuleSlotTracker &MST;
95   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
96   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
97 
98 public:
99   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
100             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
101             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
102       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
103         StackObjectOperandMapping(StackObjectOperandMapping) {}
104 
105   void print(const MachineInstr &MI);
106   void printMBBReference(const MachineBasicBlock &MBB);
107   void printIRBlockReference(const BasicBlock &BB);
108   void printStackObjectReference(int FrameIndex);
109   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
110 
111   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
112 };
113 
114 } // end anonymous namespace
115 
116 namespace llvm {
117 namespace yaml {
118 
119 /// This struct serializes the LLVM IR module.
120 template <> struct BlockScalarTraits<Module> {
121   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
122     Mod.print(OS, nullptr);
123   }
124   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
125     llvm_unreachable("LLVM Module is supposed to be parsed separately");
126     return "";
127   }
128 };
129 
130 } // end namespace yaml
131 } // end namespace llvm
132 
133 static void printReg(unsigned Reg, raw_ostream &OS,
134                      const TargetRegisterInfo *TRI) {
135   // TODO: Print Stack Slots.
136   if (!Reg)
137     OS << '_';
138   else if (TargetRegisterInfo::isVirtualRegister(Reg))
139     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
140   else if (Reg < TRI->getNumRegs())
141     OS << '%' << StringRef(TRI->getName(Reg)).lower();
142   else
143     llvm_unreachable("Can't print this kind of register yet");
144 }
145 
146 static void printReg(unsigned Reg, yaml::StringValue &Dest,
147                      const TargetRegisterInfo *TRI) {
148   raw_string_ostream OS(Dest.Value);
149   printReg(Reg, OS, TRI);
150 }
151 
152 void MIRPrinter::print(const MachineFunction &MF) {
153   initRegisterMaskIds(MF);
154 
155   yaml::MachineFunction YamlMF;
156   YamlMF.Name = MF.getName();
157   YamlMF.Alignment = MF.getAlignment();
158   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
159   YamlMF.HasInlineAsm = MF.hasInlineAsm();
160   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
161   convert(YamlMF.FrameInfo, *MF.getFrameInfo());
162   convertStackObjects(YamlMF, *MF.getFrameInfo(),
163                       MF.getSubtarget().getRegisterInfo());
164   if (const auto *ConstantPool = MF.getConstantPool())
165     convert(YamlMF, *ConstantPool);
166 
167   ModuleSlotTracker MST(MF.getFunction()->getParent());
168   MST.incorporateFunction(*MF.getFunction());
169   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
170     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
171   for (const auto &MBB : MF) {
172     yaml::MachineBasicBlock YamlMBB;
173     convert(MST, YamlMBB, MBB);
174     YamlMF.BasicBlocks.push_back(YamlMBB);
175   }
176   yaml::Output Out(OS);
177   Out << YamlMF;
178 }
179 
180 void MIRPrinter::convert(yaml::MachineFunction &MF,
181                          const MachineRegisterInfo &RegInfo,
182                          const TargetRegisterInfo *TRI) {
183   MF.IsSSA = RegInfo.isSSA();
184   MF.TracksRegLiveness = RegInfo.tracksLiveness();
185   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
186 
187   // Print the virtual register definitions.
188   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
189     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
190     yaml::VirtualRegisterDefinition VReg;
191     VReg.ID = I;
192     VReg.Class =
193         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
194     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
195     if (PreferredReg)
196       printReg(PreferredReg, VReg.PreferredRegister, TRI);
197     MF.VirtualRegisters.push_back(VReg);
198   }
199 
200   // Print the live ins.
201   for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
202     yaml::MachineFunctionLiveIn LiveIn;
203     printReg(I->first, LiveIn.Register, TRI);
204     if (I->second)
205       printReg(I->second, LiveIn.VirtualRegister, TRI);
206     MF.LiveIns.push_back(LiveIn);
207   }
208 }
209 
210 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
211                          const MachineFrameInfo &MFI) {
212   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
213   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
214   YamlMFI.HasStackMap = MFI.hasStackMap();
215   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
216   YamlMFI.StackSize = MFI.getStackSize();
217   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
218   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
219   YamlMFI.AdjustsStack = MFI.adjustsStack();
220   YamlMFI.HasCalls = MFI.hasCalls();
221   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
222   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
223   YamlMFI.HasVAStart = MFI.hasVAStart();
224   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
225 }
226 
227 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
228                                      const MachineFrameInfo &MFI,
229                                      const TargetRegisterInfo *TRI) {
230   // Process fixed stack objects.
231   unsigned ID = 0;
232   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
233     if (MFI.isDeadObjectIndex(I))
234       continue;
235 
236     yaml::FixedMachineStackObject YamlObject;
237     YamlObject.ID = ID;
238     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
239                           ? yaml::FixedMachineStackObject::SpillSlot
240                           : yaml::FixedMachineStackObject::DefaultType;
241     YamlObject.Offset = MFI.getObjectOffset(I);
242     YamlObject.Size = MFI.getObjectSize(I);
243     YamlObject.Alignment = MFI.getObjectAlignment(I);
244     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
245     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
246     MF.FixedStackObjects.push_back(YamlObject);
247     StackObjectOperandMapping.insert(
248         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
249   }
250 
251   // Process ordinary stack objects.
252   ID = 0;
253   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
254     if (MFI.isDeadObjectIndex(I))
255       continue;
256 
257     yaml::MachineStackObject YamlObject;
258     YamlObject.ID = ID;
259     if (const auto *Alloca = MFI.getObjectAllocation(I))
260       YamlObject.Name.Value =
261           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
262     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
263                           ? yaml::MachineStackObject::SpillSlot
264                           : MFI.isVariableSizedObjectIndex(I)
265                                 ? yaml::MachineStackObject::VariableSized
266                                 : yaml::MachineStackObject::DefaultType;
267     YamlObject.Offset = MFI.getObjectOffset(I);
268     YamlObject.Size = MFI.getObjectSize(I);
269     YamlObject.Alignment = MFI.getObjectAlignment(I);
270 
271     MF.StackObjects.push_back(YamlObject);
272     StackObjectOperandMapping.insert(std::make_pair(
273         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
274   }
275 
276   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
277     yaml::StringValue Reg;
278     printReg(CSInfo.getReg(), Reg, TRI);
279     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
280     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
281            "Invalid stack object index");
282     const FrameIndexOperand &StackObject = StackObjectInfo->second;
283     if (StackObject.IsFixed)
284       MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
285     else
286       MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
287   }
288 }
289 
290 void MIRPrinter::convert(yaml::MachineFunction &MF,
291                          const MachineConstantPool &ConstantPool) {
292   unsigned ID = 0;
293   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
294     // TODO: Serialize target specific constant pool entries.
295     if (Constant.isMachineConstantPoolEntry())
296       llvm_unreachable("Can't print target specific constant pool entries yet");
297 
298     yaml::MachineConstantPoolValue YamlConstant;
299     std::string Str;
300     raw_string_ostream StrOS(Str);
301     Constant.Val.ConstVal->printAsOperand(StrOS);
302     YamlConstant.ID = ID++;
303     YamlConstant.Value = StrOS.str();
304     YamlConstant.Alignment = Constant.getAlignment();
305     MF.Constants.push_back(YamlConstant);
306   }
307 }
308 
309 void MIRPrinter::convert(ModuleSlotTracker &MST,
310                          yaml::MachineJumpTable &YamlJTI,
311                          const MachineJumpTableInfo &JTI) {
312   YamlJTI.Kind = JTI.getEntryKind();
313   unsigned ID = 0;
314   for (const auto &Table : JTI.getJumpTables()) {
315     std::string Str;
316     yaml::MachineJumpTable::Entry Entry;
317     Entry.ID = ID++;
318     for (const auto *MBB : Table.MBBs) {
319       raw_string_ostream StrOS(Str);
320       MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
321           .printMBBReference(*MBB);
322       Entry.Blocks.push_back(StrOS.str());
323       Str.clear();
324     }
325     YamlJTI.Entries.push_back(Entry);
326   }
327 }
328 
329 void MIRPrinter::convert(ModuleSlotTracker &MST,
330                          yaml::MachineBasicBlock &YamlMBB,
331                          const MachineBasicBlock &MBB) {
332   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
333   YamlMBB.ID = (unsigned)MBB.getNumber();
334   if (const auto *BB = MBB.getBasicBlock()) {
335     if (BB->hasName()) {
336       YamlMBB.Name.Value = BB->getName();
337     } else {
338       int Slot = MST.getLocalSlot(BB);
339       if (Slot == -1)
340         YamlMBB.IRBlock.Value = "<badref>";
341       else
342         YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();
343     }
344   }
345   YamlMBB.Alignment = MBB.getAlignment();
346   YamlMBB.AddressTaken = MBB.hasAddressTaken();
347   YamlMBB.IsLandingPad = MBB.isLandingPad();
348   for (const auto *SuccMBB : MBB.successors()) {
349     std::string Str;
350     raw_string_ostream StrOS(Str);
351     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
352         .printMBBReference(*SuccMBB);
353     YamlMBB.Successors.push_back(StrOS.str());
354   }
355   // Print the live in registers.
356   const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
357   assert(TRI && "Expected target register info");
358   for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
359     std::string Str;
360     raw_string_ostream StrOS(Str);
361     printReg(*I, StrOS, TRI);
362     YamlMBB.LiveIns.push_back(StrOS.str());
363   }
364   // Print the machine instructions.
365   YamlMBB.Instructions.reserve(MBB.size());
366   std::string Str;
367   for (const auto &MI : MBB) {
368     raw_string_ostream StrOS(Str);
369     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
370     YamlMBB.Instructions.push_back(StrOS.str());
371     Str.clear();
372   }
373 }
374 
375 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
376   const auto *TRI = MF.getSubtarget().getRegisterInfo();
377   unsigned I = 0;
378   for (const uint32_t *Mask : TRI->getRegMasks())
379     RegisterMaskIds.insert(std::make_pair(Mask, I++));
380 }
381 
382 void MIPrinter::print(const MachineInstr &MI) {
383   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
384   const auto *TRI = SubTarget.getRegisterInfo();
385   assert(TRI && "Expected target register info");
386   const auto *TII = SubTarget.getInstrInfo();
387   assert(TII && "Expected target instruction info");
388   if (MI.isCFIInstruction())
389     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
390 
391   unsigned I = 0, E = MI.getNumOperands();
392   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
393          !MI.getOperand(I).isImplicit();
394        ++I) {
395     if (I)
396       OS << ", ";
397     print(MI.getOperand(I), TRI);
398   }
399 
400   if (I)
401     OS << " = ";
402   if (MI.getFlag(MachineInstr::FrameSetup))
403     OS << "frame-setup ";
404   OS << TII->getName(MI.getOpcode());
405   // TODO: Print the bundling instruction flags, machine mem operands.
406   if (I < E)
407     OS << ' ';
408 
409   bool NeedComma = false;
410   for (; I < E; ++I) {
411     if (NeedComma)
412       OS << ", ";
413     print(MI.getOperand(I), TRI);
414     NeedComma = true;
415   }
416 
417   if (MI.getDebugLoc()) {
418     if (NeedComma)
419       OS << ',';
420     OS << " debug-location ";
421     MI.getDebugLoc()->printAsOperand(OS, MST);
422   }
423 }
424 
425 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
426   OS << "%bb." << MBB.getNumber();
427   if (const auto *BB = MBB.getBasicBlock()) {
428     if (BB->hasName())
429       OS << '.' << BB->getName();
430   }
431 }
432 
433 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
434   OS << "%ir-block.";
435   if (BB.hasName()) {
436     printLLVMNameWithoutPrefix(OS, BB.getName());
437     return;
438   }
439   int Slot = MST.getLocalSlot(&BB);
440   if (Slot == -1)
441     OS << "<badref>";
442   else
443     OS << Slot;
444 }
445 
446 void MIPrinter::printStackObjectReference(int FrameIndex) {
447   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
448   assert(ObjectInfo != StackObjectOperandMapping.end() &&
449          "Invalid frame index");
450   const FrameIndexOperand &Operand = ObjectInfo->second;
451   if (Operand.IsFixed) {
452     OS << "%fixed-stack." << Operand.ID;
453     return;
454   }
455   OS << "%stack." << Operand.ID;
456   if (!Operand.Name.empty())
457     OS << '.' << Operand.Name;
458 }
459 
460 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
461   const auto *TII = MF.getSubtarget().getInstrInfo();
462   assert(TII && "expected instruction info");
463   auto Indices = TII->getSerializableTargetIndices();
464   for (const auto &I : Indices) {
465     if (I.first == Index) {
466       return I.second;
467     }
468   }
469   return nullptr;
470 }
471 
472 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
473   switch (Op.getType()) {
474   case MachineOperand::MO_Register:
475     // TODO: Print the other register flags.
476     if (Op.isImplicit())
477       OS << (Op.isDef() ? "implicit-def " : "implicit ");
478     if (Op.isDead())
479       OS << "dead ";
480     if (Op.isKill())
481       OS << "killed ";
482     if (Op.isUndef())
483       OS << "undef ";
484     printReg(Op.getReg(), OS, TRI);
485     // Print the sub register.
486     if (Op.getSubReg() != 0)
487       OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
488     break;
489   case MachineOperand::MO_Immediate:
490     OS << Op.getImm();
491     break;
492   case MachineOperand::MO_MachineBasicBlock:
493     printMBBReference(*Op.getMBB());
494     break;
495   case MachineOperand::MO_FrameIndex:
496     printStackObjectReference(Op.getIndex());
497     break;
498   case MachineOperand::MO_ConstantPoolIndex:
499     OS << "%const." << Op.getIndex();
500     // TODO: Print offset and target flags.
501     break;
502   case MachineOperand::MO_TargetIndex: {
503     OS << "target-index(";
504     if (const auto *Name = getTargetIndexName(
505             *Op.getParent()->getParent()->getParent(), Op.getIndex()))
506       OS << Name;
507     else
508       OS << "<unknown>";
509     OS << ')';
510     // TODO: Print the offset and target flags.
511     break;
512   }
513   case MachineOperand::MO_JumpTableIndex:
514     OS << "%jump-table." << Op.getIndex();
515     // TODO: Print target flags.
516     break;
517   case MachineOperand::MO_ExternalSymbol:
518     OS << '$';
519     printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
520     // TODO: Print the target flags.
521     break;
522   case MachineOperand::MO_GlobalAddress:
523     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
524     // TODO: Print offset and target flags.
525     break;
526   case MachineOperand::MO_BlockAddress:
527     OS << "blockaddress(";
528     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
529                                                         MST);
530     OS << ", ";
531     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
532     OS << ')';
533     // TODO: Print offset and target flags.
534     break;
535   case MachineOperand::MO_RegisterMask: {
536     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
537     if (RegMaskInfo != RegisterMaskIds.end())
538       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
539     else
540       llvm_unreachable("Can't print this machine register mask yet.");
541     break;
542   }
543   case MachineOperand::MO_Metadata:
544     Op.getMetadata()->printAsOperand(OS, MST);
545     break;
546   case MachineOperand::MO_CFIIndex: {
547     const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
548     print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
549     break;
550   }
551   default:
552     // TODO: Print the other machine operands.
553     llvm_unreachable("Can't print this machine operand at the moment");
554   }
555 }
556 
557 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
558                              const TargetRegisterInfo *TRI) {
559   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
560   if (Reg == -1) {
561     OS << "<badreg>";
562     return;
563   }
564   printReg(Reg, OS, TRI);
565 }
566 
567 void MIPrinter::print(const MCCFIInstruction &CFI,
568                       const TargetRegisterInfo *TRI) {
569   switch (CFI.getOperation()) {
570   case MCCFIInstruction::OpOffset:
571     OS << ".cfi_offset ";
572     if (CFI.getLabel())
573       OS << "<mcsymbol> ";
574     printCFIRegister(CFI.getRegister(), OS, TRI);
575     OS << ", " << CFI.getOffset();
576     break;
577   case MCCFIInstruction::OpDefCfaRegister:
578     OS << ".cfi_def_cfa_register ";
579     if (CFI.getLabel())
580       OS << "<mcsymbol> ";
581     printCFIRegister(CFI.getRegister(), OS, TRI);
582     break;
583   case MCCFIInstruction::OpDefCfaOffset:
584     OS << ".cfi_def_cfa_offset ";
585     if (CFI.getLabel())
586       OS << "<mcsymbol> ";
587     OS << CFI.getOffset();
588     break;
589   default:
590     // TODO: Print the other CFI Operations.
591     OS << "<unserializable cfi operation>";
592     break;
593   }
594 }
595 
596 void llvm::printMIR(raw_ostream &OS, const Module &M) {
597   yaml::Output Out(OS);
598   Out << const_cast<Module &>(M);
599 }
600 
601 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
602   MIRPrinter Printer(OS);
603   Printer.print(MF);
604 }
605