1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
26 #include "llvm/CodeGen/MIRYamlMapping.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalValue.h"
46 #include "llvm/IR/IRPrintingPasses.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/ModuleSlotTracker.h"
52 #include "llvm/IR/Value.h"
53 #include "llvm/MC/LaneBitmask.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132 
133 private:
134   void initRegisterMaskIds(const MachineFunction &MF);
135 };
136 
137 /// This class prints out the machine instructions using the MIR serialization
138 /// format.
139 class MIPrinter {
140   raw_ostream &OS;
141   ModuleSlotTracker &MST;
142   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144   /// Synchronization scope names registered with LLVMContext.
145   SmallVector<StringRef, 8> SSNs;
146 
147   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
149 
150 public:
151   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155         StackObjectOperandMapping(StackObjectOperandMapping) {}
156 
157   void print(const MachineBasicBlock &MBB);
158 
159   void print(const MachineInstr &MI);
160   void printIRBlockReference(const BasicBlock &BB);
161   void printIRValueReference(const Value &V);
162   void printStackObjectReference(int FrameIndex);
163   void printOffset(int64_t Offset);
164   void printTargetFlags(const MachineOperand &Op);
165   void print(const MachineInstr &MI, unsigned OpIdx,
166              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
167              LLT TypeToPrint, bool IsDef = false);
168   void print(const LLVMContext &Context, const TargetInstrInfo &TII,
169              const MachineMemOperand &Op);
170   void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID);
171 
172   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
173 };
174 
175 } // end namespace llvm
176 
177 namespace llvm {
178 namespace yaml {
179 
180 /// This struct serializes the LLVM IR module.
181 template <> struct BlockScalarTraits<Module> {
182   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
183     Mod.print(OS, nullptr);
184   }
185 
186   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
187     llvm_unreachable("LLVM Module is supposed to be parsed separately");
188     return "";
189   }
190 };
191 
192 } // end namespace yaml
193 } // end namespace llvm
194 
195 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
196                         const TargetRegisterInfo *TRI) {
197   raw_string_ostream OS(Dest.Value);
198   OS << printReg(Reg, TRI);
199 }
200 
201 void MIRPrinter::print(const MachineFunction &MF) {
202   initRegisterMaskIds(MF);
203 
204   yaml::MachineFunction YamlMF;
205   YamlMF.Name = MF.getName();
206   YamlMF.Alignment = MF.getAlignment();
207   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
208 
209   YamlMF.Legalized = MF.getProperties().hasProperty(
210       MachineFunctionProperties::Property::Legalized);
211   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
212       MachineFunctionProperties::Property::RegBankSelected);
213   YamlMF.Selected = MF.getProperties().hasProperty(
214       MachineFunctionProperties::Property::Selected);
215 
216   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
217   ModuleSlotTracker MST(MF.getFunction()->getParent());
218   MST.incorporateFunction(*MF.getFunction());
219   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
220   convertStackObjects(YamlMF, MF, MST);
221   if (const auto *ConstantPool = MF.getConstantPool())
222     convert(YamlMF, *ConstantPool);
223   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
224     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
225   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
226   bool IsNewlineNeeded = false;
227   for (const auto &MBB : MF) {
228     if (IsNewlineNeeded)
229       StrOS << "\n";
230     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
231         .print(MBB);
232     IsNewlineNeeded = true;
233   }
234   StrOS.flush();
235   yaml::Output Out(OS);
236   if (!SimplifyMIR)
237       Out.setWriteDefaultValues(true);
238   Out << YamlMF;
239 }
240 
241 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
242                                const TargetRegisterInfo *TRI) {
243   assert(RegMask && "Can't print an empty register mask");
244   OS << StringRef("CustomRegMask(");
245 
246   bool IsRegInRegMaskFound = false;
247   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
248     // Check whether the register is asserted in regmask.
249     if (RegMask[I / 32] & (1u << (I % 32))) {
250       if (IsRegInRegMaskFound)
251         OS << ',';
252       OS << printReg(I, TRI);
253       IsRegInRegMaskFound = true;
254     }
255   }
256 
257   OS << ')';
258 }
259 
260 static void printRegClassOrBank(unsigned Reg, raw_ostream &OS,
261                                 const MachineRegisterInfo &RegInfo,
262                                 const TargetRegisterInfo *TRI) {
263   if (RegInfo.getRegClassOrNull(Reg))
264     OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
265   else if (RegInfo.getRegBankOrNull(Reg))
266     OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
267   else {
268     OS << "_";
269     assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
270            "Generic registers must have a valid type");
271   }
272 }
273 
274 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
275                                 const MachineRegisterInfo &RegInfo,
276                                 const TargetRegisterInfo *TRI) {
277   raw_string_ostream OS(Dest.Value);
278   printRegClassOrBank(Reg, OS, RegInfo, TRI);
279 }
280 
281 
282 void MIRPrinter::convert(yaml::MachineFunction &MF,
283                          const MachineRegisterInfo &RegInfo,
284                          const TargetRegisterInfo *TRI) {
285   MF.TracksRegLiveness = RegInfo.tracksLiveness();
286 
287   // Print the virtual register definitions.
288   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
289     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
290     yaml::VirtualRegisterDefinition VReg;
291     VReg.ID = I;
292     printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
293     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
294     if (PreferredReg)
295       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
296     MF.VirtualRegisters.push_back(VReg);
297   }
298 
299   // Print the live ins.
300   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
301     yaml::MachineFunctionLiveIn LiveIn;
302     printRegMIR(LI.first, LiveIn.Register, TRI);
303     if (LI.second)
304       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
305     MF.LiveIns.push_back(LiveIn);
306   }
307 
308   // Prints the callee saved registers.
309   if (RegInfo.isUpdatedCSRsInitialized()) {
310     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
311     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
312     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
313       yaml::FlowStringValue Reg;
314       printRegMIR(*I, Reg, TRI);
315       CalleeSavedRegisters.push_back(Reg);
316     }
317     MF.CalleeSavedRegisters = CalleeSavedRegisters;
318   }
319 }
320 
321 void MIRPrinter::convert(ModuleSlotTracker &MST,
322                          yaml::MachineFrameInfo &YamlMFI,
323                          const MachineFrameInfo &MFI) {
324   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
325   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
326   YamlMFI.HasStackMap = MFI.hasStackMap();
327   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
328   YamlMFI.StackSize = MFI.getStackSize();
329   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
330   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
331   YamlMFI.AdjustsStack = MFI.adjustsStack();
332   YamlMFI.HasCalls = MFI.hasCalls();
333   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
334     ? MFI.getMaxCallFrameSize() : ~0u;
335   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
336   YamlMFI.HasVAStart = MFI.hasVAStart();
337   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
338   if (MFI.getSavePoint()) {
339     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
340     StrOS << printMBBReference(*MFI.getSavePoint());
341   }
342   if (MFI.getRestorePoint()) {
343     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
344     StrOS << printMBBReference(*MFI.getRestorePoint());
345   }
346 }
347 
348 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
349                                      const MachineFunction &MF,
350                                      ModuleSlotTracker &MST) {
351   const MachineFrameInfo &MFI = MF.getFrameInfo();
352   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
353   // Process fixed stack objects.
354   unsigned ID = 0;
355   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
356     if (MFI.isDeadObjectIndex(I))
357       continue;
358 
359     yaml::FixedMachineStackObject YamlObject;
360     YamlObject.ID = ID;
361     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
362                           ? yaml::FixedMachineStackObject::SpillSlot
363                           : yaml::FixedMachineStackObject::DefaultType;
364     YamlObject.Offset = MFI.getObjectOffset(I);
365     YamlObject.Size = MFI.getObjectSize(I);
366     YamlObject.Alignment = MFI.getObjectAlignment(I);
367     YamlObject.StackID = MFI.getStackID(I);
368     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
369     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
370     YMF.FixedStackObjects.push_back(YamlObject);
371     StackObjectOperandMapping.insert(
372         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
373   }
374 
375   // Process ordinary stack objects.
376   ID = 0;
377   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
378     if (MFI.isDeadObjectIndex(I))
379       continue;
380 
381     yaml::MachineStackObject YamlObject;
382     YamlObject.ID = ID;
383     if (const auto *Alloca = MFI.getObjectAllocation(I))
384       YamlObject.Name.Value =
385           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
386     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
387                           ? yaml::MachineStackObject::SpillSlot
388                           : MFI.isVariableSizedObjectIndex(I)
389                                 ? yaml::MachineStackObject::VariableSized
390                                 : yaml::MachineStackObject::DefaultType;
391     YamlObject.Offset = MFI.getObjectOffset(I);
392     YamlObject.Size = MFI.getObjectSize(I);
393     YamlObject.Alignment = MFI.getObjectAlignment(I);
394     YamlObject.StackID = MFI.getStackID(I);
395 
396     YMF.StackObjects.push_back(YamlObject);
397     StackObjectOperandMapping.insert(std::make_pair(
398         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
399   }
400 
401   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
402     yaml::StringValue Reg;
403     printRegMIR(CSInfo.getReg(), Reg, TRI);
404     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
405     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
406            "Invalid stack object index");
407     const FrameIndexOperand &StackObject = StackObjectInfo->second;
408     if (StackObject.IsFixed) {
409       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
410       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
411         CSInfo.isRestored();
412     } else {
413       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
414       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
415         CSInfo.isRestored();
416     }
417   }
418   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
419     auto LocalObject = MFI.getLocalFrameObjectMap(I);
420     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
421     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
422            "Invalid stack object index");
423     const FrameIndexOperand &StackObject = StackObjectInfo->second;
424     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
425     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
426   }
427 
428   // Print the stack object references in the frame information class after
429   // converting the stack objects.
430   if (MFI.hasStackProtectorIndex()) {
431     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
432     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
433         .printStackObjectReference(MFI.getStackProtectorIndex());
434   }
435 
436   // Print the debug variable information.
437   for (const MachineFunction::VariableDbgInfo &DebugVar :
438        MF.getVariableDbgInfo()) {
439     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
440     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
441            "Invalid stack object index");
442     const FrameIndexOperand &StackObject = StackObjectInfo->second;
443     assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
444     auto &Object = YMF.StackObjects[StackObject.ID];
445     {
446       raw_string_ostream StrOS(Object.DebugVar.Value);
447       DebugVar.Var->printAsOperand(StrOS, MST);
448     }
449     {
450       raw_string_ostream StrOS(Object.DebugExpr.Value);
451       DebugVar.Expr->printAsOperand(StrOS, MST);
452     }
453     {
454       raw_string_ostream StrOS(Object.DebugLoc.Value);
455       DebugVar.Loc->printAsOperand(StrOS, MST);
456     }
457   }
458 }
459 
460 void MIRPrinter::convert(yaml::MachineFunction &MF,
461                          const MachineConstantPool &ConstantPool) {
462   unsigned ID = 0;
463   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
464     std::string Str;
465     raw_string_ostream StrOS(Str);
466     if (Constant.isMachineConstantPoolEntry()) {
467       Constant.Val.MachineCPVal->print(StrOS);
468     } else {
469       Constant.Val.ConstVal->printAsOperand(StrOS);
470     }
471 
472     yaml::MachineConstantPoolValue YamlConstant;
473     YamlConstant.ID = ID++;
474     YamlConstant.Value = StrOS.str();
475     YamlConstant.Alignment = Constant.getAlignment();
476     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
477 
478     MF.Constants.push_back(YamlConstant);
479   }
480 }
481 
482 void MIRPrinter::convert(ModuleSlotTracker &MST,
483                          yaml::MachineJumpTable &YamlJTI,
484                          const MachineJumpTableInfo &JTI) {
485   YamlJTI.Kind = JTI.getEntryKind();
486   unsigned ID = 0;
487   for (const auto &Table : JTI.getJumpTables()) {
488     std::string Str;
489     yaml::MachineJumpTable::Entry Entry;
490     Entry.ID = ID++;
491     for (const auto *MBB : Table.MBBs) {
492       raw_string_ostream StrOS(Str);
493       StrOS << printMBBReference(*MBB);
494       Entry.Blocks.push_back(StrOS.str());
495       Str.clear();
496     }
497     YamlJTI.Entries.push_back(Entry);
498   }
499 }
500 
501 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
502   const auto *TRI = MF.getSubtarget().getRegisterInfo();
503   unsigned I = 0;
504   for (const uint32_t *Mask : TRI->getRegMasks())
505     RegisterMaskIds.insert(std::make_pair(Mask, I++));
506 }
507 
508 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
509                            SmallVectorImpl<MachineBasicBlock*> &Result,
510                            bool &IsFallthrough) {
511   SmallPtrSet<MachineBasicBlock*,8> Seen;
512 
513   for (const MachineInstr &MI : MBB) {
514     if (MI.isPHI())
515       continue;
516     for (const MachineOperand &MO : MI.operands()) {
517       if (!MO.isMBB())
518         continue;
519       MachineBasicBlock *Succ = MO.getMBB();
520       auto RP = Seen.insert(Succ);
521       if (RP.second)
522         Result.push_back(Succ);
523     }
524   }
525   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
526   IsFallthrough = I == MBB.end() || !I->isBarrier();
527 }
528 
529 bool
530 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
531   if (MBB.succ_size() <= 1)
532     return true;
533   if (!MBB.hasSuccessorProbabilities())
534     return true;
535 
536   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
537                                               MBB.Probs.end());
538   BranchProbability::normalizeProbabilities(Normalized.begin(),
539                                             Normalized.end());
540   SmallVector<BranchProbability,8> Equal(Normalized.size());
541   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
542 
543   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
544 }
545 
546 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
547   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
548   bool GuessedFallthrough;
549   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
550   if (GuessedFallthrough) {
551     const MachineFunction &MF = *MBB.getParent();
552     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
553     if (NextI != MF.end()) {
554       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
555       if (!is_contained(GuessedSuccs, Next))
556         GuessedSuccs.push_back(Next);
557     }
558   }
559   if (GuessedSuccs.size() != MBB.succ_size())
560     return false;
561   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
562 }
563 
564 void MIPrinter::print(const MachineBasicBlock &MBB) {
565   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
566   OS << "bb." << MBB.getNumber();
567   bool HasAttributes = false;
568   if (const auto *BB = MBB.getBasicBlock()) {
569     if (BB->hasName()) {
570       OS << "." << BB->getName();
571     } else {
572       HasAttributes = true;
573       OS << " (";
574       int Slot = MST.getLocalSlot(BB);
575       if (Slot == -1)
576         OS << "<ir-block badref>";
577       else
578         OS << (Twine("%ir-block.") + Twine(Slot)).str();
579     }
580   }
581   if (MBB.hasAddressTaken()) {
582     OS << (HasAttributes ? ", " : " (");
583     OS << "address-taken";
584     HasAttributes = true;
585   }
586   if (MBB.isEHPad()) {
587     OS << (HasAttributes ? ", " : " (");
588     OS << "landing-pad";
589     HasAttributes = true;
590   }
591   if (MBB.getAlignment()) {
592     OS << (HasAttributes ? ", " : " (");
593     OS << "align " << MBB.getAlignment();
594     HasAttributes = true;
595   }
596   if (HasAttributes)
597     OS << ")";
598   OS << ":\n";
599 
600   bool HasLineAttributes = false;
601   // Print the successors
602   bool canPredictProbs = canPredictBranchProbabilities(MBB);
603   // Even if the list of successors is empty, if we cannot guess it,
604   // we need to print it to tell the parser that the list is empty.
605   // This is needed, because MI model unreachable as empty blocks
606   // with an empty successor list. If the parser would see that
607   // without the successor list, it would guess the code would
608   // fallthrough.
609   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
610       !canPredictSuccessors(MBB)) {
611     OS.indent(2) << "successors: ";
612     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
613       if (I != MBB.succ_begin())
614         OS << ", ";
615       OS << printMBBReference(**I);
616       if (!SimplifyMIR || !canPredictProbs)
617         OS << '('
618            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
619            << ')';
620     }
621     OS << "\n";
622     HasLineAttributes = true;
623   }
624 
625   // Print the live in registers.
626   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
627   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
628     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
629     OS.indent(2) << "liveins: ";
630     bool First = true;
631     for (const auto &LI : MBB.liveins()) {
632       if (!First)
633         OS << ", ";
634       First = false;
635       OS << printReg(LI.PhysReg, &TRI);
636       if (!LI.LaneMask.all())
637         OS << ":0x" << PrintLaneMask(LI.LaneMask);
638     }
639     OS << "\n";
640     HasLineAttributes = true;
641   }
642 
643   if (HasLineAttributes)
644     OS << "\n";
645   bool IsInBundle = false;
646   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
647     const MachineInstr &MI = *I;
648     if (IsInBundle && !MI.isInsideBundle()) {
649       OS.indent(2) << "}\n";
650       IsInBundle = false;
651     }
652     OS.indent(IsInBundle ? 4 : 2);
653     print(MI);
654     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
655       OS << " {";
656       IsInBundle = true;
657     }
658     OS << "\n";
659   }
660   if (IsInBundle)
661     OS.indent(2) << "}\n";
662 }
663 
664 /// Return true when an instruction has tied register that can't be determined
665 /// by the instruction's descriptor.
666 static bool hasComplexRegisterTies(const MachineInstr &MI) {
667   const MCInstrDesc &MCID = MI.getDesc();
668   for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
669     const auto &Operand = MI.getOperand(I);
670     if (!Operand.isReg() || Operand.isDef())
671       // Ignore the defined registers as MCID marks only the uses as tied.
672       continue;
673     int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
674     int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
675     if (ExpectedTiedIdx != TiedIdx)
676       return true;
677   }
678   return false;
679 }
680 
681 static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
682                           SmallBitVector &PrintedTypes,
683                           const MachineRegisterInfo &MRI) {
684   const MachineOperand &Op = MI.getOperand(OpIdx);
685   if (!Op.isReg())
686     return LLT{};
687 
688   if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
689     return MRI.getType(Op.getReg());
690 
691   auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
692   if (!OpInfo.isGenericType())
693     return MRI.getType(Op.getReg());
694 
695   if (PrintedTypes[OpInfo.getGenericTypeIndex()])
696     return LLT{};
697 
698   PrintedTypes.set(OpInfo.getGenericTypeIndex());
699   return MRI.getType(Op.getReg());
700 }
701 
702 void MIPrinter::print(const MachineInstr &MI) {
703   const auto *MF = MI.getMF();
704   const auto &MRI = MF->getRegInfo();
705   const auto &SubTarget = MF->getSubtarget();
706   const auto *TRI = SubTarget.getRegisterInfo();
707   assert(TRI && "Expected target register info");
708   const auto *TII = SubTarget.getInstrInfo();
709   assert(TII && "Expected target instruction info");
710   if (MI.isCFIInstruction())
711     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
712 
713   SmallBitVector PrintedTypes(8);
714   bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
715   unsigned I = 0, E = MI.getNumOperands();
716   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
717          !MI.getOperand(I).isImplicit();
718        ++I) {
719     if (I)
720       OS << ", ";
721     print(MI, I, TRI, ShouldPrintRegisterTies,
722           getTypeToPrint(MI, I, PrintedTypes, MRI),
723           /*IsDef=*/true);
724   }
725 
726   if (I)
727     OS << " = ";
728   if (MI.getFlag(MachineInstr::FrameSetup))
729     OS << "frame-setup ";
730   OS << TII->getName(MI.getOpcode());
731   if (I < E)
732     OS << ' ';
733 
734   bool NeedComma = false;
735   for (; I < E; ++I) {
736     if (NeedComma)
737       OS << ", ";
738     print(MI, I, TRI, ShouldPrintRegisterTies,
739           getTypeToPrint(MI, I, PrintedTypes, MRI));
740     NeedComma = true;
741   }
742 
743   if (MI.getDebugLoc()) {
744     if (NeedComma)
745       OS << ',';
746     OS << " debug-location ";
747     MI.getDebugLoc()->printAsOperand(OS, MST);
748   }
749 
750   if (!MI.memoperands_empty()) {
751     OS << " :: ";
752     const LLVMContext &Context = MF->getFunction()->getContext();
753     bool NeedComma = false;
754     for (const auto *Op : MI.memoperands()) {
755       if (NeedComma)
756         OS << ", ";
757       print(Context, *TII, *Op);
758       NeedComma = true;
759     }
760   }
761 }
762 
763 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
764   if (Slot == -1)
765     OS << "<badref>";
766   else
767     OS << Slot;
768 }
769 
770 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
771   OS << "%ir-block.";
772   if (BB.hasName()) {
773     printLLVMNameWithoutPrefix(OS, BB.getName());
774     return;
775   }
776   const Function *F = BB.getParent();
777   int Slot;
778   if (F == MST.getCurrentFunction()) {
779     Slot = MST.getLocalSlot(&BB);
780   } else {
781     ModuleSlotTracker CustomMST(F->getParent(),
782                                 /*ShouldInitializeAllMetadata=*/false);
783     CustomMST.incorporateFunction(*F);
784     Slot = CustomMST.getLocalSlot(&BB);
785   }
786   printIRSlotNumber(OS, Slot);
787 }
788 
789 void MIPrinter::printIRValueReference(const Value &V) {
790   if (isa<GlobalValue>(V)) {
791     V.printAsOperand(OS, /*PrintType=*/false, MST);
792     return;
793   }
794   if (isa<Constant>(V)) {
795     // Machine memory operands can load/store to/from constant value pointers.
796     OS << '`';
797     V.printAsOperand(OS, /*PrintType=*/true, MST);
798     OS << '`';
799     return;
800   }
801   OS << "%ir.";
802   if (V.hasName()) {
803     printLLVMNameWithoutPrefix(OS, V.getName());
804     return;
805   }
806   printIRSlotNumber(OS, MST.getLocalSlot(&V));
807 }
808 
809 void MIPrinter::printStackObjectReference(int FrameIndex) {
810   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
811   assert(ObjectInfo != StackObjectOperandMapping.end() &&
812          "Invalid frame index");
813   const FrameIndexOperand &Operand = ObjectInfo->second;
814   if (Operand.IsFixed) {
815     OS << "%fixed-stack." << Operand.ID;
816     return;
817   }
818   OS << "%stack." << Operand.ID;
819   if (!Operand.Name.empty())
820     OS << '.' << Operand.Name;
821 }
822 
823 void MIPrinter::printOffset(int64_t Offset) {
824   if (Offset == 0)
825     return;
826   if (Offset < 0) {
827     OS << " - " << -Offset;
828     return;
829   }
830   OS << " + " << Offset;
831 }
832 
833 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
834   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
835   for (const auto &I : Flags) {
836     if (I.first == TF) {
837       return I.second;
838     }
839   }
840   return nullptr;
841 }
842 
843 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
844   if (!Op.getTargetFlags())
845     return;
846   const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
847   assert(TII && "expected instruction info");
848   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
849   OS << "target-flags(";
850   const bool HasDirectFlags = Flags.first;
851   const bool HasBitmaskFlags = Flags.second;
852   if (!HasDirectFlags && !HasBitmaskFlags) {
853     OS << "<unknown>) ";
854     return;
855   }
856   if (HasDirectFlags) {
857     if (const auto *Name = getTargetFlagName(TII, Flags.first))
858       OS << Name;
859     else
860       OS << "<unknown target flag>";
861   }
862   if (!HasBitmaskFlags) {
863     OS << ") ";
864     return;
865   }
866   bool IsCommaNeeded = HasDirectFlags;
867   unsigned BitMask = Flags.second;
868   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
869   for (const auto &Mask : BitMasks) {
870     // Check if the flag's bitmask has the bits of the current mask set.
871     if ((BitMask & Mask.first) == Mask.first) {
872       if (IsCommaNeeded)
873         OS << ", ";
874       IsCommaNeeded = true;
875       OS << Mask.second;
876       // Clear the bits which were serialized from the flag's bitmask.
877       BitMask &= ~(Mask.first);
878     }
879   }
880   if (BitMask) {
881     // When the resulting flag's bitmask isn't zero, we know that we didn't
882     // serialize all of the bit flags.
883     if (IsCommaNeeded)
884       OS << ", ";
885     OS << "<unknown bitmask target flag>";
886   }
887   OS << ") ";
888 }
889 
890 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
891   const auto *TII = MF.getSubtarget().getInstrInfo();
892   assert(TII && "expected instruction info");
893   auto Indices = TII->getSerializableTargetIndices();
894   for (const auto &I : Indices) {
895     if (I.first == Index) {
896       return I.second;
897     }
898   }
899   return nullptr;
900 }
901 
902 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
903                       const TargetRegisterInfo *TRI,
904                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
905                       bool IsDef) {
906   const MachineOperand &Op = MI.getOperand(OpIdx);
907   printTargetFlags(Op);
908   switch (Op.getType()) {
909   case MachineOperand::MO_Register: {
910     unsigned Reg = Op.getReg();
911     if (Op.isImplicit())
912       OS << (Op.isDef() ? "implicit-def " : "implicit ");
913     else if (!IsDef && Op.isDef())
914       // Print the 'def' flag only when the operand is defined after '='.
915       OS << "def ";
916     if (Op.isInternalRead())
917       OS << "internal ";
918     if (Op.isDead())
919       OS << "dead ";
920     if (Op.isKill())
921       OS << "killed ";
922     if (Op.isUndef())
923       OS << "undef ";
924     if (Op.isEarlyClobber())
925       OS << "early-clobber ";
926     if (Op.isDebug())
927       OS << "debug-use ";
928     OS << printReg(Reg, TRI);
929     // Print the sub register.
930     if (Op.getSubReg() != 0)
931       OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
932     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
933       const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo();
934       if (IsDef || MRI.def_empty(Reg)) {
935         OS << ':';
936         printRegClassOrBank(Reg, OS, MRI, TRI);
937       }
938     }
939     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
940       OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(OpIdx) << ")";
941     if (TypeToPrint.isValid())
942       OS << '(' << TypeToPrint << ')';
943     break;
944   }
945   case MachineOperand::MO_Immediate:
946     if (MI.isOperandSubregIdx(OpIdx))
947       OS << "%subreg." << TRI->getSubRegIndexName(Op.getImm());
948     else
949       OS << Op.getImm();
950     break;
951   case MachineOperand::MO_CImmediate:
952     Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
953     break;
954   case MachineOperand::MO_FPImmediate:
955     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
956     break;
957   case MachineOperand::MO_MachineBasicBlock:
958     OS << printMBBReference(*Op.getMBB());
959     break;
960   case MachineOperand::MO_FrameIndex:
961     printStackObjectReference(Op.getIndex());
962     break;
963   case MachineOperand::MO_ConstantPoolIndex:
964     OS << "%const." << Op.getIndex();
965     printOffset(Op.getOffset());
966     break;
967   case MachineOperand::MO_TargetIndex:
968     OS << "target-index(";
969     if (const auto *Name =
970             getTargetIndexName(*Op.getParent()->getMF(), Op.getIndex()))
971       OS << Name;
972     else
973       OS << "<unknown>";
974     OS << ')';
975     printOffset(Op.getOffset());
976     break;
977   case MachineOperand::MO_JumpTableIndex:
978     OS << "%jump-table." << Op.getIndex();
979     break;
980   case MachineOperand::MO_ExternalSymbol: {
981     StringRef Name = Op.getSymbolName();
982     OS << '$';
983     if (Name.empty()) {
984       OS << "\"\"";
985     } else {
986       printLLVMNameWithoutPrefix(OS, Name);
987     }
988     printOffset(Op.getOffset());
989     break;
990   }
991   case MachineOperand::MO_GlobalAddress:
992     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
993     printOffset(Op.getOffset());
994     break;
995   case MachineOperand::MO_BlockAddress:
996     OS << "blockaddress(";
997     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
998                                                         MST);
999     OS << ", ";
1000     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
1001     OS << ')';
1002     printOffset(Op.getOffset());
1003     break;
1004   case MachineOperand::MO_RegisterMask: {
1005     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
1006     if (RegMaskInfo != RegisterMaskIds.end())
1007       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
1008     else
1009       printCustomRegMask(Op.getRegMask(), OS, TRI);
1010     break;
1011   }
1012   case MachineOperand::MO_RegisterLiveOut: {
1013     const uint32_t *RegMask = Op.getRegLiveOut();
1014     OS << "liveout(";
1015     bool IsCommaNeeded = false;
1016     for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
1017       if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
1018         if (IsCommaNeeded)
1019           OS << ", ";
1020         OS << printReg(Reg, TRI);
1021         IsCommaNeeded = true;
1022       }
1023     }
1024     OS << ")";
1025     break;
1026   }
1027   case MachineOperand::MO_Metadata:
1028     Op.getMetadata()->printAsOperand(OS, MST);
1029     break;
1030   case MachineOperand::MO_MCSymbol:
1031     OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
1032     break;
1033   case MachineOperand::MO_CFIIndex: {
1034     const MachineFunction &MF = *Op.getParent()->getMF();
1035     print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
1036     break;
1037   }
1038   case MachineOperand::MO_IntrinsicID: {
1039     Intrinsic::ID ID = Op.getIntrinsicID();
1040     if (ID < Intrinsic::num_intrinsics)
1041       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
1042     else {
1043       const MachineFunction &MF = *Op.getParent()->getMF();
1044       const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
1045       OS << "intrinsic(@" << TII->getName(ID) << ')';
1046     }
1047     break;
1048   }
1049   case MachineOperand::MO_Predicate: {
1050     auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
1051     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
1052        << CmpInst::getPredicateName(Pred) << ')';
1053     break;
1054   }
1055   }
1056 }
1057 
1058 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
1059                                         unsigned TMMOFlag) {
1060   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
1061   for (const auto &I : Flags) {
1062     if (I.first == TMMOFlag) {
1063       return I.second;
1064     }
1065   }
1066   return nullptr;
1067 }
1068 
1069 void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII,
1070                       const MachineMemOperand &Op) {
1071   OS << '(';
1072   if (Op.isVolatile())
1073     OS << "volatile ";
1074   if (Op.isNonTemporal())
1075     OS << "non-temporal ";
1076   if (Op.isDereferenceable())
1077     OS << "dereferenceable ";
1078   if (Op.isInvariant())
1079     OS << "invariant ";
1080   if (Op.getFlags() & MachineMemOperand::MOTargetFlag1)
1081     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag1)
1082        << "\" ";
1083   if (Op.getFlags() & MachineMemOperand::MOTargetFlag2)
1084     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag2)
1085        << "\" ";
1086   if (Op.getFlags() & MachineMemOperand::MOTargetFlag3)
1087     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag3)
1088        << "\" ";
1089 
1090   assert((Op.isLoad() || Op.isStore()) && "machine memory operand must be a load or store (or both)");
1091   if (Op.isLoad())
1092     OS << "load ";
1093   if (Op.isStore())
1094     OS << "store ";
1095 
1096   printSyncScope(Context, Op.getSyncScopeID());
1097 
1098   if (Op.getOrdering() != AtomicOrdering::NotAtomic)
1099     OS << toIRString(Op.getOrdering()) << ' ';
1100   if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
1101     OS << toIRString(Op.getFailureOrdering()) << ' ';
1102 
1103   OS << Op.getSize();
1104   if (const Value *Val = Op.getValue()) {
1105     OS << ((Op.isLoad() && Op.isStore()) ? " on "
1106                                          : Op.isLoad() ? " from " : " into ");
1107     printIRValueReference(*Val);
1108   } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
1109     OS << ((Op.isLoad() && Op.isStore()) ? " on "
1110                                          : Op.isLoad() ? " from " : " into ");
1111     assert(PVal && "Expected a pseudo source value");
1112     switch (PVal->kind()) {
1113     case PseudoSourceValue::Stack:
1114       OS << "stack";
1115       break;
1116     case PseudoSourceValue::GOT:
1117       OS << "got";
1118       break;
1119     case PseudoSourceValue::JumpTable:
1120       OS << "jump-table";
1121       break;
1122     case PseudoSourceValue::ConstantPool:
1123       OS << "constant-pool";
1124       break;
1125     case PseudoSourceValue::FixedStack:
1126       printStackObjectReference(
1127           cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
1128       break;
1129     case PseudoSourceValue::GlobalValueCallEntry:
1130       OS << "call-entry ";
1131       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1132           OS, /*PrintType=*/false, MST);
1133       break;
1134     case PseudoSourceValue::ExternalSymbolCallEntry:
1135       OS << "call-entry $";
1136       printLLVMNameWithoutPrefix(
1137           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1138       break;
1139     case PseudoSourceValue::TargetCustom:
1140       llvm_unreachable("TargetCustom pseudo source values are not supported");
1141       break;
1142     }
1143   }
1144   printOffset(Op.getOffset());
1145   if (Op.getBaseAlignment() != Op.getSize())
1146     OS << ", align " << Op.getBaseAlignment();
1147   auto AAInfo = Op.getAAInfo();
1148   if (AAInfo.TBAA) {
1149     OS << ", !tbaa ";
1150     AAInfo.TBAA->printAsOperand(OS, MST);
1151   }
1152   if (AAInfo.Scope) {
1153     OS << ", !alias.scope ";
1154     AAInfo.Scope->printAsOperand(OS, MST);
1155   }
1156   if (AAInfo.NoAlias) {
1157     OS << ", !noalias ";
1158     AAInfo.NoAlias->printAsOperand(OS, MST);
1159   }
1160   if (Op.getRanges()) {
1161     OS << ", !range ";
1162     Op.getRanges()->printAsOperand(OS, MST);
1163   }
1164   OS << ')';
1165 }
1166 
1167 void MIPrinter::printSyncScope(const LLVMContext &Context, SyncScope::ID SSID) {
1168   switch (SSID) {
1169   case SyncScope::System: {
1170     break;
1171   }
1172   default: {
1173     if (SSNs.empty())
1174       Context.getSyncScopeNames(SSNs);
1175 
1176     OS << "syncscope(\"";
1177     PrintEscapedString(SSNs[SSID], OS);
1178     OS << "\") ";
1179     break;
1180   }
1181   }
1182 }
1183 
1184 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
1185                              const TargetRegisterInfo *TRI) {
1186   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
1187   if (Reg == -1) {
1188     OS << "<badreg>";
1189     return;
1190   }
1191   OS << printReg(Reg, TRI);
1192 }
1193 
1194 void MIPrinter::print(const MCCFIInstruction &CFI,
1195                       const TargetRegisterInfo *TRI) {
1196   switch (CFI.getOperation()) {
1197   case MCCFIInstruction::OpSameValue:
1198     OS << "same_value ";
1199     if (CFI.getLabel())
1200       OS << "<mcsymbol> ";
1201     printCFIRegister(CFI.getRegister(), OS, TRI);
1202     break;
1203   case MCCFIInstruction::OpOffset:
1204     OS << "offset ";
1205     if (CFI.getLabel())
1206       OS << "<mcsymbol> ";
1207     printCFIRegister(CFI.getRegister(), OS, TRI);
1208     OS << ", " << CFI.getOffset();
1209     break;
1210   case MCCFIInstruction::OpDefCfaRegister:
1211     OS << "def_cfa_register ";
1212     if (CFI.getLabel())
1213       OS << "<mcsymbol> ";
1214     printCFIRegister(CFI.getRegister(), OS, TRI);
1215     break;
1216   case MCCFIInstruction::OpDefCfaOffset:
1217     OS << "def_cfa_offset ";
1218     if (CFI.getLabel())
1219       OS << "<mcsymbol> ";
1220     OS << CFI.getOffset();
1221     break;
1222   case MCCFIInstruction::OpDefCfa:
1223     OS << "def_cfa ";
1224     if (CFI.getLabel())
1225       OS << "<mcsymbol> ";
1226     printCFIRegister(CFI.getRegister(), OS, TRI);
1227     OS << ", " << CFI.getOffset();
1228     break;
1229   case MCCFIInstruction::OpRestore:
1230     OS << "restore ";
1231     if (CFI.getLabel())
1232       OS << "<mcsymbol> ";
1233     printCFIRegister(CFI.getRegister(), OS, TRI);
1234     break;
1235   default:
1236     // TODO: Print the other CFI Operations.
1237     OS << "<unserializable cfi operation>";
1238     break;
1239   }
1240 }
1241 
1242 void llvm::printMIR(raw_ostream &OS, const Module &M) {
1243   yaml::Output Out(OS);
1244   Out << const_cast<Module &>(M);
1245 }
1246 
1247 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
1248   MIRPrinter Printer(OS);
1249   Printer.print(MF);
1250 }
1251