1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the class that prints out the LLVM IR and machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MIRPrinter.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallBitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24 #include "llvm/CodeGen/MIRYamlMapping.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/TargetInstrInfo.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/IRPrintingPasses.h"
45 #include "llvm/IR/InstrTypes.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/IR/ModuleSlotTracker.h"
50 #include "llvm/IR/Value.h"
51 #include "llvm/MC/LaneBitmask.h"
52 #include "llvm/MC/MCContext.h"
53 #include "llvm/MC/MCDwarf.h"
54 #include "llvm/MC/MCSymbol.h"
55 #include "llvm/Support/AtomicOrdering.h"
56 #include "llvm/Support/BranchProbability.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CommandLine.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/Format.h"
61 #include "llvm/Support/LowLevelTypeImpl.h"
62 #include "llvm/Support/YAMLTraits.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetIntrinsicInfo.h"
65 #include "llvm/Target/TargetMachine.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cinttypes>
69 #include <cstdint>
70 #include <iterator>
71 #include <string>
72 #include <utility>
73 #include <vector>
74 
75 using namespace llvm;
76 
77 static cl::opt<bool> SimplifyMIR(
78     "simplify-mir", cl::Hidden,
79     cl::desc("Leave out unnecessary information when printing MIR"));
80 
81 namespace {
82 
83 /// This structure describes how to print out stack object references.
84 struct FrameIndexOperand {
85   std::string Name;
86   unsigned ID;
87   bool IsFixed;
88 
89   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
90       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
91 
92   /// Return an ordinary stack object reference.
93   static FrameIndexOperand create(StringRef Name, unsigned ID) {
94     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
95   }
96 
97   /// Return a fixed stack object reference.
98   static FrameIndexOperand createFixed(unsigned ID) {
99     return FrameIndexOperand("", ID, /*IsFixed=*/true);
100   }
101 };
102 
103 } // end anonymous namespace
104 
105 namespace llvm {
106 
107 /// This class prints out the machine functions using the MIR serialization
108 /// format.
109 class MIRPrinter {
110   raw_ostream &OS;
111   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
112   /// Maps from stack object indices to operand indices which will be used when
113   /// printing frame index machine operands.
114   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
115 
116 public:
117   MIRPrinter(raw_ostream &OS) : OS(OS) {}
118 
119   void print(const MachineFunction &MF);
120 
121   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
122                const TargetRegisterInfo *TRI);
123   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
124                const MachineFrameInfo &MFI);
125   void convert(yaml::MachineFunction &MF,
126                const MachineConstantPool &ConstantPool);
127   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
128                const MachineJumpTableInfo &JTI);
129   void convertStackObjects(yaml::MachineFunction &YMF,
130                            const MachineFunction &MF, ModuleSlotTracker &MST);
131 
132 private:
133   void initRegisterMaskIds(const MachineFunction &MF);
134 };
135 
136 /// This class prints out the machine instructions using the MIR serialization
137 /// format.
138 class MIPrinter {
139   raw_ostream &OS;
140   ModuleSlotTracker &MST;
141   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
142   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143   /// Synchronization scope names registered with LLVMContext.
144   SmallVector<StringRef, 8> SSNs;
145 
146   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
147   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
148 
149 public:
150   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
151             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
152             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
153       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
154         StackObjectOperandMapping(StackObjectOperandMapping) {}
155 
156   void print(const MachineBasicBlock &MBB);
157 
158   void print(const MachineInstr &MI);
159   void printStackObjectReference(int FrameIndex);
160   void print(const MachineInstr &MI, unsigned OpIdx,
161              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
162              LLT TypeToPrint, bool PrintDef = true);
163 };
164 
165 } // end namespace llvm
166 
167 namespace llvm {
168 namespace yaml {
169 
170 /// This struct serializes the LLVM IR module.
171 template <> struct BlockScalarTraits<Module> {
172   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
173     Mod.print(OS, nullptr);
174   }
175 
176   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
177     llvm_unreachable("LLVM Module is supposed to be parsed separately");
178     return "";
179   }
180 };
181 
182 } // end namespace yaml
183 } // end namespace llvm
184 
185 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
186                         const TargetRegisterInfo *TRI) {
187   raw_string_ostream OS(Dest.Value);
188   OS << printReg(Reg, TRI);
189 }
190 
191 void MIRPrinter::print(const MachineFunction &MF) {
192   initRegisterMaskIds(MF);
193 
194   yaml::MachineFunction YamlMF;
195   YamlMF.Name = MF.getName();
196   YamlMF.Alignment = MF.getAlignment();
197   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
198   YamlMF.HasWinCFI = MF.hasWinCFI();
199 
200   YamlMF.Legalized = MF.getProperties().hasProperty(
201       MachineFunctionProperties::Property::Legalized);
202   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
203       MachineFunctionProperties::Property::RegBankSelected);
204   YamlMF.Selected = MF.getProperties().hasProperty(
205       MachineFunctionProperties::Property::Selected);
206   YamlMF.FailedISel = MF.getProperties().hasProperty(
207       MachineFunctionProperties::Property::FailedISel);
208 
209   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
210   ModuleSlotTracker MST(MF.getFunction().getParent());
211   MST.incorporateFunction(MF.getFunction());
212   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
213   convertStackObjects(YamlMF, MF, MST);
214   if (const auto *ConstantPool = MF.getConstantPool())
215     convert(YamlMF, *ConstantPool);
216   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
217     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
218 
219   const TargetMachine &TM = MF.getTarget();
220   YamlMF.MachineFuncInfo =
221       std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
222 
223   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
224   bool IsNewlineNeeded = false;
225   for (const auto &MBB : MF) {
226     if (IsNewlineNeeded)
227       StrOS << "\n";
228     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
229         .print(MBB);
230     IsNewlineNeeded = true;
231   }
232   StrOS.flush();
233   yaml::Output Out(OS);
234   if (!SimplifyMIR)
235       Out.setWriteDefaultValues(true);
236   Out << YamlMF;
237 }
238 
239 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
240                                const TargetRegisterInfo *TRI) {
241   assert(RegMask && "Can't print an empty register mask");
242   OS << StringRef("CustomRegMask(");
243 
244   bool IsRegInRegMaskFound = false;
245   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
246     // Check whether the register is asserted in regmask.
247     if (RegMask[I / 32] & (1u << (I % 32))) {
248       if (IsRegInRegMaskFound)
249         OS << ',';
250       OS << printReg(I, TRI);
251       IsRegInRegMaskFound = true;
252     }
253   }
254 
255   OS << ')';
256 }
257 
258 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
259                                 const MachineRegisterInfo &RegInfo,
260                                 const TargetRegisterInfo *TRI) {
261   raw_string_ostream OS(Dest.Value);
262   OS << printRegClassOrBank(Reg, RegInfo, TRI);
263 }
264 
265 template <typename T>
266 static void
267 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
268                         T &Object, ModuleSlotTracker &MST) {
269   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
270                                         &Object.DebugExpr.Value,
271                                         &Object.DebugLoc.Value}};
272   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
273                                         DebugVar.Expr,
274                                         DebugVar.Loc}};
275   for (unsigned i = 0; i < 3; ++i) {
276     raw_string_ostream StrOS(*Outputs[i]);
277     Metas[i]->printAsOperand(StrOS, MST);
278   }
279 }
280 
281 void MIRPrinter::convert(yaml::MachineFunction &MF,
282                          const MachineRegisterInfo &RegInfo,
283                          const TargetRegisterInfo *TRI) {
284   MF.TracksRegLiveness = RegInfo.tracksLiveness();
285 
286   // Print the virtual register definitions.
287   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
288     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
289     yaml::VirtualRegisterDefinition VReg;
290     VReg.ID = I;
291     if (RegInfo.getVRegName(Reg) != "")
292       continue;
293     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
294     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
295     if (PreferredReg)
296       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
297     MF.VirtualRegisters.push_back(VReg);
298   }
299 
300   // Print the live ins.
301   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
302     yaml::MachineFunctionLiveIn LiveIn;
303     printRegMIR(LI.first, LiveIn.Register, TRI);
304     if (LI.second)
305       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
306     MF.LiveIns.push_back(LiveIn);
307   }
308 
309   // Prints the callee saved registers.
310   if (RegInfo.isUpdatedCSRsInitialized()) {
311     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
312     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
313     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
314       yaml::FlowStringValue Reg;
315       printRegMIR(*I, Reg, TRI);
316       CalleeSavedRegisters.push_back(Reg);
317     }
318     MF.CalleeSavedRegisters = CalleeSavedRegisters;
319   }
320 }
321 
322 void MIRPrinter::convert(ModuleSlotTracker &MST,
323                          yaml::MachineFrameInfo &YamlMFI,
324                          const MachineFrameInfo &MFI) {
325   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
326   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
327   YamlMFI.HasStackMap = MFI.hasStackMap();
328   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
329   YamlMFI.StackSize = MFI.getStackSize();
330   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
331   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
332   YamlMFI.AdjustsStack = MFI.adjustsStack();
333   YamlMFI.HasCalls = MFI.hasCalls();
334   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
335     ? MFI.getMaxCallFrameSize() : ~0u;
336   YamlMFI.CVBytesOfCalleeSavedRegisters =
337       MFI.getCVBytesOfCalleeSavedRegisters();
338   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
339   YamlMFI.HasVAStart = MFI.hasVAStart();
340   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
341   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
342   if (MFI.getSavePoint()) {
343     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
344     StrOS << printMBBReference(*MFI.getSavePoint());
345   }
346   if (MFI.getRestorePoint()) {
347     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
348     StrOS << printMBBReference(*MFI.getRestorePoint());
349   }
350 }
351 
352 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
353                                      const MachineFunction &MF,
354                                      ModuleSlotTracker &MST) {
355   const MachineFrameInfo &MFI = MF.getFrameInfo();
356   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
357   // Process fixed stack objects.
358   unsigned ID = 0;
359   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I, ++ID) {
360     if (MFI.isDeadObjectIndex(I))
361       continue;
362 
363     yaml::FixedMachineStackObject YamlObject;
364     YamlObject.ID = ID;
365     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
366                           ? yaml::FixedMachineStackObject::SpillSlot
367                           : yaml::FixedMachineStackObject::DefaultType;
368     YamlObject.Offset = MFI.getObjectOffset(I);
369     YamlObject.Size = MFI.getObjectSize(I);
370     YamlObject.Alignment = MFI.getObjectAlignment(I);
371     YamlObject.StackID = MFI.getStackID(I);
372     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
373     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
374     YMF.FixedStackObjects.push_back(YamlObject);
375     StackObjectOperandMapping.insert(
376         std::make_pair(I, FrameIndexOperand::createFixed(ID)));
377   }
378 
379   // Process ordinary stack objects.
380   ID = 0;
381   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I, ++ID) {
382     if (MFI.isDeadObjectIndex(I))
383       continue;
384 
385     yaml::MachineStackObject YamlObject;
386     YamlObject.ID = ID;
387     if (const auto *Alloca = MFI.getObjectAllocation(I))
388       YamlObject.Name.Value =
389           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
390     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
391                           ? yaml::MachineStackObject::SpillSlot
392                           : MFI.isVariableSizedObjectIndex(I)
393                                 ? yaml::MachineStackObject::VariableSized
394                                 : yaml::MachineStackObject::DefaultType;
395     YamlObject.Offset = MFI.getObjectOffset(I);
396     YamlObject.Size = MFI.getObjectSize(I);
397     YamlObject.Alignment = MFI.getObjectAlignment(I);
398     YamlObject.StackID = MFI.getStackID(I);
399 
400     YMF.StackObjects.push_back(YamlObject);
401     StackObjectOperandMapping.insert(std::make_pair(
402         I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
403   }
404 
405   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
406     if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(CSInfo.getFrameIdx()))
407       continue;
408 
409     yaml::StringValue Reg;
410     printRegMIR(CSInfo.getReg(), Reg, TRI);
411     if (!CSInfo.isSpilledToReg()) {
412       auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
413       assert(StackObjectInfo != StackObjectOperandMapping.end() &&
414              "Invalid stack object index");
415       const FrameIndexOperand &StackObject = StackObjectInfo->second;
416       if (StackObject.IsFixed) {
417         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
418         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
419           CSInfo.isRestored();
420       } else {
421         YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
422         YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
423           CSInfo.isRestored();
424       }
425     }
426   }
427   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
428     auto LocalObject = MFI.getLocalFrameObjectMap(I);
429     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
430     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
431            "Invalid stack object index");
432     const FrameIndexOperand &StackObject = StackObjectInfo->second;
433     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
434     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
435   }
436 
437   // Print the stack object references in the frame information class after
438   // converting the stack objects.
439   if (MFI.hasStackProtectorIndex()) {
440     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
441     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
442         .printStackObjectReference(MFI.getStackProtectorIndex());
443   }
444 
445   // Print the debug variable information.
446   for (const MachineFunction::VariableDbgInfo &DebugVar :
447        MF.getVariableDbgInfo()) {
448     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
449     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
450            "Invalid stack object index");
451     const FrameIndexOperand &StackObject = StackObjectInfo->second;
452     if (StackObject.IsFixed) {
453       auto &Object = YMF.FixedStackObjects[StackObject.ID];
454       printStackObjectDbgInfo(DebugVar, Object, MST);
455     } else {
456       auto &Object = YMF.StackObjects[StackObject.ID];
457       printStackObjectDbgInfo(DebugVar, Object, MST);
458     }
459   }
460 }
461 
462 void MIRPrinter::convert(yaml::MachineFunction &MF,
463                          const MachineConstantPool &ConstantPool) {
464   unsigned ID = 0;
465   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
466     std::string Str;
467     raw_string_ostream StrOS(Str);
468     if (Constant.isMachineConstantPoolEntry()) {
469       Constant.Val.MachineCPVal->print(StrOS);
470     } else {
471       Constant.Val.ConstVal->printAsOperand(StrOS);
472     }
473 
474     yaml::MachineConstantPoolValue YamlConstant;
475     YamlConstant.ID = ID++;
476     YamlConstant.Value = StrOS.str();
477     YamlConstant.Alignment = Constant.getAlignment();
478     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
479 
480     MF.Constants.push_back(YamlConstant);
481   }
482 }
483 
484 void MIRPrinter::convert(ModuleSlotTracker &MST,
485                          yaml::MachineJumpTable &YamlJTI,
486                          const MachineJumpTableInfo &JTI) {
487   YamlJTI.Kind = JTI.getEntryKind();
488   unsigned ID = 0;
489   for (const auto &Table : JTI.getJumpTables()) {
490     std::string Str;
491     yaml::MachineJumpTable::Entry Entry;
492     Entry.ID = ID++;
493     for (const auto *MBB : Table.MBBs) {
494       raw_string_ostream StrOS(Str);
495       StrOS << printMBBReference(*MBB);
496       Entry.Blocks.push_back(StrOS.str());
497       Str.clear();
498     }
499     YamlJTI.Entries.push_back(Entry);
500   }
501 }
502 
503 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
504   const auto *TRI = MF.getSubtarget().getRegisterInfo();
505   unsigned I = 0;
506   for (const uint32_t *Mask : TRI->getRegMasks())
507     RegisterMaskIds.insert(std::make_pair(Mask, I++));
508 }
509 
510 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
511                            SmallVectorImpl<MachineBasicBlock*> &Result,
512                            bool &IsFallthrough) {
513   SmallPtrSet<MachineBasicBlock*,8> Seen;
514 
515   for (const MachineInstr &MI : MBB) {
516     if (MI.isPHI())
517       continue;
518     for (const MachineOperand &MO : MI.operands()) {
519       if (!MO.isMBB())
520         continue;
521       MachineBasicBlock *Succ = MO.getMBB();
522       auto RP = Seen.insert(Succ);
523       if (RP.second)
524         Result.push_back(Succ);
525     }
526   }
527   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
528   IsFallthrough = I == MBB.end() || !I->isBarrier();
529 }
530 
531 bool
532 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
533   if (MBB.succ_size() <= 1)
534     return true;
535   if (!MBB.hasSuccessorProbabilities())
536     return true;
537 
538   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
539                                               MBB.Probs.end());
540   BranchProbability::normalizeProbabilities(Normalized.begin(),
541                                             Normalized.end());
542   SmallVector<BranchProbability,8> Equal(Normalized.size());
543   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
544 
545   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
546 }
547 
548 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
549   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
550   bool GuessedFallthrough;
551   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
552   if (GuessedFallthrough) {
553     const MachineFunction &MF = *MBB.getParent();
554     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
555     if (NextI != MF.end()) {
556       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
557       if (!is_contained(GuessedSuccs, Next))
558         GuessedSuccs.push_back(Next);
559     }
560   }
561   if (GuessedSuccs.size() != MBB.succ_size())
562     return false;
563   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
564 }
565 
566 void MIPrinter::print(const MachineBasicBlock &MBB) {
567   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
568   OS << "bb." << MBB.getNumber();
569   bool HasAttributes = false;
570   if (const auto *BB = MBB.getBasicBlock()) {
571     if (BB->hasName()) {
572       OS << "." << BB->getName();
573     } else {
574       HasAttributes = true;
575       OS << " (";
576       int Slot = MST.getLocalSlot(BB);
577       if (Slot == -1)
578         OS << "<ir-block badref>";
579       else
580         OS << (Twine("%ir-block.") + Twine(Slot)).str();
581     }
582   }
583   if (MBB.hasAddressTaken()) {
584     OS << (HasAttributes ? ", " : " (");
585     OS << "address-taken";
586     HasAttributes = true;
587   }
588   if (MBB.isEHPad()) {
589     OS << (HasAttributes ? ", " : " (");
590     OS << "landing-pad";
591     HasAttributes = true;
592   }
593   if (MBB.getAlignment()) {
594     OS << (HasAttributes ? ", " : " (");
595     OS << "align " << MBB.getAlignment();
596     HasAttributes = true;
597   }
598   if (HasAttributes)
599     OS << ")";
600   OS << ":\n";
601 
602   bool HasLineAttributes = false;
603   // Print the successors
604   bool canPredictProbs = canPredictBranchProbabilities(MBB);
605   // Even if the list of successors is empty, if we cannot guess it,
606   // we need to print it to tell the parser that the list is empty.
607   // This is needed, because MI model unreachable as empty blocks
608   // with an empty successor list. If the parser would see that
609   // without the successor list, it would guess the code would
610   // fallthrough.
611   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
612       !canPredictSuccessors(MBB)) {
613     OS.indent(2) << "successors: ";
614     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
615       if (I != MBB.succ_begin())
616         OS << ", ";
617       OS << printMBBReference(**I);
618       if (!SimplifyMIR || !canPredictProbs)
619         OS << '('
620            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
621            << ')';
622     }
623     OS << "\n";
624     HasLineAttributes = true;
625   }
626 
627   // Print the live in registers.
628   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
629   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
630     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
631     OS.indent(2) << "liveins: ";
632     bool First = true;
633     for (const auto &LI : MBB.liveins()) {
634       if (!First)
635         OS << ", ";
636       First = false;
637       OS << printReg(LI.PhysReg, &TRI);
638       if (!LI.LaneMask.all())
639         OS << ":0x" << PrintLaneMask(LI.LaneMask);
640     }
641     OS << "\n";
642     HasLineAttributes = true;
643   }
644 
645   if (HasLineAttributes)
646     OS << "\n";
647   bool IsInBundle = false;
648   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
649     const MachineInstr &MI = *I;
650     if (IsInBundle && !MI.isInsideBundle()) {
651       OS.indent(2) << "}\n";
652       IsInBundle = false;
653     }
654     OS.indent(IsInBundle ? 4 : 2);
655     print(MI);
656     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
657       OS << " {";
658       IsInBundle = true;
659     }
660     OS << "\n";
661   }
662   if (IsInBundle)
663     OS.indent(2) << "}\n";
664 }
665 
666 void MIPrinter::print(const MachineInstr &MI) {
667   const auto *MF = MI.getMF();
668   const auto &MRI = MF->getRegInfo();
669   const auto &SubTarget = MF->getSubtarget();
670   const auto *TRI = SubTarget.getRegisterInfo();
671   assert(TRI && "Expected target register info");
672   const auto *TII = SubTarget.getInstrInfo();
673   assert(TII && "Expected target instruction info");
674   if (MI.isCFIInstruction())
675     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
676 
677   SmallBitVector PrintedTypes(8);
678   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
679   unsigned I = 0, E = MI.getNumOperands();
680   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
681          !MI.getOperand(I).isImplicit();
682        ++I) {
683     if (I)
684       OS << ", ";
685     print(MI, I, TRI, ShouldPrintRegisterTies,
686           MI.getTypeToPrint(I, PrintedTypes, MRI),
687           /*PrintDef=*/false);
688   }
689 
690   if (I)
691     OS << " = ";
692   if (MI.getFlag(MachineInstr::FrameSetup))
693     OS << "frame-setup ";
694   if (MI.getFlag(MachineInstr::FrameDestroy))
695     OS << "frame-destroy ";
696   if (MI.getFlag(MachineInstr::FmNoNans))
697     OS << "nnan ";
698   if (MI.getFlag(MachineInstr::FmNoInfs))
699     OS << "ninf ";
700   if (MI.getFlag(MachineInstr::FmNsz))
701     OS << "nsz ";
702   if (MI.getFlag(MachineInstr::FmArcp))
703     OS << "arcp ";
704   if (MI.getFlag(MachineInstr::FmContract))
705     OS << "contract ";
706   if (MI.getFlag(MachineInstr::FmAfn))
707     OS << "afn ";
708   if (MI.getFlag(MachineInstr::FmReassoc))
709     OS << "reassoc ";
710   if (MI.getFlag(MachineInstr::NoUWrap))
711     OS << "nuw ";
712   if (MI.getFlag(MachineInstr::NoSWrap))
713     OS << "nsw ";
714   if (MI.getFlag(MachineInstr::IsExact))
715     OS << "exact ";
716 
717   OS << TII->getName(MI.getOpcode());
718   if (I < E)
719     OS << ' ';
720 
721   bool NeedComma = false;
722   for (; I < E; ++I) {
723     if (NeedComma)
724       OS << ", ";
725     print(MI, I, TRI, ShouldPrintRegisterTies,
726           MI.getTypeToPrint(I, PrintedTypes, MRI));
727     NeedComma = true;
728   }
729 
730   // Print any optional symbols attached to this instruction as-if they were
731   // operands.
732   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
733     if (NeedComma)
734       OS << ',';
735     OS << " pre-instr-symbol ";
736     MachineOperand::printSymbol(OS, *PreInstrSymbol);
737     NeedComma = true;
738   }
739   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
740     if (NeedComma)
741       OS << ',';
742     OS << " post-instr-symbol ";
743     MachineOperand::printSymbol(OS, *PostInstrSymbol);
744     NeedComma = true;
745   }
746 
747   if (const DebugLoc &DL = MI.getDebugLoc()) {
748     if (NeedComma)
749       OS << ',';
750     OS << " debug-location ";
751     DL->printAsOperand(OS, MST);
752   }
753 
754   if (!MI.memoperands_empty()) {
755     OS << " :: ";
756     const LLVMContext &Context = MF->getFunction().getContext();
757     const MachineFrameInfo &MFI = MF->getFrameInfo();
758     bool NeedComma = false;
759     for (const auto *Op : MI.memoperands()) {
760       if (NeedComma)
761         OS << ", ";
762       Op->print(OS, MST, SSNs, Context, &MFI, TII);
763       NeedComma = true;
764     }
765   }
766 }
767 
768 void MIPrinter::printStackObjectReference(int FrameIndex) {
769   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
770   assert(ObjectInfo != StackObjectOperandMapping.end() &&
771          "Invalid frame index");
772   const FrameIndexOperand &Operand = ObjectInfo->second;
773   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
774                                             Operand.Name);
775 }
776 
777 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
778                       const TargetRegisterInfo *TRI,
779                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
780                       bool PrintDef) {
781   const MachineOperand &Op = MI.getOperand(OpIdx);
782   switch (Op.getType()) {
783   case MachineOperand::MO_Immediate:
784     if (MI.isOperandSubregIdx(OpIdx)) {
785       MachineOperand::printTargetFlags(OS, Op);
786       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
787       break;
788     }
789     LLVM_FALLTHROUGH;
790   case MachineOperand::MO_Register:
791   case MachineOperand::MO_CImmediate:
792   case MachineOperand::MO_FPImmediate:
793   case MachineOperand::MO_MachineBasicBlock:
794   case MachineOperand::MO_ConstantPoolIndex:
795   case MachineOperand::MO_TargetIndex:
796   case MachineOperand::MO_JumpTableIndex:
797   case MachineOperand::MO_ExternalSymbol:
798   case MachineOperand::MO_GlobalAddress:
799   case MachineOperand::MO_RegisterLiveOut:
800   case MachineOperand::MO_Metadata:
801   case MachineOperand::MO_MCSymbol:
802   case MachineOperand::MO_CFIIndex:
803   case MachineOperand::MO_IntrinsicID:
804   case MachineOperand::MO_Predicate:
805   case MachineOperand::MO_BlockAddress: {
806     unsigned TiedOperandIdx = 0;
807     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
808       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
809     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
810     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
811              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
812     break;
813   }
814   case MachineOperand::MO_FrameIndex:
815     printStackObjectReference(Op.getIndex());
816     break;
817   case MachineOperand::MO_RegisterMask: {
818     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
819     if (RegMaskInfo != RegisterMaskIds.end())
820       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
821     else
822       printCustomRegMask(Op.getRegMask(), OS, TRI);
823     break;
824   }
825   }
826 }
827 
828 void llvm::printMIR(raw_ostream &OS, const Module &M) {
829   yaml::Output Out(OS);
830   Out << const_cast<Module &>(M);
831 }
832 
833 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
834   MIRPrinter Printer(OS);
835   Printer.print(MF);
836 }
837