1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/MemoryBuffer.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Support/YAMLTraits.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
36 
37 using namespace llvm;
38 
39 namespace {
40 
41 /// This structure describes how to print out stack object references.
42 struct FrameIndexOperand {
43   std::string Name;
44   unsigned ID;
45   bool IsFixed;
46 
47   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
48       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
49 
50   /// Return an ordinary stack object reference.
51   static FrameIndexOperand create(StringRef Name, unsigned ID) {
52     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
53   }
54 
55   /// Return a fixed stack object reference.
56   static FrameIndexOperand createFixed(unsigned ID) {
57     return FrameIndexOperand("", ID, /*IsFixed=*/true);
58   }
59 };
60 
61 } // end anonymous namespace
62 
63 namespace llvm {
64 
65 /// This class prints out the machine functions using the MIR serialization
66 /// format.
67 class MIRPrinter {
68   raw_ostream &OS;
69   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
70   /// Maps from stack object indices to operand indices which will be used when
71   /// printing frame index machine operands.
72   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
73 
74 public:
75   MIRPrinter(raw_ostream &OS) : OS(OS) {}
76 
77   void print(const MachineFunction &MF);
78 
79   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
80                const TargetRegisterInfo *TRI);
81   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
82                const MachineFrameInfo &MFI);
83   void convert(yaml::MachineFunction &MF,
84                const MachineConstantPool &ConstantPool);
85   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
86                const MachineJumpTableInfo &JTI);
87   void convertStackObjects(yaml::MachineFunction &MF,
88                            const MachineFrameInfo &MFI, MachineModuleInfo &MMI,
89                            ModuleSlotTracker &MST,
90                            const TargetRegisterInfo *TRI);
91 
92 private:
93   void initRegisterMaskIds(const MachineFunction &MF);
94 };
95 
96 /// This class prints out the machine instructions using the MIR serialization
97 /// format.
98 class MIPrinter {
99   raw_ostream &OS;
100   ModuleSlotTracker &MST;
101   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
102   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
103 
104 public:
105   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
106             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
107             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
108       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
109         StackObjectOperandMapping(StackObjectOperandMapping) {}
110 
111   void print(const MachineBasicBlock &MBB);
112 
113   void print(const MachineInstr &MI);
114   void printMBBReference(const MachineBasicBlock &MBB);
115   void printIRBlockReference(const BasicBlock &BB);
116   void printIRValueReference(const Value &V);
117   void printStackObjectReference(int FrameIndex);
118   void printOffset(int64_t Offset);
119   void printTargetFlags(const MachineOperand &Op);
120   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
121              unsigned I, bool ShouldPrintRegisterTies, bool IsDef = false);
122   void print(const MachineMemOperand &Op);
123 
124   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
125 };
126 
127 } // end namespace llvm
128 
129 namespace llvm {
130 namespace yaml {
131 
132 /// This struct serializes the LLVM IR module.
133 template <> struct BlockScalarTraits<Module> {
134   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
135     Mod.print(OS, nullptr);
136   }
137   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
138     llvm_unreachable("LLVM Module is supposed to be parsed separately");
139     return "";
140   }
141 };
142 
143 } // end namespace yaml
144 } // end namespace llvm
145 
146 static void printReg(unsigned Reg, raw_ostream &OS,
147                      const TargetRegisterInfo *TRI) {
148   // TODO: Print Stack Slots.
149   if (!Reg)
150     OS << '_';
151   else if (TargetRegisterInfo::isVirtualRegister(Reg))
152     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
153   else if (Reg < TRI->getNumRegs())
154     OS << '%' << StringRef(TRI->getName(Reg)).lower();
155   else
156     llvm_unreachable("Can't print this kind of register yet");
157 }
158 
159 static void printReg(unsigned Reg, yaml::StringValue &Dest,
160                      const TargetRegisterInfo *TRI) {
161   raw_string_ostream OS(Dest.Value);
162   printReg(Reg, OS, TRI);
163 }
164 
165 void MIRPrinter::print(const MachineFunction &MF) {
166   initRegisterMaskIds(MF);
167 
168   yaml::MachineFunction YamlMF;
169   YamlMF.Name = MF.getName();
170   YamlMF.Alignment = MF.getAlignment();
171   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
172   YamlMF.HasInlineAsm = MF.hasInlineAsm();
173   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
174   ModuleSlotTracker MST(MF.getFunction()->getParent());
175   MST.incorporateFunction(*MF.getFunction());
176   convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
177   convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
178                       MF.getSubtarget().getRegisterInfo());
179   if (const auto *ConstantPool = MF.getConstantPool())
180     convert(YamlMF, *ConstantPool);
181   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
182     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
183   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
184   bool IsNewlineNeeded = false;
185   for (const auto &MBB : MF) {
186     if (IsNewlineNeeded)
187       StrOS << "\n";
188     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
189         .print(MBB);
190     IsNewlineNeeded = true;
191   }
192   StrOS.flush();
193   yaml::Output Out(OS);
194   Out << YamlMF;
195 }
196 
197 void MIRPrinter::convert(yaml::MachineFunction &MF,
198                          const MachineRegisterInfo &RegInfo,
199                          const TargetRegisterInfo *TRI) {
200   MF.IsSSA = RegInfo.isSSA();
201   MF.TracksRegLiveness = RegInfo.tracksLiveness();
202   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
203 
204   // Print the virtual register definitions.
205   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
206     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
207     yaml::VirtualRegisterDefinition VReg;
208     VReg.ID = I;
209     VReg.Class =
210         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
211     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
212     if (PreferredReg)
213       printReg(PreferredReg, VReg.PreferredRegister, TRI);
214     MF.VirtualRegisters.push_back(VReg);
215   }
216 
217   // Print the live ins.
218   for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
219     yaml::MachineFunctionLiveIn LiveIn;
220     printReg(I->first, LiveIn.Register, TRI);
221     if (I->second)
222       printReg(I->second, LiveIn.VirtualRegister, TRI);
223     MF.LiveIns.push_back(LiveIn);
224   }
225   // The used physical register mask is printed as an inverted callee saved
226   // register mask.
227   const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
228   if (UsedPhysRegMask.none())
229     return;
230   std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
231   for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
232     if (!UsedPhysRegMask[I]) {
233       yaml::FlowStringValue Reg;
234       printReg(I, Reg, TRI);
235       CalleeSavedRegisters.push_back(Reg);
236     }
237   }
238   MF.CalleeSavedRegisters = CalleeSavedRegisters;
239 }
240 
241 void MIRPrinter::convert(ModuleSlotTracker &MST,
242                          yaml::MachineFrameInfo &YamlMFI,
243                          const MachineFrameInfo &MFI) {
244   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
245   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
246   YamlMFI.HasStackMap = MFI.hasStackMap();
247   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
248   YamlMFI.StackSize = MFI.getStackSize();
249   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
250   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
251   YamlMFI.AdjustsStack = MFI.adjustsStack();
252   YamlMFI.HasCalls = MFI.hasCalls();
253   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
254   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
255   YamlMFI.HasVAStart = MFI.hasVAStart();
256   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
257   if (MFI.getSavePoint()) {
258     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
259     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
260         .printMBBReference(*MFI.getSavePoint());
261   }
262   if (MFI.getRestorePoint()) {
263     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
264     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
265         .printMBBReference(*MFI.getRestorePoint());
266   }
267 }
268 
269 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
270                                      const MachineFrameInfo &MFI,
271                                      MachineModuleInfo &MMI,
272                                      ModuleSlotTracker &MST,
273                                      const TargetRegisterInfo *TRI) {
274   // Process fixed stack objects.
275   unsigned ID = 0;
276   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
277     if (MFI.isDeadObjectIndex(I))
278       continue;
279 
280     yaml::FixedMachineStackObject YamlObject;
281     YamlObject.ID = ID;
282     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
283                           ? yaml::FixedMachineStackObject::SpillSlot
284                           : yaml::FixedMachineStackObject::DefaultType;
285     YamlObject.Offset = MFI.getObjectOffset(I);
286     YamlObject.Size = MFI.getObjectSize(I);
287     YamlObject.Alignment = MFI.getObjectAlignment(I);
288     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
289     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
290     MF.FixedStackObjects.push_back(YamlObject);
291     StackObjectOperandMapping.insert(
292         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
293   }
294 
295   // Process ordinary stack objects.
296   ID = 0;
297   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
298     if (MFI.isDeadObjectIndex(I))
299       continue;
300 
301     yaml::MachineStackObject YamlObject;
302     YamlObject.ID = ID;
303     if (const auto *Alloca = MFI.getObjectAllocation(I))
304       YamlObject.Name.Value =
305           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
306     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
307                           ? yaml::MachineStackObject::SpillSlot
308                           : MFI.isVariableSizedObjectIndex(I)
309                                 ? yaml::MachineStackObject::VariableSized
310                                 : yaml::MachineStackObject::DefaultType;
311     YamlObject.Offset = MFI.getObjectOffset(I);
312     YamlObject.Size = MFI.getObjectSize(I);
313     YamlObject.Alignment = MFI.getObjectAlignment(I);
314 
315     MF.StackObjects.push_back(YamlObject);
316     StackObjectOperandMapping.insert(std::make_pair(
317         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
318   }
319 
320   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
321     yaml::StringValue Reg;
322     printReg(CSInfo.getReg(), Reg, TRI);
323     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
324     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
325            "Invalid stack object index");
326     const FrameIndexOperand &StackObject = StackObjectInfo->second;
327     if (StackObject.IsFixed)
328       MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
329     else
330       MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
331   }
332   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
333     auto LocalObject = MFI.getLocalFrameObjectMap(I);
334     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
335     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
336            "Invalid stack object index");
337     const FrameIndexOperand &StackObject = StackObjectInfo->second;
338     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
339     MF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
340   }
341 
342   // Print the stack object references in the frame information class after
343   // converting the stack objects.
344   if (MFI.hasStackProtectorIndex()) {
345     raw_string_ostream StrOS(MF.FrameInfo.StackProtector.Value);
346     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
347         .printStackObjectReference(MFI.getStackProtectorIndex());
348   }
349 
350   // Print the debug variable information.
351   for (MachineModuleInfo::VariableDbgInfo &DebugVar :
352        MMI.getVariableDbgInfo()) {
353     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
354     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
355            "Invalid stack object index");
356     const FrameIndexOperand &StackObject = StackObjectInfo->second;
357     assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
358     auto &Object = MF.StackObjects[StackObject.ID];
359     {
360       raw_string_ostream StrOS(Object.DebugVar.Value);
361       DebugVar.Var->printAsOperand(StrOS, MST);
362     }
363     {
364       raw_string_ostream StrOS(Object.DebugExpr.Value);
365       DebugVar.Expr->printAsOperand(StrOS, MST);
366     }
367     {
368       raw_string_ostream StrOS(Object.DebugLoc.Value);
369       DebugVar.Loc->printAsOperand(StrOS, MST);
370     }
371   }
372 }
373 
374 void MIRPrinter::convert(yaml::MachineFunction &MF,
375                          const MachineConstantPool &ConstantPool) {
376   unsigned ID = 0;
377   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
378     // TODO: Serialize target specific constant pool entries.
379     if (Constant.isMachineConstantPoolEntry())
380       llvm_unreachable("Can't print target specific constant pool entries yet");
381 
382     yaml::MachineConstantPoolValue YamlConstant;
383     std::string Str;
384     raw_string_ostream StrOS(Str);
385     Constant.Val.ConstVal->printAsOperand(StrOS);
386     YamlConstant.ID = ID++;
387     YamlConstant.Value = StrOS.str();
388     YamlConstant.Alignment = Constant.getAlignment();
389     MF.Constants.push_back(YamlConstant);
390   }
391 }
392 
393 void MIRPrinter::convert(ModuleSlotTracker &MST,
394                          yaml::MachineJumpTable &YamlJTI,
395                          const MachineJumpTableInfo &JTI) {
396   YamlJTI.Kind = JTI.getEntryKind();
397   unsigned ID = 0;
398   for (const auto &Table : JTI.getJumpTables()) {
399     std::string Str;
400     yaml::MachineJumpTable::Entry Entry;
401     Entry.ID = ID++;
402     for (const auto *MBB : Table.MBBs) {
403       raw_string_ostream StrOS(Str);
404       MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
405           .printMBBReference(*MBB);
406       Entry.Blocks.push_back(StrOS.str());
407       Str.clear();
408     }
409     YamlJTI.Entries.push_back(Entry);
410   }
411 }
412 
413 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
414   const auto *TRI = MF.getSubtarget().getRegisterInfo();
415   unsigned I = 0;
416   for (const uint32_t *Mask : TRI->getRegMasks())
417     RegisterMaskIds.insert(std::make_pair(Mask, I++));
418 }
419 
420 void MIPrinter::print(const MachineBasicBlock &MBB) {
421   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
422   OS << "bb." << MBB.getNumber();
423   bool HasAttributes = false;
424   if (const auto *BB = MBB.getBasicBlock()) {
425     if (BB->hasName()) {
426       OS << "." << BB->getName();
427     } else {
428       HasAttributes = true;
429       OS << " (";
430       int Slot = MST.getLocalSlot(BB);
431       if (Slot == -1)
432         OS << "<ir-block badref>";
433       else
434         OS << (Twine("%ir-block.") + Twine(Slot)).str();
435     }
436   }
437   if (MBB.hasAddressTaken()) {
438     OS << (HasAttributes ? ", " : " (");
439     OS << "address-taken";
440     HasAttributes = true;
441   }
442   if (MBB.isLandingPad()) {
443     OS << (HasAttributes ? ", " : " (");
444     OS << "landing-pad";
445     HasAttributes = true;
446   }
447   if (MBB.getAlignment()) {
448     OS << (HasAttributes ? ", " : " (");
449     OS << "align " << MBB.getAlignment();
450     HasAttributes = true;
451   }
452   if (HasAttributes)
453     OS << ")";
454   OS << ":\n";
455 
456   bool HasLineAttributes = false;
457   // Print the successors
458   if (!MBB.succ_empty()) {
459     OS.indent(2) << "successors: ";
460     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
461       if (I != MBB.succ_begin())
462         OS << ", ";
463       printMBBReference(**I);
464       if (MBB.hasSuccessorWeights())
465         OS << '(' << MBB.getSuccWeight(I) << ')';
466     }
467     OS << "\n";
468     HasLineAttributes = true;
469   }
470 
471   // Print the live in registers.
472   const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
473   assert(TRI && "Expected target register info");
474   if (!MBB.livein_empty()) {
475     OS.indent(2) << "liveins: ";
476     bool First = true;
477     for (unsigned LI : MBB.liveins()) {
478       if (!First)
479         OS << ", ";
480       First = false;
481       printReg(LI, OS, TRI);
482     }
483     OS << "\n";
484     HasLineAttributes = true;
485   }
486 
487   if (HasLineAttributes)
488     OS << "\n";
489   bool IsInBundle = false;
490   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
491     const MachineInstr &MI = *I;
492     if (IsInBundle && !MI.isInsideBundle()) {
493       OS.indent(2) << "}\n";
494       IsInBundle = false;
495     }
496     OS.indent(IsInBundle ? 4 : 2);
497     print(MI);
498     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
499       OS << " {";
500       IsInBundle = true;
501     }
502     OS << "\n";
503   }
504   if (IsInBundle)
505     OS.indent(2) << "}\n";
506 }
507 
508 /// Return true when an instruction has tied register that can't be determined
509 /// by the instruction's descriptor.
510 static bool hasComplexRegisterTies(const MachineInstr &MI) {
511   const MCInstrDesc &MCID = MI.getDesc();
512   for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
513     const auto &Operand = MI.getOperand(I);
514     if (!Operand.isReg() || Operand.isDef())
515       // Ignore the defined registers as MCID marks only the uses as tied.
516       continue;
517     int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
518     int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
519     if (ExpectedTiedIdx != TiedIdx)
520       return true;
521   }
522   return false;
523 }
524 
525 void MIPrinter::print(const MachineInstr &MI) {
526   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
527   const auto *TRI = SubTarget.getRegisterInfo();
528   assert(TRI && "Expected target register info");
529   const auto *TII = SubTarget.getInstrInfo();
530   assert(TII && "Expected target instruction info");
531   if (MI.isCFIInstruction())
532     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
533 
534   bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
535   unsigned I = 0, E = MI.getNumOperands();
536   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
537          !MI.getOperand(I).isImplicit();
538        ++I) {
539     if (I)
540       OS << ", ";
541     print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, /*IsDef=*/true);
542   }
543 
544   if (I)
545     OS << " = ";
546   if (MI.getFlag(MachineInstr::FrameSetup))
547     OS << "frame-setup ";
548   OS << TII->getName(MI.getOpcode());
549   if (I < E)
550     OS << ' ';
551 
552   bool NeedComma = false;
553   for (; I < E; ++I) {
554     if (NeedComma)
555       OS << ", ";
556     print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies);
557     NeedComma = true;
558   }
559 
560   if (MI.getDebugLoc()) {
561     if (NeedComma)
562       OS << ',';
563     OS << " debug-location ";
564     MI.getDebugLoc()->printAsOperand(OS, MST);
565   }
566 
567   if (!MI.memoperands_empty()) {
568     OS << " :: ";
569     bool NeedComma = false;
570     for (const auto *Op : MI.memoperands()) {
571       if (NeedComma)
572         OS << ", ";
573       print(*Op);
574       NeedComma = true;
575     }
576   }
577 }
578 
579 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
580   OS << "%bb." << MBB.getNumber();
581   if (const auto *BB = MBB.getBasicBlock()) {
582     if (BB->hasName())
583       OS << '.' << BB->getName();
584   }
585 }
586 
587 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
588   if (Slot == -1)
589     OS << "<badref>";
590   else
591     OS << Slot;
592 }
593 
594 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
595   OS << "%ir-block.";
596   if (BB.hasName()) {
597     printLLVMNameWithoutPrefix(OS, BB.getName());
598     return;
599   }
600   const Function *F = BB.getParent();
601   int Slot;
602   if (F == MST.getCurrentFunction()) {
603     Slot = MST.getLocalSlot(&BB);
604   } else {
605     ModuleSlotTracker CustomMST(F->getParent(),
606                                 /*ShouldInitializeAllMetadata=*/false);
607     CustomMST.incorporateFunction(*F);
608     Slot = CustomMST.getLocalSlot(&BB);
609   }
610   printIRSlotNumber(OS, Slot);
611 }
612 
613 void MIPrinter::printIRValueReference(const Value &V) {
614   if (isa<GlobalValue>(V)) {
615     V.printAsOperand(OS, /*PrintType=*/false, MST);
616     return;
617   }
618   if (isa<Constant>(V)) {
619     // Machine memory operands can load/store to/from constant value pointers.
620     OS << '`';
621     V.printAsOperand(OS, /*PrintType=*/true, MST);
622     OS << '`';
623     return;
624   }
625   OS << "%ir.";
626   if (V.hasName()) {
627     printLLVMNameWithoutPrefix(OS, V.getName());
628     return;
629   }
630   printIRSlotNumber(OS, MST.getLocalSlot(&V));
631 }
632 
633 void MIPrinter::printStackObjectReference(int FrameIndex) {
634   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
635   assert(ObjectInfo != StackObjectOperandMapping.end() &&
636          "Invalid frame index");
637   const FrameIndexOperand &Operand = ObjectInfo->second;
638   if (Operand.IsFixed) {
639     OS << "%fixed-stack." << Operand.ID;
640     return;
641   }
642   OS << "%stack." << Operand.ID;
643   if (!Operand.Name.empty())
644     OS << '.' << Operand.Name;
645 }
646 
647 void MIPrinter::printOffset(int64_t Offset) {
648   if (Offset == 0)
649     return;
650   if (Offset < 0) {
651     OS << " - " << -Offset;
652     return;
653   }
654   OS << " + " << Offset;
655 }
656 
657 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
658   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
659   for (const auto &I : Flags) {
660     if (I.first == TF) {
661       return I.second;
662     }
663   }
664   return nullptr;
665 }
666 
667 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
668   if (!Op.getTargetFlags())
669     return;
670   const auto *TII =
671       Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
672   assert(TII && "expected instruction info");
673   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
674   OS << "target-flags(";
675   const bool HasDirectFlags = Flags.first;
676   const bool HasBitmaskFlags = Flags.second;
677   if (!HasDirectFlags && !HasBitmaskFlags) {
678     OS << "<unknown>) ";
679     return;
680   }
681   if (HasDirectFlags) {
682     if (const auto *Name = getTargetFlagName(TII, Flags.first))
683       OS << Name;
684     else
685       OS << "<unknown target flag>";
686   }
687   if (!HasBitmaskFlags) {
688     OS << ") ";
689     return;
690   }
691   bool IsCommaNeeded = HasDirectFlags;
692   unsigned BitMask = Flags.second;
693   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
694   for (const auto &Mask : BitMasks) {
695     // Check if the flag's bitmask has the bits of the current mask set.
696     if ((BitMask & Mask.first) == Mask.first) {
697       if (IsCommaNeeded)
698         OS << ", ";
699       IsCommaNeeded = true;
700       OS << Mask.second;
701       // Clear the bits which were serialized from the flag's bitmask.
702       BitMask &= ~(Mask.first);
703     }
704   }
705   if (BitMask) {
706     // When the resulting flag's bitmask isn't zero, we know that we didn't
707     // serialize all of the bit flags.
708     if (IsCommaNeeded)
709       OS << ", ";
710     OS << "<unknown bitmask target flag>";
711   }
712   OS << ") ";
713 }
714 
715 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
716   const auto *TII = MF.getSubtarget().getInstrInfo();
717   assert(TII && "expected instruction info");
718   auto Indices = TII->getSerializableTargetIndices();
719   for (const auto &I : Indices) {
720     if (I.first == Index) {
721       return I.second;
722     }
723   }
724   return nullptr;
725 }
726 
727 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
728                       unsigned I, bool ShouldPrintRegisterTies, bool IsDef) {
729   printTargetFlags(Op);
730   switch (Op.getType()) {
731   case MachineOperand::MO_Register:
732     if (Op.isImplicit())
733       OS << (Op.isDef() ? "implicit-def " : "implicit ");
734     else if (!IsDef && Op.isDef())
735       // Print the 'def' flag only when the operand is defined after '='.
736       OS << "def ";
737     if (Op.isInternalRead())
738       OS << "internal ";
739     if (Op.isDead())
740       OS << "dead ";
741     if (Op.isKill())
742       OS << "killed ";
743     if (Op.isUndef())
744       OS << "undef ";
745     if (Op.isEarlyClobber())
746       OS << "early-clobber ";
747     if (Op.isDebug())
748       OS << "debug-use ";
749     printReg(Op.getReg(), OS, TRI);
750     // Print the sub register.
751     if (Op.getSubReg() != 0)
752       OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
753     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
754       OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
755     break;
756   case MachineOperand::MO_Immediate:
757     OS << Op.getImm();
758     break;
759   case MachineOperand::MO_CImmediate:
760     Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
761     break;
762   case MachineOperand::MO_FPImmediate:
763     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
764     break;
765   case MachineOperand::MO_MachineBasicBlock:
766     printMBBReference(*Op.getMBB());
767     break;
768   case MachineOperand::MO_FrameIndex:
769     printStackObjectReference(Op.getIndex());
770     break;
771   case MachineOperand::MO_ConstantPoolIndex:
772     OS << "%const." << Op.getIndex();
773     printOffset(Op.getOffset());
774     break;
775   case MachineOperand::MO_TargetIndex: {
776     OS << "target-index(";
777     if (const auto *Name = getTargetIndexName(
778             *Op.getParent()->getParent()->getParent(), Op.getIndex()))
779       OS << Name;
780     else
781       OS << "<unknown>";
782     OS << ')';
783     printOffset(Op.getOffset());
784     break;
785   }
786   case MachineOperand::MO_JumpTableIndex:
787     OS << "%jump-table." << Op.getIndex();
788     break;
789   case MachineOperand::MO_ExternalSymbol:
790     OS << '$';
791     printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
792     printOffset(Op.getOffset());
793     break;
794   case MachineOperand::MO_GlobalAddress:
795     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
796     printOffset(Op.getOffset());
797     break;
798   case MachineOperand::MO_BlockAddress:
799     OS << "blockaddress(";
800     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
801                                                         MST);
802     OS << ", ";
803     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
804     OS << ')';
805     printOffset(Op.getOffset());
806     break;
807   case MachineOperand::MO_RegisterMask: {
808     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
809     if (RegMaskInfo != RegisterMaskIds.end())
810       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
811     else
812       llvm_unreachable("Can't print this machine register mask yet.");
813     break;
814   }
815   case MachineOperand::MO_RegisterLiveOut: {
816     const uint32_t *RegMask = Op.getRegLiveOut();
817     OS << "liveout(";
818     bool IsCommaNeeded = false;
819     for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
820       if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
821         if (IsCommaNeeded)
822           OS << ", ";
823         printReg(Reg, OS, TRI);
824         IsCommaNeeded = true;
825       }
826     }
827     OS << ")";
828     break;
829   }
830   case MachineOperand::MO_Metadata:
831     Op.getMetadata()->printAsOperand(OS, MST);
832     break;
833   case MachineOperand::MO_MCSymbol:
834     OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
835     break;
836   case MachineOperand::MO_CFIIndex: {
837     const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
838     print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
839     break;
840   }
841   }
842 }
843 
844 void MIPrinter::print(const MachineMemOperand &Op) {
845   OS << '(';
846   // TODO: Print operand's target specific flags.
847   if (Op.isVolatile())
848     OS << "volatile ";
849   if (Op.isNonTemporal())
850     OS << "non-temporal ";
851   if (Op.isInvariant())
852     OS << "invariant ";
853   if (Op.isLoad())
854     OS << "load ";
855   else {
856     assert(Op.isStore() && "Non load machine operand must be a store");
857     OS << "store ";
858   }
859   OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
860   if (const Value *Val = Op.getValue()) {
861     printIRValueReference(*Val);
862   } else {
863     const PseudoSourceValue *PVal = Op.getPseudoValue();
864     assert(PVal && "Expected a pseudo source value");
865     switch (PVal->kind()) {
866     case PseudoSourceValue::Stack:
867       OS << "stack";
868       break;
869     case PseudoSourceValue::GOT:
870       OS << "got";
871       break;
872     case PseudoSourceValue::JumpTable:
873       OS << "jump-table";
874       break;
875     case PseudoSourceValue::ConstantPool:
876       OS << "constant-pool";
877       break;
878     case PseudoSourceValue::FixedStack:
879       printStackObjectReference(
880           cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
881       break;
882     case PseudoSourceValue::GlobalValueCallEntry:
883       OS << "call-entry ";
884       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
885           OS, /*PrintType=*/false, MST);
886       break;
887     case PseudoSourceValue::ExternalSymbolCallEntry:
888       OS << "call-entry $";
889       printLLVMNameWithoutPrefix(
890           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
891       break;
892     }
893   }
894   printOffset(Op.getOffset());
895   if (Op.getBaseAlignment() != Op.getSize())
896     OS << ", align " << Op.getBaseAlignment();
897   auto AAInfo = Op.getAAInfo();
898   if (AAInfo.TBAA) {
899     OS << ", !tbaa ";
900     AAInfo.TBAA->printAsOperand(OS, MST);
901   }
902   if (AAInfo.Scope) {
903     OS << ", !alias.scope ";
904     AAInfo.Scope->printAsOperand(OS, MST);
905   }
906   if (AAInfo.NoAlias) {
907     OS << ", !noalias ";
908     AAInfo.NoAlias->printAsOperand(OS, MST);
909   }
910   if (Op.getRanges()) {
911     OS << ", !range ";
912     Op.getRanges()->printAsOperand(OS, MST);
913   }
914   OS << ')';
915 }
916 
917 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
918                              const TargetRegisterInfo *TRI) {
919   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
920   if (Reg == -1) {
921     OS << "<badreg>";
922     return;
923   }
924   printReg(Reg, OS, TRI);
925 }
926 
927 void MIPrinter::print(const MCCFIInstruction &CFI,
928                       const TargetRegisterInfo *TRI) {
929   switch (CFI.getOperation()) {
930   case MCCFIInstruction::OpSameValue:
931     OS << ".cfi_same_value ";
932     if (CFI.getLabel())
933       OS << "<mcsymbol> ";
934     printCFIRegister(CFI.getRegister(), OS, TRI);
935     break;
936   case MCCFIInstruction::OpOffset:
937     OS << ".cfi_offset ";
938     if (CFI.getLabel())
939       OS << "<mcsymbol> ";
940     printCFIRegister(CFI.getRegister(), OS, TRI);
941     OS << ", " << CFI.getOffset();
942     break;
943   case MCCFIInstruction::OpDefCfaRegister:
944     OS << ".cfi_def_cfa_register ";
945     if (CFI.getLabel())
946       OS << "<mcsymbol> ";
947     printCFIRegister(CFI.getRegister(), OS, TRI);
948     break;
949   case MCCFIInstruction::OpDefCfaOffset:
950     OS << ".cfi_def_cfa_offset ";
951     if (CFI.getLabel())
952       OS << "<mcsymbol> ";
953     OS << CFI.getOffset();
954     break;
955   case MCCFIInstruction::OpDefCfa:
956     OS << ".cfi_def_cfa ";
957     if (CFI.getLabel())
958       OS << "<mcsymbol> ";
959     printCFIRegister(CFI.getRegister(), OS, TRI);
960     OS << ", " << CFI.getOffset();
961     break;
962   default:
963     // TODO: Print the other CFI Operations.
964     OS << "<unserializable cfi operation>";
965     break;
966   }
967 }
968 
969 void llvm::printMIR(raw_ostream &OS, const Module &M) {
970   yaml::Output Out(OS);
971   Out << const_cast<Module &>(M);
972 }
973 
974 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
975   MIRPrinter Printer(OS);
976   Printer.print(MF);
977 }
978