1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/MIRYamlMapping.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCDwarf.h"
54 #include "llvm/MC/MCSymbol.h"
55 #include "llvm/Support/AtomicOrdering.h"
56 #include "llvm/Support/BranchProbability.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CommandLine.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/Format.h"
61 #include "llvm/Support/LowLevelTypeImpl.h"
62 #include "llvm/Support/YAMLTraits.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetIntrinsicInfo.h"
65 #include "llvm/Target/TargetMachine.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cinttypes>
69 #include <cstdint>
70 #include <iterator>
71 #include <string>
72 #include <utility>
73 #include <vector>
74 
75 using namespace llvm;
76 
77 static cl::opt<bool> SimplifyMIR(
78     "simplify-mir", cl::Hidden,
79     cl::desc("Leave out unnecessary information when printing MIR"));
80 
81 namespace {
82 
83 /// This structure describes how to print out stack object references.
84 struct FrameIndexOperand {
85   std::string Name;
86   unsigned ID;
87   bool IsFixed;
88 
89   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
90       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
91 
92   /// Return an ordinary stack object reference.
93   static FrameIndexOperand create(StringRef Name, unsigned ID) {
94     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
95   }
96 
97   /// Return a fixed stack object reference.
98   static FrameIndexOperand createFixed(unsigned ID) {
99     return FrameIndexOperand("", ID, /*IsFixed=*/true);
100   }
101 };
102 
103 } // end anonymous namespace
104 
105 namespace llvm {
106 
107 /// This class prints out the machine functions using the MIR serialization
108 /// format.
109 class MIRPrinter {
110   raw_ostream &OS;
111   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
112   /// Maps from stack object indices to operand indices which will be used when
113   /// printing frame index machine operands.
114   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
115 
116 public:
117   MIRPrinter(raw_ostream &OS) : OS(OS) {}
118 
119   void print(const MachineFunction &MF);
120 
121   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
122                const TargetRegisterInfo *TRI);
123   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
124                const MachineFrameInfo &MFI);
125   void convert(yaml::MachineFunction &MF,
126                const MachineConstantPool &ConstantPool);
127   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
128                const MachineJumpTableInfo &JTI);
129   void convertStackObjects(yaml::MachineFunction &YMF,
130                            const MachineFunction &MF, ModuleSlotTracker &MST);
131 
132 private:
133   void initRegisterMaskIds(const MachineFunction &MF);
134 };
135 
136 /// This class prints out the machine instructions using the MIR serialization
137 /// format.
138 class MIPrinter {
139   raw_ostream &OS;
140   ModuleSlotTracker &MST;
141   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
142   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143   /// Synchronization scope names registered with LLVMContext.
144   SmallVector<StringRef, 8> SSNs;
145 
146   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
147   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
148 
149 public:
150   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
151             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
152             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
153       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
154         StackObjectOperandMapping(StackObjectOperandMapping) {}
155 
156   void print(const MachineBasicBlock &MBB);
157 
158   void print(const MachineInstr &MI);
159   void printStackObjectReference(int FrameIndex);
160   void print(const MachineInstr &MI, unsigned OpIdx,
161              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
162              LLT TypeToPrint, bool PrintDef = true);
163 };
164 
165 } // end namespace llvm
166 
167 namespace llvm {
168 namespace yaml {
169 
170 /// This struct serializes the LLVM IR module.
171 template <> struct BlockScalarTraits<Module> {
172   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
173     Mod.print(OS, nullptr);
174   }
175 
176   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
177     llvm_unreachable("LLVM Module is supposed to be parsed separately");
178     return "";
179   }
180 };
181 
182 } // end namespace yaml
183 } // end namespace llvm
184 
185 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
186                         const TargetRegisterInfo *TRI) {
187   raw_string_ostream OS(Dest.Value);
188   OS << printReg(Reg, TRI);
189 }
190 
191 void MIRPrinter::print(const MachineFunction &MF) {
192   initRegisterMaskIds(MF);
193 
194   yaml::MachineFunction YamlMF;
195   YamlMF.Name = MF.getName();
196   YamlMF.Alignment = MF.getAlignment();
197   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
198 
199   YamlMF.Legalized = MF.getProperties().hasProperty(
200       MachineFunctionProperties::Property::Legalized);
201   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
202       MachineFunctionProperties::Property::RegBankSelected);
203   YamlMF.Selected = MF.getProperties().hasProperty(
204       MachineFunctionProperties::Property::Selected);
205   YamlMF.FailedISel = MF.getProperties().hasProperty(
206       MachineFunctionProperties::Property::FailedISel);
207 
208   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
209   ModuleSlotTracker MST(MF.getFunction().getParent());
210   MST.incorporateFunction(MF.getFunction());
211   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
212   convertStackObjects(YamlMF, MF, MST);
213   if (const auto *ConstantPool = MF.getConstantPool())
214     convert(YamlMF, *ConstantPool);
215   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
216     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
217   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
218   bool IsNewlineNeeded = false;
219   for (const auto &MBB : MF) {
220     if (IsNewlineNeeded)
221       StrOS << "\n";
222     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
223         .print(MBB);
224     IsNewlineNeeded = true;
225   }
226   StrOS.flush();
227   yaml::Output Out(OS);
228   if (!SimplifyMIR)
229       Out.setWriteDefaultValues(true);
230   Out << YamlMF;
231 }
232 
233 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
234                                const TargetRegisterInfo *TRI) {
235   assert(RegMask && "Can't print an empty register mask");
236   OS << StringRef("CustomRegMask(");
237 
238   bool IsRegInRegMaskFound = false;
239   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
240     // Check whether the register is asserted in regmask.
241     if (RegMask[I / 32] & (1u << (I % 32))) {
242       if (IsRegInRegMaskFound)
243         OS << ',';
244       OS << printReg(I, TRI);
245       IsRegInRegMaskFound = true;
246     }
247   }
248 
249   OS << ')';
250 }
251 
252 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
253                                 const MachineRegisterInfo &RegInfo,
254                                 const TargetRegisterInfo *TRI) {
255   raw_string_ostream OS(Dest.Value);
256   OS << printRegClassOrBank(Reg, RegInfo, TRI);
257 }
258 
259 
260 void MIRPrinter::convert(yaml::MachineFunction &MF,
261                          const MachineRegisterInfo &RegInfo,
262                          const TargetRegisterInfo *TRI) {
263   MF.TracksRegLiveness = RegInfo.tracksLiveness();
264 
265   // Print the virtual register definitions.
266   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
267     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
268     yaml::VirtualRegisterDefinition VReg;
269     VReg.ID = I;
270     if (RegInfo.getVRegName(Reg) != "")
271       continue;
272     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
273     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
274     if (PreferredReg)
275       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
276     MF.VirtualRegisters.push_back(VReg);
277   }
278 
279   // Print the live ins.
280   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
281     yaml::MachineFunctionLiveIn LiveIn;
282     printRegMIR(LI.first, LiveIn.Register, TRI);
283     if (LI.second)
284       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
285     MF.LiveIns.push_back(LiveIn);
286   }
287 
288   // Prints the callee saved registers.
289   if (RegInfo.isUpdatedCSRsInitialized()) {
290     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
291     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
292     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
293       yaml::FlowStringValue Reg;
294       printRegMIR(*I, Reg, TRI);
295       CalleeSavedRegisters.push_back(Reg);
296     }
297     MF.CalleeSavedRegisters = CalleeSavedRegisters;
298   }
299 }
300 
301 void MIRPrinter::convert(ModuleSlotTracker &MST,
302                          yaml::MachineFrameInfo &YamlMFI,
303                          const MachineFrameInfo &MFI) {
304   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
305   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
306   YamlMFI.HasStackMap = MFI.hasStackMap();
307   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
308   YamlMFI.StackSize = MFI.getStackSize();
309   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
310   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
311   YamlMFI.AdjustsStack = MFI.adjustsStack();
312   YamlMFI.HasCalls = MFI.hasCalls();
313   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
314     ? MFI.getMaxCallFrameSize() : ~0u;
315   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
316   YamlMFI.HasVAStart = MFI.hasVAStart();
317   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
318   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
319   if (MFI.getSavePoint()) {
320     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
321     StrOS << printMBBReference(*MFI.getSavePoint());
322   }
323   if (MFI.getRestorePoint()) {
324     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
325     StrOS << printMBBReference(*MFI.getRestorePoint());
326   }
327 }
328 
329 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
330                                      const MachineFunction &MF,
331                                      ModuleSlotTracker &MST) {
332   const MachineFrameInfo &MFI = MF.getFrameInfo();
333   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
334   // Process fixed stack objects.
335   unsigned ID = 0;
336   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
337     if (MFI.isDeadObjectIndex(I))
338       continue;
339 
340     yaml::FixedMachineStackObject YamlObject;
341     YamlObject.ID = ID;
342     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
343                           ? yaml::FixedMachineStackObject::SpillSlot
344                           : yaml::FixedMachineStackObject::DefaultType;
345     YamlObject.Offset = MFI.getObjectOffset(I);
346     YamlObject.Size = MFI.getObjectSize(I);
347     YamlObject.Alignment = MFI.getObjectAlignment(I);
348     YamlObject.StackID = MFI.getStackID(I);
349     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
350     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
351     YMF.FixedStackObjects.push_back(YamlObject);
352     StackObjectOperandMapping.insert(
353         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
354   }
355 
356   // Process ordinary stack objects.
357   ID = 0;
358   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
359     if (MFI.isDeadObjectIndex(I))
360       continue;
361 
362     yaml::MachineStackObject YamlObject;
363     YamlObject.ID = ID;
364     if (const auto *Alloca = MFI.getObjectAllocation(I))
365       YamlObject.Name.Value =
366           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
367     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
368                           ? yaml::MachineStackObject::SpillSlot
369                           : MFI.isVariableSizedObjectIndex(I)
370                                 ? yaml::MachineStackObject::VariableSized
371                                 : yaml::MachineStackObject::DefaultType;
372     YamlObject.Offset = MFI.getObjectOffset(I);
373     YamlObject.Size = MFI.getObjectSize(I);
374     YamlObject.Alignment = MFI.getObjectAlignment(I);
375     YamlObject.StackID = MFI.getStackID(I);
376 
377     YMF.StackObjects.push_back(YamlObject);
378     StackObjectOperandMapping.insert(std::make_pair(
379         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
380   }
381 
382   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
383     yaml::StringValue Reg;
384     printRegMIR(CSInfo.getReg(), Reg, TRI);
385     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
386     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
387            "Invalid stack object index");
388     const FrameIndexOperand &StackObject = StackObjectInfo->second;
389     if (StackObject.IsFixed) {
390       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
391       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
392         CSInfo.isRestored();
393     } else {
394       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
395       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
396         CSInfo.isRestored();
397     }
398   }
399   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
400     auto LocalObject = MFI.getLocalFrameObjectMap(I);
401     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
402     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
403            "Invalid stack object index");
404     const FrameIndexOperand &StackObject = StackObjectInfo->second;
405     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
406     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
407   }
408 
409   // Print the stack object references in the frame information class after
410   // converting the stack objects.
411   if (MFI.hasStackProtectorIndex()) {
412     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
413     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
414         .printStackObjectReference(MFI.getStackProtectorIndex());
415   }
416 
417   // Print the debug variable information.
418   for (const MachineFunction::VariableDbgInfo &DebugVar :
419        MF.getVariableDbgInfo()) {
420     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
421     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
422            "Invalid stack object index");
423     const FrameIndexOperand &StackObject = StackObjectInfo->second;
424     assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
425     auto &Object = YMF.StackObjects[StackObject.ID];
426     {
427       raw_string_ostream StrOS(Object.DebugVar.Value);
428       DebugVar.Var->printAsOperand(StrOS, MST);
429     }
430     {
431       raw_string_ostream StrOS(Object.DebugExpr.Value);
432       DebugVar.Expr->printAsOperand(StrOS, MST);
433     }
434     {
435       raw_string_ostream StrOS(Object.DebugLoc.Value);
436       DebugVar.Loc->printAsOperand(StrOS, MST);
437     }
438   }
439 }
440 
441 void MIRPrinter::convert(yaml::MachineFunction &MF,
442                          const MachineConstantPool &ConstantPool) {
443   unsigned ID = 0;
444   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
445     std::string Str;
446     raw_string_ostream StrOS(Str);
447     if (Constant.isMachineConstantPoolEntry()) {
448       Constant.Val.MachineCPVal->print(StrOS);
449     } else {
450       Constant.Val.ConstVal->printAsOperand(StrOS);
451     }
452 
453     yaml::MachineConstantPoolValue YamlConstant;
454     YamlConstant.ID = ID++;
455     YamlConstant.Value = StrOS.str();
456     YamlConstant.Alignment = Constant.getAlignment();
457     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
458 
459     MF.Constants.push_back(YamlConstant);
460   }
461 }
462 
463 void MIRPrinter::convert(ModuleSlotTracker &MST,
464                          yaml::MachineJumpTable &YamlJTI,
465                          const MachineJumpTableInfo &JTI) {
466   YamlJTI.Kind = JTI.getEntryKind();
467   unsigned ID = 0;
468   for (const auto &Table : JTI.getJumpTables()) {
469     std::string Str;
470     yaml::MachineJumpTable::Entry Entry;
471     Entry.ID = ID++;
472     for (const auto *MBB : Table.MBBs) {
473       raw_string_ostream StrOS(Str);
474       StrOS << printMBBReference(*MBB);
475       Entry.Blocks.push_back(StrOS.str());
476       Str.clear();
477     }
478     YamlJTI.Entries.push_back(Entry);
479   }
480 }
481 
482 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
483   const auto *TRI = MF.getSubtarget().getRegisterInfo();
484   unsigned I = 0;
485   for (const uint32_t *Mask : TRI->getRegMasks())
486     RegisterMaskIds.insert(std::make_pair(Mask, I++));
487 }
488 
489 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
490                            SmallVectorImpl<MachineBasicBlock*> &Result,
491                            bool &IsFallthrough) {
492   SmallPtrSet<MachineBasicBlock*,8> Seen;
493 
494   for (const MachineInstr &MI : MBB) {
495     if (MI.isPHI())
496       continue;
497     for (const MachineOperand &MO : MI.operands()) {
498       if (!MO.isMBB())
499         continue;
500       MachineBasicBlock *Succ = MO.getMBB();
501       auto RP = Seen.insert(Succ);
502       if (RP.second)
503         Result.push_back(Succ);
504     }
505   }
506   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
507   IsFallthrough = I == MBB.end() || !I->isBarrier();
508 }
509 
510 bool
511 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
512   if (MBB.succ_size() <= 1)
513     return true;
514   if (!MBB.hasSuccessorProbabilities())
515     return true;
516 
517   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
518                                               MBB.Probs.end());
519   BranchProbability::normalizeProbabilities(Normalized.begin(),
520                                             Normalized.end());
521   SmallVector<BranchProbability,8> Equal(Normalized.size());
522   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
523 
524   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
525 }
526 
527 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
528   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
529   bool GuessedFallthrough;
530   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
531   if (GuessedFallthrough) {
532     const MachineFunction &MF = *MBB.getParent();
533     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
534     if (NextI != MF.end()) {
535       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
536       if (!is_contained(GuessedSuccs, Next))
537         GuessedSuccs.push_back(Next);
538     }
539   }
540   if (GuessedSuccs.size() != MBB.succ_size())
541     return false;
542   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
543 }
544 
545 void MIPrinter::print(const MachineBasicBlock &MBB) {
546   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
547   OS << "bb." << MBB.getNumber();
548   bool HasAttributes = false;
549   if (const auto *BB = MBB.getBasicBlock()) {
550     if (BB->hasName()) {
551       OS << "." << BB->getName();
552     } else {
553       HasAttributes = true;
554       OS << " (";
555       int Slot = MST.getLocalSlot(BB);
556       if (Slot == -1)
557         OS << "<ir-block badref>";
558       else
559         OS << (Twine("%ir-block.") + Twine(Slot)).str();
560     }
561   }
562   if (MBB.hasAddressTaken()) {
563     OS << (HasAttributes ? ", " : " (");
564     OS << "address-taken";
565     HasAttributes = true;
566   }
567   if (MBB.isEHPad()) {
568     OS << (HasAttributes ? ", " : " (");
569     OS << "landing-pad";
570     HasAttributes = true;
571   }
572   if (MBB.getAlignment()) {
573     OS << (HasAttributes ? ", " : " (");
574     OS << "align " << MBB.getAlignment();
575     HasAttributes = true;
576   }
577   if (HasAttributes)
578     OS << ")";
579   OS << ":\n";
580 
581   bool HasLineAttributes = false;
582   // Print the successors
583   bool canPredictProbs = canPredictBranchProbabilities(MBB);
584   // Even if the list of successors is empty, if we cannot guess it,
585   // we need to print it to tell the parser that the list is empty.
586   // This is needed, because MI model unreachable as empty blocks
587   // with an empty successor list. If the parser would see that
588   // without the successor list, it would guess the code would
589   // fallthrough.
590   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
591       !canPredictSuccessors(MBB)) {
592     OS.indent(2) << "successors: ";
593     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
594       if (I != MBB.succ_begin())
595         OS << ", ";
596       OS << printMBBReference(**I);
597       if (!SimplifyMIR || !canPredictProbs)
598         OS << '('
599            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
600            << ')';
601     }
602     OS << "\n";
603     HasLineAttributes = true;
604   }
605 
606   // Print the live in registers.
607   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
608   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
609     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
610     OS.indent(2) << "liveins: ";
611     bool First = true;
612     for (const auto &LI : MBB.liveins()) {
613       if (!First)
614         OS << ", ";
615       First = false;
616       OS << printReg(LI.PhysReg, &TRI);
617       if (!LI.LaneMask.all())
618         OS << ":0x" << PrintLaneMask(LI.LaneMask);
619     }
620     OS << "\n";
621     HasLineAttributes = true;
622   }
623 
624   if (HasLineAttributes)
625     OS << "\n";
626   bool IsInBundle = false;
627   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
628     const MachineInstr &MI = *I;
629     if (IsInBundle && !MI.isInsideBundle()) {
630       OS.indent(2) << "}\n";
631       IsInBundle = false;
632     }
633     OS.indent(IsInBundle ? 4 : 2);
634     print(MI);
635     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
636       OS << " {";
637       IsInBundle = true;
638     }
639     OS << "\n";
640   }
641   if (IsInBundle)
642     OS.indent(2) << "}\n";
643 }
644 
645 void MIPrinter::print(const MachineInstr &MI) {
646   const auto *MF = MI.getMF();
647   const auto &MRI = MF->getRegInfo();
648   const auto &SubTarget = MF->getSubtarget();
649   const auto *TRI = SubTarget.getRegisterInfo();
650   assert(TRI && "Expected target register info");
651   const auto *TII = SubTarget.getInstrInfo();
652   assert(TII && "Expected target instruction info");
653   if (MI.isCFIInstruction())
654     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
655 
656   SmallBitVector PrintedTypes(8);
657   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
658   unsigned I = 0, E = MI.getNumOperands();
659   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
660          !MI.getOperand(I).isImplicit();
661        ++I) {
662     if (I)
663       OS << ", ";
664     print(MI, I, TRI, ShouldPrintRegisterTies,
665           MI.getTypeToPrint(I, PrintedTypes, MRI),
666           /*PrintDef=*/false);
667   }
668 
669   if (I)
670     OS << " = ";
671   if (MI.getFlag(MachineInstr::FrameSetup))
672     OS << "frame-setup ";
673   if (MI.getFlag(MachineInstr::FrameDestroy))
674     OS << "frame-destroy ";
675 
676   OS << TII->getName(MI.getOpcode());
677   if (I < E)
678     OS << ' ';
679 
680   bool NeedComma = false;
681   for (; I < E; ++I) {
682     if (NeedComma)
683       OS << ", ";
684     print(MI, I, TRI, ShouldPrintRegisterTies,
685           MI.getTypeToPrint(I, PrintedTypes, MRI));
686     NeedComma = true;
687   }
688 
689   if (const DebugLoc &DL = MI.getDebugLoc()) {
690     if (NeedComma)
691       OS << ',';
692     OS << " debug-location ";
693     DL->printAsOperand(OS, MST);
694   }
695 
696   if (!MI.memoperands_empty()) {
697     OS << " :: ";
698     const LLVMContext &Context = MF->getFunction().getContext();
699     const MachineFrameInfo &MFI = MF->getFrameInfo();
700     bool NeedComma = false;
701     for (const auto *Op : MI.memoperands()) {
702       if (NeedComma)
703         OS << ", ";
704       Op->print(OS, MST, SSNs, Context, &MFI, TII);
705       NeedComma = true;
706     }
707   }
708 }
709 
710 void MIPrinter::printStackObjectReference(int FrameIndex) {
711   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
712   assert(ObjectInfo != StackObjectOperandMapping.end() &&
713          "Invalid frame index");
714   const FrameIndexOperand &Operand = ObjectInfo->second;
715   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
716                                             Operand.Name);
717 }
718 
719 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
720                       const TargetRegisterInfo *TRI,
721                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
722                       bool PrintDef) {
723   const MachineOperand &Op = MI.getOperand(OpIdx);
724   switch (Op.getType()) {
725   case MachineOperand::MO_Immediate:
726     if (MI.isOperandSubregIdx(OpIdx)) {
727       MachineOperand::printTargetFlags(OS, Op);
728       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
729       break;
730     }
731     LLVM_FALLTHROUGH;
732   case MachineOperand::MO_Register:
733   case MachineOperand::MO_CImmediate:
734   case MachineOperand::MO_FPImmediate:
735   case MachineOperand::MO_MachineBasicBlock:
736   case MachineOperand::MO_ConstantPoolIndex:
737   case MachineOperand::MO_TargetIndex:
738   case MachineOperand::MO_JumpTableIndex:
739   case MachineOperand::MO_ExternalSymbol:
740   case MachineOperand::MO_GlobalAddress:
741   case MachineOperand::MO_RegisterLiveOut:
742   case MachineOperand::MO_Metadata:
743   case MachineOperand::MO_MCSymbol:
744   case MachineOperand::MO_CFIIndex:
745   case MachineOperand::MO_IntrinsicID:
746   case MachineOperand::MO_Predicate:
747   case MachineOperand::MO_BlockAddress: {
748     unsigned TiedOperandIdx = 0;
749     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
750       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
751     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
752     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
753              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
754     break;
755   }
756   case MachineOperand::MO_FrameIndex:
757     printStackObjectReference(Op.getIndex());
758     break;
759   case MachineOperand::MO_RegisterMask: {
760     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
761     if (RegMaskInfo != RegisterMaskIds.end())
762       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
763     else
764       printCustomRegMask(Op.getRegMask(), OS, TRI);
765     break;
766   }
767   }
768 }
769 
770 void llvm::printMIR(raw_ostream &OS, const Module &M) {
771   yaml::Output Out(OS);
772   Out << const_cast<Module &>(M);
773 }
774 
775 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
776   MIRPrinter Printer(OS);
777   Printer.print(MF);
778 }
779