1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 
34 /// This class prints out the machine functions using the MIR serialization
35 /// format.
36 class MIRPrinter {
37   raw_ostream &OS;
38   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
39 
40 public:
41   MIRPrinter(raw_ostream &OS) : OS(OS) {}
42 
43   void print(const MachineFunction &MF);
44 
45   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
46                const TargetRegisterInfo *TRI);
47   void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
48   void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
49                const MachineBasicBlock &MBB);
50   void convertStackObjects(yaml::MachineFunction &MF,
51                            const MachineFrameInfo &MFI);
52 
53 private:
54   void initRegisterMaskIds(const MachineFunction &MF);
55 };
56 
57 /// This class prints out the machine instructions using the MIR serialization
58 /// format.
59 class MIPrinter {
60   raw_ostream &OS;
61   ModuleSlotTracker &MST;
62   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
63 
64 public:
65   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
66             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
67       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
68 
69   void print(const MachineInstr &MI);
70   void printMBBReference(const MachineBasicBlock &MBB);
71   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
72 };
73 
74 } // end anonymous namespace
75 
76 namespace llvm {
77 namespace yaml {
78 
79 /// This struct serializes the LLVM IR module.
80 template <> struct BlockScalarTraits<Module> {
81   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
82     Mod.print(OS, nullptr);
83   }
84   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
85     llvm_unreachable("LLVM Module is supposed to be parsed separately");
86     return "";
87   }
88 };
89 
90 } // end namespace yaml
91 } // end namespace llvm
92 
93 void MIRPrinter::print(const MachineFunction &MF) {
94   initRegisterMaskIds(MF);
95 
96   yaml::MachineFunction YamlMF;
97   YamlMF.Name = MF.getName();
98   YamlMF.Alignment = MF.getAlignment();
99   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
100   YamlMF.HasInlineAsm = MF.hasInlineAsm();
101   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
102   convert(YamlMF.FrameInfo, *MF.getFrameInfo());
103   convertStackObjects(YamlMF, *MF.getFrameInfo());
104 
105   int I = 0;
106   ModuleSlotTracker MST(MF.getFunction()->getParent());
107   for (const auto &MBB : MF) {
108     // TODO: Allow printing of non sequentially numbered MBBs.
109     // This is currently needed as the basic block references get their index
110     // from MBB.getNumber(), thus it should be sequential so that the parser can
111     // map back to the correct MBBs when parsing the output.
112     assert(MBB.getNumber() == I++ &&
113            "Can't print MBBs that aren't sequentially numbered");
114     (void)I;
115     yaml::MachineBasicBlock YamlMBB;
116     convert(MST, YamlMBB, MBB);
117     YamlMF.BasicBlocks.push_back(YamlMBB);
118   }
119   yaml::Output Out(OS);
120   Out << YamlMF;
121 }
122 
123 void MIRPrinter::convert(yaml::MachineFunction &MF,
124                          const MachineRegisterInfo &RegInfo,
125                          const TargetRegisterInfo *TRI) {
126   MF.IsSSA = RegInfo.isSSA();
127   MF.TracksRegLiveness = RegInfo.tracksLiveness();
128   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
129 
130   // Print the virtual register definitions.
131   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
132     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
133     yaml::VirtualRegisterDefinition VReg;
134     VReg.ID = I;
135     VReg.Class =
136         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
137     MF.VirtualRegisters.push_back(VReg);
138   }
139 }
140 
141 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
142                          const MachineFrameInfo &MFI) {
143   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
144   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
145   YamlMFI.HasStackMap = MFI.hasStackMap();
146   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
147   YamlMFI.StackSize = MFI.getStackSize();
148   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
149   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
150   YamlMFI.AdjustsStack = MFI.adjustsStack();
151   YamlMFI.HasCalls = MFI.hasCalls();
152   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
153   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
154   YamlMFI.HasVAStart = MFI.hasVAStart();
155   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
156 }
157 
158 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
159                                      const MachineFrameInfo &MFI) {
160   // Process fixed stack objects.
161   unsigned ID = 0;
162   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
163     if (MFI.isDeadObjectIndex(I))
164       continue;
165 
166     yaml::FixedMachineStackObject YamlObject;
167     YamlObject.ID = ID++;
168     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
169                           ? yaml::FixedMachineStackObject::SpillSlot
170                           : yaml::FixedMachineStackObject::DefaultType;
171     YamlObject.Offset = MFI.getObjectOffset(I);
172     YamlObject.Size = MFI.getObjectSize(I);
173     YamlObject.Alignment = MFI.getObjectAlignment(I);
174     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
175     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
176     MF.FixedStackObjects.push_back(YamlObject);
177     // TODO: Store the mapping between fixed object IDs and object indices to
178     // print the fixed stack object references correctly.
179   }
180 
181   // Process ordinary stack objects.
182   ID = 0;
183   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
184     if (MFI.isDeadObjectIndex(I))
185       continue;
186 
187     yaml::MachineStackObject YamlObject;
188     YamlObject.ID = ID++;
189     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
190                           ? yaml::MachineStackObject::SpillSlot
191                           : MFI.isVariableSizedObjectIndex(I)
192                                 ? yaml::MachineStackObject::VariableSized
193                                 : yaml::MachineStackObject::DefaultType;
194     YamlObject.Offset = MFI.getObjectOffset(I);
195     YamlObject.Size = MFI.getObjectSize(I);
196     YamlObject.Alignment = MFI.getObjectAlignment(I);
197 
198     MF.StackObjects.push_back(YamlObject);
199     // TODO: Store the mapping between object IDs and object indices to print
200     // the stack object references correctly.
201   }
202 }
203 
204 void MIRPrinter::convert(ModuleSlotTracker &MST,
205                          yaml::MachineBasicBlock &YamlMBB,
206                          const MachineBasicBlock &MBB) {
207   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
208   YamlMBB.ID = (unsigned)MBB.getNumber();
209   // TODO: Serialize unnamed BB references.
210   if (const auto *BB = MBB.getBasicBlock())
211     YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
212   else
213     YamlMBB.Name.Value = "";
214   YamlMBB.Alignment = MBB.getAlignment();
215   YamlMBB.AddressTaken = MBB.hasAddressTaken();
216   YamlMBB.IsLandingPad = MBB.isLandingPad();
217   for (const auto *SuccMBB : MBB.successors()) {
218     std::string Str;
219     raw_string_ostream StrOS(Str);
220     MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
221     YamlMBB.Successors.push_back(StrOS.str());
222   }
223 
224   // Print the machine instructions.
225   YamlMBB.Instructions.reserve(MBB.size());
226   std::string Str;
227   for (const auto &MI : MBB) {
228     raw_string_ostream StrOS(Str);
229     MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
230     YamlMBB.Instructions.push_back(StrOS.str());
231     Str.clear();
232   }
233 }
234 
235 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
236   const auto *TRI = MF.getSubtarget().getRegisterInfo();
237   unsigned I = 0;
238   for (const uint32_t *Mask : TRI->getRegMasks())
239     RegisterMaskIds.insert(std::make_pair(Mask, I++));
240 }
241 
242 void MIPrinter::print(const MachineInstr &MI) {
243   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
244   const auto *TRI = SubTarget.getRegisterInfo();
245   assert(TRI && "Expected target register info");
246   const auto *TII = SubTarget.getInstrInfo();
247   assert(TII && "Expected target instruction info");
248 
249   unsigned I = 0, E = MI.getNumOperands();
250   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
251          !MI.getOperand(I).isImplicit();
252        ++I) {
253     if (I)
254       OS << ", ";
255     print(MI.getOperand(I), TRI);
256   }
257 
258   if (I)
259     OS << " = ";
260   OS << TII->getName(MI.getOpcode());
261   // TODO: Print the instruction flags, machine mem operands.
262   if (I < E)
263     OS << ' ';
264 
265   bool NeedComma = false;
266   for (; I < E; ++I) {
267     if (NeedComma)
268       OS << ", ";
269     print(MI.getOperand(I), TRI);
270     NeedComma = true;
271   }
272 }
273 
274 static void printReg(unsigned Reg, raw_ostream &OS,
275                      const TargetRegisterInfo *TRI) {
276   // TODO: Print Stack Slots.
277   if (!Reg)
278     OS << '_';
279   else if (TargetRegisterInfo::isVirtualRegister(Reg))
280     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
281   else if (Reg < TRI->getNumRegs())
282     OS << '%' << StringRef(TRI->getName(Reg)).lower();
283   else
284     llvm_unreachable("Can't print this kind of register yet");
285 }
286 
287 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
288   OS << "%bb." << MBB.getNumber();
289   if (const auto *BB = MBB.getBasicBlock()) {
290     if (BB->hasName())
291       OS << '.' << BB->getName();
292   }
293 }
294 
295 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
296   switch (Op.getType()) {
297   case MachineOperand::MO_Register:
298     // TODO: Print the other register flags.
299     if (Op.isImplicit())
300       OS << (Op.isDef() ? "implicit-def " : "implicit ");
301     if (Op.isDead())
302       OS << "dead ";
303     if (Op.isKill())
304       OS << "killed ";
305     if (Op.isUndef())
306       OS << "undef ";
307     printReg(Op.getReg(), OS, TRI);
308     // Print the sub register.
309     if (Op.getSubReg() != 0)
310       OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
311     break;
312   case MachineOperand::MO_Immediate:
313     OS << Op.getImm();
314     break;
315   case MachineOperand::MO_MachineBasicBlock:
316     printMBBReference(*Op.getMBB());
317     break;
318   case MachineOperand::MO_GlobalAddress:
319     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
320     // TODO: Print offset and target flags.
321     break;
322   case MachineOperand::MO_RegisterMask: {
323     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
324     if (RegMaskInfo != RegisterMaskIds.end())
325       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
326     else
327       llvm_unreachable("Can't print this machine register mask yet.");
328     break;
329   }
330   default:
331     // TODO: Print the other machine operands.
332     llvm_unreachable("Can't print this machine operand at the moment");
333   }
334 }
335 
336 void llvm::printMIR(raw_ostream &OS, const Module &M) {
337   yaml::Output Out(OS);
338   Out << const_cast<Module &>(M);
339 }
340 
341 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
342   MIRPrinter Printer(OS);
343   Printer.print(MF);
344 }
345