1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 
34 /// This class prints out the machine functions using the MIR serialization
35 /// format.
36 class MIRPrinter {
37   raw_ostream &OS;
38   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
39 
40 public:
41   MIRPrinter(raw_ostream &OS) : OS(OS) {}
42 
43   void print(const MachineFunction &MF);
44 
45   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
46                const TargetRegisterInfo *TRI);
47   void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
48   void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
49                const MachineBasicBlock &MBB);
50 
51 private:
52   void initRegisterMaskIds(const MachineFunction &MF);
53 };
54 
55 /// This class prints out the machine instructions using the MIR serialization
56 /// format.
57 class MIPrinter {
58   raw_ostream &OS;
59   ModuleSlotTracker &MST;
60   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
61 
62 public:
63   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
64             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
65       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
66 
67   void print(const MachineInstr &MI);
68   void printMBBReference(const MachineBasicBlock &MBB);
69   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
70 };
71 
72 } // end anonymous namespace
73 
74 namespace llvm {
75 namespace yaml {
76 
77 /// This struct serializes the LLVM IR module.
78 template <> struct BlockScalarTraits<Module> {
79   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
80     Mod.print(OS, nullptr);
81   }
82   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
83     llvm_unreachable("LLVM Module is supposed to be parsed separately");
84     return "";
85   }
86 };
87 
88 } // end namespace yaml
89 } // end namespace llvm
90 
91 void MIRPrinter::print(const MachineFunction &MF) {
92   initRegisterMaskIds(MF);
93 
94   yaml::MachineFunction YamlMF;
95   YamlMF.Name = MF.getName();
96   YamlMF.Alignment = MF.getAlignment();
97   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
98   YamlMF.HasInlineAsm = MF.hasInlineAsm();
99   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
100   convert(YamlMF.FrameInfo, *MF.getFrameInfo());
101 
102   int I = 0;
103   ModuleSlotTracker MST(MF.getFunction()->getParent());
104   for (const auto &MBB : MF) {
105     // TODO: Allow printing of non sequentially numbered MBBs.
106     // This is currently needed as the basic block references get their index
107     // from MBB.getNumber(), thus it should be sequential so that the parser can
108     // map back to the correct MBBs when parsing the output.
109     assert(MBB.getNumber() == I++ &&
110            "Can't print MBBs that aren't sequentially numbered");
111     (void)I;
112     yaml::MachineBasicBlock YamlMBB;
113     convert(MST, YamlMBB, MBB);
114     YamlMF.BasicBlocks.push_back(YamlMBB);
115   }
116   yaml::Output Out(OS);
117   Out << YamlMF;
118 }
119 
120 void MIRPrinter::convert(yaml::MachineFunction &MF,
121                          const MachineRegisterInfo &RegInfo,
122                          const TargetRegisterInfo *TRI) {
123   MF.IsSSA = RegInfo.isSSA();
124   MF.TracksRegLiveness = RegInfo.tracksLiveness();
125   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
126 
127   // Print the virtual register definitions.
128   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
129     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
130     yaml::VirtualRegisterDefinition VReg;
131     VReg.ID = I;
132     VReg.Class =
133         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
134     MF.VirtualRegisters.push_back(VReg);
135   }
136 }
137 
138 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
139                          const MachineFrameInfo &MFI) {
140   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
141   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
142   YamlMFI.HasStackMap = MFI.hasStackMap();
143   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
144   YamlMFI.StackSize = MFI.getStackSize();
145   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
146   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
147   YamlMFI.AdjustsStack = MFI.adjustsStack();
148   YamlMFI.HasCalls = MFI.hasCalls();
149   YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
150   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
151   YamlMFI.HasVAStart = MFI.hasVAStart();
152   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
153 }
154 
155 void MIRPrinter::convert(ModuleSlotTracker &MST,
156                          yaml::MachineBasicBlock &YamlMBB,
157                          const MachineBasicBlock &MBB) {
158   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
159   YamlMBB.ID = (unsigned)MBB.getNumber();
160   // TODO: Serialize unnamed BB references.
161   if (const auto *BB = MBB.getBasicBlock())
162     YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
163   else
164     YamlMBB.Name.Value = "";
165   YamlMBB.Alignment = MBB.getAlignment();
166   YamlMBB.AddressTaken = MBB.hasAddressTaken();
167   YamlMBB.IsLandingPad = MBB.isLandingPad();
168   for (const auto *SuccMBB : MBB.successors()) {
169     std::string Str;
170     raw_string_ostream StrOS(Str);
171     MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
172     YamlMBB.Successors.push_back(StrOS.str());
173   }
174 
175   // Print the machine instructions.
176   YamlMBB.Instructions.reserve(MBB.size());
177   std::string Str;
178   for (const auto &MI : MBB) {
179     raw_string_ostream StrOS(Str);
180     MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
181     YamlMBB.Instructions.push_back(StrOS.str());
182     Str.clear();
183   }
184 }
185 
186 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
187   const auto *TRI = MF.getSubtarget().getRegisterInfo();
188   unsigned I = 0;
189   for (const uint32_t *Mask : TRI->getRegMasks())
190     RegisterMaskIds.insert(std::make_pair(Mask, I++));
191 }
192 
193 void MIPrinter::print(const MachineInstr &MI) {
194   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
195   const auto *TRI = SubTarget.getRegisterInfo();
196   assert(TRI && "Expected target register info");
197   const auto *TII = SubTarget.getInstrInfo();
198   assert(TII && "Expected target instruction info");
199 
200   unsigned I = 0, E = MI.getNumOperands();
201   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
202          !MI.getOperand(I).isImplicit();
203        ++I) {
204     if (I)
205       OS << ", ";
206     print(MI.getOperand(I), TRI);
207   }
208 
209   if (I)
210     OS << " = ";
211   OS << TII->getName(MI.getOpcode());
212   // TODO: Print the instruction flags, machine mem operands.
213   if (I < E)
214     OS << ' ';
215 
216   bool NeedComma = false;
217   for (; I < E; ++I) {
218     if (NeedComma)
219       OS << ", ";
220     print(MI.getOperand(I), TRI);
221     NeedComma = true;
222   }
223 }
224 
225 static void printReg(unsigned Reg, raw_ostream &OS,
226                      const TargetRegisterInfo *TRI) {
227   // TODO: Print Stack Slots.
228   // TODO: Print virtual registers.
229   if (!Reg)
230     OS << '_';
231   else if (Reg < TRI->getNumRegs())
232     OS << '%' << StringRef(TRI->getName(Reg)).lower();
233   else
234     llvm_unreachable("Can't print this kind of register yet");
235 }
236 
237 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
238   OS << "%bb." << MBB.getNumber();
239   if (const auto *BB = MBB.getBasicBlock()) {
240     if (BB->hasName())
241       OS << '.' << BB->getName();
242   }
243 }
244 
245 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
246   switch (Op.getType()) {
247   case MachineOperand::MO_Register:
248     // TODO: Print the other register flags.
249     if (Op.isImplicit())
250       OS << (Op.isDef() ? "implicit-def " : "implicit ");
251     if (Op.isDead())
252       OS << "dead ";
253     if (Op.isKill())
254       OS << "killed ";
255     if (Op.isUndef())
256       OS << "undef ";
257     printReg(Op.getReg(), OS, TRI);
258     // TODO: Print sub register.
259     break;
260   case MachineOperand::MO_Immediate:
261     OS << Op.getImm();
262     break;
263   case MachineOperand::MO_MachineBasicBlock:
264     printMBBReference(*Op.getMBB());
265     break;
266   case MachineOperand::MO_GlobalAddress:
267     Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
268     // TODO: Print offset and target flags.
269     break;
270   case MachineOperand::MO_RegisterMask: {
271     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
272     if (RegMaskInfo != RegisterMaskIds.end())
273       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
274     else
275       llvm_unreachable("Can't print this machine register mask yet.");
276     break;
277   }
278   default:
279     // TODO: Print the other machine operands.
280     llvm_unreachable("Can't print this machine operand at the moment");
281   }
282 }
283 
284 void llvm::printMIR(raw_ostream &OS, const Module &M) {
285   yaml::Output Out(OS);
286   Out << const_cast<Module &>(M);
287 }
288 
289 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
290   MIRPrinter Printer(OS);
291   Printer.print(MF);
292 }
293