1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the class that prints out the LLVM IR and machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MIRPrinter.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallBitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24 #include "llvm/CodeGen/MIRYamlMapping.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/TargetInstrInfo.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/IRPrintingPasses.h"
45 #include "llvm/IR/InstrTypes.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/IR/ModuleSlotTracker.h"
50 #include "llvm/IR/Value.h"
51 #include "llvm/MC/LaneBitmask.h"
52 #include "llvm/MC/MCContext.h"
53 #include "llvm/MC/MCDwarf.h"
54 #include "llvm/MC/MCSymbol.h"
55 #include "llvm/Support/AtomicOrdering.h"
56 #include "llvm/Support/BranchProbability.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CommandLine.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/Format.h"
61 #include "llvm/Support/LowLevelTypeImpl.h"
62 #include "llvm/Support/YAMLTraits.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetIntrinsicInfo.h"
65 #include "llvm/Target/TargetMachine.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cinttypes>
69 #include <cstdint>
70 #include <iterator>
71 #include <string>
72 #include <utility>
73 #include <vector>
74 
75 using namespace llvm;
76 
77 static cl::opt<bool> SimplifyMIR(
78     "simplify-mir", cl::Hidden,
79     cl::desc("Leave out unnecessary information when printing MIR"));
80 
81 namespace {
82 
83 /// This structure describes how to print out stack object references.
84 struct FrameIndexOperand {
85   std::string Name;
86   unsigned ID;
87   bool IsFixed;
88 
89   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
90       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
91 
92   /// Return an ordinary stack object reference.
93   static FrameIndexOperand create(StringRef Name, unsigned ID) {
94     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
95   }
96 
97   /// Return a fixed stack object reference.
98   static FrameIndexOperand createFixed(unsigned ID) {
99     return FrameIndexOperand("", ID, /*IsFixed=*/true);
100   }
101 };
102 
103 } // end anonymous namespace
104 
105 namespace llvm {
106 
107 /// This class prints out the machine functions using the MIR serialization
108 /// format.
109 class MIRPrinter {
110   raw_ostream &OS;
111   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
112   /// Maps from stack object indices to operand indices which will be used when
113   /// printing frame index machine operands.
114   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
115 
116 public:
117   MIRPrinter(raw_ostream &OS) : OS(OS) {}
118 
119   void print(const MachineFunction &MF);
120 
121   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
122                const TargetRegisterInfo *TRI);
123   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
124                const MachineFrameInfo &MFI);
125   void convert(yaml::MachineFunction &MF,
126                const MachineConstantPool &ConstantPool);
127   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
128                const MachineJumpTableInfo &JTI);
129   void convertStackObjects(yaml::MachineFunction &YMF,
130                            const MachineFunction &MF, ModuleSlotTracker &MST);
131 
132 private:
133   void initRegisterMaskIds(const MachineFunction &MF);
134 };
135 
136 /// This class prints out the machine instructions using the MIR serialization
137 /// format.
138 class MIPrinter {
139   raw_ostream &OS;
140   ModuleSlotTracker &MST;
141   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
142   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143   /// Synchronization scope names registered with LLVMContext.
144   SmallVector<StringRef, 8> SSNs;
145 
146   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
147   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
148 
149 public:
150   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
151             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
152             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
153       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
154         StackObjectOperandMapping(StackObjectOperandMapping) {}
155 
156   void print(const MachineBasicBlock &MBB);
157 
158   void print(const MachineInstr &MI);
159   void printStackObjectReference(int FrameIndex);
160   void print(const MachineInstr &MI, unsigned OpIdx,
161              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
162              LLT TypeToPrint, bool PrintDef = true);
163 };
164 
165 } // end namespace llvm
166 
167 namespace llvm {
168 namespace yaml {
169 
170 /// This struct serializes the LLVM IR module.
171 template <> struct BlockScalarTraits<Module> {
172   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
173     Mod.print(OS, nullptr);
174   }
175 
176   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
177     llvm_unreachable("LLVM Module is supposed to be parsed separately");
178     return "";
179   }
180 };
181 
182 } // end namespace yaml
183 } // end namespace llvm
184 
185 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
186                         const TargetRegisterInfo *TRI) {
187   raw_string_ostream OS(Dest.Value);
188   OS << printReg(Reg, TRI);
189 }
190 
191 void MIRPrinter::print(const MachineFunction &MF) {
192   initRegisterMaskIds(MF);
193 
194   yaml::MachineFunction YamlMF;
195   YamlMF.Name = MF.getName();
196   YamlMF.Alignment = MF.getAlignment();
197   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
198   YamlMF.HasWinCFI = MF.hasWinCFI();
199 
200   YamlMF.Legalized = MF.getProperties().hasProperty(
201       MachineFunctionProperties::Property::Legalized);
202   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
203       MachineFunctionProperties::Property::RegBankSelected);
204   YamlMF.Selected = MF.getProperties().hasProperty(
205       MachineFunctionProperties::Property::Selected);
206   YamlMF.FailedISel = MF.getProperties().hasProperty(
207       MachineFunctionProperties::Property::FailedISel);
208 
209   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
210   ModuleSlotTracker MST(MF.getFunction().getParent());
211   MST.incorporateFunction(MF.getFunction());
212   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
213   convertStackObjects(YamlMF, MF, MST);
214   if (const auto *ConstantPool = MF.getConstantPool())
215     convert(YamlMF, *ConstantPool);
216   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
217     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
218   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
219   bool IsNewlineNeeded = false;
220   for (const auto &MBB : MF) {
221     if (IsNewlineNeeded)
222       StrOS << "\n";
223     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
224         .print(MBB);
225     IsNewlineNeeded = true;
226   }
227   StrOS.flush();
228   yaml::Output Out(OS);
229   if (!SimplifyMIR)
230       Out.setWriteDefaultValues(true);
231   Out << YamlMF;
232 }
233 
234 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
235                                const TargetRegisterInfo *TRI) {
236   assert(RegMask && "Can't print an empty register mask");
237   OS << StringRef("CustomRegMask(");
238 
239   bool IsRegInRegMaskFound = false;
240   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
241     // Check whether the register is asserted in regmask.
242     if (RegMask[I / 32] & (1u << (I % 32))) {
243       if (IsRegInRegMaskFound)
244         OS << ',';
245       OS << printReg(I, TRI);
246       IsRegInRegMaskFound = true;
247     }
248   }
249 
250   OS << ')';
251 }
252 
253 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
254                                 const MachineRegisterInfo &RegInfo,
255                                 const TargetRegisterInfo *TRI) {
256   raw_string_ostream OS(Dest.Value);
257   OS << printRegClassOrBank(Reg, RegInfo, TRI);
258 }
259 
260 template <typename T>
261 static void
262 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
263                         T &Object, ModuleSlotTracker &MST) {
264   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
265                                         &Object.DebugExpr.Value,
266                                         &Object.DebugLoc.Value}};
267   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
268                                         DebugVar.Expr,
269                                         DebugVar.Loc}};
270   for (unsigned i = 0; i < 3; ++i) {
271     raw_string_ostream StrOS(*Outputs[i]);
272     Metas[i]->printAsOperand(StrOS, MST);
273   }
274 }
275 
276 void MIRPrinter::convert(yaml::MachineFunction &MF,
277                          const MachineRegisterInfo &RegInfo,
278                          const TargetRegisterInfo *TRI) {
279   MF.TracksRegLiveness = RegInfo.tracksLiveness();
280 
281   // Print the virtual register definitions.
282   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
283     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
284     yaml::VirtualRegisterDefinition VReg;
285     VReg.ID = I;
286     if (RegInfo.getVRegName(Reg) != "")
287       continue;
288     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
289     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
290     if (PreferredReg)
291       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
292     MF.VirtualRegisters.push_back(VReg);
293   }
294 
295   // Print the live ins.
296   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
297     yaml::MachineFunctionLiveIn LiveIn;
298     printRegMIR(LI.first, LiveIn.Register, TRI);
299     if (LI.second)
300       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
301     MF.LiveIns.push_back(LiveIn);
302   }
303 
304   // Prints the callee saved registers.
305   if (RegInfo.isUpdatedCSRsInitialized()) {
306     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
307     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
308     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
309       yaml::FlowStringValue Reg;
310       printRegMIR(*I, Reg, TRI);
311       CalleeSavedRegisters.push_back(Reg);
312     }
313     MF.CalleeSavedRegisters = CalleeSavedRegisters;
314   }
315 }
316 
317 void MIRPrinter::convert(ModuleSlotTracker &MST,
318                          yaml::MachineFrameInfo &YamlMFI,
319                          const MachineFrameInfo &MFI) {
320   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
321   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
322   YamlMFI.HasStackMap = MFI.hasStackMap();
323   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
324   YamlMFI.StackSize = MFI.getStackSize();
325   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
326   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
327   YamlMFI.AdjustsStack = MFI.adjustsStack();
328   YamlMFI.HasCalls = MFI.hasCalls();
329   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
330     ? MFI.getMaxCallFrameSize() : ~0u;
331   YamlMFI.CVBytesOfCalleeSavedRegisters =
332       MFI.getCVBytesOfCalleeSavedRegisters();
333   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
334   YamlMFI.HasVAStart = MFI.hasVAStart();
335   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
336   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
337   if (MFI.getSavePoint()) {
338     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
339     StrOS << printMBBReference(*MFI.getSavePoint());
340   }
341   if (MFI.getRestorePoint()) {
342     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
343     StrOS << printMBBReference(*MFI.getRestorePoint());
344   }
345 }
346 
347 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
348                                      const MachineFunction &MF,
349                                      ModuleSlotTracker &MST) {
350   const MachineFrameInfo &MFI = MF.getFrameInfo();
351   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
352   // Process fixed stack objects.
353   unsigned ID = 0;
354   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
355     if (MFI.isDeadObjectIndex(I))
356       continue;
357 
358     yaml::FixedMachineStackObject YamlObject;
359     YamlObject.ID = ID;
360     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
361                           ? yaml::FixedMachineStackObject::SpillSlot
362                           : yaml::FixedMachineStackObject::DefaultType;
363     YamlObject.Offset = MFI.getObjectOffset(I);
364     YamlObject.Size = MFI.getObjectSize(I);
365     YamlObject.Alignment = MFI.getObjectAlignment(I);
366     YamlObject.StackID = MFI.getStackID(I);
367     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
368     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
369     YMF.FixedStackObjects.push_back(YamlObject);
370     StackObjectOperandMapping.insert(
371         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
372   }
373 
374   // Process ordinary stack objects.
375   ID = 0;
376   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
377     if (MFI.isDeadObjectIndex(I))
378       continue;
379 
380     yaml::MachineStackObject YamlObject;
381     YamlObject.ID = ID;
382     if (const auto *Alloca = MFI.getObjectAllocation(I))
383       YamlObject.Name.Value =
384           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
385     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
386                           ? yaml::MachineStackObject::SpillSlot
387                           : MFI.isVariableSizedObjectIndex(I)
388                                 ? yaml::MachineStackObject::VariableSized
389                                 : yaml::MachineStackObject::DefaultType;
390     YamlObject.Offset = MFI.getObjectOffset(I);
391     YamlObject.Size = MFI.getObjectSize(I);
392     YamlObject.Alignment = MFI.getObjectAlignment(I);
393     YamlObject.StackID = MFI.getStackID(I);
394 
395     YMF.StackObjects.push_back(YamlObject);
396     StackObjectOperandMapping.insert(std::make_pair(
397         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
398   }
399 
400   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
401     yaml::StringValue Reg;
402     printRegMIR(CSInfo.getReg(), Reg, TRI);
403     if (!CSInfo.isSpilledToReg()) {
404       auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
405       assert(StackObjectInfo != StackObjectOperandMapping.end() &&
406              "Invalid stack object index");
407       const FrameIndexOperand &StackObject = StackObjectInfo->second;
408       if (StackObject.IsFixed) {
409         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
410         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
411           CSInfo.isRestored();
412       } else {
413         YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
414         YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
415           CSInfo.isRestored();
416       }
417     }
418   }
419   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
420     auto LocalObject = MFI.getLocalFrameObjectMap(I);
421     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
422     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
423            "Invalid stack object index");
424     const FrameIndexOperand &StackObject = StackObjectInfo->second;
425     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
426     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
427   }
428 
429   // Print the stack object references in the frame information class after
430   // converting the stack objects.
431   if (MFI.hasStackProtectorIndex()) {
432     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
433     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
434         .printStackObjectReference(MFI.getStackProtectorIndex());
435   }
436 
437   // Print the debug variable information.
438   for (const MachineFunction::VariableDbgInfo &DebugVar :
439        MF.getVariableDbgInfo()) {
440     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
441     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
442            "Invalid stack object index");
443     const FrameIndexOperand &StackObject = StackObjectInfo->second;
444     if (StackObject.IsFixed) {
445       auto &Object = YMF.FixedStackObjects[StackObject.ID];
446       printStackObjectDbgInfo(DebugVar, Object, MST);
447     } else {
448       auto &Object = YMF.StackObjects[StackObject.ID];
449       printStackObjectDbgInfo(DebugVar, Object, MST);
450     }
451   }
452 }
453 
454 void MIRPrinter::convert(yaml::MachineFunction &MF,
455                          const MachineConstantPool &ConstantPool) {
456   unsigned ID = 0;
457   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
458     std::string Str;
459     raw_string_ostream StrOS(Str);
460     if (Constant.isMachineConstantPoolEntry()) {
461       Constant.Val.MachineCPVal->print(StrOS);
462     } else {
463       Constant.Val.ConstVal->printAsOperand(StrOS);
464     }
465 
466     yaml::MachineConstantPoolValue YamlConstant;
467     YamlConstant.ID = ID++;
468     YamlConstant.Value = StrOS.str();
469     YamlConstant.Alignment = Constant.getAlignment();
470     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
471 
472     MF.Constants.push_back(YamlConstant);
473   }
474 }
475 
476 void MIRPrinter::convert(ModuleSlotTracker &MST,
477                          yaml::MachineJumpTable &YamlJTI,
478                          const MachineJumpTableInfo &JTI) {
479   YamlJTI.Kind = JTI.getEntryKind();
480   unsigned ID = 0;
481   for (const auto &Table : JTI.getJumpTables()) {
482     std::string Str;
483     yaml::MachineJumpTable::Entry Entry;
484     Entry.ID = ID++;
485     for (const auto *MBB : Table.MBBs) {
486       raw_string_ostream StrOS(Str);
487       StrOS << printMBBReference(*MBB);
488       Entry.Blocks.push_back(StrOS.str());
489       Str.clear();
490     }
491     YamlJTI.Entries.push_back(Entry);
492   }
493 }
494 
495 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
496   const auto *TRI = MF.getSubtarget().getRegisterInfo();
497   unsigned I = 0;
498   for (const uint32_t *Mask : TRI->getRegMasks())
499     RegisterMaskIds.insert(std::make_pair(Mask, I++));
500 }
501 
502 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
503                            SmallVectorImpl<MachineBasicBlock*> &Result,
504                            bool &IsFallthrough) {
505   SmallPtrSet<MachineBasicBlock*,8> Seen;
506 
507   for (const MachineInstr &MI : MBB) {
508     if (MI.isPHI())
509       continue;
510     for (const MachineOperand &MO : MI.operands()) {
511       if (!MO.isMBB())
512         continue;
513       MachineBasicBlock *Succ = MO.getMBB();
514       auto RP = Seen.insert(Succ);
515       if (RP.second)
516         Result.push_back(Succ);
517     }
518   }
519   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
520   IsFallthrough = I == MBB.end() || !I->isBarrier();
521 }
522 
523 bool
524 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
525   if (MBB.succ_size() <= 1)
526     return true;
527   if (!MBB.hasSuccessorProbabilities())
528     return true;
529 
530   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
531                                               MBB.Probs.end());
532   BranchProbability::normalizeProbabilities(Normalized.begin(),
533                                             Normalized.end());
534   SmallVector<BranchProbability,8> Equal(Normalized.size());
535   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
536 
537   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
538 }
539 
540 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
541   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
542   bool GuessedFallthrough;
543   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
544   if (GuessedFallthrough) {
545     const MachineFunction &MF = *MBB.getParent();
546     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
547     if (NextI != MF.end()) {
548       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
549       if (!is_contained(GuessedSuccs, Next))
550         GuessedSuccs.push_back(Next);
551     }
552   }
553   if (GuessedSuccs.size() != MBB.succ_size())
554     return false;
555   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
556 }
557 
558 void MIPrinter::print(const MachineBasicBlock &MBB) {
559   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
560   OS << "bb." << MBB.getNumber();
561   bool HasAttributes = false;
562   if (const auto *BB = MBB.getBasicBlock()) {
563     if (BB->hasName()) {
564       OS << "." << BB->getName();
565     } else {
566       HasAttributes = true;
567       OS << " (";
568       int Slot = MST.getLocalSlot(BB);
569       if (Slot == -1)
570         OS << "<ir-block badref>";
571       else
572         OS << (Twine("%ir-block.") + Twine(Slot)).str();
573     }
574   }
575   if (MBB.hasAddressTaken()) {
576     OS << (HasAttributes ? ", " : " (");
577     OS << "address-taken";
578     HasAttributes = true;
579   }
580   if (MBB.isEHPad()) {
581     OS << (HasAttributes ? ", " : " (");
582     OS << "landing-pad";
583     HasAttributes = true;
584   }
585   if (MBB.getAlignment()) {
586     OS << (HasAttributes ? ", " : " (");
587     OS << "align " << MBB.getAlignment();
588     HasAttributes = true;
589   }
590   if (HasAttributes)
591     OS << ")";
592   OS << ":\n";
593 
594   bool HasLineAttributes = false;
595   // Print the successors
596   bool canPredictProbs = canPredictBranchProbabilities(MBB);
597   // Even if the list of successors is empty, if we cannot guess it,
598   // we need to print it to tell the parser that the list is empty.
599   // This is needed, because MI model unreachable as empty blocks
600   // with an empty successor list. If the parser would see that
601   // without the successor list, it would guess the code would
602   // fallthrough.
603   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
604       !canPredictSuccessors(MBB)) {
605     OS.indent(2) << "successors: ";
606     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
607       if (I != MBB.succ_begin())
608         OS << ", ";
609       OS << printMBBReference(**I);
610       if (!SimplifyMIR || !canPredictProbs)
611         OS << '('
612            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
613            << ')';
614     }
615     OS << "\n";
616     HasLineAttributes = true;
617   }
618 
619   // Print the live in registers.
620   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
621   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
622     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
623     OS.indent(2) << "liveins: ";
624     bool First = true;
625     for (const auto &LI : MBB.liveins()) {
626       if (!First)
627         OS << ", ";
628       First = false;
629       OS << printReg(LI.PhysReg, &TRI);
630       if (!LI.LaneMask.all())
631         OS << ":0x" << PrintLaneMask(LI.LaneMask);
632     }
633     OS << "\n";
634     HasLineAttributes = true;
635   }
636 
637   if (HasLineAttributes)
638     OS << "\n";
639   bool IsInBundle = false;
640   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
641     const MachineInstr &MI = *I;
642     if (IsInBundle && !MI.isInsideBundle()) {
643       OS.indent(2) << "}\n";
644       IsInBundle = false;
645     }
646     OS.indent(IsInBundle ? 4 : 2);
647     print(MI);
648     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
649       OS << " {";
650       IsInBundle = true;
651     }
652     OS << "\n";
653   }
654   if (IsInBundle)
655     OS.indent(2) << "}\n";
656 }
657 
658 void MIPrinter::print(const MachineInstr &MI) {
659   const auto *MF = MI.getMF();
660   const auto &MRI = MF->getRegInfo();
661   const auto &SubTarget = MF->getSubtarget();
662   const auto *TRI = SubTarget.getRegisterInfo();
663   assert(TRI && "Expected target register info");
664   const auto *TII = SubTarget.getInstrInfo();
665   assert(TII && "Expected target instruction info");
666   if (MI.isCFIInstruction())
667     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
668 
669   SmallBitVector PrintedTypes(8);
670   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
671   unsigned I = 0, E = MI.getNumOperands();
672   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
673          !MI.getOperand(I).isImplicit();
674        ++I) {
675     if (I)
676       OS << ", ";
677     print(MI, I, TRI, ShouldPrintRegisterTies,
678           MI.getTypeToPrint(I, PrintedTypes, MRI),
679           /*PrintDef=*/false);
680   }
681 
682   if (I)
683     OS << " = ";
684   if (MI.getFlag(MachineInstr::FrameSetup))
685     OS << "frame-setup ";
686   if (MI.getFlag(MachineInstr::FrameDestroy))
687     OS << "frame-destroy ";
688   if (MI.getFlag(MachineInstr::FmNoNans))
689     OS << "nnan ";
690   if (MI.getFlag(MachineInstr::FmNoInfs))
691     OS << "ninf ";
692   if (MI.getFlag(MachineInstr::FmNsz))
693     OS << "nsz ";
694   if (MI.getFlag(MachineInstr::FmArcp))
695     OS << "arcp ";
696   if (MI.getFlag(MachineInstr::FmContract))
697     OS << "contract ";
698   if (MI.getFlag(MachineInstr::FmAfn))
699     OS << "afn ";
700   if (MI.getFlag(MachineInstr::FmReassoc))
701     OS << "reassoc ";
702   if (MI.getFlag(MachineInstr::NoUWrap))
703     OS << "nuw ";
704   if (MI.getFlag(MachineInstr::NoSWrap))
705     OS << "nsw ";
706   if (MI.getFlag(MachineInstr::IsExact))
707     OS << "exact ";
708 
709   OS << TII->getName(MI.getOpcode());
710   if (I < E)
711     OS << ' ';
712 
713   bool NeedComma = false;
714   for (; I < E; ++I) {
715     if (NeedComma)
716       OS << ", ";
717     print(MI, I, TRI, ShouldPrintRegisterTies,
718           MI.getTypeToPrint(I, PrintedTypes, MRI));
719     NeedComma = true;
720   }
721 
722   // Print any optional symbols attached to this instruction as-if they were
723   // operands.
724   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
725     if (NeedComma)
726       OS << ',';
727     OS << " pre-instr-symbol ";
728     MachineOperand::printSymbol(OS, *PreInstrSymbol);
729     NeedComma = true;
730   }
731   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
732     if (NeedComma)
733       OS << ',';
734     OS << " post-instr-symbol ";
735     MachineOperand::printSymbol(OS, *PostInstrSymbol);
736     NeedComma = true;
737   }
738 
739   if (const DebugLoc &DL = MI.getDebugLoc()) {
740     if (NeedComma)
741       OS << ',';
742     OS << " debug-location ";
743     DL->printAsOperand(OS, MST);
744   }
745 
746   if (!MI.memoperands_empty()) {
747     OS << " :: ";
748     const LLVMContext &Context = MF->getFunction().getContext();
749     const MachineFrameInfo &MFI = MF->getFrameInfo();
750     bool NeedComma = false;
751     for (const auto *Op : MI.memoperands()) {
752       if (NeedComma)
753         OS << ", ";
754       Op->print(OS, MST, SSNs, Context, &MFI, TII);
755       NeedComma = true;
756     }
757   }
758 }
759 
760 void MIPrinter::printStackObjectReference(int FrameIndex) {
761   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
762   assert(ObjectInfo != StackObjectOperandMapping.end() &&
763          "Invalid frame index");
764   const FrameIndexOperand &Operand = ObjectInfo->second;
765   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
766                                             Operand.Name);
767 }
768 
769 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
770                       const TargetRegisterInfo *TRI,
771                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
772                       bool PrintDef) {
773   const MachineOperand &Op = MI.getOperand(OpIdx);
774   switch (Op.getType()) {
775   case MachineOperand::MO_Immediate:
776     if (MI.isOperandSubregIdx(OpIdx)) {
777       MachineOperand::printTargetFlags(OS, Op);
778       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
779       break;
780     }
781     LLVM_FALLTHROUGH;
782   case MachineOperand::MO_Register:
783   case MachineOperand::MO_CImmediate:
784   case MachineOperand::MO_FPImmediate:
785   case MachineOperand::MO_MachineBasicBlock:
786   case MachineOperand::MO_ConstantPoolIndex:
787   case MachineOperand::MO_TargetIndex:
788   case MachineOperand::MO_JumpTableIndex:
789   case MachineOperand::MO_ExternalSymbol:
790   case MachineOperand::MO_GlobalAddress:
791   case MachineOperand::MO_RegisterLiveOut:
792   case MachineOperand::MO_Metadata:
793   case MachineOperand::MO_MCSymbol:
794   case MachineOperand::MO_CFIIndex:
795   case MachineOperand::MO_IntrinsicID:
796   case MachineOperand::MO_Predicate:
797   case MachineOperand::MO_BlockAddress: {
798     unsigned TiedOperandIdx = 0;
799     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
800       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
801     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
802     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
803              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
804     break;
805   }
806   case MachineOperand::MO_FrameIndex:
807     printStackObjectReference(Op.getIndex());
808     break;
809   case MachineOperand::MO_RegisterMask: {
810     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
811     if (RegMaskInfo != RegisterMaskIds.end())
812       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
813     else
814       printCustomRegMask(Op.getRegMask(), OS, TRI);
815     break;
816   }
817   }
818 }
819 
820 void llvm::printMIR(raw_ostream &OS, const Module &M) {
821   yaml::Output Out(OS);
822   Out << const_cast<Module &>(M);
823 }
824 
825 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
826   MIRPrinter Printer(OS);
827   Printer.print(MF);
828 }
829