1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
26 #include "llvm/CodeGen/MIRYamlMapping.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalValue.h"
46 #include "llvm/IR/IRPrintingPasses.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/ModuleSlotTracker.h"
52 #include "llvm/IR/Value.h"
53 #include "llvm/MC/LaneBitmask.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132 
133 private:
134   void initRegisterMaskIds(const MachineFunction &MF);
135 };
136 
137 /// This class prints out the machine instructions using the MIR serialization
138 /// format.
139 class MIPrinter {
140   raw_ostream &OS;
141   ModuleSlotTracker &MST;
142   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144   /// Synchronization scope names registered with LLVMContext.
145   SmallVector<StringRef, 8> SSNs;
146 
147   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
149 
150 public:
151   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155         StackObjectOperandMapping(StackObjectOperandMapping) {}
156 
157   void print(const MachineBasicBlock &MBB);
158 
159   void print(const MachineInstr &MI);
160   void printIRValueReference(const Value &V);
161   void printStackObjectReference(int FrameIndex);
162   void print(const MachineInstr &MI, unsigned OpIdx,
163              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
164              LLT TypeToPrint, bool PrintDef = true);
165   void print(const LLVMContext &Context, const TargetInstrInfo &TII,
166              const MachineMemOperand &Op);
167   void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID);
168 };
169 
170 } // end namespace llvm
171 
172 namespace llvm {
173 namespace yaml {
174 
175 /// This struct serializes the LLVM IR module.
176 template <> struct BlockScalarTraits<Module> {
177   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
178     Mod.print(OS, nullptr);
179   }
180 
181   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
182     llvm_unreachable("LLVM Module is supposed to be parsed separately");
183     return "";
184   }
185 };
186 
187 } // end namespace yaml
188 } // end namespace llvm
189 
190 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
191                         const TargetRegisterInfo *TRI) {
192   raw_string_ostream OS(Dest.Value);
193   OS << printReg(Reg, TRI);
194 }
195 
196 void MIRPrinter::print(const MachineFunction &MF) {
197   initRegisterMaskIds(MF);
198 
199   yaml::MachineFunction YamlMF;
200   YamlMF.Name = MF.getName();
201   YamlMF.Alignment = MF.getAlignment();
202   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
203 
204   YamlMF.Legalized = MF.getProperties().hasProperty(
205       MachineFunctionProperties::Property::Legalized);
206   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
207       MachineFunctionProperties::Property::RegBankSelected);
208   YamlMF.Selected = MF.getProperties().hasProperty(
209       MachineFunctionProperties::Property::Selected);
210   YamlMF.FailedISel = MF.getProperties().hasProperty(
211       MachineFunctionProperties::Property::FailedISel);
212 
213   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
214   ModuleSlotTracker MST(MF.getFunction().getParent());
215   MST.incorporateFunction(MF.getFunction());
216   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
217   convertStackObjects(YamlMF, MF, MST);
218   if (const auto *ConstantPool = MF.getConstantPool())
219     convert(YamlMF, *ConstantPool);
220   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
221     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
222   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
223   bool IsNewlineNeeded = false;
224   for (const auto &MBB : MF) {
225     if (IsNewlineNeeded)
226       StrOS << "\n";
227     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
228         .print(MBB);
229     IsNewlineNeeded = true;
230   }
231   StrOS.flush();
232   yaml::Output Out(OS);
233   if (!SimplifyMIR)
234       Out.setWriteDefaultValues(true);
235   Out << YamlMF;
236 }
237 
238 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
239                                const TargetRegisterInfo *TRI) {
240   assert(RegMask && "Can't print an empty register mask");
241   OS << StringRef("CustomRegMask(");
242 
243   bool IsRegInRegMaskFound = false;
244   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
245     // Check whether the register is asserted in regmask.
246     if (RegMask[I / 32] & (1u << (I % 32))) {
247       if (IsRegInRegMaskFound)
248         OS << ',';
249       OS << printReg(I, TRI);
250       IsRegInRegMaskFound = true;
251     }
252   }
253 
254   OS << ')';
255 }
256 
257 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
258                                 const MachineRegisterInfo &RegInfo,
259                                 const TargetRegisterInfo *TRI) {
260   raw_string_ostream OS(Dest.Value);
261   OS << printRegClassOrBank(Reg, RegInfo, TRI);
262 }
263 
264 
265 void MIRPrinter::convert(yaml::MachineFunction &MF,
266                          const MachineRegisterInfo &RegInfo,
267                          const TargetRegisterInfo *TRI) {
268   MF.TracksRegLiveness = RegInfo.tracksLiveness();
269 
270   // Print the virtual register definitions.
271   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
272     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
273     yaml::VirtualRegisterDefinition VReg;
274     VReg.ID = I;
275     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
276     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
277     if (PreferredReg)
278       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
279     MF.VirtualRegisters.push_back(VReg);
280   }
281 
282   // Print the live ins.
283   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
284     yaml::MachineFunctionLiveIn LiveIn;
285     printRegMIR(LI.first, LiveIn.Register, TRI);
286     if (LI.second)
287       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
288     MF.LiveIns.push_back(LiveIn);
289   }
290 
291   // Prints the callee saved registers.
292   if (RegInfo.isUpdatedCSRsInitialized()) {
293     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
294     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
295     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
296       yaml::FlowStringValue Reg;
297       printRegMIR(*I, Reg, TRI);
298       CalleeSavedRegisters.push_back(Reg);
299     }
300     MF.CalleeSavedRegisters = CalleeSavedRegisters;
301   }
302 }
303 
304 void MIRPrinter::convert(ModuleSlotTracker &MST,
305                          yaml::MachineFrameInfo &YamlMFI,
306                          const MachineFrameInfo &MFI) {
307   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
308   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
309   YamlMFI.HasStackMap = MFI.hasStackMap();
310   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
311   YamlMFI.StackSize = MFI.getStackSize();
312   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
313   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
314   YamlMFI.AdjustsStack = MFI.adjustsStack();
315   YamlMFI.HasCalls = MFI.hasCalls();
316   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
317     ? MFI.getMaxCallFrameSize() : ~0u;
318   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
319   YamlMFI.HasVAStart = MFI.hasVAStart();
320   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
321   if (MFI.getSavePoint()) {
322     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
323     StrOS << printMBBReference(*MFI.getSavePoint());
324   }
325   if (MFI.getRestorePoint()) {
326     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
327     StrOS << printMBBReference(*MFI.getRestorePoint());
328   }
329 }
330 
331 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
332                                      const MachineFunction &MF,
333                                      ModuleSlotTracker &MST) {
334   const MachineFrameInfo &MFI = MF.getFrameInfo();
335   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
336   // Process fixed stack objects.
337   unsigned ID = 0;
338   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
339     if (MFI.isDeadObjectIndex(I))
340       continue;
341 
342     yaml::FixedMachineStackObject YamlObject;
343     YamlObject.ID = ID;
344     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
345                           ? yaml::FixedMachineStackObject::SpillSlot
346                           : yaml::FixedMachineStackObject::DefaultType;
347     YamlObject.Offset = MFI.getObjectOffset(I);
348     YamlObject.Size = MFI.getObjectSize(I);
349     YamlObject.Alignment = MFI.getObjectAlignment(I);
350     YamlObject.StackID = MFI.getStackID(I);
351     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
352     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
353     YMF.FixedStackObjects.push_back(YamlObject);
354     StackObjectOperandMapping.insert(
355         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
356   }
357 
358   // Process ordinary stack objects.
359   ID = 0;
360   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
361     if (MFI.isDeadObjectIndex(I))
362       continue;
363 
364     yaml::MachineStackObject YamlObject;
365     YamlObject.ID = ID;
366     if (const auto *Alloca = MFI.getObjectAllocation(I))
367       YamlObject.Name.Value =
368           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
369     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
370                           ? yaml::MachineStackObject::SpillSlot
371                           : MFI.isVariableSizedObjectIndex(I)
372                                 ? yaml::MachineStackObject::VariableSized
373                                 : yaml::MachineStackObject::DefaultType;
374     YamlObject.Offset = MFI.getObjectOffset(I);
375     YamlObject.Size = MFI.getObjectSize(I);
376     YamlObject.Alignment = MFI.getObjectAlignment(I);
377     YamlObject.StackID = MFI.getStackID(I);
378 
379     YMF.StackObjects.push_back(YamlObject);
380     StackObjectOperandMapping.insert(std::make_pair(
381         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
382   }
383 
384   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
385     yaml::StringValue Reg;
386     printRegMIR(CSInfo.getReg(), Reg, TRI);
387     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
388     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
389            "Invalid stack object index");
390     const FrameIndexOperand &StackObject = StackObjectInfo->second;
391     if (StackObject.IsFixed) {
392       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
393       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
394         CSInfo.isRestored();
395     } else {
396       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
397       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
398         CSInfo.isRestored();
399     }
400   }
401   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
402     auto LocalObject = MFI.getLocalFrameObjectMap(I);
403     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
404     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
405            "Invalid stack object index");
406     const FrameIndexOperand &StackObject = StackObjectInfo->second;
407     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
408     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
409   }
410 
411   // Print the stack object references in the frame information class after
412   // converting the stack objects.
413   if (MFI.hasStackProtectorIndex()) {
414     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
415     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
416         .printStackObjectReference(MFI.getStackProtectorIndex());
417   }
418 
419   // Print the debug variable information.
420   for (const MachineFunction::VariableDbgInfo &DebugVar :
421        MF.getVariableDbgInfo()) {
422     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
423     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
424            "Invalid stack object index");
425     const FrameIndexOperand &StackObject = StackObjectInfo->second;
426     assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
427     auto &Object = YMF.StackObjects[StackObject.ID];
428     {
429       raw_string_ostream StrOS(Object.DebugVar.Value);
430       DebugVar.Var->printAsOperand(StrOS, MST);
431     }
432     {
433       raw_string_ostream StrOS(Object.DebugExpr.Value);
434       DebugVar.Expr->printAsOperand(StrOS, MST);
435     }
436     {
437       raw_string_ostream StrOS(Object.DebugLoc.Value);
438       DebugVar.Loc->printAsOperand(StrOS, MST);
439     }
440   }
441 }
442 
443 void MIRPrinter::convert(yaml::MachineFunction &MF,
444                          const MachineConstantPool &ConstantPool) {
445   unsigned ID = 0;
446   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
447     std::string Str;
448     raw_string_ostream StrOS(Str);
449     if (Constant.isMachineConstantPoolEntry()) {
450       Constant.Val.MachineCPVal->print(StrOS);
451     } else {
452       Constant.Val.ConstVal->printAsOperand(StrOS);
453     }
454 
455     yaml::MachineConstantPoolValue YamlConstant;
456     YamlConstant.ID = ID++;
457     YamlConstant.Value = StrOS.str();
458     YamlConstant.Alignment = Constant.getAlignment();
459     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
460 
461     MF.Constants.push_back(YamlConstant);
462   }
463 }
464 
465 void MIRPrinter::convert(ModuleSlotTracker &MST,
466                          yaml::MachineJumpTable &YamlJTI,
467                          const MachineJumpTableInfo &JTI) {
468   YamlJTI.Kind = JTI.getEntryKind();
469   unsigned ID = 0;
470   for (const auto &Table : JTI.getJumpTables()) {
471     std::string Str;
472     yaml::MachineJumpTable::Entry Entry;
473     Entry.ID = ID++;
474     for (const auto *MBB : Table.MBBs) {
475       raw_string_ostream StrOS(Str);
476       StrOS << printMBBReference(*MBB);
477       Entry.Blocks.push_back(StrOS.str());
478       Str.clear();
479     }
480     YamlJTI.Entries.push_back(Entry);
481   }
482 }
483 
484 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
485   const auto *TRI = MF.getSubtarget().getRegisterInfo();
486   unsigned I = 0;
487   for (const uint32_t *Mask : TRI->getRegMasks())
488     RegisterMaskIds.insert(std::make_pair(Mask, I++));
489 }
490 
491 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
492                            SmallVectorImpl<MachineBasicBlock*> &Result,
493                            bool &IsFallthrough) {
494   SmallPtrSet<MachineBasicBlock*,8> Seen;
495 
496   for (const MachineInstr &MI : MBB) {
497     if (MI.isPHI())
498       continue;
499     for (const MachineOperand &MO : MI.operands()) {
500       if (!MO.isMBB())
501         continue;
502       MachineBasicBlock *Succ = MO.getMBB();
503       auto RP = Seen.insert(Succ);
504       if (RP.second)
505         Result.push_back(Succ);
506     }
507   }
508   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
509   IsFallthrough = I == MBB.end() || !I->isBarrier();
510 }
511 
512 bool
513 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
514   if (MBB.succ_size() <= 1)
515     return true;
516   if (!MBB.hasSuccessorProbabilities())
517     return true;
518 
519   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
520                                               MBB.Probs.end());
521   BranchProbability::normalizeProbabilities(Normalized.begin(),
522                                             Normalized.end());
523   SmallVector<BranchProbability,8> Equal(Normalized.size());
524   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
525 
526   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
527 }
528 
529 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
530   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
531   bool GuessedFallthrough;
532   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
533   if (GuessedFallthrough) {
534     const MachineFunction &MF = *MBB.getParent();
535     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
536     if (NextI != MF.end()) {
537       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
538       if (!is_contained(GuessedSuccs, Next))
539         GuessedSuccs.push_back(Next);
540     }
541   }
542   if (GuessedSuccs.size() != MBB.succ_size())
543     return false;
544   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
545 }
546 
547 void MIPrinter::print(const MachineBasicBlock &MBB) {
548   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
549   OS << "bb." << MBB.getNumber();
550   bool HasAttributes = false;
551   if (const auto *BB = MBB.getBasicBlock()) {
552     if (BB->hasName()) {
553       OS << "." << BB->getName();
554     } else {
555       HasAttributes = true;
556       OS << " (";
557       int Slot = MST.getLocalSlot(BB);
558       if (Slot == -1)
559         OS << "<ir-block badref>";
560       else
561         OS << (Twine("%ir-block.") + Twine(Slot)).str();
562     }
563   }
564   if (MBB.hasAddressTaken()) {
565     OS << (HasAttributes ? ", " : " (");
566     OS << "address-taken";
567     HasAttributes = true;
568   }
569   if (MBB.isEHPad()) {
570     OS << (HasAttributes ? ", " : " (");
571     OS << "landing-pad";
572     HasAttributes = true;
573   }
574   if (MBB.getAlignment()) {
575     OS << (HasAttributes ? ", " : " (");
576     OS << "align " << MBB.getAlignment();
577     HasAttributes = true;
578   }
579   if (HasAttributes)
580     OS << ")";
581   OS << ":\n";
582 
583   bool HasLineAttributes = false;
584   // Print the successors
585   bool canPredictProbs = canPredictBranchProbabilities(MBB);
586   // Even if the list of successors is empty, if we cannot guess it,
587   // we need to print it to tell the parser that the list is empty.
588   // This is needed, because MI model unreachable as empty blocks
589   // with an empty successor list. If the parser would see that
590   // without the successor list, it would guess the code would
591   // fallthrough.
592   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
593       !canPredictSuccessors(MBB)) {
594     OS.indent(2) << "successors: ";
595     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
596       if (I != MBB.succ_begin())
597         OS << ", ";
598       OS << printMBBReference(**I);
599       if (!SimplifyMIR || !canPredictProbs)
600         OS << '('
601            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
602            << ')';
603     }
604     OS << "\n";
605     HasLineAttributes = true;
606   }
607 
608   // Print the live in registers.
609   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
610   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
611     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
612     OS.indent(2) << "liveins: ";
613     bool First = true;
614     for (const auto &LI : MBB.liveins()) {
615       if (!First)
616         OS << ", ";
617       First = false;
618       OS << printReg(LI.PhysReg, &TRI);
619       if (!LI.LaneMask.all())
620         OS << ":0x" << PrintLaneMask(LI.LaneMask);
621     }
622     OS << "\n";
623     HasLineAttributes = true;
624   }
625 
626   if (HasLineAttributes)
627     OS << "\n";
628   bool IsInBundle = false;
629   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
630     const MachineInstr &MI = *I;
631     if (IsInBundle && !MI.isInsideBundle()) {
632       OS.indent(2) << "}\n";
633       IsInBundle = false;
634     }
635     OS.indent(IsInBundle ? 4 : 2);
636     print(MI);
637     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
638       OS << " {";
639       IsInBundle = true;
640     }
641     OS << "\n";
642   }
643   if (IsInBundle)
644     OS.indent(2) << "}\n";
645 }
646 
647 void MIPrinter::print(const MachineInstr &MI) {
648   const auto *MF = MI.getMF();
649   const auto &MRI = MF->getRegInfo();
650   const auto &SubTarget = MF->getSubtarget();
651   const auto *TRI = SubTarget.getRegisterInfo();
652   assert(TRI && "Expected target register info");
653   const auto *TII = SubTarget.getInstrInfo();
654   assert(TII && "Expected target instruction info");
655   if (MI.isCFIInstruction())
656     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
657 
658   SmallBitVector PrintedTypes(8);
659   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
660   unsigned I = 0, E = MI.getNumOperands();
661   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
662          !MI.getOperand(I).isImplicit();
663        ++I) {
664     if (I)
665       OS << ", ";
666     print(MI, I, TRI, ShouldPrintRegisterTies,
667           MI.getTypeToPrint(I, PrintedTypes, MRI),
668           /*PrintDef=*/false);
669   }
670 
671   if (I)
672     OS << " = ";
673   if (MI.getFlag(MachineInstr::FrameSetup))
674     OS << "frame-setup ";
675   else if (MI.getFlag(MachineInstr::FrameDestroy))
676     OS << "frame-destroy ";
677 
678   OS << TII->getName(MI.getOpcode());
679   if (I < E)
680     OS << ' ';
681 
682   bool NeedComma = false;
683   for (; I < E; ++I) {
684     if (NeedComma)
685       OS << ", ";
686     print(MI, I, TRI, ShouldPrintRegisterTies,
687           MI.getTypeToPrint(I, PrintedTypes, MRI));
688     NeedComma = true;
689   }
690 
691   if (const DebugLoc &DL = MI.getDebugLoc()) {
692     if (NeedComma)
693       OS << ',';
694     OS << " debug-location ";
695     DL->printAsOperand(OS, MST);
696   }
697 
698   if (!MI.memoperands_empty()) {
699     OS << " :: ";
700     const LLVMContext &Context = MF->getFunction().getContext();
701     bool NeedComma = false;
702     for (const auto *Op : MI.memoperands()) {
703       if (NeedComma)
704         OS << ", ";
705       print(Context, *TII, *Op);
706       NeedComma = true;
707     }
708   }
709 }
710 
711 void MIPrinter::printIRValueReference(const Value &V) {
712   if (isa<GlobalValue>(V)) {
713     V.printAsOperand(OS, /*PrintType=*/false, MST);
714     return;
715   }
716   if (isa<Constant>(V)) {
717     // Machine memory operands can load/store to/from constant value pointers.
718     OS << '`';
719     V.printAsOperand(OS, /*PrintType=*/true, MST);
720     OS << '`';
721     return;
722   }
723   OS << "%ir.";
724   if (V.hasName()) {
725     printLLVMNameWithoutPrefix(OS, V.getName());
726     return;
727   }
728   MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V));
729 }
730 
731 void MIPrinter::printStackObjectReference(int FrameIndex) {
732   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
733   assert(ObjectInfo != StackObjectOperandMapping.end() &&
734          "Invalid frame index");
735   const FrameIndexOperand &Operand = ObjectInfo->second;
736   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
737                                             Operand.Name);
738 }
739 
740 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
741                       const TargetRegisterInfo *TRI,
742                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
743                       bool PrintDef) {
744   const MachineOperand &Op = MI.getOperand(OpIdx);
745   switch (Op.getType()) {
746   case MachineOperand::MO_Immediate:
747     if (MI.isOperandSubregIdx(OpIdx)) {
748       MachineOperand::printTargetFlags(OS, Op);
749       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
750       break;
751     }
752     LLVM_FALLTHROUGH;
753   case MachineOperand::MO_Register:
754   case MachineOperand::MO_CImmediate:
755   case MachineOperand::MO_FPImmediate:
756   case MachineOperand::MO_MachineBasicBlock:
757   case MachineOperand::MO_ConstantPoolIndex:
758   case MachineOperand::MO_TargetIndex:
759   case MachineOperand::MO_JumpTableIndex:
760   case MachineOperand::MO_ExternalSymbol:
761   case MachineOperand::MO_GlobalAddress:
762   case MachineOperand::MO_RegisterLiveOut:
763   case MachineOperand::MO_Metadata:
764   case MachineOperand::MO_MCSymbol:
765   case MachineOperand::MO_CFIIndex:
766   case MachineOperand::MO_IntrinsicID:
767   case MachineOperand::MO_Predicate:
768   case MachineOperand::MO_BlockAddress: {
769     unsigned TiedOperandIdx = 0;
770     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
771       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
772     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
773     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
774              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
775     break;
776   }
777   case MachineOperand::MO_FrameIndex:
778     printStackObjectReference(Op.getIndex());
779     break;
780   case MachineOperand::MO_RegisterMask: {
781     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
782     if (RegMaskInfo != RegisterMaskIds.end())
783       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
784     else
785       printCustomRegMask(Op.getRegMask(), OS, TRI);
786     break;
787   }
788   }
789 }
790 
791 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
792                                         unsigned TMMOFlag) {
793   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
794   for (const auto &I : Flags) {
795     if (I.first == TMMOFlag) {
796       return I.second;
797     }
798   }
799   return nullptr;
800 }
801 
802 void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII,
803                       const MachineMemOperand &Op) {
804   OS << '(';
805   if (Op.isVolatile())
806     OS << "volatile ";
807   if (Op.isNonTemporal())
808     OS << "non-temporal ";
809   if (Op.isDereferenceable())
810     OS << "dereferenceable ";
811   if (Op.isInvariant())
812     OS << "invariant ";
813   if (Op.getFlags() & MachineMemOperand::MOTargetFlag1)
814     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag1)
815        << "\" ";
816   if (Op.getFlags() & MachineMemOperand::MOTargetFlag2)
817     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag2)
818        << "\" ";
819   if (Op.getFlags() & MachineMemOperand::MOTargetFlag3)
820     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag3)
821        << "\" ";
822 
823   assert((Op.isLoad() || Op.isStore()) && "machine memory operand must be a load or store (or both)");
824   if (Op.isLoad())
825     OS << "load ";
826   if (Op.isStore())
827     OS << "store ";
828 
829   printSyncScope(Context, Op.getSyncScopeID());
830 
831   if (Op.getOrdering() != AtomicOrdering::NotAtomic)
832     OS << toIRString(Op.getOrdering()) << ' ';
833   if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
834     OS << toIRString(Op.getFailureOrdering()) << ' ';
835 
836   OS << Op.getSize();
837   if (const Value *Val = Op.getValue()) {
838     OS << ((Op.isLoad() && Op.isStore()) ? " on "
839                                          : Op.isLoad() ? " from " : " into ");
840     printIRValueReference(*Val);
841   } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
842     OS << ((Op.isLoad() && Op.isStore()) ? " on "
843                                          : Op.isLoad() ? " from " : " into ");
844     assert(PVal && "Expected a pseudo source value");
845     switch (PVal->kind()) {
846     case PseudoSourceValue::Stack:
847       OS << "stack";
848       break;
849     case PseudoSourceValue::GOT:
850       OS << "got";
851       break;
852     case PseudoSourceValue::JumpTable:
853       OS << "jump-table";
854       break;
855     case PseudoSourceValue::ConstantPool:
856       OS << "constant-pool";
857       break;
858     case PseudoSourceValue::FixedStack:
859       printStackObjectReference(
860           cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
861       break;
862     case PseudoSourceValue::GlobalValueCallEntry:
863       OS << "call-entry ";
864       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
865           OS, /*PrintType=*/false, MST);
866       break;
867     case PseudoSourceValue::ExternalSymbolCallEntry:
868       OS << "call-entry &";
869       printLLVMNameWithoutPrefix(
870           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
871       break;
872     case PseudoSourceValue::TargetCustom:
873       llvm_unreachable("TargetCustom pseudo source values are not supported");
874       break;
875     }
876   }
877   MachineOperand::printOperandOffset(OS, Op.getOffset());
878   if (Op.getBaseAlignment() != Op.getSize())
879     OS << ", align " << Op.getBaseAlignment();
880   auto AAInfo = Op.getAAInfo();
881   if (AAInfo.TBAA) {
882     OS << ", !tbaa ";
883     AAInfo.TBAA->printAsOperand(OS, MST);
884   }
885   if (AAInfo.Scope) {
886     OS << ", !alias.scope ";
887     AAInfo.Scope->printAsOperand(OS, MST);
888   }
889   if (AAInfo.NoAlias) {
890     OS << ", !noalias ";
891     AAInfo.NoAlias->printAsOperand(OS, MST);
892   }
893   if (Op.getRanges()) {
894     OS << ", !range ";
895     Op.getRanges()->printAsOperand(OS, MST);
896   }
897   if (unsigned AS = Op.getAddrSpace())
898     OS << ", addrspace " << AS;
899   OS << ')';
900 }
901 
902 void MIPrinter::printSyncScope(const LLVMContext &Context, SyncScope::ID SSID) {
903   switch (SSID) {
904   case SyncScope::System: {
905     break;
906   }
907   default: {
908     if (SSNs.empty())
909       Context.getSyncScopeNames(SSNs);
910 
911     OS << "syncscope(\"";
912     PrintEscapedString(SSNs[SSID], OS);
913     OS << "\") ";
914     break;
915   }
916   }
917 }
918 
919 void llvm::printMIR(raw_ostream &OS, const Module &M) {
920   yaml::Output Out(OS);
921   Out << const_cast<Module &>(M);
922 }
923 
924 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
925   MIRPrinter Printer(OS);
926   Printer.print(MF);
927 }
928