1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/MIRYamlMapping.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCDwarf.h"
54 #include "llvm/MC/MCSymbol.h"
55 #include "llvm/Support/AtomicOrdering.h"
56 #include "llvm/Support/BranchProbability.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CommandLine.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/Format.h"
61 #include "llvm/Support/LowLevelTypeImpl.h"
62 #include "llvm/Support/YAMLTraits.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetIntrinsicInfo.h"
65 #include "llvm/Target/TargetMachine.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cinttypes>
69 #include <cstdint>
70 #include <iterator>
71 #include <string>
72 #include <utility>
73 #include <vector>
74 
75 using namespace llvm;
76 
77 static cl::opt<bool> SimplifyMIR(
78     "simplify-mir", cl::Hidden,
79     cl::desc("Leave out unnecessary information when printing MIR"));
80 
81 namespace {
82 
83 /// This structure describes how to print out stack object references.
84 struct FrameIndexOperand {
85   std::string Name;
86   unsigned ID;
87   bool IsFixed;
88 
89   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
90       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
91 
92   /// Return an ordinary stack object reference.
93   static FrameIndexOperand create(StringRef Name, unsigned ID) {
94     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
95   }
96 
97   /// Return a fixed stack object reference.
98   static FrameIndexOperand createFixed(unsigned ID) {
99     return FrameIndexOperand("", ID, /*IsFixed=*/true);
100   }
101 };
102 
103 } // end anonymous namespace
104 
105 namespace llvm {
106 
107 /// This class prints out the machine functions using the MIR serialization
108 /// format.
109 class MIRPrinter {
110   raw_ostream &OS;
111   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
112   /// Maps from stack object indices to operand indices which will be used when
113   /// printing frame index machine operands.
114   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
115 
116 public:
117   MIRPrinter(raw_ostream &OS) : OS(OS) {}
118 
119   void print(const MachineFunction &MF);
120 
121   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
122                const TargetRegisterInfo *TRI);
123   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
124                const MachineFrameInfo &MFI);
125   void convert(yaml::MachineFunction &MF,
126                const MachineConstantPool &ConstantPool);
127   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
128                const MachineJumpTableInfo &JTI);
129   void convertStackObjects(yaml::MachineFunction &YMF,
130                            const MachineFunction &MF, ModuleSlotTracker &MST);
131 
132 private:
133   void initRegisterMaskIds(const MachineFunction &MF);
134 };
135 
136 /// This class prints out the machine instructions using the MIR serialization
137 /// format.
138 class MIPrinter {
139   raw_ostream &OS;
140   ModuleSlotTracker &MST;
141   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
142   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143   /// Synchronization scope names registered with LLVMContext.
144   SmallVector<StringRef, 8> SSNs;
145 
146   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
147   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
148 
149 public:
150   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
151             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
152             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
153       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
154         StackObjectOperandMapping(StackObjectOperandMapping) {}
155 
156   void print(const MachineBasicBlock &MBB);
157 
158   void print(const MachineInstr &MI);
159   void printStackObjectReference(int FrameIndex);
160   void print(const MachineInstr &MI, unsigned OpIdx,
161              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
162              LLT TypeToPrint, bool PrintDef = true);
163 };
164 
165 } // end namespace llvm
166 
167 namespace llvm {
168 namespace yaml {
169 
170 /// This struct serializes the LLVM IR module.
171 template <> struct BlockScalarTraits<Module> {
172   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
173     Mod.print(OS, nullptr);
174   }
175 
176   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
177     llvm_unreachable("LLVM Module is supposed to be parsed separately");
178     return "";
179   }
180 };
181 
182 } // end namespace yaml
183 } // end namespace llvm
184 
185 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
186                         const TargetRegisterInfo *TRI) {
187   raw_string_ostream OS(Dest.Value);
188   OS << printReg(Reg, TRI);
189 }
190 
191 void MIRPrinter::print(const MachineFunction &MF) {
192   initRegisterMaskIds(MF);
193 
194   yaml::MachineFunction YamlMF;
195   YamlMF.Name = MF.getName();
196   YamlMF.Alignment = MF.getAlignment();
197   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
198 
199   YamlMF.Legalized = MF.getProperties().hasProperty(
200       MachineFunctionProperties::Property::Legalized);
201   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
202       MachineFunctionProperties::Property::RegBankSelected);
203   YamlMF.Selected = MF.getProperties().hasProperty(
204       MachineFunctionProperties::Property::Selected);
205   YamlMF.FailedISel = MF.getProperties().hasProperty(
206       MachineFunctionProperties::Property::FailedISel);
207 
208   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
209   ModuleSlotTracker MST(MF.getFunction().getParent());
210   MST.incorporateFunction(MF.getFunction());
211   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
212   convertStackObjects(YamlMF, MF, MST);
213   if (const auto *ConstantPool = MF.getConstantPool())
214     convert(YamlMF, *ConstantPool);
215   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
216     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
217   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
218   bool IsNewlineNeeded = false;
219   for (const auto &MBB : MF) {
220     if (IsNewlineNeeded)
221       StrOS << "\n";
222     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
223         .print(MBB);
224     IsNewlineNeeded = true;
225   }
226   StrOS.flush();
227   yaml::Output Out(OS);
228   if (!SimplifyMIR)
229       Out.setWriteDefaultValues(true);
230   Out << YamlMF;
231 }
232 
233 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
234                                const TargetRegisterInfo *TRI) {
235   assert(RegMask && "Can't print an empty register mask");
236   OS << StringRef("CustomRegMask(");
237 
238   bool IsRegInRegMaskFound = false;
239   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
240     // Check whether the register is asserted in regmask.
241     if (RegMask[I / 32] & (1u << (I % 32))) {
242       if (IsRegInRegMaskFound)
243         OS << ',';
244       OS << printReg(I, TRI);
245       IsRegInRegMaskFound = true;
246     }
247   }
248 
249   OS << ')';
250 }
251 
252 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
253                                 const MachineRegisterInfo &RegInfo,
254                                 const TargetRegisterInfo *TRI) {
255   raw_string_ostream OS(Dest.Value);
256   OS << printRegClassOrBank(Reg, RegInfo, TRI);
257 }
258 
259 
260 void MIRPrinter::convert(yaml::MachineFunction &MF,
261                          const MachineRegisterInfo &RegInfo,
262                          const TargetRegisterInfo *TRI) {
263   MF.TracksRegLiveness = RegInfo.tracksLiveness();
264 
265   // Print the virtual register definitions.
266   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
267     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
268     yaml::VirtualRegisterDefinition VReg;
269     VReg.ID = I;
270     if (RegInfo.getVRegName(Reg) != "")
271       continue;
272     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
273     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
274     if (PreferredReg)
275       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
276     MF.VirtualRegisters.push_back(VReg);
277   }
278 
279   // Print the live ins.
280   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
281     yaml::MachineFunctionLiveIn LiveIn;
282     printRegMIR(LI.first, LiveIn.Register, TRI);
283     if (LI.second)
284       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
285     MF.LiveIns.push_back(LiveIn);
286   }
287 
288   // Prints the callee saved registers.
289   if (RegInfo.isUpdatedCSRsInitialized()) {
290     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
291     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
292     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
293       yaml::FlowStringValue Reg;
294       printRegMIR(*I, Reg, TRI);
295       CalleeSavedRegisters.push_back(Reg);
296     }
297     MF.CalleeSavedRegisters = CalleeSavedRegisters;
298   }
299 }
300 
301 void MIRPrinter::convert(ModuleSlotTracker &MST,
302                          yaml::MachineFrameInfo &YamlMFI,
303                          const MachineFrameInfo &MFI) {
304   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
305   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
306   YamlMFI.HasStackMap = MFI.hasStackMap();
307   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
308   YamlMFI.StackSize = MFI.getStackSize();
309   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
310   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
311   YamlMFI.AdjustsStack = MFI.adjustsStack();
312   YamlMFI.HasCalls = MFI.hasCalls();
313   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
314     ? MFI.getMaxCallFrameSize() : ~0u;
315   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
316   YamlMFI.HasVAStart = MFI.hasVAStart();
317   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
318   if (MFI.getSavePoint()) {
319     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
320     StrOS << printMBBReference(*MFI.getSavePoint());
321   }
322   if (MFI.getRestorePoint()) {
323     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
324     StrOS << printMBBReference(*MFI.getRestorePoint());
325   }
326 }
327 
328 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
329                                      const MachineFunction &MF,
330                                      ModuleSlotTracker &MST) {
331   const MachineFrameInfo &MFI = MF.getFrameInfo();
332   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
333   // Process fixed stack objects.
334   unsigned ID = 0;
335   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
336     if (MFI.isDeadObjectIndex(I))
337       continue;
338 
339     yaml::FixedMachineStackObject YamlObject;
340     YamlObject.ID = ID;
341     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
342                           ? yaml::FixedMachineStackObject::SpillSlot
343                           : yaml::FixedMachineStackObject::DefaultType;
344     YamlObject.Offset = MFI.getObjectOffset(I);
345     YamlObject.Size = MFI.getObjectSize(I);
346     YamlObject.Alignment = MFI.getObjectAlignment(I);
347     YamlObject.StackID = MFI.getStackID(I);
348     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
349     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
350     YMF.FixedStackObjects.push_back(YamlObject);
351     StackObjectOperandMapping.insert(
352         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
353   }
354 
355   // Process ordinary stack objects.
356   ID = 0;
357   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
358     if (MFI.isDeadObjectIndex(I))
359       continue;
360 
361     yaml::MachineStackObject YamlObject;
362     YamlObject.ID = ID;
363     if (const auto *Alloca = MFI.getObjectAllocation(I))
364       YamlObject.Name.Value =
365           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
366     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
367                           ? yaml::MachineStackObject::SpillSlot
368                           : MFI.isVariableSizedObjectIndex(I)
369                                 ? yaml::MachineStackObject::VariableSized
370                                 : yaml::MachineStackObject::DefaultType;
371     YamlObject.Offset = MFI.getObjectOffset(I);
372     YamlObject.Size = MFI.getObjectSize(I);
373     YamlObject.Alignment = MFI.getObjectAlignment(I);
374     YamlObject.StackID = MFI.getStackID(I);
375 
376     YMF.StackObjects.push_back(YamlObject);
377     StackObjectOperandMapping.insert(std::make_pair(
378         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
379   }
380 
381   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
382     yaml::StringValue Reg;
383     printRegMIR(CSInfo.getReg(), Reg, TRI);
384     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
385     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
386            "Invalid stack object index");
387     const FrameIndexOperand &StackObject = StackObjectInfo->second;
388     if (StackObject.IsFixed) {
389       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
390       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
391         CSInfo.isRestored();
392     } else {
393       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
394       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
395         CSInfo.isRestored();
396     }
397   }
398   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
399     auto LocalObject = MFI.getLocalFrameObjectMap(I);
400     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
401     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
402            "Invalid stack object index");
403     const FrameIndexOperand &StackObject = StackObjectInfo->second;
404     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
405     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
406   }
407 
408   // Print the stack object references in the frame information class after
409   // converting the stack objects.
410   if (MFI.hasStackProtectorIndex()) {
411     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
412     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
413         .printStackObjectReference(MFI.getStackProtectorIndex());
414   }
415 
416   // Print the debug variable information.
417   for (const MachineFunction::VariableDbgInfo &DebugVar :
418        MF.getVariableDbgInfo()) {
419     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
420     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
421            "Invalid stack object index");
422     const FrameIndexOperand &StackObject = StackObjectInfo->second;
423     assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
424     auto &Object = YMF.StackObjects[StackObject.ID];
425     {
426       raw_string_ostream StrOS(Object.DebugVar.Value);
427       DebugVar.Var->printAsOperand(StrOS, MST);
428     }
429     {
430       raw_string_ostream StrOS(Object.DebugExpr.Value);
431       DebugVar.Expr->printAsOperand(StrOS, MST);
432     }
433     {
434       raw_string_ostream StrOS(Object.DebugLoc.Value);
435       DebugVar.Loc->printAsOperand(StrOS, MST);
436     }
437   }
438 }
439 
440 void MIRPrinter::convert(yaml::MachineFunction &MF,
441                          const MachineConstantPool &ConstantPool) {
442   unsigned ID = 0;
443   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
444     std::string Str;
445     raw_string_ostream StrOS(Str);
446     if (Constant.isMachineConstantPoolEntry()) {
447       Constant.Val.MachineCPVal->print(StrOS);
448     } else {
449       Constant.Val.ConstVal->printAsOperand(StrOS);
450     }
451 
452     yaml::MachineConstantPoolValue YamlConstant;
453     YamlConstant.ID = ID++;
454     YamlConstant.Value = StrOS.str();
455     YamlConstant.Alignment = Constant.getAlignment();
456     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
457 
458     MF.Constants.push_back(YamlConstant);
459   }
460 }
461 
462 void MIRPrinter::convert(ModuleSlotTracker &MST,
463                          yaml::MachineJumpTable &YamlJTI,
464                          const MachineJumpTableInfo &JTI) {
465   YamlJTI.Kind = JTI.getEntryKind();
466   unsigned ID = 0;
467   for (const auto &Table : JTI.getJumpTables()) {
468     std::string Str;
469     yaml::MachineJumpTable::Entry Entry;
470     Entry.ID = ID++;
471     for (const auto *MBB : Table.MBBs) {
472       raw_string_ostream StrOS(Str);
473       StrOS << printMBBReference(*MBB);
474       Entry.Blocks.push_back(StrOS.str());
475       Str.clear();
476     }
477     YamlJTI.Entries.push_back(Entry);
478   }
479 }
480 
481 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
482   const auto *TRI = MF.getSubtarget().getRegisterInfo();
483   unsigned I = 0;
484   for (const uint32_t *Mask : TRI->getRegMasks())
485     RegisterMaskIds.insert(std::make_pair(Mask, I++));
486 }
487 
488 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
489                            SmallVectorImpl<MachineBasicBlock*> &Result,
490                            bool &IsFallthrough) {
491   SmallPtrSet<MachineBasicBlock*,8> Seen;
492 
493   for (const MachineInstr &MI : MBB) {
494     if (MI.isPHI())
495       continue;
496     for (const MachineOperand &MO : MI.operands()) {
497       if (!MO.isMBB())
498         continue;
499       MachineBasicBlock *Succ = MO.getMBB();
500       auto RP = Seen.insert(Succ);
501       if (RP.second)
502         Result.push_back(Succ);
503     }
504   }
505   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
506   IsFallthrough = I == MBB.end() || !I->isBarrier();
507 }
508 
509 bool
510 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
511   if (MBB.succ_size() <= 1)
512     return true;
513   if (!MBB.hasSuccessorProbabilities())
514     return true;
515 
516   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
517                                               MBB.Probs.end());
518   BranchProbability::normalizeProbabilities(Normalized.begin(),
519                                             Normalized.end());
520   SmallVector<BranchProbability,8> Equal(Normalized.size());
521   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
522 
523   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
524 }
525 
526 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
527   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
528   bool GuessedFallthrough;
529   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
530   if (GuessedFallthrough) {
531     const MachineFunction &MF = *MBB.getParent();
532     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
533     if (NextI != MF.end()) {
534       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
535       if (!is_contained(GuessedSuccs, Next))
536         GuessedSuccs.push_back(Next);
537     }
538   }
539   if (GuessedSuccs.size() != MBB.succ_size())
540     return false;
541   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
542 }
543 
544 void MIPrinter::print(const MachineBasicBlock &MBB) {
545   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
546   OS << "bb." << MBB.getNumber();
547   bool HasAttributes = false;
548   if (const auto *BB = MBB.getBasicBlock()) {
549     if (BB->hasName()) {
550       OS << "." << BB->getName();
551     } else {
552       HasAttributes = true;
553       OS << " (";
554       int Slot = MST.getLocalSlot(BB);
555       if (Slot == -1)
556         OS << "<ir-block badref>";
557       else
558         OS << (Twine("%ir-block.") + Twine(Slot)).str();
559     }
560   }
561   if (MBB.hasAddressTaken()) {
562     OS << (HasAttributes ? ", " : " (");
563     OS << "address-taken";
564     HasAttributes = true;
565   }
566   if (MBB.isEHPad()) {
567     OS << (HasAttributes ? ", " : " (");
568     OS << "landing-pad";
569     HasAttributes = true;
570   }
571   if (MBB.getAlignment()) {
572     OS << (HasAttributes ? ", " : " (");
573     OS << "align " << MBB.getAlignment();
574     HasAttributes = true;
575   }
576   if (HasAttributes)
577     OS << ")";
578   OS << ":\n";
579 
580   bool HasLineAttributes = false;
581   // Print the successors
582   bool canPredictProbs = canPredictBranchProbabilities(MBB);
583   // Even if the list of successors is empty, if we cannot guess it,
584   // we need to print it to tell the parser that the list is empty.
585   // This is needed, because MI model unreachable as empty blocks
586   // with an empty successor list. If the parser would see that
587   // without the successor list, it would guess the code would
588   // fallthrough.
589   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
590       !canPredictSuccessors(MBB)) {
591     OS.indent(2) << "successors: ";
592     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
593       if (I != MBB.succ_begin())
594         OS << ", ";
595       OS << printMBBReference(**I);
596       if (!SimplifyMIR || !canPredictProbs)
597         OS << '('
598            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
599            << ')';
600     }
601     OS << "\n";
602     HasLineAttributes = true;
603   }
604 
605   // Print the live in registers.
606   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
607   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
608     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
609     OS.indent(2) << "liveins: ";
610     bool First = true;
611     for (const auto &LI : MBB.liveins()) {
612       if (!First)
613         OS << ", ";
614       First = false;
615       OS << printReg(LI.PhysReg, &TRI);
616       if (!LI.LaneMask.all())
617         OS << ":0x" << PrintLaneMask(LI.LaneMask);
618     }
619     OS << "\n";
620     HasLineAttributes = true;
621   }
622 
623   if (HasLineAttributes)
624     OS << "\n";
625   bool IsInBundle = false;
626   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
627     const MachineInstr &MI = *I;
628     if (IsInBundle && !MI.isInsideBundle()) {
629       OS.indent(2) << "}\n";
630       IsInBundle = false;
631     }
632     OS.indent(IsInBundle ? 4 : 2);
633     print(MI);
634     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
635       OS << " {";
636       IsInBundle = true;
637     }
638     OS << "\n";
639   }
640   if (IsInBundle)
641     OS.indent(2) << "}\n";
642 }
643 
644 void MIPrinter::print(const MachineInstr &MI) {
645   const auto *MF = MI.getMF();
646   const auto &MRI = MF->getRegInfo();
647   const auto &SubTarget = MF->getSubtarget();
648   const auto *TRI = SubTarget.getRegisterInfo();
649   assert(TRI && "Expected target register info");
650   const auto *TII = SubTarget.getInstrInfo();
651   assert(TII && "Expected target instruction info");
652   if (MI.isCFIInstruction())
653     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
654 
655   SmallBitVector PrintedTypes(8);
656   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
657   unsigned I = 0, E = MI.getNumOperands();
658   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
659          !MI.getOperand(I).isImplicit();
660        ++I) {
661     if (I)
662       OS << ", ";
663     print(MI, I, TRI, ShouldPrintRegisterTies,
664           MI.getTypeToPrint(I, PrintedTypes, MRI),
665           /*PrintDef=*/false);
666   }
667 
668   if (I)
669     OS << " = ";
670   if (MI.getFlag(MachineInstr::FrameSetup))
671     OS << "frame-setup ";
672   if (MI.getFlag(MachineInstr::FrameDestroy))
673     OS << "frame-destroy ";
674 
675   OS << TII->getName(MI.getOpcode());
676   if (I < E)
677     OS << ' ';
678 
679   bool NeedComma = false;
680   for (; I < E; ++I) {
681     if (NeedComma)
682       OS << ", ";
683     print(MI, I, TRI, ShouldPrintRegisterTies,
684           MI.getTypeToPrint(I, PrintedTypes, MRI));
685     NeedComma = true;
686   }
687 
688   if (const DebugLoc &DL = MI.getDebugLoc()) {
689     if (NeedComma)
690       OS << ',';
691     OS << " debug-location ";
692     DL->printAsOperand(OS, MST);
693   }
694 
695   if (!MI.memoperands_empty()) {
696     OS << " :: ";
697     const LLVMContext &Context = MF->getFunction().getContext();
698     const MachineFrameInfo &MFI = MF->getFrameInfo();
699     bool NeedComma = false;
700     for (const auto *Op : MI.memoperands()) {
701       if (NeedComma)
702         OS << ", ";
703       Op->print(OS, MST, SSNs, Context, &MFI, TII);
704       NeedComma = true;
705     }
706   }
707 }
708 
709 void MIPrinter::printStackObjectReference(int FrameIndex) {
710   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
711   assert(ObjectInfo != StackObjectOperandMapping.end() &&
712          "Invalid frame index");
713   const FrameIndexOperand &Operand = ObjectInfo->second;
714   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
715                                             Operand.Name);
716 }
717 
718 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
719                       const TargetRegisterInfo *TRI,
720                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
721                       bool PrintDef) {
722   const MachineOperand &Op = MI.getOperand(OpIdx);
723   switch (Op.getType()) {
724   case MachineOperand::MO_Immediate:
725     if (MI.isOperandSubregIdx(OpIdx)) {
726       MachineOperand::printTargetFlags(OS, Op);
727       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
728       break;
729     }
730     LLVM_FALLTHROUGH;
731   case MachineOperand::MO_Register:
732   case MachineOperand::MO_CImmediate:
733   case MachineOperand::MO_FPImmediate:
734   case MachineOperand::MO_MachineBasicBlock:
735   case MachineOperand::MO_ConstantPoolIndex:
736   case MachineOperand::MO_TargetIndex:
737   case MachineOperand::MO_JumpTableIndex:
738   case MachineOperand::MO_ExternalSymbol:
739   case MachineOperand::MO_GlobalAddress:
740   case MachineOperand::MO_RegisterLiveOut:
741   case MachineOperand::MO_Metadata:
742   case MachineOperand::MO_MCSymbol:
743   case MachineOperand::MO_CFIIndex:
744   case MachineOperand::MO_IntrinsicID:
745   case MachineOperand::MO_Predicate:
746   case MachineOperand::MO_BlockAddress: {
747     unsigned TiedOperandIdx = 0;
748     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
749       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
750     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
751     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
752              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
753     break;
754   }
755   case MachineOperand::MO_FrameIndex:
756     printStackObjectReference(Op.getIndex());
757     break;
758   case MachineOperand::MO_RegisterMask: {
759     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
760     if (RegMaskInfo != RegisterMaskIds.end())
761       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
762     else
763       printCustomRegMask(Op.getRegMask(), OS, TRI);
764     break;
765   }
766   }
767 }
768 
769 void llvm::printMIR(raw_ostream &OS, const Module &M) {
770   yaml::Output Out(OS);
771   Out << const_cast<Module &>(M);
772 }
773 
774 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
775   MIRPrinter Printer(OS);
776   Printer.print(MF);
777 }
778