1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/MIRYamlMapping.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCContext.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132 
133 private:
134   void initRegisterMaskIds(const MachineFunction &MF);
135 };
136 
137 /// This class prints out the machine instructions using the MIR serialization
138 /// format.
139 class MIPrinter {
140   raw_ostream &OS;
141   ModuleSlotTracker &MST;
142   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144   /// Synchronization scope names registered with LLVMContext.
145   SmallVector<StringRef, 8> SSNs;
146 
147   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
149 
150 public:
151   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155         StackObjectOperandMapping(StackObjectOperandMapping) {}
156 
157   void print(const MachineBasicBlock &MBB);
158 
159   void print(const MachineInstr &MI);
160   void printStackObjectReference(int FrameIndex);
161   void print(const MachineInstr &MI, unsigned OpIdx,
162              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
163              LLT TypeToPrint, bool PrintDef = true);
164 };
165 
166 } // end namespace llvm
167 
168 namespace llvm {
169 namespace yaml {
170 
171 /// This struct serializes the LLVM IR module.
172 template <> struct BlockScalarTraits<Module> {
173   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
174     Mod.print(OS, nullptr);
175   }
176 
177   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
178     llvm_unreachable("LLVM Module is supposed to be parsed separately");
179     return "";
180   }
181 };
182 
183 } // end namespace yaml
184 } // end namespace llvm
185 
186 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
187                         const TargetRegisterInfo *TRI) {
188   raw_string_ostream OS(Dest.Value);
189   OS << printReg(Reg, TRI);
190 }
191 
192 void MIRPrinter::print(const MachineFunction &MF) {
193   initRegisterMaskIds(MF);
194 
195   yaml::MachineFunction YamlMF;
196   YamlMF.Name = MF.getName();
197   YamlMF.Alignment = MF.getAlignment();
198   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
199   YamlMF.HasWinCFI = MF.hasWinCFI();
200 
201   YamlMF.Legalized = MF.getProperties().hasProperty(
202       MachineFunctionProperties::Property::Legalized);
203   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
204       MachineFunctionProperties::Property::RegBankSelected);
205   YamlMF.Selected = MF.getProperties().hasProperty(
206       MachineFunctionProperties::Property::Selected);
207   YamlMF.FailedISel = MF.getProperties().hasProperty(
208       MachineFunctionProperties::Property::FailedISel);
209 
210   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
211   ModuleSlotTracker MST(MF.getFunction().getParent());
212   MST.incorporateFunction(MF.getFunction());
213   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
214   convertStackObjects(YamlMF, MF, MST);
215   if (const auto *ConstantPool = MF.getConstantPool())
216     convert(YamlMF, *ConstantPool);
217   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
218     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
219   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
220   bool IsNewlineNeeded = false;
221   for (const auto &MBB : MF) {
222     if (IsNewlineNeeded)
223       StrOS << "\n";
224     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
225         .print(MBB);
226     IsNewlineNeeded = true;
227   }
228   StrOS.flush();
229   yaml::Output Out(OS);
230   if (!SimplifyMIR)
231       Out.setWriteDefaultValues(true);
232   Out << YamlMF;
233 }
234 
235 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
236                                const TargetRegisterInfo *TRI) {
237   assert(RegMask && "Can't print an empty register mask");
238   OS << StringRef("CustomRegMask(");
239 
240   bool IsRegInRegMaskFound = false;
241   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
242     // Check whether the register is asserted in regmask.
243     if (RegMask[I / 32] & (1u << (I % 32))) {
244       if (IsRegInRegMaskFound)
245         OS << ',';
246       OS << printReg(I, TRI);
247       IsRegInRegMaskFound = true;
248     }
249   }
250 
251   OS << ')';
252 }
253 
254 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
255                                 const MachineRegisterInfo &RegInfo,
256                                 const TargetRegisterInfo *TRI) {
257   raw_string_ostream OS(Dest.Value);
258   OS << printRegClassOrBank(Reg, RegInfo, TRI);
259 }
260 
261 template <typename T>
262 static void
263 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
264                         T &Object, ModuleSlotTracker &MST) {
265   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
266                                         &Object.DebugExpr.Value,
267                                         &Object.DebugLoc.Value}};
268   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
269                                         DebugVar.Expr,
270                                         DebugVar.Loc}};
271   for (unsigned i = 0; i < 3; ++i) {
272     raw_string_ostream StrOS(*Outputs[i]);
273     Metas[i]->printAsOperand(StrOS, MST);
274   }
275 }
276 
277 void MIRPrinter::convert(yaml::MachineFunction &MF,
278                          const MachineRegisterInfo &RegInfo,
279                          const TargetRegisterInfo *TRI) {
280   MF.TracksRegLiveness = RegInfo.tracksLiveness();
281 
282   // Print the virtual register definitions.
283   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
284     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
285     yaml::VirtualRegisterDefinition VReg;
286     VReg.ID = I;
287     if (RegInfo.getVRegName(Reg) != "")
288       continue;
289     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
290     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
291     if (PreferredReg)
292       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
293     MF.VirtualRegisters.push_back(VReg);
294   }
295 
296   // Print the live ins.
297   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
298     yaml::MachineFunctionLiveIn LiveIn;
299     printRegMIR(LI.first, LiveIn.Register, TRI);
300     if (LI.second)
301       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
302     MF.LiveIns.push_back(LiveIn);
303   }
304 
305   // Prints the callee saved registers.
306   if (RegInfo.isUpdatedCSRsInitialized()) {
307     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
308     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
309     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
310       yaml::FlowStringValue Reg;
311       printRegMIR(*I, Reg, TRI);
312       CalleeSavedRegisters.push_back(Reg);
313     }
314     MF.CalleeSavedRegisters = CalleeSavedRegisters;
315   }
316 }
317 
318 void MIRPrinter::convert(ModuleSlotTracker &MST,
319                          yaml::MachineFrameInfo &YamlMFI,
320                          const MachineFrameInfo &MFI) {
321   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
322   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
323   YamlMFI.HasStackMap = MFI.hasStackMap();
324   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
325   YamlMFI.StackSize = MFI.getStackSize();
326   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
327   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
328   YamlMFI.AdjustsStack = MFI.adjustsStack();
329   YamlMFI.HasCalls = MFI.hasCalls();
330   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
331     ? MFI.getMaxCallFrameSize() : ~0u;
332   YamlMFI.CVBytesOfCalleeSavedRegisters =
333       MFI.getCVBytesOfCalleeSavedRegisters();
334   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
335   YamlMFI.HasVAStart = MFI.hasVAStart();
336   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
337   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
338   if (MFI.getSavePoint()) {
339     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
340     StrOS << printMBBReference(*MFI.getSavePoint());
341   }
342   if (MFI.getRestorePoint()) {
343     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
344     StrOS << printMBBReference(*MFI.getRestorePoint());
345   }
346 }
347 
348 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
349                                      const MachineFunction &MF,
350                                      ModuleSlotTracker &MST) {
351   const MachineFrameInfo &MFI = MF.getFrameInfo();
352   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
353   // Process fixed stack objects.
354   unsigned ID = 0;
355   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
356     if (MFI.isDeadObjectIndex(I))
357       continue;
358 
359     yaml::FixedMachineStackObject YamlObject;
360     YamlObject.ID = ID;
361     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
362                           ? yaml::FixedMachineStackObject::SpillSlot
363                           : yaml::FixedMachineStackObject::DefaultType;
364     YamlObject.Offset = MFI.getObjectOffset(I);
365     YamlObject.Size = MFI.getObjectSize(I);
366     YamlObject.Alignment = MFI.getObjectAlignment(I);
367     YamlObject.StackID = MFI.getStackID(I);
368     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
369     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
370     YMF.FixedStackObjects.push_back(YamlObject);
371     StackObjectOperandMapping.insert(
372         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
373   }
374 
375   // Process ordinary stack objects.
376   ID = 0;
377   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
378     if (MFI.isDeadObjectIndex(I))
379       continue;
380 
381     yaml::MachineStackObject YamlObject;
382     YamlObject.ID = ID;
383     if (const auto *Alloca = MFI.getObjectAllocation(I))
384       YamlObject.Name.Value =
385           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
386     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
387                           ? yaml::MachineStackObject::SpillSlot
388                           : MFI.isVariableSizedObjectIndex(I)
389                                 ? yaml::MachineStackObject::VariableSized
390                                 : yaml::MachineStackObject::DefaultType;
391     YamlObject.Offset = MFI.getObjectOffset(I);
392     YamlObject.Size = MFI.getObjectSize(I);
393     YamlObject.Alignment = MFI.getObjectAlignment(I);
394     YamlObject.StackID = MFI.getStackID(I);
395 
396     YMF.StackObjects.push_back(YamlObject);
397     StackObjectOperandMapping.insert(std::make_pair(
398         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
399   }
400 
401   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
402     yaml::StringValue Reg;
403     printRegMIR(CSInfo.getReg(), Reg, TRI);
404     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
405     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
406            "Invalid stack object index");
407     const FrameIndexOperand &StackObject = StackObjectInfo->second;
408     if (StackObject.IsFixed) {
409       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
410       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
411         CSInfo.isRestored();
412     } else {
413       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
414       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
415         CSInfo.isRestored();
416     }
417   }
418   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
419     auto LocalObject = MFI.getLocalFrameObjectMap(I);
420     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
421     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
422            "Invalid stack object index");
423     const FrameIndexOperand &StackObject = StackObjectInfo->second;
424     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
425     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
426   }
427 
428   // Print the stack object references in the frame information class after
429   // converting the stack objects.
430   if (MFI.hasStackProtectorIndex()) {
431     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
432     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
433         .printStackObjectReference(MFI.getStackProtectorIndex());
434   }
435 
436   // Print the debug variable information.
437   for (const MachineFunction::VariableDbgInfo &DebugVar :
438        MF.getVariableDbgInfo()) {
439     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
440     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
441            "Invalid stack object index");
442     const FrameIndexOperand &StackObject = StackObjectInfo->second;
443     if (StackObject.IsFixed) {
444       auto &Object = YMF.FixedStackObjects[StackObject.ID];
445       printStackObjectDbgInfo(DebugVar, Object, MST);
446     } else {
447       auto &Object = YMF.StackObjects[StackObject.ID];
448       printStackObjectDbgInfo(DebugVar, Object, MST);
449     }
450   }
451 }
452 
453 void MIRPrinter::convert(yaml::MachineFunction &MF,
454                          const MachineConstantPool &ConstantPool) {
455   unsigned ID = 0;
456   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
457     std::string Str;
458     raw_string_ostream StrOS(Str);
459     if (Constant.isMachineConstantPoolEntry()) {
460       Constant.Val.MachineCPVal->print(StrOS);
461     } else {
462       Constant.Val.ConstVal->printAsOperand(StrOS);
463     }
464 
465     yaml::MachineConstantPoolValue YamlConstant;
466     YamlConstant.ID = ID++;
467     YamlConstant.Value = StrOS.str();
468     YamlConstant.Alignment = Constant.getAlignment();
469     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
470 
471     MF.Constants.push_back(YamlConstant);
472   }
473 }
474 
475 void MIRPrinter::convert(ModuleSlotTracker &MST,
476                          yaml::MachineJumpTable &YamlJTI,
477                          const MachineJumpTableInfo &JTI) {
478   YamlJTI.Kind = JTI.getEntryKind();
479   unsigned ID = 0;
480   for (const auto &Table : JTI.getJumpTables()) {
481     std::string Str;
482     yaml::MachineJumpTable::Entry Entry;
483     Entry.ID = ID++;
484     for (const auto *MBB : Table.MBBs) {
485       raw_string_ostream StrOS(Str);
486       StrOS << printMBBReference(*MBB);
487       Entry.Blocks.push_back(StrOS.str());
488       Str.clear();
489     }
490     YamlJTI.Entries.push_back(Entry);
491   }
492 }
493 
494 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
495   const auto *TRI = MF.getSubtarget().getRegisterInfo();
496   unsigned I = 0;
497   for (const uint32_t *Mask : TRI->getRegMasks())
498     RegisterMaskIds.insert(std::make_pair(Mask, I++));
499 }
500 
501 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
502                            SmallVectorImpl<MachineBasicBlock*> &Result,
503                            bool &IsFallthrough) {
504   SmallPtrSet<MachineBasicBlock*,8> Seen;
505 
506   for (const MachineInstr &MI : MBB) {
507     if (MI.isPHI())
508       continue;
509     for (const MachineOperand &MO : MI.operands()) {
510       if (!MO.isMBB())
511         continue;
512       MachineBasicBlock *Succ = MO.getMBB();
513       auto RP = Seen.insert(Succ);
514       if (RP.second)
515         Result.push_back(Succ);
516     }
517   }
518   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
519   IsFallthrough = I == MBB.end() || !I->isBarrier();
520 }
521 
522 bool
523 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
524   if (MBB.succ_size() <= 1)
525     return true;
526   if (!MBB.hasSuccessorProbabilities())
527     return true;
528 
529   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
530                                               MBB.Probs.end());
531   BranchProbability::normalizeProbabilities(Normalized.begin(),
532                                             Normalized.end());
533   SmallVector<BranchProbability,8> Equal(Normalized.size());
534   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
535 
536   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
537 }
538 
539 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
540   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
541   bool GuessedFallthrough;
542   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
543   if (GuessedFallthrough) {
544     const MachineFunction &MF = *MBB.getParent();
545     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
546     if (NextI != MF.end()) {
547       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
548       if (!is_contained(GuessedSuccs, Next))
549         GuessedSuccs.push_back(Next);
550     }
551   }
552   if (GuessedSuccs.size() != MBB.succ_size())
553     return false;
554   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
555 }
556 
557 void MIPrinter::print(const MachineBasicBlock &MBB) {
558   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
559   OS << "bb." << MBB.getNumber();
560   bool HasAttributes = false;
561   if (const auto *BB = MBB.getBasicBlock()) {
562     if (BB->hasName()) {
563       OS << "." << BB->getName();
564     } else {
565       HasAttributes = true;
566       OS << " (";
567       int Slot = MST.getLocalSlot(BB);
568       if (Slot == -1)
569         OS << "<ir-block badref>";
570       else
571         OS << (Twine("%ir-block.") + Twine(Slot)).str();
572     }
573   }
574   if (MBB.hasAddressTaken()) {
575     OS << (HasAttributes ? ", " : " (");
576     OS << "address-taken";
577     HasAttributes = true;
578   }
579   if (MBB.isEHPad()) {
580     OS << (HasAttributes ? ", " : " (");
581     OS << "landing-pad";
582     HasAttributes = true;
583   }
584   if (MBB.getAlignment()) {
585     OS << (HasAttributes ? ", " : " (");
586     OS << "align " << MBB.getAlignment();
587     HasAttributes = true;
588   }
589   if (HasAttributes)
590     OS << ")";
591   OS << ":\n";
592 
593   bool HasLineAttributes = false;
594   // Print the successors
595   bool canPredictProbs = canPredictBranchProbabilities(MBB);
596   // Even if the list of successors is empty, if we cannot guess it,
597   // we need to print it to tell the parser that the list is empty.
598   // This is needed, because MI model unreachable as empty blocks
599   // with an empty successor list. If the parser would see that
600   // without the successor list, it would guess the code would
601   // fallthrough.
602   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
603       !canPredictSuccessors(MBB)) {
604     OS.indent(2) << "successors: ";
605     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
606       if (I != MBB.succ_begin())
607         OS << ", ";
608       OS << printMBBReference(**I);
609       if (!SimplifyMIR || !canPredictProbs)
610         OS << '('
611            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
612            << ')';
613     }
614     OS << "\n";
615     HasLineAttributes = true;
616   }
617 
618   // Print the live in registers.
619   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
620   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
621     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
622     OS.indent(2) << "liveins: ";
623     bool First = true;
624     for (const auto &LI : MBB.liveins()) {
625       if (!First)
626         OS << ", ";
627       First = false;
628       OS << printReg(LI.PhysReg, &TRI);
629       if (!LI.LaneMask.all())
630         OS << ":0x" << PrintLaneMask(LI.LaneMask);
631     }
632     OS << "\n";
633     HasLineAttributes = true;
634   }
635 
636   if (HasLineAttributes)
637     OS << "\n";
638   bool IsInBundle = false;
639   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
640     const MachineInstr &MI = *I;
641     if (IsInBundle && !MI.isInsideBundle()) {
642       OS.indent(2) << "}\n";
643       IsInBundle = false;
644     }
645     OS.indent(IsInBundle ? 4 : 2);
646     print(MI);
647     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
648       OS << " {";
649       IsInBundle = true;
650     }
651     OS << "\n";
652   }
653   if (IsInBundle)
654     OS.indent(2) << "}\n";
655 }
656 
657 void MIPrinter::print(const MachineInstr &MI) {
658   const auto *MF = MI.getMF();
659   const auto &MRI = MF->getRegInfo();
660   const auto &SubTarget = MF->getSubtarget();
661   const auto *TRI = SubTarget.getRegisterInfo();
662   assert(TRI && "Expected target register info");
663   const auto *TII = SubTarget.getInstrInfo();
664   assert(TII && "Expected target instruction info");
665   if (MI.isCFIInstruction())
666     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
667 
668   SmallBitVector PrintedTypes(8);
669   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
670   unsigned I = 0, E = MI.getNumOperands();
671   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
672          !MI.getOperand(I).isImplicit();
673        ++I) {
674     if (I)
675       OS << ", ";
676     print(MI, I, TRI, ShouldPrintRegisterTies,
677           MI.getTypeToPrint(I, PrintedTypes, MRI),
678           /*PrintDef=*/false);
679   }
680 
681   if (I)
682     OS << " = ";
683   if (MI.getFlag(MachineInstr::FrameSetup))
684     OS << "frame-setup ";
685   if (MI.getFlag(MachineInstr::FrameDestroy))
686     OS << "frame-destroy ";
687   if (MI.getFlag(MachineInstr::FmNoNans))
688     OS << "nnan ";
689   if (MI.getFlag(MachineInstr::FmNoInfs))
690     OS << "ninf ";
691   if (MI.getFlag(MachineInstr::FmNsz))
692     OS << "nsz ";
693   if (MI.getFlag(MachineInstr::FmArcp))
694     OS << "arcp ";
695   if (MI.getFlag(MachineInstr::FmContract))
696     OS << "contract ";
697   if (MI.getFlag(MachineInstr::FmAfn))
698     OS << "afn ";
699   if (MI.getFlag(MachineInstr::FmReassoc))
700     OS << "reassoc ";
701   if (MI.getFlag(MachineInstr::NoUWrap))
702     OS << "nuw ";
703   if (MI.getFlag(MachineInstr::NoSWrap))
704     OS << "nsw ";
705   if (MI.getFlag(MachineInstr::IsExact))
706     OS << "exact ";
707 
708   OS << TII->getName(MI.getOpcode());
709   if (I < E)
710     OS << ' ';
711 
712   bool NeedComma = false;
713   for (; I < E; ++I) {
714     if (NeedComma)
715       OS << ", ";
716     print(MI, I, TRI, ShouldPrintRegisterTies,
717           MI.getTypeToPrint(I, PrintedTypes, MRI));
718     NeedComma = true;
719   }
720 
721   // Print any optional symbols attached to this instruction as-if they were
722   // operands.
723   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
724     if (NeedComma)
725       OS << ',';
726     OS << " pre-instr-symbol ";
727     MachineOperand::printSymbol(OS, *PreInstrSymbol);
728     NeedComma = true;
729   }
730   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
731     if (NeedComma)
732       OS << ',';
733     OS << " post-instr-symbol ";
734     MachineOperand::printSymbol(OS, *PostInstrSymbol);
735     NeedComma = true;
736   }
737 
738   if (const DebugLoc &DL = MI.getDebugLoc()) {
739     if (NeedComma)
740       OS << ',';
741     OS << " debug-location ";
742     DL->printAsOperand(OS, MST);
743   }
744 
745   if (!MI.memoperands_empty()) {
746     OS << " :: ";
747     const LLVMContext &Context = MF->getFunction().getContext();
748     const MachineFrameInfo &MFI = MF->getFrameInfo();
749     bool NeedComma = false;
750     for (const auto *Op : MI.memoperands()) {
751       if (NeedComma)
752         OS << ", ";
753       Op->print(OS, MST, SSNs, Context, &MFI, TII);
754       NeedComma = true;
755     }
756   }
757 }
758 
759 void MIPrinter::printStackObjectReference(int FrameIndex) {
760   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
761   assert(ObjectInfo != StackObjectOperandMapping.end() &&
762          "Invalid frame index");
763   const FrameIndexOperand &Operand = ObjectInfo->second;
764   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
765                                             Operand.Name);
766 }
767 
768 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
769                       const TargetRegisterInfo *TRI,
770                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
771                       bool PrintDef) {
772   const MachineOperand &Op = MI.getOperand(OpIdx);
773   switch (Op.getType()) {
774   case MachineOperand::MO_Immediate:
775     if (MI.isOperandSubregIdx(OpIdx)) {
776       MachineOperand::printTargetFlags(OS, Op);
777       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
778       break;
779     }
780     LLVM_FALLTHROUGH;
781   case MachineOperand::MO_Register:
782   case MachineOperand::MO_CImmediate:
783   case MachineOperand::MO_FPImmediate:
784   case MachineOperand::MO_MachineBasicBlock:
785   case MachineOperand::MO_ConstantPoolIndex:
786   case MachineOperand::MO_TargetIndex:
787   case MachineOperand::MO_JumpTableIndex:
788   case MachineOperand::MO_ExternalSymbol:
789   case MachineOperand::MO_GlobalAddress:
790   case MachineOperand::MO_RegisterLiveOut:
791   case MachineOperand::MO_Metadata:
792   case MachineOperand::MO_MCSymbol:
793   case MachineOperand::MO_CFIIndex:
794   case MachineOperand::MO_IntrinsicID:
795   case MachineOperand::MO_Predicate:
796   case MachineOperand::MO_BlockAddress: {
797     unsigned TiedOperandIdx = 0;
798     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
799       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
800     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
801     Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
802              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
803     break;
804   }
805   case MachineOperand::MO_FrameIndex:
806     printStackObjectReference(Op.getIndex());
807     break;
808   case MachineOperand::MO_RegisterMask: {
809     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
810     if (RegMaskInfo != RegisterMaskIds.end())
811       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
812     else
813       printCustomRegMask(Op.getRegMask(), OS, TRI);
814     break;
815   }
816   }
817 }
818 
819 void llvm::printMIR(raw_ostream &OS, const Module &M) {
820   yaml::Output Out(OS);
821   Out << const_cast<Module &>(M);
822 }
823 
824 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
825   MIRPrinter Printer(OS);
826   Printer.print(MF);
827 }
828