1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the class that prints out the LLVM IR and machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MIRPrinter.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallBitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24 #include "llvm/CodeGen/MIRYamlMapping.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/TargetInstrInfo.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/CodeGen/TargetFrameLowering.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCContext.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true),
83                                     cl::desc("Print MIR debug-locations"));
84 
85 namespace {
86 
87 /// This structure describes how to print out stack object references.
88 struct FrameIndexOperand {
89   std::string Name;
90   unsigned ID;
91   bool IsFixed;
92 
93   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
94       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
95 
96   /// Return an ordinary stack object reference.
97   static FrameIndexOperand create(StringRef Name, unsigned ID) {
98     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
99   }
100 
101   /// Return a fixed stack object reference.
102   static FrameIndexOperand createFixed(unsigned ID) {
103     return FrameIndexOperand("", ID, /*IsFixed=*/true);
104   }
105 };
106 
107 } // end anonymous namespace
108 
109 namespace llvm {
110 
111 /// This class prints out the machine functions using the MIR serialization
112 /// format.
113 class MIRPrinter {
114   raw_ostream &OS;
115   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
116   /// Maps from stack object indices to operand indices which will be used when
117   /// printing frame index machine operands.
118   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
119 
120 public:
121   MIRPrinter(raw_ostream &OS) : OS(OS) {}
122 
123   void print(const MachineFunction &MF);
124 
125   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
126                const TargetRegisterInfo *TRI);
127   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
128                const MachineFrameInfo &MFI);
129   void convert(yaml::MachineFunction &MF,
130                const MachineConstantPool &ConstantPool);
131   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
132                const MachineJumpTableInfo &JTI);
133   void convertStackObjects(yaml::MachineFunction &YMF,
134                            const MachineFunction &MF, ModuleSlotTracker &MST);
135   void convertCallSiteObjects(yaml::MachineFunction &YMF,
136                               const MachineFunction &MF,
137                               ModuleSlotTracker &MST);
138 
139 private:
140   void initRegisterMaskIds(const MachineFunction &MF);
141 };
142 
143 /// This class prints out the machine instructions using the MIR serialization
144 /// format.
145 class MIPrinter {
146   raw_ostream &OS;
147   ModuleSlotTracker &MST;
148   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
149   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
150   /// Synchronization scope names registered with LLVMContext.
151   SmallVector<StringRef, 8> SSNs;
152 
153   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
154   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
155 
156 public:
157   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
158             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
159             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
160       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
161         StackObjectOperandMapping(StackObjectOperandMapping) {}
162 
163   void print(const MachineBasicBlock &MBB);
164 
165   void print(const MachineInstr &MI);
166   void printStackObjectReference(int FrameIndex);
167   void print(const MachineInstr &MI, unsigned OpIdx,
168              const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
169              bool ShouldPrintRegisterTies, LLT TypeToPrint,
170              bool PrintDef = true);
171 };
172 
173 } // end namespace llvm
174 
175 namespace llvm {
176 namespace yaml {
177 
178 /// This struct serializes the LLVM IR module.
179 template <> struct BlockScalarTraits<Module> {
180   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
181     Mod.print(OS, nullptr);
182   }
183 
184   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
185     llvm_unreachable("LLVM Module is supposed to be parsed separately");
186     return "";
187   }
188 };
189 
190 } // end namespace yaml
191 } // end namespace llvm
192 
193 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
194                         const TargetRegisterInfo *TRI) {
195   raw_string_ostream OS(Dest.Value);
196   OS << printReg(Reg, TRI);
197 }
198 
199 void MIRPrinter::print(const MachineFunction &MF) {
200   initRegisterMaskIds(MF);
201 
202   yaml::MachineFunction YamlMF;
203   YamlMF.Name = MF.getName();
204   YamlMF.Alignment = MF.getAlignment();
205   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
206   YamlMF.HasWinCFI = MF.hasWinCFI();
207 
208   YamlMF.Legalized = MF.getProperties().hasProperty(
209       MachineFunctionProperties::Property::Legalized);
210   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
211       MachineFunctionProperties::Property::RegBankSelected);
212   YamlMF.Selected = MF.getProperties().hasProperty(
213       MachineFunctionProperties::Property::Selected);
214   YamlMF.FailedISel = MF.getProperties().hasProperty(
215       MachineFunctionProperties::Property::FailedISel);
216 
217   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
218   ModuleSlotTracker MST(MF.getFunction().getParent());
219   MST.incorporateFunction(MF.getFunction());
220   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
221   convertStackObjects(YamlMF, MF, MST);
222   convertCallSiteObjects(YamlMF, MF, MST);
223   for (auto &Sub : MF.DebugValueSubstitutions)
224     YamlMF.DebugValueSubstitutions.push_back({Sub.first.first, Sub.first.second,
225                                               Sub.second.first,
226                                               Sub.second.second});
227   if (const auto *ConstantPool = MF.getConstantPool())
228     convert(YamlMF, *ConstantPool);
229   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
230     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
231 
232   const TargetMachine &TM = MF.getTarget();
233   YamlMF.MachineFuncInfo =
234       std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
235 
236   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
237   bool IsNewlineNeeded = false;
238   for (const auto &MBB : MF) {
239     if (IsNewlineNeeded)
240       StrOS << "\n";
241     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
242         .print(MBB);
243     IsNewlineNeeded = true;
244   }
245   StrOS.flush();
246   yaml::Output Out(OS);
247   if (!SimplifyMIR)
248       Out.setWriteDefaultValues(true);
249   Out << YamlMF;
250 }
251 
252 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
253                                const TargetRegisterInfo *TRI) {
254   assert(RegMask && "Can't print an empty register mask");
255   OS << StringRef("CustomRegMask(");
256 
257   bool IsRegInRegMaskFound = false;
258   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
259     // Check whether the register is asserted in regmask.
260     if (RegMask[I / 32] & (1u << (I % 32))) {
261       if (IsRegInRegMaskFound)
262         OS << ',';
263       OS << printReg(I, TRI);
264       IsRegInRegMaskFound = true;
265     }
266   }
267 
268   OS << ')';
269 }
270 
271 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
272                                 const MachineRegisterInfo &RegInfo,
273                                 const TargetRegisterInfo *TRI) {
274   raw_string_ostream OS(Dest.Value);
275   OS << printRegClassOrBank(Reg, RegInfo, TRI);
276 }
277 
278 template <typename T>
279 static void
280 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
281                         T &Object, ModuleSlotTracker &MST) {
282   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
283                                         &Object.DebugExpr.Value,
284                                         &Object.DebugLoc.Value}};
285   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
286                                         DebugVar.Expr,
287                                         DebugVar.Loc}};
288   for (unsigned i = 0; i < 3; ++i) {
289     raw_string_ostream StrOS(*Outputs[i]);
290     Metas[i]->printAsOperand(StrOS, MST);
291   }
292 }
293 
294 void MIRPrinter::convert(yaml::MachineFunction &MF,
295                          const MachineRegisterInfo &RegInfo,
296                          const TargetRegisterInfo *TRI) {
297   MF.TracksRegLiveness = RegInfo.tracksLiveness();
298 
299   // Print the virtual register definitions.
300   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
301     unsigned Reg = Register::index2VirtReg(I);
302     yaml::VirtualRegisterDefinition VReg;
303     VReg.ID = I;
304     if (RegInfo.getVRegName(Reg) != "")
305       continue;
306     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
307     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
308     if (PreferredReg)
309       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
310     MF.VirtualRegisters.push_back(VReg);
311   }
312 
313   // Print the live ins.
314   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
315     yaml::MachineFunctionLiveIn LiveIn;
316     printRegMIR(LI.first, LiveIn.Register, TRI);
317     if (LI.second)
318       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
319     MF.LiveIns.push_back(LiveIn);
320   }
321 
322   // Prints the callee saved registers.
323   if (RegInfo.isUpdatedCSRsInitialized()) {
324     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
325     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
326     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
327       yaml::FlowStringValue Reg;
328       printRegMIR(*I, Reg, TRI);
329       CalleeSavedRegisters.push_back(Reg);
330     }
331     MF.CalleeSavedRegisters = CalleeSavedRegisters;
332   }
333 }
334 
335 void MIRPrinter::convert(ModuleSlotTracker &MST,
336                          yaml::MachineFrameInfo &YamlMFI,
337                          const MachineFrameInfo &MFI) {
338   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
339   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
340   YamlMFI.HasStackMap = MFI.hasStackMap();
341   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
342   YamlMFI.StackSize = MFI.getStackSize();
343   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
344   YamlMFI.MaxAlignment = MFI.getMaxAlign().value();
345   YamlMFI.AdjustsStack = MFI.adjustsStack();
346   YamlMFI.HasCalls = MFI.hasCalls();
347   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
348     ? MFI.getMaxCallFrameSize() : ~0u;
349   YamlMFI.CVBytesOfCalleeSavedRegisters =
350       MFI.getCVBytesOfCalleeSavedRegisters();
351   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
352   YamlMFI.HasVAStart = MFI.hasVAStart();
353   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
354   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
355   if (MFI.getSavePoint()) {
356     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
357     StrOS << printMBBReference(*MFI.getSavePoint());
358   }
359   if (MFI.getRestorePoint()) {
360     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
361     StrOS << printMBBReference(*MFI.getRestorePoint());
362   }
363 }
364 
365 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
366                                      const MachineFunction &MF,
367                                      ModuleSlotTracker &MST) {
368   const MachineFrameInfo &MFI = MF.getFrameInfo();
369   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
370   // Process fixed stack objects.
371   unsigned ID = 0;
372   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I, ++ID) {
373     if (MFI.isDeadObjectIndex(I))
374       continue;
375 
376     yaml::FixedMachineStackObject YamlObject;
377     YamlObject.ID = ID;
378     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
379                           ? yaml::FixedMachineStackObject::SpillSlot
380                           : yaml::FixedMachineStackObject::DefaultType;
381     YamlObject.Offset = MFI.getObjectOffset(I);
382     YamlObject.Size = MFI.getObjectSize(I);
383     YamlObject.Alignment = MFI.getObjectAlign(I);
384     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
385     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
386     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
387     YMF.FixedStackObjects.push_back(YamlObject);
388     StackObjectOperandMapping.insert(
389         std::make_pair(I, FrameIndexOperand::createFixed(ID)));
390   }
391 
392   // Process ordinary stack objects.
393   ID = 0;
394   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I, ++ID) {
395     if (MFI.isDeadObjectIndex(I))
396       continue;
397 
398     yaml::MachineStackObject YamlObject;
399     YamlObject.ID = ID;
400     if (const auto *Alloca = MFI.getObjectAllocation(I))
401       YamlObject.Name.Value = std::string(
402           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>");
403     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
404                           ? yaml::MachineStackObject::SpillSlot
405                           : MFI.isVariableSizedObjectIndex(I)
406                                 ? yaml::MachineStackObject::VariableSized
407                                 : yaml::MachineStackObject::DefaultType;
408     YamlObject.Offset = MFI.getObjectOffset(I);
409     YamlObject.Size = MFI.getObjectSize(I);
410     YamlObject.Alignment = MFI.getObjectAlign(I);
411     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
412 
413     YMF.StackObjects.push_back(YamlObject);
414     StackObjectOperandMapping.insert(std::make_pair(
415         I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
416   }
417 
418   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
419     if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(CSInfo.getFrameIdx()))
420       continue;
421 
422     yaml::StringValue Reg;
423     printRegMIR(CSInfo.getReg(), Reg, TRI);
424     if (!CSInfo.isSpilledToReg()) {
425       auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
426       assert(StackObjectInfo != StackObjectOperandMapping.end() &&
427              "Invalid stack object index");
428       const FrameIndexOperand &StackObject = StackObjectInfo->second;
429       if (StackObject.IsFixed) {
430         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
431         YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
432           CSInfo.isRestored();
433       } else {
434         YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
435         YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
436           CSInfo.isRestored();
437       }
438     }
439   }
440   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
441     auto LocalObject = MFI.getLocalFrameObjectMap(I);
442     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
443     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
444            "Invalid stack object index");
445     const FrameIndexOperand &StackObject = StackObjectInfo->second;
446     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
447     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
448   }
449 
450   // Print the stack object references in the frame information class after
451   // converting the stack objects.
452   if (MFI.hasStackProtectorIndex()) {
453     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
454     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
455         .printStackObjectReference(MFI.getStackProtectorIndex());
456   }
457 
458   // Print the debug variable information.
459   for (const MachineFunction::VariableDbgInfo &DebugVar :
460        MF.getVariableDbgInfo()) {
461     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
462     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
463            "Invalid stack object index");
464     const FrameIndexOperand &StackObject = StackObjectInfo->second;
465     if (StackObject.IsFixed) {
466       auto &Object = YMF.FixedStackObjects[StackObject.ID];
467       printStackObjectDbgInfo(DebugVar, Object, MST);
468     } else {
469       auto &Object = YMF.StackObjects[StackObject.ID];
470       printStackObjectDbgInfo(DebugVar, Object, MST);
471     }
472   }
473 }
474 
475 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
476                                         const MachineFunction &MF,
477                                         ModuleSlotTracker &MST) {
478   const auto *TRI = MF.getSubtarget().getRegisterInfo();
479   for (auto CSInfo : MF.getCallSitesInfo()) {
480     yaml::CallSiteInfo YmlCS;
481     yaml::CallSiteInfo::MachineInstrLoc CallLocation;
482 
483     // Prepare instruction position.
484     MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator();
485     CallLocation.BlockNum = CallI->getParent()->getNumber();
486     // Get call instruction offset from the beginning of block.
487     CallLocation.Offset =
488         std::distance(CallI->getParent()->instr_begin(), CallI);
489     YmlCS.CallLocation = CallLocation;
490     // Construct call arguments and theirs forwarding register info.
491     for (auto ArgReg : CSInfo.second) {
492       yaml::CallSiteInfo::ArgRegPair YmlArgReg;
493       YmlArgReg.ArgNo = ArgReg.ArgNo;
494       printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
495       YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
496     }
497     YMF.CallSitesInfo.push_back(YmlCS);
498   }
499 
500   // Sort call info by position of call instructions.
501   llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
502              [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
503                if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
504                  return A.CallLocation.Offset < B.CallLocation.Offset;
505                return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
506              });
507 }
508 
509 void MIRPrinter::convert(yaml::MachineFunction &MF,
510                          const MachineConstantPool &ConstantPool) {
511   unsigned ID = 0;
512   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
513     std::string Str;
514     raw_string_ostream StrOS(Str);
515     if (Constant.isMachineConstantPoolEntry()) {
516       Constant.Val.MachineCPVal->print(StrOS);
517     } else {
518       Constant.Val.ConstVal->printAsOperand(StrOS);
519     }
520 
521     yaml::MachineConstantPoolValue YamlConstant;
522     YamlConstant.ID = ID++;
523     YamlConstant.Value = StrOS.str();
524     YamlConstant.Alignment = Constant.getAlign();
525     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
526 
527     MF.Constants.push_back(YamlConstant);
528   }
529 }
530 
531 void MIRPrinter::convert(ModuleSlotTracker &MST,
532                          yaml::MachineJumpTable &YamlJTI,
533                          const MachineJumpTableInfo &JTI) {
534   YamlJTI.Kind = JTI.getEntryKind();
535   unsigned ID = 0;
536   for (const auto &Table : JTI.getJumpTables()) {
537     std::string Str;
538     yaml::MachineJumpTable::Entry Entry;
539     Entry.ID = ID++;
540     for (const auto *MBB : Table.MBBs) {
541       raw_string_ostream StrOS(Str);
542       StrOS << printMBBReference(*MBB);
543       Entry.Blocks.push_back(StrOS.str());
544       Str.clear();
545     }
546     YamlJTI.Entries.push_back(Entry);
547   }
548 }
549 
550 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
551   const auto *TRI = MF.getSubtarget().getRegisterInfo();
552   unsigned I = 0;
553   for (const uint32_t *Mask : TRI->getRegMasks())
554     RegisterMaskIds.insert(std::make_pair(Mask, I++));
555 }
556 
557 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
558                            SmallVectorImpl<MachineBasicBlock*> &Result,
559                            bool &IsFallthrough) {
560   SmallPtrSet<MachineBasicBlock*,8> Seen;
561 
562   for (const MachineInstr &MI : MBB) {
563     if (MI.isPHI())
564       continue;
565     for (const MachineOperand &MO : MI.operands()) {
566       if (!MO.isMBB())
567         continue;
568       MachineBasicBlock *Succ = MO.getMBB();
569       auto RP = Seen.insert(Succ);
570       if (RP.second)
571         Result.push_back(Succ);
572     }
573   }
574   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
575   IsFallthrough = I == MBB.end() || !I->isBarrier();
576 }
577 
578 bool
579 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
580   if (MBB.succ_size() <= 1)
581     return true;
582   if (!MBB.hasSuccessorProbabilities())
583     return true;
584 
585   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
586                                               MBB.Probs.end());
587   BranchProbability::normalizeProbabilities(Normalized.begin(),
588                                             Normalized.end());
589   SmallVector<BranchProbability,8> Equal(Normalized.size());
590   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
591 
592   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
593 }
594 
595 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
596   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
597   bool GuessedFallthrough;
598   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
599   if (GuessedFallthrough) {
600     const MachineFunction &MF = *MBB.getParent();
601     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
602     if (NextI != MF.end()) {
603       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
604       if (!is_contained(GuessedSuccs, Next))
605         GuessedSuccs.push_back(Next);
606     }
607   }
608   if (GuessedSuccs.size() != MBB.succ_size())
609     return false;
610   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
611 }
612 
613 void MIPrinter::print(const MachineBasicBlock &MBB) {
614   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
615   MBB.printName(OS,
616                 MachineBasicBlock::PrintNameIr |
617                     MachineBasicBlock::PrintNameAttributes,
618                 &MST);
619   OS << ":\n";
620 
621   bool HasLineAttributes = false;
622   // Print the successors
623   bool canPredictProbs = canPredictBranchProbabilities(MBB);
624   // Even if the list of successors is empty, if we cannot guess it,
625   // we need to print it to tell the parser that the list is empty.
626   // This is needed, because MI model unreachable as empty blocks
627   // with an empty successor list. If the parser would see that
628   // without the successor list, it would guess the code would
629   // fallthrough.
630   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
631       !canPredictSuccessors(MBB)) {
632     OS.indent(2) << "successors: ";
633     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
634       if (I != MBB.succ_begin())
635         OS << ", ";
636       OS << printMBBReference(**I);
637       if (!SimplifyMIR || !canPredictProbs)
638         OS << '('
639            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
640            << ')';
641     }
642     OS << "\n";
643     HasLineAttributes = true;
644   }
645 
646   // Print the live in registers.
647   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
648   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
649     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
650     OS.indent(2) << "liveins: ";
651     bool First = true;
652     for (const auto &LI : MBB.liveins()) {
653       if (!First)
654         OS << ", ";
655       First = false;
656       OS << printReg(LI.PhysReg, &TRI);
657       if (!LI.LaneMask.all())
658         OS << ":0x" << PrintLaneMask(LI.LaneMask);
659     }
660     OS << "\n";
661     HasLineAttributes = true;
662   }
663 
664   if (HasLineAttributes)
665     OS << "\n";
666   bool IsInBundle = false;
667   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
668     const MachineInstr &MI = *I;
669     if (IsInBundle && !MI.isInsideBundle()) {
670       OS.indent(2) << "}\n";
671       IsInBundle = false;
672     }
673     OS.indent(IsInBundle ? 4 : 2);
674     print(MI);
675     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
676       OS << " {";
677       IsInBundle = true;
678     }
679     OS << "\n";
680   }
681   if (IsInBundle)
682     OS.indent(2) << "}\n";
683 }
684 
685 void MIPrinter::print(const MachineInstr &MI) {
686   const auto *MF = MI.getMF();
687   const auto &MRI = MF->getRegInfo();
688   const auto &SubTarget = MF->getSubtarget();
689   const auto *TRI = SubTarget.getRegisterInfo();
690   assert(TRI && "Expected target register info");
691   const auto *TII = SubTarget.getInstrInfo();
692   assert(TII && "Expected target instruction info");
693   if (MI.isCFIInstruction())
694     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
695 
696   SmallBitVector PrintedTypes(8);
697   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
698   unsigned I = 0, E = MI.getNumOperands();
699   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
700          !MI.getOperand(I).isImplicit();
701        ++I) {
702     if (I)
703       OS << ", ";
704     print(MI, I, TRI, TII, ShouldPrintRegisterTies,
705           MI.getTypeToPrint(I, PrintedTypes, MRI),
706           /*PrintDef=*/false);
707   }
708 
709   if (I)
710     OS << " = ";
711   if (MI.getFlag(MachineInstr::FrameSetup))
712     OS << "frame-setup ";
713   if (MI.getFlag(MachineInstr::FrameDestroy))
714     OS << "frame-destroy ";
715   if (MI.getFlag(MachineInstr::FmNoNans))
716     OS << "nnan ";
717   if (MI.getFlag(MachineInstr::FmNoInfs))
718     OS << "ninf ";
719   if (MI.getFlag(MachineInstr::FmNsz))
720     OS << "nsz ";
721   if (MI.getFlag(MachineInstr::FmArcp))
722     OS << "arcp ";
723   if (MI.getFlag(MachineInstr::FmContract))
724     OS << "contract ";
725   if (MI.getFlag(MachineInstr::FmAfn))
726     OS << "afn ";
727   if (MI.getFlag(MachineInstr::FmReassoc))
728     OS << "reassoc ";
729   if (MI.getFlag(MachineInstr::NoUWrap))
730     OS << "nuw ";
731   if (MI.getFlag(MachineInstr::NoSWrap))
732     OS << "nsw ";
733   if (MI.getFlag(MachineInstr::IsExact))
734     OS << "exact ";
735   if (MI.getFlag(MachineInstr::NoFPExcept))
736     OS << "nofpexcept ";
737   if (MI.getFlag(MachineInstr::NoMerge))
738     OS << "nomerge ";
739 
740   OS << TII->getName(MI.getOpcode());
741   if (I < E)
742     OS << ' ';
743 
744   bool NeedComma = false;
745   for (; I < E; ++I) {
746     if (NeedComma)
747       OS << ", ";
748     print(MI, I, TRI, TII, ShouldPrintRegisterTies,
749           MI.getTypeToPrint(I, PrintedTypes, MRI));
750     NeedComma = true;
751   }
752 
753   // Print any optional symbols attached to this instruction as-if they were
754   // operands.
755   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
756     if (NeedComma)
757       OS << ',';
758     OS << " pre-instr-symbol ";
759     MachineOperand::printSymbol(OS, *PreInstrSymbol);
760     NeedComma = true;
761   }
762   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
763     if (NeedComma)
764       OS << ',';
765     OS << " post-instr-symbol ";
766     MachineOperand::printSymbol(OS, *PostInstrSymbol);
767     NeedComma = true;
768   }
769   if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) {
770     if (NeedComma)
771       OS << ',';
772     OS << " heap-alloc-marker ";
773     HeapAllocMarker->printAsOperand(OS, MST);
774     NeedComma = true;
775   }
776 
777   if (auto Num = MI.peekDebugInstrNum()) {
778     if (NeedComma)
779       OS << ',';
780     OS << " debug-instr-number " << Num;
781     NeedComma = true;
782   }
783 
784   if (PrintLocations) {
785     if (const DebugLoc &DL = MI.getDebugLoc()) {
786       if (NeedComma)
787         OS << ',';
788       OS << " debug-location ";
789       DL->printAsOperand(OS, MST);
790     }
791   }
792 
793   if (!MI.memoperands_empty()) {
794     OS << " :: ";
795     const LLVMContext &Context = MF->getFunction().getContext();
796     const MachineFrameInfo &MFI = MF->getFrameInfo();
797     bool NeedComma = false;
798     for (const auto *Op : MI.memoperands()) {
799       if (NeedComma)
800         OS << ", ";
801       Op->print(OS, MST, SSNs, Context, &MFI, TII);
802       NeedComma = true;
803     }
804   }
805 }
806 
807 void MIPrinter::printStackObjectReference(int FrameIndex) {
808   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
809   assert(ObjectInfo != StackObjectOperandMapping.end() &&
810          "Invalid frame index");
811   const FrameIndexOperand &Operand = ObjectInfo->second;
812   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
813                                             Operand.Name);
814 }
815 
816 static std::string formatOperandComment(std::string Comment) {
817   if (Comment.empty())
818     return Comment;
819   return std::string(" /* " + Comment + " */");
820 }
821 
822 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
823                       const TargetRegisterInfo *TRI,
824                       const TargetInstrInfo *TII,
825                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
826                       bool PrintDef) {
827   const MachineOperand &Op = MI.getOperand(OpIdx);
828   std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
829 
830   switch (Op.getType()) {
831   case MachineOperand::MO_Immediate:
832     if (MI.isOperandSubregIdx(OpIdx)) {
833       MachineOperand::printTargetFlags(OS, Op);
834       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
835       break;
836     }
837     LLVM_FALLTHROUGH;
838   case MachineOperand::MO_Register:
839   case MachineOperand::MO_CImmediate:
840   case MachineOperand::MO_FPImmediate:
841   case MachineOperand::MO_MachineBasicBlock:
842   case MachineOperand::MO_ConstantPoolIndex:
843   case MachineOperand::MO_TargetIndex:
844   case MachineOperand::MO_JumpTableIndex:
845   case MachineOperand::MO_ExternalSymbol:
846   case MachineOperand::MO_GlobalAddress:
847   case MachineOperand::MO_RegisterLiveOut:
848   case MachineOperand::MO_Metadata:
849   case MachineOperand::MO_MCSymbol:
850   case MachineOperand::MO_CFIIndex:
851   case MachineOperand::MO_IntrinsicID:
852   case MachineOperand::MO_Predicate:
853   case MachineOperand::MO_BlockAddress:
854   case MachineOperand::MO_ShuffleMask: {
855     unsigned TiedOperandIdx = 0;
856     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
857       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
858     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
859     Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
860              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
861       OS << formatOperandComment(MOComment);
862     break;
863   }
864   case MachineOperand::MO_FrameIndex:
865     printStackObjectReference(Op.getIndex());
866     break;
867   case MachineOperand::MO_RegisterMask: {
868     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
869     if (RegMaskInfo != RegisterMaskIds.end())
870       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
871     else
872       printCustomRegMask(Op.getRegMask(), OS, TRI);
873     break;
874   }
875   }
876 }
877 
878 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V,
879                                 ModuleSlotTracker &MST) {
880   if (isa<GlobalValue>(V)) {
881     V.printAsOperand(OS, /*PrintType=*/false, MST);
882     return;
883   }
884   if (isa<Constant>(V)) {
885     // Machine memory operands can load/store to/from constant value pointers.
886     OS << '`';
887     V.printAsOperand(OS, /*PrintType=*/true, MST);
888     OS << '`';
889     return;
890   }
891   OS << "%ir.";
892   if (V.hasName()) {
893     printLLVMNameWithoutPrefix(OS, V.getName());
894     return;
895   }
896   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
897   MachineOperand::printIRSlotNumber(OS, Slot);
898 }
899 
900 void llvm::printMIR(raw_ostream &OS, const Module &M) {
901   yaml::Output Out(OS);
902   Out << const_cast<Module &>(M);
903 }
904 
905 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
906   MIRPrinter Printer(OS);
907   Printer.print(MF);
908 }
909