1 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "regalloc"
15 #include "LiveRangeEdit.h"
16 #include "VirtRegMap.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/CodeGen/CalcSpillWeights.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 
25 using namespace llvm;
26 
27 LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg,
28                                         LiveIntervals &LIS,
29                                         VirtRegMap &VRM) {
30   MachineRegisterInfo &MRI = VRM.getRegInfo();
31   unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
32   VRM.grow();
33   VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
34   LiveInterval &LI = LIS.getOrCreateInterval(VReg);
35   newRegs_.push_back(&LI);
36   return LI;
37 }
38 
39 bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
40                                           const MachineInstr *DefMI,
41                                           const TargetInstrInfo &tii,
42                                           AliasAnalysis *aa) {
43   assert(DefMI && "Missing instruction");
44   scannedRemattable_ = true;
45   if (!tii.isTriviallyReMaterializable(DefMI, aa))
46     return false;
47   remattable_.insert(VNI);
48   return true;
49 }
50 
51 void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
52                                    const TargetInstrInfo &tii,
53                                    AliasAnalysis *aa) {
54   for (LiveInterval::vni_iterator I = parent_.vni_begin(),
55        E = parent_.vni_end(); I != E; ++I) {
56     VNInfo *VNI = *I;
57     if (VNI->isUnused())
58       continue;
59     MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
60     if (!DefMI)
61       continue;
62     checkRematerializable(VNI, DefMI, tii, aa);
63   }
64   scannedRemattable_ = true;
65 }
66 
67 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
68                                         const TargetInstrInfo &tii,
69                                         AliasAnalysis *aa) {
70   if (!scannedRemattable_)
71     scanRemattable(lis, tii, aa);
72   return !remattable_.empty();
73 }
74 
75 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
76 /// OrigIdx are also available with the same value at UseIdx.
77 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
78                                        SlotIndex OrigIdx,
79                                        SlotIndex UseIdx,
80                                        LiveIntervals &lis) {
81   OrigIdx = OrigIdx.getUseIndex();
82   UseIdx = UseIdx.getUseIndex();
83   for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
84     const MachineOperand &MO = OrigMI->getOperand(i);
85     if (!MO.isReg() || !MO.getReg() || MO.isDef())
86       continue;
87     // Reserved registers are OK.
88     if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
89       continue;
90     // We cannot depend on virtual registers in uselessRegs_.
91     if (uselessRegs_)
92       for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
93         if ((*uselessRegs_)[ui]->reg == MO.getReg())
94           return false;
95 
96     LiveInterval &li = lis.getInterval(MO.getReg());
97     const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
98     if (!OVNI)
99       continue;
100     if (OVNI != li.getVNInfoAt(UseIdx))
101       return false;
102   }
103   return true;
104 }
105 
106 bool LiveRangeEdit::canRematerializeAt(Remat &RM,
107                                        SlotIndex UseIdx,
108                                        bool cheapAsAMove,
109                                        LiveIntervals &lis) {
110   assert(scannedRemattable_ && "Call anyRematerializable first");
111 
112   // Use scanRemattable info.
113   if (!remattable_.count(RM.ParentVNI))
114     return false;
115 
116   // No defining instruction provided.
117   SlotIndex DefIdx;
118   if (RM.OrigMI)
119     DefIdx = lis.getInstructionIndex(RM.OrigMI);
120   else {
121     DefIdx = RM.ParentVNI->def;
122     RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
123     assert(RM.OrigMI && "No defining instruction for remattable value");
124   }
125 
126   // If only cheap remats were requested, bail out early.
127   if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
128     return false;
129 
130   // Verify that all used registers are available with the same values.
131   if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
132     return false;
133 
134   return true;
135 }
136 
137 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
138                                          MachineBasicBlock::iterator MI,
139                                          unsigned DestReg,
140                                          const Remat &RM,
141                                          LiveIntervals &lis,
142                                          const TargetInstrInfo &tii,
143                                          const TargetRegisterInfo &tri) {
144   assert(RM.OrigMI && "Invalid remat");
145   tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
146   rematted_.insert(RM.ParentVNI);
147   return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
148 }
149 
150 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
151   if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
152     LIS.removeInterval(Reg);
153 }
154 
155 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
156                                SmallVectorImpl<MachineInstr*> &Dead,
157                                MachineRegisterInfo &MRI,
158                                LiveIntervals &LIS,
159                                const TargetInstrInfo &TII) {
160   MachineInstr *DefMI = 0, *UseMI = 0;
161 
162   // Check that there is a single def and a single use.
163   for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
164        E = MRI.reg_nodbg_end(); I != E; ++I) {
165     MachineOperand &MO = I.getOperand();
166     MachineInstr *MI = MO.getParent();
167     if (MO.isDef()) {
168       if (DefMI && DefMI != MI)
169         return false;
170       if (!MI->getDesc().canFoldAsLoad())
171         return false;
172       DefMI = MI;
173     } else if (!MO.isUndef()) {
174       if (UseMI && UseMI != MI)
175         return false;
176       // FIXME: Targets don't know how to fold subreg uses.
177       if (MO.getSubReg())
178         return false;
179       UseMI = MI;
180     }
181   }
182   if (!DefMI || !UseMI)
183     return false;
184 
185   DEBUG(dbgs() << "Try to fold single def: " << *DefMI
186                << "       into single use: " << *UseMI);
187 
188   SmallVector<unsigned, 8> Ops;
189   if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
190     return false;
191 
192   MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
193   if (!FoldMI)
194     return false;
195   DEBUG(dbgs() << "                folded: " << *FoldMI);
196   LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
197   UseMI->eraseFromParent();
198   DefMI->addRegisterDead(LI->reg, 0);
199   Dead.push_back(DefMI);
200   return true;
201 }
202 
203 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
204                                       LiveIntervals &LIS, VirtRegMap &VRM,
205                                       const TargetInstrInfo &TII) {
206   SetVector<LiveInterval*,
207             SmallVector<LiveInterval*, 8>,
208             SmallPtrSet<LiveInterval*, 8> > ToShrink;
209   MachineRegisterInfo &MRI = VRM.getRegInfo();
210 
211   for (;;) {
212     // Erase all dead defs.
213     while (!Dead.empty()) {
214       MachineInstr *MI = Dead.pop_back_val();
215       assert(MI->allDefsAreDead() && "Def isn't really dead");
216       SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
217 
218       // Never delete inline asm.
219       if (MI->isInlineAsm()) {
220         DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
221         continue;
222       }
223 
224       // Use the same criteria as DeadMachineInstructionElim.
225       bool SawStore = false;
226       if (!MI->isSafeToMove(&TII, 0, SawStore)) {
227         DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
228         continue;
229       }
230 
231       DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
232 
233       // Check for live intervals that may shrink
234       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
235              MOE = MI->operands_end(); MOI != MOE; ++MOI) {
236         if (!MOI->isReg())
237           continue;
238         unsigned Reg = MOI->getReg();
239         if (!TargetRegisterInfo::isVirtualRegister(Reg))
240           continue;
241         LiveInterval &LI = LIS.getInterval(Reg);
242 
243         // Shrink read registers, unless it is likely to be expensive and
244         // unlikely to change anything. We typically don't want to shrink the
245         // PIC base register that has lots of uses everywhere.
246         // Always shrink COPY uses that probably come from live range splitting.
247         if (MI->readsVirtualRegister(Reg) &&
248             (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) ||
249              LI.killedAt(Idx)))
250           ToShrink.insert(&LI);
251 
252         // Remove defined value.
253         if (MOI->isDef()) {
254           if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
255             if (delegate_)
256               delegate_->LRE_WillShrinkVirtReg(LI.reg);
257             LI.removeValNo(VNI);
258             if (LI.empty()) {
259               ToShrink.remove(&LI);
260               eraseVirtReg(Reg, LIS);
261             }
262           }
263         }
264       }
265 
266       if (delegate_)
267         delegate_->LRE_WillEraseInstruction(MI);
268       LIS.RemoveMachineInstrFromMaps(MI);
269       MI->eraseFromParent();
270     }
271 
272     if (ToShrink.empty())
273       break;
274 
275     // Shrink just one live interval. Then delete new dead defs.
276     LiveInterval *LI = ToShrink.back();
277     ToShrink.pop_back();
278     if (foldAsLoad(LI, Dead, MRI, LIS, TII))
279       continue;
280     if (delegate_)
281       delegate_->LRE_WillShrinkVirtReg(LI->reg);
282     if (!LIS.shrinkToUses(LI, &Dead))
283       continue;
284 
285     // LI may have been separated, create new intervals.
286     LI->RenumberValues(LIS);
287     ConnectedVNInfoEqClasses ConEQ(LIS);
288     unsigned NumComp = ConEQ.Classify(LI);
289     if (NumComp <= 1)
290       continue;
291     DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
292     SmallVector<LiveInterval*, 8> Dups(1, LI);
293     for (unsigned i = 1; i != NumComp; ++i) {
294       Dups.push_back(&createFrom(LI->reg, LIS, VRM));
295       if (delegate_)
296         delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
297     }
298     ConEQ.Distribute(&Dups[0], MRI);
299   }
300 }
301 
302 void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
303                                              LiveIntervals &LIS,
304                                              const MachineLoopInfo &Loops) {
305   VirtRegAuxInfo VRAI(MF, LIS, Loops);
306   for (iterator I = begin(), E = end(); I != E; ++I) {
307     LiveInterval &LI = **I;
308     VRAI.CalculateRegClass(LI.reg);
309     VRAI.CalculateWeightAndHint(LI);
310   }
311 }
312