1 //===- LiveIntervalCalc.cpp - Calculate live interval --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the LiveIntervalCalc class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/LiveIntervalCalc.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/LiveInterval.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SlotIndexes.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/MC/LaneBitmask.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include <algorithm>
27 #include <cassert>
28 #include <iterator>
29 #include <tuple>
30 #include <utility>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "regalloc"
35 
36 // Reserve an address that indicates a value that is known to be "undef".
37 static VNInfo UndefVNI(0xbad, SlotIndex());
38 
39 static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
40                           LiveRange &LR, const MachineOperand &MO) {
41   const MachineInstr &MI = *MO.getParent();
42   SlotIndex DefIdx =
43       Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
44 
45   // Create the def in LR. This may find an existing def.
46   LR.createDeadDef(DefIdx, Alloc);
47 }
48 
49 void LiveIntervalCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
50   const MachineRegisterInfo *MRI = getRegInfo();
51   SlotIndexes *Indexes = getIndexes();
52   VNInfo::Allocator *Alloc = getVNAlloc();
53 
54   assert(MRI && Indexes && "call reset() first");
55 
56   // Step 1: Create minimal live segments for every definition of Reg.
57   // Visit all def operands. If the same instruction has multiple defs of Reg,
58   // createDeadDef() will deduplicate.
59   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
60   unsigned Reg = LI.reg();
61   for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
62     if (!MO.isDef() && !MO.readsReg())
63       continue;
64 
65     unsigned SubReg = MO.getSubReg();
66     if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
67       LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
68                                         : MRI->getMaxLaneMaskForVReg(Reg);
69       // If this is the first time we see a subregister def, initialize
70       // subranges by creating a copy of the main range.
71       if (!LI.hasSubRanges() && !LI.empty()) {
72         LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
73         LI.createSubRangeFrom(*Alloc, ClassMask, LI);
74       }
75 
76       LI.refineSubRanges(
77           *Alloc, SubMask,
78           [&MO, Indexes, Alloc](LiveInterval::SubRange &SR) {
79             if (MO.isDef())
80               createDeadDef(*Indexes, *Alloc, SR, MO);
81           },
82           *Indexes, TRI);
83     }
84 
85     // Create the def in the main liverange. We do not have to do this if
86     // subranges are tracked as we recreate the main range later in this case.
87     if (MO.isDef() && !LI.hasSubRanges())
88       createDeadDef(*Indexes, *Alloc, LI, MO);
89   }
90 
91   // We may have created empty live ranges for partially undefined uses, we
92   // can't keep them because we won't find defs in them later.
93   LI.removeEmptySubRanges();
94 
95   const MachineFunction *MF = getMachineFunction();
96   MachineDominatorTree *DomTree = getDomTree();
97   // Step 2: Extend live segments to all uses, constructing SSA form as
98   // necessary.
99   if (LI.hasSubRanges()) {
100     for (LiveInterval::SubRange &S : LI.subranges()) {
101       LiveIntervalCalc SubLIC;
102       SubLIC.reset(MF, Indexes, DomTree, Alloc);
103       SubLIC.extendToUses(S, Reg, S.LaneMask, &LI);
104     }
105     LI.clear();
106     constructMainRangeFromSubranges(LI);
107   } else {
108     resetLiveOutMap();
109     extendToUses(LI, Reg, LaneBitmask::getAll());
110   }
111 }
112 
113 void LiveIntervalCalc::constructMainRangeFromSubranges(LiveInterval &LI) {
114   // First create dead defs at all defs found in subranges.
115   LiveRange &MainRange = LI;
116   assert(MainRange.segments.empty() && MainRange.valnos.empty() &&
117          "Expect empty main liverange");
118 
119   VNInfo::Allocator *Alloc = getVNAlloc();
120   for (const LiveInterval::SubRange &SR : LI.subranges()) {
121     for (const VNInfo *VNI : SR.valnos) {
122       if (!VNI->isUnused() && !VNI->isPHIDef())
123         MainRange.createDeadDef(VNI->def, *Alloc);
124     }
125   }
126   resetLiveOutMap();
127   extendToUses(MainRange, LI.reg(), LaneBitmask::getAll(), &LI);
128 }
129 
130 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) {
131   const MachineRegisterInfo *MRI = getRegInfo();
132   SlotIndexes *Indexes = getIndexes();
133   VNInfo::Allocator *Alloc = getVNAlloc();
134   assert(MRI && Indexes && "call reset() first");
135 
136   // Visit all def operands. If the same instruction has multiple defs of Reg,
137   // LR.createDeadDef() will deduplicate.
138   for (MachineOperand &MO : MRI->def_operands(Reg))
139     createDeadDef(*Indexes, *Alloc, LR, MO);
140 }
141 
142 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg,
143                                     LaneBitmask Mask, LiveInterval *LI) {
144   const MachineRegisterInfo *MRI = getRegInfo();
145   SlotIndexes *Indexes = getIndexes();
146   SmallVector<SlotIndex, 4> Undefs;
147   if (LI != nullptr)
148     LI->computeSubRangeUndefs(Undefs, Mask, *MRI, *Indexes);
149 
150   // Visit all operands that read Reg. This may include partial defs.
151   bool IsSubRange = !Mask.all();
152   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
153   for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
154     // Clear all kill flags. They will be reinserted after register allocation
155     // by LiveIntervals::addKillFlags().
156     if (MO.isUse())
157       MO.setIsKill(false);
158     // MO::readsReg returns "true" for subregister defs. This is for keeping
159     // liveness of the entire register (i.e. for the main range of the live
160     // interval). For subranges, definitions of non-overlapping subregisters
161     // do not count as uses.
162     if (!MO.readsReg() || (IsSubRange && MO.isDef()))
163       continue;
164 
165     unsigned SubReg = MO.getSubReg();
166     if (SubReg != 0) {
167       LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
168       if (MO.isDef())
169         SLM = ~SLM;
170       // Ignore uses not reading the current (sub)range.
171       if ((SLM & Mask).none())
172         continue;
173     }
174 
175     // Determine the actual place of the use.
176     const MachineInstr *MI = MO.getParent();
177     unsigned OpNo = (&MO - &MI->getOperand(0));
178     SlotIndex UseIdx;
179     if (MI->isPHI()) {
180       assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
181       // The actual place where a phi operand is used is the end of the pred
182       // MBB. PHI operands are paired: (Reg, PredMBB).
183       UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo + 1).getMBB());
184     } else {
185       // Check for early-clobber redefs.
186       bool isEarlyClobber = false;
187       unsigned DefIdx;
188       if (MO.isDef())
189         isEarlyClobber = MO.isEarlyClobber();
190       else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
191         // FIXME: This would be a lot easier if tied early-clobber uses also
192         // had an early-clobber flag.
193         isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
194       }
195       UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
196     }
197 
198     // MI is reading Reg. We may have visited MI before if it happens to be
199     // reading Reg multiple times. That is OK, extend() is idempotent.
200     extend(LR, UseIdx, Reg, Undefs);
201   }
202 }
203