1 //===- LiveIntervalCalc.cpp - Calculate live interval --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the LiveIntervalCalc class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/LiveIntervalCalc.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SlotIndexes.h"
26 #include "llvm/CodeGen/TargetRegisterInfo.h"
27 #include "llvm/MC/LaneBitmask.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <iterator>
33 #include <tuple>
34 #include <utility>
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "regalloc"
39 
40 // Reserve an address that indicates a value that is known to be "undef".
41 static VNInfo UndefVNI(0xbad, SlotIndex());
42 
43 static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
44                           LiveRange &LR, const MachineOperand &MO) {
45   const MachineInstr &MI = *MO.getParent();
46   SlotIndex DefIdx =
47       Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
48 
49   // Create the def in LR. This may find an existing def.
50   LR.createDeadDef(DefIdx, Alloc);
51 }
52 
53 void LiveIntervalCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
54   const MachineRegisterInfo *MRI = getRegInfo();
55   SlotIndexes *Indexes = getIndexes();
56   VNInfo::Allocator *Alloc = getVNAlloc();
57 
58   assert(MRI && Indexes && "call reset() first");
59 
60   // Step 1: Create minimal live segments for every definition of Reg.
61   // Visit all def operands. If the same instruction has multiple defs of Reg,
62   // createDeadDef() will deduplicate.
63   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
64   unsigned Reg = LI.reg;
65   for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
66     if (!MO.isDef() && !MO.readsReg())
67       continue;
68 
69     unsigned SubReg = MO.getSubReg();
70     if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
71       LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
72                                         : MRI->getMaxLaneMaskForVReg(Reg);
73       // If this is the first time we see a subregister def, initialize
74       // subranges by creating a copy of the main range.
75       if (!LI.hasSubRanges() && !LI.empty()) {
76         LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
77         LI.createSubRangeFrom(*Alloc, ClassMask, LI);
78       }
79 
80       LI.refineSubRanges(
81           *Alloc, SubMask,
82           [&MO, Indexes, Alloc](LiveInterval::SubRange &SR) {
83             if (MO.isDef())
84               createDeadDef(*Indexes, *Alloc, SR, MO);
85           },
86           *Indexes, TRI);
87     }
88 
89     // Create the def in the main liverange. We do not have to do this if
90     // subranges are tracked as we recreate the main range later in this case.
91     if (MO.isDef() && !LI.hasSubRanges())
92       createDeadDef(*Indexes, *Alloc, LI, MO);
93   }
94 
95   // We may have created empty live ranges for partially undefined uses, we
96   // can't keep them because we won't find defs in them later.
97   LI.removeEmptySubRanges();
98 
99   const MachineFunction *MF = getMachineFunction();
100   MachineDominatorTree *DomTree = getDomTree();
101   // Step 2: Extend live segments to all uses, constructing SSA form as
102   // necessary.
103   if (LI.hasSubRanges()) {
104     for (LiveInterval::SubRange &S : LI.subranges()) {
105       LiveIntervalCalc SubLIC;
106       SubLIC.reset(MF, Indexes, DomTree, Alloc);
107       SubLIC.extendToUses(S, Reg, S.LaneMask, &LI);
108     }
109     LI.clear();
110     constructMainRangeFromSubranges(LI);
111   } else {
112     resetLiveOutMap();
113     extendToUses(LI, Reg, LaneBitmask::getAll());
114   }
115 }
116 
117 void LiveIntervalCalc::constructMainRangeFromSubranges(LiveInterval &LI) {
118   // First create dead defs at all defs found in subranges.
119   LiveRange &MainRange = LI;
120   assert(MainRange.segments.empty() && MainRange.valnos.empty() &&
121          "Expect empty main liverange");
122 
123   VNInfo::Allocator *Alloc = getVNAlloc();
124   for (const LiveInterval::SubRange &SR : LI.subranges()) {
125     for (const VNInfo *VNI : SR.valnos) {
126       if (!VNI->isUnused() && !VNI->isPHIDef())
127         MainRange.createDeadDef(VNI->def, *Alloc);
128     }
129   }
130   resetLiveOutMap();
131   extendToUses(MainRange, LI.reg, LaneBitmask::getAll(), &LI);
132 }
133 
134 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) {
135   const MachineRegisterInfo *MRI = getRegInfo();
136   SlotIndexes *Indexes = getIndexes();
137   VNInfo::Allocator *Alloc = getVNAlloc();
138   assert(MRI && Indexes && "call reset() first");
139 
140   // Visit all def operands. If the same instruction has multiple defs of Reg,
141   // LR.createDeadDef() will deduplicate.
142   for (MachineOperand &MO : MRI->def_operands(Reg))
143     createDeadDef(*Indexes, *Alloc, LR, MO);
144 }
145 
146 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg,
147                                     LaneBitmask Mask, LiveInterval *LI) {
148   const MachineRegisterInfo *MRI = getRegInfo();
149   SlotIndexes *Indexes = getIndexes();
150   SmallVector<SlotIndex, 4> Undefs;
151   if (LI != nullptr)
152     LI->computeSubRangeUndefs(Undefs, Mask, *MRI, *Indexes);
153 
154   // Visit all operands that read Reg. This may include partial defs.
155   bool IsSubRange = !Mask.all();
156   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
157   for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
158     // Clear all kill flags. They will be reinserted after register allocation
159     // by LiveIntervals::addKillFlags().
160     if (MO.isUse())
161       MO.setIsKill(false);
162     // MO::readsReg returns "true" for subregister defs. This is for keeping
163     // liveness of the entire register (i.e. for the main range of the live
164     // interval). For subranges, definitions of non-overlapping subregisters
165     // do not count as uses.
166     if (!MO.readsReg() || (IsSubRange && MO.isDef()))
167       continue;
168 
169     unsigned SubReg = MO.getSubReg();
170     if (SubReg != 0) {
171       LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
172       if (MO.isDef())
173         SLM = ~SLM;
174       // Ignore uses not reading the current (sub)range.
175       if ((SLM & Mask).none())
176         continue;
177     }
178 
179     // Determine the actual place of the use.
180     const MachineInstr *MI = MO.getParent();
181     unsigned OpNo = (&MO - &MI->getOperand(0));
182     SlotIndex UseIdx;
183     if (MI->isPHI()) {
184       assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
185       // The actual place where a phi operand is used is the end of the pred
186       // MBB. PHI operands are paired: (Reg, PredMBB).
187       UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo + 1).getMBB());
188     } else {
189       // Check for early-clobber redefs.
190       bool isEarlyClobber = false;
191       unsigned DefIdx;
192       if (MO.isDef())
193         isEarlyClobber = MO.isEarlyClobber();
194       else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
195         // FIXME: This would be a lot easier if tied early-clobber uses also
196         // had an early-clobber flag.
197         isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
198       }
199       UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
200     }
201 
202     // MI is reading Reg. We may have visited MI before if it happens to be
203     // reading Reg multiple times. That is OK, extend() is idempotent.
204     extend(LR, UseIdx, Reg, Undefs);
205   }
206 }