1 //===- LiveIntervalCalc.cpp - Calculate live interval --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the LiveIntervalCalc class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/LiveIntervalCalc.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/iterator_range.h"
16 #include "llvm/CodeGen/LiveInterval.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SlotIndexes.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/MC/LaneBitmask.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <cassert>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "regalloc"
30 
31 // Reserve an address that indicates a value that is known to be "undef".
32 static VNInfo UndefVNI(0xbad, SlotIndex());
33 
34 static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
35                           LiveRange &LR, const MachineOperand &MO) {
36   const MachineInstr &MI = *MO.getParent();
37   SlotIndex DefIdx =
38       Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
39 
40   // Create the def in LR. This may find an existing def.
41   LR.createDeadDef(DefIdx, Alloc);
42 }
43 
44 void LiveIntervalCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
45   const MachineRegisterInfo *MRI = getRegInfo();
46   SlotIndexes *Indexes = getIndexes();
47   VNInfo::Allocator *Alloc = getVNAlloc();
48 
49   assert(MRI && Indexes && "call reset() first");
50 
51   // Step 1: Create minimal live segments for every definition of Reg.
52   // Visit all def operands. If the same instruction has multiple defs of Reg,
53   // createDeadDef() will deduplicate.
54   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
55   unsigned Reg = LI.reg();
56   for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
57     if (!MO.isDef() && !MO.readsReg())
58       continue;
59 
60     unsigned SubReg = MO.getSubReg();
61     if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
62       LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
63                                         : MRI->getMaxLaneMaskForVReg(Reg);
64       // If this is the first time we see a subregister def, initialize
65       // subranges by creating a copy of the main range.
66       if (!LI.hasSubRanges() && !LI.empty()) {
67         LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
68         LI.createSubRangeFrom(*Alloc, ClassMask, LI);
69       }
70 
71       LI.refineSubRanges(
72           *Alloc, SubMask,
73           [&MO, Indexes, Alloc](LiveInterval::SubRange &SR) {
74             if (MO.isDef())
75               createDeadDef(*Indexes, *Alloc, SR, MO);
76           },
77           *Indexes, TRI);
78     }
79 
80     // Create the def in the main liverange. We do not have to do this if
81     // subranges are tracked as we recreate the main range later in this case.
82     if (MO.isDef() && !LI.hasSubRanges())
83       createDeadDef(*Indexes, *Alloc, LI, MO);
84   }
85 
86   // We may have created empty live ranges for partially undefined uses, we
87   // can't keep them because we won't find defs in them later.
88   LI.removeEmptySubRanges();
89 
90   const MachineFunction *MF = getMachineFunction();
91   MachineDominatorTree *DomTree = getDomTree();
92   // Step 2: Extend live segments to all uses, constructing SSA form as
93   // necessary.
94   if (LI.hasSubRanges()) {
95     for (LiveInterval::SubRange &S : LI.subranges()) {
96       LiveIntervalCalc SubLIC;
97       SubLIC.reset(MF, Indexes, DomTree, Alloc);
98       SubLIC.extendToUses(S, Reg, S.LaneMask, &LI);
99     }
100     LI.clear();
101     constructMainRangeFromSubranges(LI);
102   } else {
103     resetLiveOutMap();
104     extendToUses(LI, Reg, LaneBitmask::getAll());
105   }
106 }
107 
108 void LiveIntervalCalc::constructMainRangeFromSubranges(LiveInterval &LI) {
109   // First create dead defs at all defs found in subranges.
110   LiveRange &MainRange = LI;
111   assert(MainRange.segments.empty() && MainRange.valnos.empty() &&
112          "Expect empty main liverange");
113 
114   VNInfo::Allocator *Alloc = getVNAlloc();
115   for (const LiveInterval::SubRange &SR : LI.subranges()) {
116     for (const VNInfo *VNI : SR.valnos) {
117       if (!VNI->isUnused() && !VNI->isPHIDef())
118         MainRange.createDeadDef(VNI->def, *Alloc);
119     }
120   }
121   resetLiveOutMap();
122   extendToUses(MainRange, LI.reg(), LaneBitmask::getAll(), &LI);
123 }
124 
125 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) {
126   const MachineRegisterInfo *MRI = getRegInfo();
127   SlotIndexes *Indexes = getIndexes();
128   VNInfo::Allocator *Alloc = getVNAlloc();
129   assert(MRI && Indexes && "call reset() first");
130 
131   // Visit all def operands. If the same instruction has multiple defs of Reg,
132   // LR.createDeadDef() will deduplicate.
133   for (MachineOperand &MO : MRI->def_operands(Reg))
134     createDeadDef(*Indexes, *Alloc, LR, MO);
135 }
136 
137 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg,
138                                     LaneBitmask Mask, LiveInterval *LI) {
139   const MachineRegisterInfo *MRI = getRegInfo();
140   SlotIndexes *Indexes = getIndexes();
141   SmallVector<SlotIndex, 4> Undefs;
142   if (LI != nullptr)
143     LI->computeSubRangeUndefs(Undefs, Mask, *MRI, *Indexes);
144 
145   // Visit all operands that read Reg. This may include partial defs.
146   bool IsSubRange = !Mask.all();
147   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
148   for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
149     // Clear all kill flags. They will be reinserted after register allocation
150     // by LiveIntervals::addKillFlags().
151     if (MO.isUse())
152       MO.setIsKill(false);
153     // MO::readsReg returns "true" for subregister defs. This is for keeping
154     // liveness of the entire register (i.e. for the main range of the live
155     // interval). For subranges, definitions of non-overlapping subregisters
156     // do not count as uses.
157     if (!MO.readsReg() || (IsSubRange && MO.isDef()))
158       continue;
159 
160     unsigned SubReg = MO.getSubReg();
161     if (SubReg != 0) {
162       LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
163       if (MO.isDef())
164         SLM = ~SLM;
165       // Ignore uses not reading the current (sub)range.
166       if ((SLM & Mask).none())
167         continue;
168     }
169 
170     // Determine the actual place of the use.
171     const MachineInstr *MI = MO.getParent();
172     unsigned OpNo = (&MO - &MI->getOperand(0));
173     SlotIndex UseIdx;
174     if (MI->isPHI()) {
175       assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
176       // The actual place where a phi operand is used is the end of the pred
177       // MBB. PHI operands are paired: (Reg, PredMBB).
178       UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo + 1).getMBB());
179     } else {
180       // Check for early-clobber redefs.
181       bool isEarlyClobber = false;
182       unsigned DefIdx;
183       if (MO.isDef())
184         isEarlyClobber = MO.isEarlyClobber();
185       else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
186         // FIXME: This would be a lot easier if tied early-clobber uses also
187         // had an early-clobber flag.
188         isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
189       }
190       UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
191     }
192 
193     // MI is reading Reg. We may have visited MI before if it happens to be
194     // reading Reg multiple times. That is OK, extend() is idempotent.
195     extend(LR, UseIdx, Reg, Undefs);
196   }
197 }
198