1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LLVMTargetMachine class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/Analysis/Verifier.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/AsmPrinter.h"
20 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/GCStrategy.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Target/TargetData.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include "llvm/ADT/OwningPtr.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/FormattedStream.h"
41 #include "llvm/Support/TargetRegistry.h"
42 using namespace llvm;
43 
44 namespace llvm {
45   bool EnableFastISel;
46 }
47 
48 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
49     cl::desc("Disable Post Regalloc"));
50 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
51     cl::desc("Disable branch folding"));
52 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
53     cl::desc("Disable tail duplication"));
54 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
55     cl::desc("Disable pre-register allocation tail duplication"));
56 static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
57     cl::Hidden, cl::desc("Enable probability-driven block placement"));
58 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
59     cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
60 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
61     cl::desc("Disable code placement"));
62 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
63     cl::desc("Disable Stack Slot Coloring"));
64 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
65     cl::desc("Disable Machine Dead Code Elimination"));
66 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
67     cl::desc("Disable Machine LICM"));
68 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
69     cl::desc("Disable Machine Common Subexpression Elimination"));
70 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
71     cl::Hidden,
72     cl::desc("Disable Machine LICM"));
73 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
74     cl::desc("Disable Machine Sinking"));
75 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
76     cl::desc("Disable Loop Strength Reduction Pass"));
77 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
78     cl::desc("Disable Codegen Prepare"));
79 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
80     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
81 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
82     cl::desc("Print LLVM IR input to isel pass"));
83 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
84     cl::desc("Dump garbage collector data"));
85 static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
86     cl::desc("Show encoding in .s output"));
87 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
88     cl::desc("Show instruction structure in .s output"));
89 static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
90     cl::desc("Enable MC API logging"));
91 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
92     cl::desc("Verify generated machine code"),
93     cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
94 
95 static cl::opt<cl::boolOrDefault>
96 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
97            cl::init(cl::BOU_UNSET));
98 
99 static bool getVerboseAsm() {
100   switch (AsmVerbose) {
101   default:
102   case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
103   case cl::BOU_TRUE:  return true;
104   case cl::BOU_FALSE: return false;
105   }
106 }
107 
108 // Enable or disable FastISel. Both options are needed, because
109 // FastISel is enabled by default with -fast, and we wish to be
110 // able to enable or disable fast-isel independently from -O0.
111 static cl::opt<cl::boolOrDefault>
112 EnableFastISelOption("fast-isel", cl::Hidden,
113   cl::desc("Enable the \"fast\" instruction selector"));
114 
115 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
116                                      StringRef CPU, StringRef FS,
117                                      Reloc::Model RM, CodeModel::Model CM,
118                                      CodeGenOpt::Level OL)
119   : TargetMachine(T, Triple, CPU, FS) {
120   CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
121   AsmInfo = T.createMCAsmInfo(Triple);
122   // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
123   // and if the old one gets included then MCAsmInfo will be NULL and
124   // we'll crash later.
125   // Provide the user with a useful error message about what's wrong.
126   assert(AsmInfo && "MCAsmInfo not initialized."
127          "Make sure you include the correct TargetSelect.h"
128          "and that InitializeAllTargetMCs() is being invoked!");
129 }
130 
131 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
132                                             formatted_raw_ostream &Out,
133                                             CodeGenFileType FileType,
134                                             bool DisableVerify) {
135   // Add common CodeGen passes.
136   MCContext *Context = 0;
137   if (addCommonCodeGenPasses(PM, DisableVerify, Context))
138     return true;
139   assert(Context != 0 && "Failed to get MCContext");
140 
141   if (hasMCSaveTempLabels())
142     Context->setAllowTemporaryLabels(false);
143 
144   const MCAsmInfo &MAI = *getMCAsmInfo();
145   const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
146   OwningPtr<MCStreamer> AsmStreamer;
147 
148   switch (FileType) {
149   default: return true;
150   case CGFT_AssemblyFile: {
151     MCInstPrinter *InstPrinter =
152       getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
153 
154     // Create a code emitter if asked to show the encoding.
155     MCCodeEmitter *MCE = 0;
156     MCAsmBackend *MAB = 0;
157     if (ShowMCEncoding) {
158       const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
159       MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
160       MAB = getTarget().createMCAsmBackend(getTargetTriple());
161     }
162 
163     MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
164                                                   getVerboseAsm(),
165                                                   hasMCUseLoc(),
166                                                   hasMCUseCFI(),
167                                                   hasMCUseDwarfDirectory(),
168                                                   InstPrinter,
169                                                   MCE, MAB,
170                                                   ShowMCInst);
171     AsmStreamer.reset(S);
172     break;
173   }
174   case CGFT_ObjectFile: {
175     // Create the code emitter for the target if it exists.  If not, .o file
176     // emission fails.
177     MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
178                                                          *Context);
179     MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
180     if (MCE == 0 || MAB == 0)
181       return true;
182 
183     AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
184                                                          *Context, *MAB, Out,
185                                                          MCE, hasMCRelaxAll(),
186                                                          hasMCNoExecStack()));
187     AsmStreamer.get()->InitSections();
188     break;
189   }
190   case CGFT_Null:
191     // The Null output is intended for use for performance analysis and testing,
192     // not real users.
193     AsmStreamer.reset(createNullStreamer(*Context));
194     break;
195   }
196 
197   if (EnableMCLogging)
198     AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
199 
200   // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
201   FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
202   if (Printer == 0)
203     return true;
204 
205   // If successful, createAsmPrinter took ownership of AsmStreamer.
206   AsmStreamer.take();
207 
208   PM.add(Printer);
209 
210   PM.add(createGCInfoDeleter());
211   return false;
212 }
213 
214 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
215 /// get machine code emitted.  This uses a JITCodeEmitter object to handle
216 /// actually outputting the machine code and resolving things like the address
217 /// of functions.  This method should returns true if machine code emission is
218 /// not supported.
219 ///
220 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
221                                                    JITCodeEmitter &JCE,
222                                                    bool DisableVerify) {
223   // Add common CodeGen passes.
224   MCContext *Ctx = 0;
225   if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
226     return true;
227 
228   addCodeEmitter(PM, JCE);
229   PM.add(createGCInfoDeleter());
230 
231   return false; // success!
232 }
233 
234 /// addPassesToEmitMC - Add passes to the specified pass manager to get
235 /// machine code emitted with the MCJIT. This method returns true if machine
236 /// code is not supported. It fills the MCContext Ctx pointer which can be
237 /// used to build custom MCStreamer.
238 ///
239 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
240                                           MCContext *&Ctx,
241                                           raw_ostream &Out,
242                                           bool DisableVerify) {
243   // Add common CodeGen passes.
244   if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
245     return true;
246 
247   if (hasMCSaveTempLabels())
248     Ctx->setAllowTemporaryLabels(false);
249 
250   // Create the code emitter for the target if it exists.  If not, .o file
251   // emission fails.
252   const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
253   MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
254   MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
255   if (MCE == 0 || MAB == 0)
256     return true;
257 
258   OwningPtr<MCStreamer> AsmStreamer;
259   AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
260                                                        *MAB, Out, MCE,
261                                                        hasMCRelaxAll(),
262                                                        hasMCNoExecStack()));
263   AsmStreamer.get()->InitSections();
264 
265   // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
266   FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
267   if (Printer == 0)
268     return true;
269 
270   // If successful, createAsmPrinter took ownership of AsmStreamer.
271   AsmStreamer.take();
272 
273   PM.add(Printer);
274 
275   return false; // success!
276 }
277 
278 static void printNoVerify(PassManagerBase &PM, const char *Banner) {
279   if (PrintMachineCode)
280     PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
281 }
282 
283 static void printAndVerify(PassManagerBase &PM,
284                            const char *Banner) {
285   if (PrintMachineCode)
286     PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
287 
288   if (VerifyMachineCode)
289     PM.add(createMachineVerifierPass(Banner));
290 }
291 
292 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
293 /// emitting to assembly files or machine code output.
294 ///
295 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
296                                                bool DisableVerify,
297                                                MCContext *&OutContext) {
298   // Standard LLVM-Level Passes.
299 
300   // Basic AliasAnalysis support.
301   // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
302   // BasicAliasAnalysis wins if they disagree. This is intended to help
303   // support "obvious" type-punning idioms.
304   PM.add(createTypeBasedAliasAnalysisPass());
305   PM.add(createBasicAliasAnalysisPass());
306 
307   // Before running any passes, run the verifier to determine if the input
308   // coming from the front-end and/or optimizer is valid.
309   if (!DisableVerify)
310     PM.add(createVerifierPass());
311 
312   // Run loop strength reduction before anything else.
313   if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
314     PM.add(createLoopStrengthReducePass(getTargetLowering()));
315     if (PrintLSR)
316       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
317   }
318 
319   PM.add(createGCLoweringPass());
320 
321   // Make sure that no unreachable blocks are instruction selected.
322   PM.add(createUnreachableBlockEliminationPass());
323 
324   // Turn exception handling constructs into something the code generators can
325   // handle.
326   switch (getMCAsmInfo()->getExceptionHandlingType()) {
327   case ExceptionHandling::SjLj:
328     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
329     // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
330     // catch info can get misplaced when a selector ends up more than one block
331     // removed from the parent invoke(s). This could happen when a landing
332     // pad is shared by multiple invokes and is also a target of a normal
333     // edge from elsewhere.
334     PM.add(createSjLjEHPass(getTargetLowering()));
335     // FALLTHROUGH
336   case ExceptionHandling::DwarfCFI:
337   case ExceptionHandling::ARM:
338   case ExceptionHandling::Win64:
339     PM.add(createDwarfEHPass(this));
340     break;
341   case ExceptionHandling::None:
342     PM.add(createLowerInvokePass(getTargetLowering()));
343 
344     // The lower invoke pass may create unreachable code. Remove it.
345     PM.add(createUnreachableBlockEliminationPass());
346     break;
347   }
348 
349   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
350     PM.add(createCodeGenPreparePass(getTargetLowering()));
351 
352   PM.add(createStackProtectorPass(getTargetLowering()));
353 
354   addPreISel(PM);
355 
356   if (PrintISelInput)
357     PM.add(createPrintFunctionPass("\n\n"
358                                    "*** Final LLVM Code input to ISel ***\n",
359                                    &dbgs()));
360 
361   // All passes which modify the LLVM IR are now complete; run the verifier
362   // to ensure that the IR is valid.
363   if (!DisableVerify)
364     PM.add(createVerifierPass());
365 
366   // Standard Lower-Level Passes.
367 
368   // Install a MachineModuleInfo class, which is an immutable pass that holds
369   // all the per-module stuff we're generating, including MCContext.
370   MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
371                                                  *getRegisterInfo(),
372                                      &getTargetLowering()->getObjFileLowering());
373   PM.add(MMI);
374   OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
375 
376   // Set up a MachineFunction for the rest of CodeGen to work on.
377   PM.add(new MachineFunctionAnalysis(*this));
378 
379   // Enable FastISel with -fast, but allow that to be overridden.
380   if (EnableFastISelOption == cl::BOU_TRUE ||
381       (getOptLevel() == CodeGenOpt::None &&
382        EnableFastISelOption != cl::BOU_FALSE))
383     EnableFastISel = true;
384 
385   // Ask the target for an isel.
386   if (addInstSelector(PM))
387     return true;
388 
389   // Print the instruction selected machine code...
390   printAndVerify(PM, "After Instruction Selection");
391 
392   // Expand pseudo-instructions emitted by ISel.
393   PM.add(createExpandISelPseudosPass());
394 
395   // Pre-ra tail duplication.
396   if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
397     PM.add(createTailDuplicatePass(true));
398     printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
399   }
400 
401   // Optimize PHIs before DCE: removing dead PHI cycles may make more
402   // instructions dead.
403   if (getOptLevel() != CodeGenOpt::None)
404     PM.add(createOptimizePHIsPass());
405 
406   // If the target requests it, assign local variables to stack slots relative
407   // to one another and simplify frame index references where possible.
408   PM.add(createLocalStackSlotAllocationPass());
409 
410   if (getOptLevel() != CodeGenOpt::None) {
411     // With optimization, dead code should already be eliminated. However
412     // there is one known exception: lowered code for arguments that are only
413     // used by tail calls, where the tail calls reuse the incoming stack
414     // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
415     if (!DisableMachineDCE)
416       PM.add(createDeadMachineInstructionElimPass());
417     printAndVerify(PM, "After codegen DCE pass");
418 
419     if (!DisableMachineLICM)
420       PM.add(createMachineLICMPass());
421     if (!DisableMachineCSE)
422       PM.add(createMachineCSEPass());
423     if (!DisableMachineSink)
424       PM.add(createMachineSinkingPass());
425     printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
426 
427     PM.add(createPeepholeOptimizerPass());
428     printAndVerify(PM, "After codegen peephole optimization pass");
429   }
430 
431   // Run pre-ra passes.
432   if (addPreRegAlloc(PM))
433     printAndVerify(PM, "After PreRegAlloc passes");
434 
435   // Perform register allocation.
436   PM.add(createRegisterAllocator(getOptLevel()));
437   printAndVerify(PM, "After Register Allocation");
438 
439   // Perform stack slot coloring and post-ra machine LICM.
440   if (getOptLevel() != CodeGenOpt::None) {
441     // FIXME: Re-enable coloring with register when it's capable of adding
442     // kill markers.
443     if (!DisableSSC)
444       PM.add(createStackSlotColoringPass(false));
445 
446     // Run post-ra machine LICM to hoist reloads / remats.
447     if (!DisablePostRAMachineLICM)
448       PM.add(createMachineLICMPass(false));
449 
450     printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
451   }
452 
453   // Run post-ra passes.
454   if (addPostRegAlloc(PM))
455     printAndVerify(PM, "After PostRegAlloc passes");
456 
457   PM.add(createExpandPostRAPseudosPass());
458   printAndVerify(PM, "After ExpandPostRAPseudos");
459 
460   // Insert prolog/epilog code.  Eliminate abstract frame index references...
461   PM.add(createPrologEpilogCodeInserter());
462   printAndVerify(PM, "After PrologEpilogCodeInserter");
463 
464   // Run pre-sched2 passes.
465   if (addPreSched2(PM))
466     printAndVerify(PM, "After PreSched2 passes");
467 
468   // Second pass scheduler.
469   if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
470     PM.add(createPostRAScheduler(getOptLevel()));
471     printAndVerify(PM, "After PostRAScheduler");
472   }
473 
474   // Branch folding must be run after regalloc and prolog/epilog insertion.
475   if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
476     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
477     printNoVerify(PM, "After BranchFolding");
478   }
479 
480   // Tail duplication.
481   if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
482     PM.add(createTailDuplicatePass(false));
483     printNoVerify(PM, "After TailDuplicate");
484   }
485 
486   PM.add(createGCMachineCodeAnalysisPass());
487 
488   if (PrintGCInfo)
489     PM.add(createGCInfoPrinter(dbgs()));
490 
491   if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
492     if (EnableBlockPlacement) {
493       // MachineBlockPlacement is an experimental pass which is disabled by
494       // default currently. Eventually it should subsume CodePlacementOpt, so
495       // when enabled, the other is disabled.
496       PM.add(createMachineBlockPlacementPass());
497       printNoVerify(PM, "After MachineBlockPlacement");
498     } else {
499       PM.add(createCodePlacementOptPass());
500       printNoVerify(PM, "After CodePlacementOpt");
501     }
502 
503     // Run a separate pass to collect block placement statistics.
504     if (EnableBlockPlacementStats) {
505       PM.add(createMachineBlockPlacementStatsPass());
506       printNoVerify(PM, "After MachineBlockPlacementStats");
507     }
508   }
509 
510   if (addPreEmitPass(PM))
511     printNoVerify(PM, "After PreEmit passes");
512 
513   return false;
514 }
515