1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LLVMTargetMachine class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 namespace llvm {
29   bool EnableFastISel;
30 }
31 
32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35     cl::desc("Print LLVM IR input to isel pass"));
36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37     cl::desc("Dump emitter generated instructions as assembly"));
38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39     cl::desc("Dump garbage collector data"));
40 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
41     cl::desc("Verify generated machine code"),
42     cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
43 
44 // When this works it will be on by default.
45 static cl::opt<bool>
46 DisablePostRAScheduler("disable-post-RA-scheduler",
47                        cl::desc("Disable scheduling after register allocation"),
48                        cl::init(true));
49 
50 // Enable or disable FastISel. Both options are needed, because
51 // FastISel is enabled by default with -fast, and we wish to be
52 // able to enable or disable fast-isel independently from -fast.
53 static cl::opt<cl::boolOrDefault>
54 EnableFastISelOption("fast-isel", cl::Hidden,
55   cl::desc("Enable the experimental \"fast\" instruction selector"));
56 
57 FileModel::Model
58 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
59                                        raw_ostream &Out,
60                                        CodeGenFileType FileType,
61                                        CodeGenOpt::Level OptLevel) {
62   // Add common CodeGen passes.
63   if (addCommonCodeGenPasses(PM, OptLevel))
64     return FileModel::Error;
65 
66   // Fold redundant debug labels.
67   PM.add(createDebugLabelFoldingPass());
68 
69   if (PrintMachineCode)
70     PM.add(createMachineFunctionPrinterPass(cerr));
71 
72   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
73     PM.add(createMachineFunctionPrinterPass(cerr));
74 
75   if (OptLevel != CodeGenOpt::None)
76     PM.add(createCodePlacementOptPass());
77 
78   switch (FileType) {
79   default:
80     break;
81   case TargetMachine::AssemblyFile:
82     if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
83       return FileModel::Error;
84     return FileModel::AsmFile;
85   case TargetMachine::ObjectFile:
86     if (getMachOWriterInfo())
87       return FileModel::MachOFile;
88     else if (getELFWriterInfo())
89       return FileModel::ElfFile;
90   }
91 
92   return FileModel::Error;
93 }
94 
95 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
96 /// be split up (e.g., to add an object writer pass), this method can be used to
97 /// finish up adding passes to emit the file, if necessary.
98 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
99                                                   MachineCodeEmitter *MCE,
100                                                   CodeGenOpt::Level OptLevel) {
101   if (MCE)
102     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
103 
104   PM.add(createGCInfoDeleter());
105 
106   // Delete machine code for this function
107   PM.add(createMachineCodeDeleter());
108 
109   return false; // success!
110 }
111 
112 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
113 /// be split up (e.g., to add an object writer pass), this method can be used to
114 /// finish up adding passes to emit the file, if necessary.
115 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
116                                                   JITCodeEmitter *JCE,
117                                                   CodeGenOpt::Level OptLevel) {
118   if (JCE)
119     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *JCE);
120 
121   PM.add(createGCInfoDeleter());
122 
123   // Delete machine code for this function
124   PM.add(createMachineCodeDeleter());
125 
126   return false; // success!
127 }
128 
129 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
130 /// be split up (e.g., to add an object writer pass), this method can be used to
131 /// finish up adding passes to emit the file, if necessary.
132 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
133                                                   ObjectCodeEmitter *OCE,
134                                                   CodeGenOpt::Level OptLevel) {
135   if (OCE)
136     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *OCE);
137 
138   PM.add(createGCInfoDeleter());
139 
140   // Delete machine code for this function
141   PM.add(createMachineCodeDeleter());
142 
143   return false; // success!
144 }
145 
146 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
147 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
148 /// actually outputting the machine code and resolving things like the address
149 /// of functions.  This method should returns true if machine code emission is
150 /// not supported.
151 ///
152 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
153                                                    MachineCodeEmitter &MCE,
154                                                    CodeGenOpt::Level OptLevel) {
155   // Add common CodeGen passes.
156   if (addCommonCodeGenPasses(PM, OptLevel))
157     return true;
158 
159   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
160     PM.add(createMachineFunctionPrinterPass(cerr));
161 
162   addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
163 
164   PM.add(createGCInfoDeleter());
165 
166   // Delete machine code for this function
167   PM.add(createMachineCodeDeleter());
168 
169   return false; // success!
170 }
171 
172 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
173 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
174 /// actually outputting the machine code and resolving things like the address
175 /// of functions.  This method should returns true if machine code emission is
176 /// not supported.
177 ///
178 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
179                                                    JITCodeEmitter &JCE,
180                                                    CodeGenOpt::Level OptLevel) {
181   // Add common CodeGen passes.
182   if (addCommonCodeGenPasses(PM, OptLevel))
183     return true;
184 
185   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
186     PM.add(createMachineFunctionPrinterPass(cerr));
187 
188   addCodeEmitter(PM, OptLevel, PrintEmittedAsm, JCE);
189 
190   PM.add(createGCInfoDeleter());
191 
192   // Delete machine code for this function
193   PM.add(createMachineCodeDeleter());
194 
195   return false; // success!
196 }
197 
198 static void printAndVerify(PassManagerBase &PM,
199                            bool allowDoubleDefs = false) {
200   if (PrintMachineCode)
201     PM.add(createMachineFunctionPrinterPass(cerr));
202 
203   if (VerifyMachineCode)
204     PM.add(createMachineVerifierPass(allowDoubleDefs));
205 }
206 
207 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
208 /// emitting to assembly files or machine code output.
209 ///
210 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
211                                                CodeGenOpt::Level OptLevel) {
212   // Standard LLVM-Level Passes.
213 
214   // Run loop strength reduction before anything else.
215   if (OptLevel != CodeGenOpt::None) {
216     PM.add(createLoopStrengthReducePass(getTargetLowering()));
217     if (PrintLSR)
218       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
219   }
220 
221   // Turn exception handling constructs into something the code generators can
222   // handle.
223   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
224     PM.add(createLowerInvokePass(getTargetLowering()));
225   else
226     PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
227 
228   PM.add(createGCLoweringPass());
229 
230   // Make sure that no unreachable blocks are instruction selected.
231   PM.add(createUnreachableBlockEliminationPass());
232 
233   if (OptLevel != CodeGenOpt::None)
234     PM.add(createCodeGenPreparePass(getTargetLowering()));
235 
236   PM.add(createStackProtectorPass(getTargetLowering()));
237 
238   if (PrintISelInput)
239     PM.add(createPrintFunctionPass("\n\n"
240                                    "*** Final LLVM Code input to ISel ***\n",
241                                    &errs()));
242 
243   // Standard Lower-Level Passes.
244 
245   // Enable FastISel with -fast, but allow that to be overridden.
246   if (EnableFastISelOption == cl::BOU_TRUE ||
247       (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
248     EnableFastISel = true;
249 
250   // Ask the target for an isel.
251   if (addInstSelector(PM, OptLevel))
252     return true;
253 
254   // Print the instruction selected machine code...
255   printAndVerify(PM, /* allowDoubleDefs= */ true);
256 
257   if (OptLevel != CodeGenOpt::None) {
258     PM.add(createMachineLICMPass());
259     PM.add(createMachineSinkingPass());
260     printAndVerify(PM, /* allowDoubleDefs= */ false);
261   }
262 
263   // Run pre-ra passes.
264   if (addPreRegAlloc(PM, OptLevel))
265     printAndVerify(PM);
266 
267   // Perform register allocation.
268   PM.add(createRegisterAllocator());
269 
270   // Perform stack slot coloring.
271   if (OptLevel != CodeGenOpt::None)
272     PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
273 
274   printAndVerify(PM);           // Print the register-allocated code
275 
276   // Run post-ra passes.
277   if (addPostRegAlloc(PM, OptLevel))
278     printAndVerify(PM);
279 
280   PM.add(createLowerSubregsPass());
281   printAndVerify(PM);
282 
283   // Insert prolog/epilog code.  Eliminate abstract frame index references...
284   PM.add(createPrologEpilogCodeInserter());
285   printAndVerify(PM);
286 
287   // Second pass scheduler.
288   if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
289     PM.add(createPostRAScheduler());
290     printAndVerify(PM);
291   }
292 
293   // Branch folding must be run after regalloc and prolog/epilog insertion.
294   if (OptLevel != CodeGenOpt::None) {
295     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
296     printAndVerify(PM);
297   }
298 
299   PM.add(createGCMachineCodeAnalysisPass());
300   printAndVerify(PM);
301 
302   if (PrintGCInfo)
303     PM.add(createGCInfoPrinter(*cerr));
304 
305   return false;
306 }
307