1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res,
164                                                          const SrcOp &Size,
165                                                          unsigned Align) {
166   assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
167   auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
168   Res.addDefToMIB(*getMRI(), MIB);
169   Size.addSrcToMIB(MIB);
170   MIB.addImm(Align);
171   return MIB;
172 }
173 
174 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res,
175                                                       int Idx) {
176   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
177   auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
178   Res.addDefToMIB(*getMRI(), MIB);
179   MIB.addFrameIndex(Idx);
180   return MIB;
181 }
182 
183 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res,
184                                                        const GlobalValue *GV) {
185   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
186   assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
187              GV->getType()->getAddressSpace() &&
188          "address space mismatch");
189 
190   auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
191   Res.addDefToMIB(*getMRI(), MIB);
192   MIB.addGlobalAddress(GV);
193   return MIB;
194 }
195 
196 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
197                                                      unsigned JTI) {
198   return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
199       .addJumpTableIndex(JTI);
200 }
201 
202 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
203                                         const LLT Op1) {
204   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
205   assert((Res == Op0 && Res == Op1) && "type mismatch");
206 }
207 
208 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
209                                        const LLT Op1) {
210   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
211   assert((Res == Op0) && "type mismatch");
212 }
213 
214 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res,
215                                                   const SrcOp &Op0,
216                                                   const SrcOp &Op1) {
217   assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
218          Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
219   assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
220 
221   return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
222 }
223 
224 Optional<MachineInstrBuilder>
225 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
226                                     const LLT ValueTy, uint64_t Value) {
227   assert(Res == 0 && "Res is a result argument");
228   assert(ValueTy.isScalar()  && "invalid offset type");
229 
230   if (Value == 0) {
231     Res = Op0;
232     return None;
233   }
234 
235   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
236   auto Cst = buildConstant(ValueTy, Value);
237   return buildPtrAdd(Res, Op0, Cst.getReg(0));
238 }
239 
240 MachineInstrBuilder MachineIRBuilder::buildPtrMask(const DstOp &Res,
241                                                    const SrcOp &Op0,
242                                                    uint32_t NumBits) {
243   assert(Res.getLLTTy(*getMRI()).isPointer() &&
244          Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
245 
246   auto MIB = buildInstr(TargetOpcode::G_PTR_MASK);
247   Res.addDefToMIB(*getMRI(), MIB);
248   Op0.addSrcToMIB(MIB);
249   MIB.addImm(NumBits);
250   return MIB;
251 }
252 
253 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
254   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
255 }
256 
257 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
258   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
259   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
260 }
261 
262 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
263                                                 unsigned JTI,
264                                                 Register IndexReg) {
265   assert(getMRI()->getType(TablePtr).isPointer() &&
266          "Table reg must be a pointer");
267   return buildInstr(TargetOpcode::G_BRJT)
268       .addUse(TablePtr)
269       .addJumpTableIndex(JTI)
270       .addUse(IndexReg);
271 }
272 
273 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
274                                                 const SrcOp &Op) {
275   return buildInstr(TargetOpcode::COPY, Res, Op);
276 }
277 
278 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
279                                                     const ConstantInt &Val) {
280   LLT Ty = Res.getLLTTy(*getMRI());
281   LLT EltTy = Ty.getScalarType();
282   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
283          "creating constant with the wrong size");
284 
285   if (Ty.isVector()) {
286     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
287     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
288     .addCImm(&Val);
289     return buildSplatVector(Res, Const);
290   }
291 
292   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
293   Res.addDefToMIB(*getMRI(), Const);
294   Const.addCImm(&Val);
295   return Const;
296 }
297 
298 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
299                                                     int64_t Val) {
300   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
301                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
302   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
303   return buildConstant(Res, *CI);
304 }
305 
306 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
307                                                      const ConstantFP &Val) {
308   LLT Ty = Res.getLLTTy(*getMRI());
309   LLT EltTy = Ty.getScalarType();
310 
311   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
312          == EltTy.getSizeInBits() &&
313          "creating fconstant with the wrong size");
314 
315   assert(!Ty.isPointer() && "invalid operand type");
316 
317   if (Ty.isVector()) {
318     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
319     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
320     .addFPImm(&Val);
321 
322     return buildSplatVector(Res, Const);
323   }
324 
325   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
326   Res.addDefToMIB(*getMRI(), Const);
327   Const.addFPImm(&Val);
328   return Const;
329 }
330 
331 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
332                                                     const APInt &Val) {
333   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
334   return buildConstant(Res, *CI);
335 }
336 
337 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
338                                                      double Val) {
339   LLT DstTy = Res.getLLTTy(*getMRI());
340   auto &Ctx = getMF().getFunction().getContext();
341   auto *CFP =
342       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
343   return buildFConstant(Res, *CFP);
344 }
345 
346 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
347                                                      const APFloat &Val) {
348   auto &Ctx = getMF().getFunction().getContext();
349   auto *CFP = ConstantFP::get(Ctx, Val);
350   return buildFConstant(Res, *CFP);
351 }
352 
353 MachineInstrBuilder MachineIRBuilder::buildBrCond(Register Tst,
354                                                   MachineBasicBlock &Dest) {
355   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
356 
357   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
358 }
359 
360 MachineInstrBuilder MachineIRBuilder::buildLoad(const DstOp &Res,
361                                                 const SrcOp &Addr,
362                                                 MachineMemOperand &MMO) {
363   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
364 }
365 
366 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
367                                                      const DstOp &Res,
368                                                      const SrcOp &Addr,
369                                                      MachineMemOperand &MMO) {
370   assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
371   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
372 
373   auto MIB = buildInstr(Opcode);
374   Res.addDefToMIB(*getMRI(), MIB);
375   Addr.addSrcToMIB(MIB);
376   MIB.addMemOperand(&MMO);
377   return MIB;
378 }
379 
380 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
381                                                  const SrcOp &Addr,
382                                                  MachineMemOperand &MMO) {
383   assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
384   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
385 
386   auto MIB = buildInstr(TargetOpcode::G_STORE);
387   Val.addSrcToMIB(MIB);
388   Addr.addSrcToMIB(MIB);
389   MIB.addMemOperand(&MMO);
390   return MIB;
391 }
392 
393 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
394                                                   const SrcOp &Op) {
395   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
396 }
397 
398 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
399                                                 const SrcOp &Op) {
400   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
401 }
402 
403 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
404                                                 const SrcOp &Op) {
405   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
406 }
407 
408 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
409   const auto *TLI = getMF().getSubtarget().getTargetLowering();
410   switch (TLI->getBooleanContents(IsVec, IsFP)) {
411   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
412     return TargetOpcode::G_SEXT;
413   case TargetLoweringBase::ZeroOrOneBooleanContent:
414     return TargetOpcode::G_ZEXT;
415   default:
416     return TargetOpcode::G_ANYEXT;
417   }
418 }
419 
420 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
421                                                    const SrcOp &Op,
422                                                    bool IsFP) {
423   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
424   return buildInstr(ExtOp, Res, Op);
425 }
426 
427 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
428                                                       const DstOp &Res,
429                                                       const SrcOp &Op) {
430   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
431           TargetOpcode::G_SEXT == ExtOpc) &&
432          "Expecting Extending Opc");
433   assert(Res.getLLTTy(*getMRI()).isScalar() ||
434          Res.getLLTTy(*getMRI()).isVector());
435   assert(Res.getLLTTy(*getMRI()).isScalar() ==
436          Op.getLLTTy(*getMRI()).isScalar());
437 
438   unsigned Opcode = TargetOpcode::COPY;
439   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
440       Op.getLLTTy(*getMRI()).getSizeInBits())
441     Opcode = ExtOpc;
442   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
443            Op.getLLTTy(*getMRI()).getSizeInBits())
444     Opcode = TargetOpcode::G_TRUNC;
445   else
446     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
447 
448   return buildInstr(Opcode, Res, Op);
449 }
450 
451 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
452                                                        const SrcOp &Op) {
453   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
454 }
455 
456 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
457                                                        const SrcOp &Op) {
458   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
459 }
460 
461 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
462                                                          const SrcOp &Op) {
463   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
464 }
465 
466 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
467                                                 const SrcOp &Src) {
468   LLT SrcTy = Src.getLLTTy(*getMRI());
469   LLT DstTy = Dst.getLLTTy(*getMRI());
470   if (SrcTy == DstTy)
471     return buildCopy(Dst, Src);
472 
473   unsigned Opcode;
474   if (SrcTy.isPointer() && DstTy.isScalar())
475     Opcode = TargetOpcode::G_PTRTOINT;
476   else if (DstTy.isPointer() && SrcTy.isScalar())
477     Opcode = TargetOpcode::G_INTTOPTR;
478   else {
479     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
480     Opcode = TargetOpcode::G_BITCAST;
481   }
482 
483   return buildInstr(Opcode, Dst, Src);
484 }
485 
486 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
487                                                    const SrcOp &Src,
488                                                    uint64_t Index) {
489   LLT SrcTy = Src.getLLTTy(*getMRI());
490   LLT DstTy = Dst.getLLTTy(*getMRI());
491 
492 #ifndef NDEBUG
493   assert(SrcTy.isValid() && "invalid operand type");
494   assert(DstTy.isValid() && "invalid operand type");
495   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
496          "extracting off end of register");
497 #endif
498 
499   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
500     assert(Index == 0 && "insertion past the end of a register");
501     return buildCast(Dst, Src);
502   }
503 
504   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
505   Dst.addDefToMIB(*getMRI(), Extract);
506   Src.addSrcToMIB(Extract);
507   Extract.addImm(Index);
508   return Extract;
509 }
510 
511 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
512                                      ArrayRef<uint64_t> Indices) {
513 #ifndef NDEBUG
514   assert(Ops.size() == Indices.size() && "incompatible args");
515   assert(!Ops.empty() && "invalid trivial sequence");
516   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
517          "sequence offsets must be in ascending order");
518 
519   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
520   for (auto Op : Ops)
521     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
522 #endif
523 
524   LLT ResTy = getMRI()->getType(Res);
525   LLT OpTy = getMRI()->getType(Ops[0]);
526   unsigned OpSize = OpTy.getSizeInBits();
527   bool MaybeMerge = true;
528   for (unsigned i = 0; i < Ops.size(); ++i) {
529     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
530       MaybeMerge = false;
531       break;
532     }
533   }
534 
535   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
536     buildMerge(Res, Ops);
537     return;
538   }
539 
540   Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
541   buildUndef(ResIn);
542 
543   for (unsigned i = 0; i < Ops.size(); ++i) {
544     Register ResOut = i + 1 == Ops.size()
545                           ? Res
546                           : getMRI()->createGenericVirtualRegister(ResTy);
547     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
548     ResIn = ResOut;
549   }
550 }
551 
552 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
553   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
554 }
555 
556 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
557                                                  ArrayRef<Register> Ops) {
558   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
559   // we need some temporary storage for the DstOp objects. Here we use a
560   // sufficiently large SmallVector to not go through the heap.
561   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
562   assert(TmpVec.size() > 1);
563   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
564 }
565 
566 MachineInstrBuilder
567 MachineIRBuilder::buildMerge(const DstOp &Res,
568                              std::initializer_list<SrcOp> Ops) {
569   assert(Ops.size() > 1);
570   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
571 }
572 
573 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
574                                                    const SrcOp &Op) {
575   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
576   // we need some temporary storage for the DstOp objects. Here we use a
577   // sufficiently large SmallVector to not go through the heap.
578   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
579   assert(TmpVec.size() > 1);
580   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
581 }
582 
583 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
584                                                    const SrcOp &Op) {
585   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
586   SmallVector<Register, 8> TmpVec;
587   for (unsigned I = 0; I != NumReg; ++I)
588     TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
589   return buildUnmerge(TmpVec, Op);
590 }
591 
592 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
593                                                    const SrcOp &Op) {
594   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
595   // we need some temporary storage for the DstOp objects. Here we use a
596   // sufficiently large SmallVector to not go through the heap.
597   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
598   assert(TmpVec.size() > 1);
599   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
600 }
601 
602 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
603                                                        ArrayRef<Register> Ops) {
604   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
605   // we need some temporary storage for the DstOp objects. Here we use a
606   // sufficiently large SmallVector to not go through the heap.
607   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
608   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
609 }
610 
611 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
612                                                        const SrcOp &Src) {
613   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
614   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
615 }
616 
617 MachineInstrBuilder
618 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
619                                         ArrayRef<Register> Ops) {
620   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
621   // we need some temporary storage for the DstOp objects. Here we use a
622   // sufficiently large SmallVector to not go through the heap.
623   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
624   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
625 }
626 
627 MachineInstrBuilder
628 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
629   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
630   // we need some temporary storage for the DstOp objects. Here we use a
631   // sufficiently large SmallVector to not go through the heap.
632   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
633   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
634 }
635 
636 MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
637                                                   const SrcOp &Src,
638                                                   const SrcOp &Op,
639                                                   unsigned Index) {
640   assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
641              Res.getLLTTy(*getMRI()).getSizeInBits() &&
642          "insertion past the end of a register");
643 
644   if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
645       Op.getLLTTy(*getMRI()).getSizeInBits()) {
646     return buildCast(Res, Op);
647   }
648 
649   return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
650 }
651 
652 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
653                                                      ArrayRef<Register> ResultRegs,
654                                                      bool HasSideEffects) {
655   auto MIB =
656       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
657                                 : TargetOpcode::G_INTRINSIC);
658   for (unsigned ResultReg : ResultRegs)
659     MIB.addDef(ResultReg);
660   MIB.addIntrinsicID(ID);
661   return MIB;
662 }
663 
664 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
665                                                      ArrayRef<DstOp> Results,
666                                                      bool HasSideEffects) {
667   auto MIB =
668       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
669                                 : TargetOpcode::G_INTRINSIC);
670   for (DstOp Result : Results)
671     Result.addDefToMIB(*getMRI(), MIB);
672   MIB.addIntrinsicID(ID);
673   return MIB;
674 }
675 
676 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
677                                                  const SrcOp &Op) {
678   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
679 }
680 
681 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
682                                                    const SrcOp &Op,
683                                                    Optional<unsigned> Flags) {
684   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
685 }
686 
687 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
688                                                 const DstOp &Res,
689                                                 const SrcOp &Op0,
690                                                 const SrcOp &Op1) {
691   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
692 }
693 
694 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
695                                                 const DstOp &Res,
696                                                 const SrcOp &Op0,
697                                                 const SrcOp &Op1,
698                                                 Optional<unsigned> Flags) {
699 
700   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
701 }
702 
703 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
704                                                   const SrcOp &Tst,
705                                                   const SrcOp &Op0,
706                                                   const SrcOp &Op1,
707                                                   Optional<unsigned> Flags) {
708 
709   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
710 }
711 
712 MachineInstrBuilder
713 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
714                                            const SrcOp &Elt, const SrcOp &Idx) {
715   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
716 }
717 
718 MachineInstrBuilder
719 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
720                                             const SrcOp &Idx) {
721   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
722 }
723 
724 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
725     Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
726     Register NewVal, MachineMemOperand &MMO) {
727 #ifndef NDEBUG
728   LLT OldValResTy = getMRI()->getType(OldValRes);
729   LLT SuccessResTy = getMRI()->getType(SuccessRes);
730   LLT AddrTy = getMRI()->getType(Addr);
731   LLT CmpValTy = getMRI()->getType(CmpVal);
732   LLT NewValTy = getMRI()->getType(NewVal);
733   assert(OldValResTy.isScalar() && "invalid operand type");
734   assert(SuccessResTy.isScalar() && "invalid operand type");
735   assert(AddrTy.isPointer() && "invalid operand type");
736   assert(CmpValTy.isValid() && "invalid operand type");
737   assert(NewValTy.isValid() && "invalid operand type");
738   assert(OldValResTy == CmpValTy && "type mismatch");
739   assert(OldValResTy == NewValTy && "type mismatch");
740 #endif
741 
742   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
743       .addDef(OldValRes)
744       .addDef(SuccessRes)
745       .addUse(Addr)
746       .addUse(CmpVal)
747       .addUse(NewVal)
748       .addMemOperand(&MMO);
749 }
750 
751 MachineInstrBuilder
752 MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
753                                      Register CmpVal, Register NewVal,
754                                      MachineMemOperand &MMO) {
755 #ifndef NDEBUG
756   LLT OldValResTy = getMRI()->getType(OldValRes);
757   LLT AddrTy = getMRI()->getType(Addr);
758   LLT CmpValTy = getMRI()->getType(CmpVal);
759   LLT NewValTy = getMRI()->getType(NewVal);
760   assert(OldValResTy.isScalar() && "invalid operand type");
761   assert(AddrTy.isPointer() && "invalid operand type");
762   assert(CmpValTy.isValid() && "invalid operand type");
763   assert(NewValTy.isValid() && "invalid operand type");
764   assert(OldValResTy == CmpValTy && "type mismatch");
765   assert(OldValResTy == NewValTy && "type mismatch");
766 #endif
767 
768   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
769       .addDef(OldValRes)
770       .addUse(Addr)
771       .addUse(CmpVal)
772       .addUse(NewVal)
773       .addMemOperand(&MMO);
774 }
775 
776 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(
777   unsigned Opcode, const DstOp &OldValRes,
778   const SrcOp &Addr, const SrcOp &Val,
779   MachineMemOperand &MMO) {
780 
781 #ifndef NDEBUG
782   LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
783   LLT AddrTy = Addr.getLLTTy(*getMRI());
784   LLT ValTy = Val.getLLTTy(*getMRI());
785   assert(OldValResTy.isScalar() && "invalid operand type");
786   assert(AddrTy.isPointer() && "invalid operand type");
787   assert(ValTy.isValid() && "invalid operand type");
788   assert(OldValResTy == ValTy && "type mismatch");
789   assert(MMO.isAtomic() && "not atomic mem operand");
790 #endif
791 
792   auto MIB = buildInstr(Opcode);
793   OldValRes.addDefToMIB(*getMRI(), MIB);
794   Addr.addSrcToMIB(MIB);
795   Val.addSrcToMIB(MIB);
796   MIB.addMemOperand(&MMO);
797   return MIB;
798 }
799 
800 MachineInstrBuilder
801 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
802                                      Register Val, MachineMemOperand &MMO) {
803   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
804                         MMO);
805 }
806 MachineInstrBuilder
807 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
808                                     Register Val, MachineMemOperand &MMO) {
809   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
810                         MMO);
811 }
812 MachineInstrBuilder
813 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
814                                     Register Val, MachineMemOperand &MMO) {
815   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
816                         MMO);
817 }
818 MachineInstrBuilder
819 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
820                                     Register Val, MachineMemOperand &MMO) {
821   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
822                         MMO);
823 }
824 MachineInstrBuilder
825 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
826                                      Register Val, MachineMemOperand &MMO) {
827   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
828                         MMO);
829 }
830 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
831                                                        Register Addr,
832                                                        Register Val,
833                                                        MachineMemOperand &MMO) {
834   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
835                         MMO);
836 }
837 MachineInstrBuilder
838 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
839                                     Register Val, MachineMemOperand &MMO) {
840   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
841                         MMO);
842 }
843 MachineInstrBuilder
844 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
845                                     Register Val, MachineMemOperand &MMO) {
846   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
847                         MMO);
848 }
849 MachineInstrBuilder
850 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
851                                     Register Val, MachineMemOperand &MMO) {
852   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
853                         MMO);
854 }
855 MachineInstrBuilder
856 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
857                                      Register Val, MachineMemOperand &MMO) {
858   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
859                         MMO);
860 }
861 MachineInstrBuilder
862 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
863                                      Register Val, MachineMemOperand &MMO) {
864   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
865                         MMO);
866 }
867 
868 MachineInstrBuilder
869 MachineIRBuilder::buildAtomicRMWFAdd(
870   const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
871   MachineMemOperand &MMO) {
872   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
873                         MMO);
874 }
875 
876 MachineInstrBuilder
877 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
878                                      MachineMemOperand &MMO) {
879   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
880                         MMO);
881 }
882 
883 MachineInstrBuilder
884 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
885   return buildInstr(TargetOpcode::G_FENCE)
886     .addImm(Ordering)
887     .addImm(Scope);
888 }
889 
890 MachineInstrBuilder
891 MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
892 #ifndef NDEBUG
893   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
894 #endif
895 
896   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
897 }
898 
899 void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
900                                         bool IsExtend) {
901 #ifndef NDEBUG
902   if (DstTy.isVector()) {
903     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
904     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
905            "different number of elements in a trunc/ext");
906   } else
907     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
908 
909   if (IsExtend)
910     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
911            "invalid narrowing extend");
912   else
913     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
914            "invalid widening trunc");
915 #endif
916 }
917 
918 void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
919                                         const LLT Op0Ty, const LLT Op1Ty) {
920 #ifndef NDEBUG
921   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
922          "invalid operand type");
923   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
924   if (ResTy.isScalar() || ResTy.isPointer())
925     assert(TstTy.isScalar() && "type mismatch");
926   else
927     assert((TstTy.isScalar() ||
928             (TstTy.isVector() &&
929              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
930            "type mismatch");
931 #endif
932 }
933 
934 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
935                                                  ArrayRef<DstOp> DstOps,
936                                                  ArrayRef<SrcOp> SrcOps,
937                                                  Optional<unsigned> Flags) {
938   switch (Opc) {
939   default:
940     break;
941   case TargetOpcode::G_SELECT: {
942     assert(DstOps.size() == 1 && "Invalid select");
943     assert(SrcOps.size() == 3 && "Invalid select");
944     validateSelectOp(
945         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
946         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
947     break;
948   }
949   case TargetOpcode::G_ADD:
950   case TargetOpcode::G_AND:
951   case TargetOpcode::G_MUL:
952   case TargetOpcode::G_OR:
953   case TargetOpcode::G_SUB:
954   case TargetOpcode::G_XOR:
955   case TargetOpcode::G_UDIV:
956   case TargetOpcode::G_SDIV:
957   case TargetOpcode::G_UREM:
958   case TargetOpcode::G_SREM:
959   case TargetOpcode::G_SMIN:
960   case TargetOpcode::G_SMAX:
961   case TargetOpcode::G_UMIN:
962   case TargetOpcode::G_UMAX: {
963     // All these are binary ops.
964     assert(DstOps.size() == 1 && "Invalid Dst");
965     assert(SrcOps.size() == 2 && "Invalid Srcs");
966     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
967                      SrcOps[0].getLLTTy(*getMRI()),
968                      SrcOps[1].getLLTTy(*getMRI()));
969     break;
970   }
971   case TargetOpcode::G_SHL:
972   case TargetOpcode::G_ASHR:
973   case TargetOpcode::G_LSHR: {
974     assert(DstOps.size() == 1 && "Invalid Dst");
975     assert(SrcOps.size() == 2 && "Invalid Srcs");
976     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
977                     SrcOps[0].getLLTTy(*getMRI()),
978                     SrcOps[1].getLLTTy(*getMRI()));
979     break;
980   }
981   case TargetOpcode::G_SEXT:
982   case TargetOpcode::G_ZEXT:
983   case TargetOpcode::G_ANYEXT:
984     assert(DstOps.size() == 1 && "Invalid Dst");
985     assert(SrcOps.size() == 1 && "Invalid Srcs");
986     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
987                      SrcOps[0].getLLTTy(*getMRI()), true);
988     break;
989   case TargetOpcode::G_TRUNC:
990   case TargetOpcode::G_FPTRUNC: {
991     assert(DstOps.size() == 1 && "Invalid Dst");
992     assert(SrcOps.size() == 1 && "Invalid Srcs");
993     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
994                      SrcOps[0].getLLTTy(*getMRI()), false);
995     break;
996   }
997   case TargetOpcode::G_BITCAST: {
998     assert(DstOps.size() == 1 && "Invalid Dst");
999     assert(SrcOps.size() == 1 && "Invalid Srcs");
1000     assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1001            SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
1002     break;
1003   }
1004   case TargetOpcode::COPY:
1005     assert(DstOps.size() == 1 && "Invalid Dst");
1006     // If the caller wants to add a subreg source it has to be done separately
1007     // so we may not have any SrcOps at this point yet.
1008     break;
1009   case TargetOpcode::G_FCMP:
1010   case TargetOpcode::G_ICMP: {
1011     assert(DstOps.size() == 1 && "Invalid Dst Operands");
1012     assert(SrcOps.size() == 3 && "Invalid Src Operands");
1013     // For F/ICMP, the first src operand is the predicate, followed by
1014     // the two comparands.
1015     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1016            "Expecting predicate");
1017     assert([&]() -> bool {
1018       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1019       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1020                                          : CmpInst::isFPPredicate(Pred);
1021     }() && "Invalid predicate");
1022     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1023            "Type mismatch");
1024     assert([&]() -> bool {
1025       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1026       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1027       if (Op0Ty.isScalar() || Op0Ty.isPointer())
1028         return DstTy.isScalar();
1029       else
1030         return DstTy.isVector() &&
1031                DstTy.getNumElements() == Op0Ty.getNumElements();
1032     }() && "Type Mismatch");
1033     break;
1034   }
1035   case TargetOpcode::G_UNMERGE_VALUES: {
1036     assert(!DstOps.empty() && "Invalid trivial sequence");
1037     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1038     assert(std::all_of(DstOps.begin(), DstOps.end(),
1039                        [&, this](const DstOp &Op) {
1040                          return Op.getLLTTy(*getMRI()) ==
1041                                 DstOps[0].getLLTTy(*getMRI());
1042                        }) &&
1043            "type mismatch in output list");
1044     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1045                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1046            "input operands do not cover output register");
1047     break;
1048   }
1049   case TargetOpcode::G_MERGE_VALUES: {
1050     assert(!SrcOps.empty() && "invalid trivial sequence");
1051     assert(DstOps.size() == 1 && "Invalid Dst");
1052     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1053                        [&, this](const SrcOp &Op) {
1054                          return Op.getLLTTy(*getMRI()) ==
1055                                 SrcOps[0].getLLTTy(*getMRI());
1056                        }) &&
1057            "type mismatch in input list");
1058     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1059                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1060            "input operands do not cover output register");
1061     if (SrcOps.size() == 1)
1062       return buildCast(DstOps[0], SrcOps[0]);
1063     if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
1064       if (SrcOps[0].getLLTTy(*getMRI()).isVector())
1065         return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1066       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1067     }
1068     break;
1069   }
1070   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1071     assert(DstOps.size() == 1 && "Invalid Dst size");
1072     assert(SrcOps.size() == 2 && "Invalid Src size");
1073     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1074     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1075             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1076            "Invalid operand type");
1077     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1078     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1079                DstOps[0].getLLTTy(*getMRI()) &&
1080            "Type mismatch");
1081     break;
1082   }
1083   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1084     assert(DstOps.size() == 1 && "Invalid dst size");
1085     assert(SrcOps.size() == 3 && "Invalid src size");
1086     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1087            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1088     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1089                SrcOps[1].getLLTTy(*getMRI()) &&
1090            "Type mismatch");
1091     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1092     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1093                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1094            "Type mismatch");
1095     break;
1096   }
1097   case TargetOpcode::G_BUILD_VECTOR: {
1098     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1099            "Must have at least 2 operands");
1100     assert(DstOps.size() == 1 && "Invalid DstOps");
1101     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1102            "Res type must be a vector");
1103     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1104                        [&, this](const SrcOp &Op) {
1105                          return Op.getLLTTy(*getMRI()) ==
1106                                 SrcOps[0].getLLTTy(*getMRI());
1107                        }) &&
1108            "type mismatch in input list");
1109     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1110                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1111            "input scalars do not exactly cover the output vector register");
1112     break;
1113   }
1114   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1115     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1116            "Must have at least 2 operands");
1117     assert(DstOps.size() == 1 && "Invalid DstOps");
1118     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1119            "Res type must be a vector");
1120     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1121                        [&, this](const SrcOp &Op) {
1122                          return Op.getLLTTy(*getMRI()) ==
1123                                 SrcOps[0].getLLTTy(*getMRI());
1124                        }) &&
1125            "type mismatch in input list");
1126     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1127         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1128       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1129     break;
1130   }
1131   case TargetOpcode::G_CONCAT_VECTORS: {
1132     assert(DstOps.size() == 1 && "Invalid DstOps");
1133     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1134            "Must have at least 2 operands");
1135     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1136                        [&, this](const SrcOp &Op) {
1137                          return (Op.getLLTTy(*getMRI()).isVector() &&
1138                                  Op.getLLTTy(*getMRI()) ==
1139                                      SrcOps[0].getLLTTy(*getMRI()));
1140                        }) &&
1141            "type mismatch in input list");
1142     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1143                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1144            "input vectors do not exactly cover the output vector register");
1145     break;
1146   }
1147   case TargetOpcode::G_UADDE: {
1148     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1149     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1150     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1151     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1152            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1153            "Invalid operand");
1154     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1155     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1156            "type mismatch");
1157     break;
1158   }
1159   }
1160 
1161   auto MIB = buildInstr(Opc);
1162   for (const DstOp &Op : DstOps)
1163     Op.addDefToMIB(*getMRI(), MIB);
1164   for (const SrcOp &Op : SrcOps)
1165     Op.addSrcToMIB(MIB);
1166   if (Flags)
1167     MIB->setFlags(*Flags);
1168   return MIB;
1169 }
1170