1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/TargetInstrInfo.h"
17 #include "llvm/CodeGen/TargetLowering.h"
18 #include "llvm/CodeGen/TargetOpcodes.h"
19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
20 #include "llvm/IR/DebugInfoMetadata.h"
21 
22 using namespace llvm;
23 
24 void MachineIRBuilder::setMF(MachineFunction &MF) {
25   State.MF = &MF;
26   State.MBB = nullptr;
27   State.MRI = &MF.getRegInfo();
28   State.TII = MF.getSubtarget().getInstrInfo();
29   State.DL = DebugLoc();
30   State.II = MachineBasicBlock::iterator();
31   State.Observer = nullptr;
32 }
33 
34 //------------------------------------------------------------------------------
35 // Build instruction variants.
36 //------------------------------------------------------------------------------
37 
38 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
39   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
40   return MIB;
41 }
42 
43 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
44   getMBB().insert(getInsertPt(), MIB);
45   recordInsertion(MIB);
46   return MIB;
47 }
48 
49 MachineInstrBuilder
50 MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable,
51                                       const MDNode *Expr) {
52   assert(isa<DILocalVariable>(Variable) && "not a variable");
53   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
54   assert(
55       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
56       "Expected inlined-at fields to agree");
57   return insertInstr(BuildMI(getMF(), getDL(),
58                              getTII().get(TargetOpcode::DBG_VALUE),
59                              /*IsIndirect*/ false, Reg, Variable, Expr));
60 }
61 
62 MachineInstrBuilder
63 MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable,
64                                         const MDNode *Expr) {
65   assert(isa<DILocalVariable>(Variable) && "not a variable");
66   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
67   assert(
68       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
69       "Expected inlined-at fields to agree");
70   return insertInstr(BuildMI(getMF(), getDL(),
71                              getTII().get(TargetOpcode::DBG_VALUE),
72                              /*IsIndirect*/ true, Reg, Variable, Expr));
73 }
74 
75 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
76                                                       const MDNode *Variable,
77                                                       const MDNode *Expr) {
78   assert(isa<DILocalVariable>(Variable) && "not a variable");
79   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
80   assert(
81       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
82       "Expected inlined-at fields to agree");
83   return buildInstr(TargetOpcode::DBG_VALUE)
84       .addFrameIndex(FI)
85       .addImm(0)
86       .addMetadata(Variable)
87       .addMetadata(Expr);
88 }
89 
90 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
91                                                          const MDNode *Variable,
92                                                          const MDNode *Expr) {
93   assert(isa<DILocalVariable>(Variable) && "not a variable");
94   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
95   assert(
96       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
97       "Expected inlined-at fields to agree");
98   auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE);
99   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
100     if (CI->getBitWidth() > 64)
101       MIB.addCImm(CI);
102     else
103       MIB.addImm(CI->getZExtValue());
104   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
105     MIB.addFPImm(CFP);
106   } else {
107     // Insert $noreg if we didn't find a usable constant and had to drop it.
108     MIB.addReg(Register());
109   }
110 
111   MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
112   return insertInstr(MIB);
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
116   assert(isa<DILabel>(Label) && "not a label");
117   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
118          "Expected inlined-at fields to agree");
119   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
120 
121   return MIB.addMetadata(Label);
122 }
123 
124 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res,
125                                                          const SrcOp &Size,
126                                                          Align Alignment) {
127   assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
128   auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
129   Res.addDefToMIB(*getMRI(), MIB);
130   Size.addSrcToMIB(MIB);
131   MIB.addImm(Alignment.value());
132   return MIB;
133 }
134 
135 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res,
136                                                       int Idx) {
137   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
138   auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
139   Res.addDefToMIB(*getMRI(), MIB);
140   MIB.addFrameIndex(Idx);
141   return MIB;
142 }
143 
144 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res,
145                                                        const GlobalValue *GV) {
146   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
147   assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
148              GV->getType()->getAddressSpace() &&
149          "address space mismatch");
150 
151   auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
152   Res.addDefToMIB(*getMRI(), MIB);
153   MIB.addGlobalAddress(GV);
154   return MIB;
155 }
156 
157 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
158                                                      unsigned JTI) {
159   return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
160       .addJumpTableIndex(JTI);
161 }
162 
163 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) {
164   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
165   assert((Res == Op0) && "type mismatch");
166 }
167 
168 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
169                                         const LLT Op1) {
170   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
171   assert((Res == Op0 && Res == Op1) && "type mismatch");
172 }
173 
174 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
175                                        const LLT Op1) {
176   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
177   assert((Res == Op0) && "type mismatch");
178 }
179 
180 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res,
181                                                   const SrcOp &Op0,
182                                                   const SrcOp &Op1) {
183   assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
184          Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
185   assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
186 
187   return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
188 }
189 
190 Optional<MachineInstrBuilder>
191 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
192                                     const LLT ValueTy, uint64_t Value) {
193   assert(Res == 0 && "Res is a result argument");
194   assert(ValueTy.isScalar()  && "invalid offset type");
195 
196   if (Value == 0) {
197     Res = Op0;
198     return None;
199   }
200 
201   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
202   auto Cst = buildConstant(ValueTy, Value);
203   return buildPtrAdd(Res, Op0, Cst.getReg(0));
204 }
205 
206 MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res,
207                                                           const SrcOp &Op0,
208                                                           uint32_t NumBits) {
209   LLT PtrTy = Res.getLLTTy(*getMRI());
210   LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
211   Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
212   buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
213   return buildPtrMask(Res, Op0, MaskReg);
214 }
215 
216 MachineInstrBuilder
217 MachineIRBuilder::buildPadVectorWithUndefElements(const DstOp &Res,
218                                                   const SrcOp &Op0) {
219   LLT ResTy = Res.getLLTTy(*getMRI());
220   LLT Op0Ty = Op0.getLLTTy(*getMRI());
221 
222   assert((ResTy.isVector() && Op0Ty.isVector()) && "Non vector type");
223   assert((ResTy.getElementType() == Op0Ty.getElementType()) &&
224          "Different vector element types");
225   assert((ResTy.getNumElements() > Op0Ty.getNumElements()) &&
226          "Op0 has more elements");
227 
228   auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
229   SmallVector<Register, 8> Regs;
230   for (auto Op : Unmerge.getInstr()->defs())
231     Regs.push_back(Op.getReg());
232   Register Undef = buildUndef(Op0Ty.getElementType()).getReg(0);
233   unsigned NumberOfPadElts = ResTy.getNumElements() - Regs.size();
234   for (unsigned i = 0; i < NumberOfPadElts; ++i)
235     Regs.push_back(Undef);
236   return buildMerge(Res, Regs);
237 }
238 
239 MachineInstrBuilder
240 MachineIRBuilder::buildDeleteTrailingVectorElements(const DstOp &Res,
241                                                     const SrcOp &Op0) {
242   LLT ResTy = Res.getLLTTy(*getMRI());
243   LLT Op0Ty = Op0.getLLTTy(*getMRI());
244 
245   assert((ResTy.isVector() && Op0Ty.isVector()) && "Non vector type");
246   assert((ResTy.getElementType() == Op0Ty.getElementType()) &&
247          "Different vector element types");
248   assert((ResTy.getNumElements() < Op0Ty.getNumElements()) &&
249          "Op0 has fewer elements");
250 
251   SmallVector<Register, 8> Regs;
252   auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
253   for (unsigned i = 0; i < ResTy.getNumElements(); ++i)
254     Regs.push_back(Unmerge.getReg(i));
255   return buildMerge(Res, Regs);
256 }
257 
258 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
259   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
260 }
261 
262 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
263   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
264   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
265 }
266 
267 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
268                                                 unsigned JTI,
269                                                 Register IndexReg) {
270   assert(getMRI()->getType(TablePtr).isPointer() &&
271          "Table reg must be a pointer");
272   return buildInstr(TargetOpcode::G_BRJT)
273       .addUse(TablePtr)
274       .addJumpTableIndex(JTI)
275       .addUse(IndexReg);
276 }
277 
278 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
279                                                 const SrcOp &Op) {
280   return buildInstr(TargetOpcode::COPY, Res, Op);
281 }
282 
283 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
284                                                     const ConstantInt &Val) {
285   LLT Ty = Res.getLLTTy(*getMRI());
286   LLT EltTy = Ty.getScalarType();
287   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
288          "creating constant with the wrong size");
289 
290   if (Ty.isVector()) {
291     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
292     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
293     .addCImm(&Val);
294     return buildSplatVector(Res, Const);
295   }
296 
297   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
298   Const->setDebugLoc(DebugLoc());
299   Res.addDefToMIB(*getMRI(), Const);
300   Const.addCImm(&Val);
301   return Const;
302 }
303 
304 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
305                                                     int64_t Val) {
306   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
307                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
308   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
309   return buildConstant(Res, *CI);
310 }
311 
312 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
313                                                      const ConstantFP &Val) {
314   LLT Ty = Res.getLLTTy(*getMRI());
315   LLT EltTy = Ty.getScalarType();
316 
317   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
318          == EltTy.getSizeInBits() &&
319          "creating fconstant with the wrong size");
320 
321   assert(!Ty.isPointer() && "invalid operand type");
322 
323   if (Ty.isVector()) {
324     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
325     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
326     .addFPImm(&Val);
327 
328     return buildSplatVector(Res, Const);
329   }
330 
331   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
332   Const->setDebugLoc(DebugLoc());
333   Res.addDefToMIB(*getMRI(), Const);
334   Const.addFPImm(&Val);
335   return Const;
336 }
337 
338 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
339                                                     const APInt &Val) {
340   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
341   return buildConstant(Res, *CI);
342 }
343 
344 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
345                                                      double Val) {
346   LLT DstTy = Res.getLLTTy(*getMRI());
347   auto &Ctx = getMF().getFunction().getContext();
348   auto *CFP =
349       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
350   return buildFConstant(Res, *CFP);
351 }
352 
353 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
354                                                      const APFloat &Val) {
355   auto &Ctx = getMF().getFunction().getContext();
356   auto *CFP = ConstantFP::get(Ctx, Val);
357   return buildFConstant(Res, *CFP);
358 }
359 
360 MachineInstrBuilder MachineIRBuilder::buildBrCond(const SrcOp &Tst,
361                                                   MachineBasicBlock &Dest) {
362   assert(Tst.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
363 
364   auto MIB = buildInstr(TargetOpcode::G_BRCOND);
365   Tst.addSrcToMIB(MIB);
366   MIB.addMBB(&Dest);
367   return MIB;
368 }
369 
370 MachineInstrBuilder
371 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr,
372                             MachinePointerInfo PtrInfo, Align Alignment,
373                             MachineMemOperand::Flags MMOFlags,
374                             const AAMDNodes &AAInfo) {
375   MMOFlags |= MachineMemOperand::MOLoad;
376   assert((MMOFlags & MachineMemOperand::MOStore) == 0);
377 
378   LLT Ty = Dst.getLLTTy(*getMRI());
379   MachineMemOperand *MMO =
380       getMF().getMachineMemOperand(PtrInfo, MMOFlags, Ty, Alignment, AAInfo);
381   return buildLoad(Dst, Addr, *MMO);
382 }
383 
384 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
385                                                      const DstOp &Res,
386                                                      const SrcOp &Addr,
387                                                      MachineMemOperand &MMO) {
388   assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
389   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
390 
391   auto MIB = buildInstr(Opcode);
392   Res.addDefToMIB(*getMRI(), MIB);
393   Addr.addSrcToMIB(MIB);
394   MIB.addMemOperand(&MMO);
395   return MIB;
396 }
397 
398 MachineInstrBuilder MachineIRBuilder::buildLoadFromOffset(
399   const DstOp &Dst, const SrcOp &BasePtr,
400   MachineMemOperand &BaseMMO, int64_t Offset) {
401   LLT LoadTy = Dst.getLLTTy(*getMRI());
402   MachineMemOperand *OffsetMMO =
403       getMF().getMachineMemOperand(&BaseMMO, Offset, LoadTy);
404 
405   if (Offset == 0) // This may be a size or type changing load.
406     return buildLoad(Dst, BasePtr, *OffsetMMO);
407 
408   LLT PtrTy = BasePtr.getLLTTy(*getMRI());
409   LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
410   auto ConstOffset = buildConstant(OffsetTy, Offset);
411   auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
412   return buildLoad(Dst, Ptr, *OffsetMMO);
413 }
414 
415 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
416                                                  const SrcOp &Addr,
417                                                  MachineMemOperand &MMO) {
418   assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
419   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
420 
421   auto MIB = buildInstr(TargetOpcode::G_STORE);
422   Val.addSrcToMIB(MIB);
423   Addr.addSrcToMIB(MIB);
424   MIB.addMemOperand(&MMO);
425   return MIB;
426 }
427 
428 MachineInstrBuilder
429 MachineIRBuilder::buildStore(const SrcOp &Val, const SrcOp &Addr,
430                              MachinePointerInfo PtrInfo, Align Alignment,
431                              MachineMemOperand::Flags MMOFlags,
432                              const AAMDNodes &AAInfo) {
433   MMOFlags |= MachineMemOperand::MOStore;
434   assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
435 
436   LLT Ty = Val.getLLTTy(*getMRI());
437   MachineMemOperand *MMO =
438       getMF().getMachineMemOperand(PtrInfo, MMOFlags, Ty, Alignment, AAInfo);
439   return buildStore(Val, Addr, *MMO);
440 }
441 
442 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
443                                                   const SrcOp &Op) {
444   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
445 }
446 
447 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
448                                                 const SrcOp &Op) {
449   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
450 }
451 
452 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
453                                                 const SrcOp &Op) {
454   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
455 }
456 
457 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
458   const auto *TLI = getMF().getSubtarget().getTargetLowering();
459   switch (TLI->getBooleanContents(IsVec, IsFP)) {
460   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
461     return TargetOpcode::G_SEXT;
462   case TargetLoweringBase::ZeroOrOneBooleanContent:
463     return TargetOpcode::G_ZEXT;
464   default:
465     return TargetOpcode::G_ANYEXT;
466   }
467 }
468 
469 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
470                                                    const SrcOp &Op,
471                                                    bool IsFP) {
472   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
473   return buildInstr(ExtOp, Res, Op);
474 }
475 
476 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
477                                                       const DstOp &Res,
478                                                       const SrcOp &Op) {
479   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
480           TargetOpcode::G_SEXT == ExtOpc) &&
481          "Expecting Extending Opc");
482   assert(Res.getLLTTy(*getMRI()).isScalar() ||
483          Res.getLLTTy(*getMRI()).isVector());
484   assert(Res.getLLTTy(*getMRI()).isScalar() ==
485          Op.getLLTTy(*getMRI()).isScalar());
486 
487   unsigned Opcode = TargetOpcode::COPY;
488   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
489       Op.getLLTTy(*getMRI()).getSizeInBits())
490     Opcode = ExtOpc;
491   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
492            Op.getLLTTy(*getMRI()).getSizeInBits())
493     Opcode = TargetOpcode::G_TRUNC;
494   else
495     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
496 
497   return buildInstr(Opcode, Res, Op);
498 }
499 
500 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
501                                                        const SrcOp &Op) {
502   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
503 }
504 
505 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
506                                                        const SrcOp &Op) {
507   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
508 }
509 
510 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
511                                                          const SrcOp &Op) {
512   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
513 }
514 
515 MachineInstrBuilder MachineIRBuilder::buildZExtInReg(const DstOp &Res,
516                                                      const SrcOp &Op,
517                                                      int64_t ImmOp) {
518   LLT ResTy = Res.getLLTTy(*getMRI());
519   auto Mask = buildConstant(
520       ResTy, APInt::getLowBitsSet(ResTy.getScalarSizeInBits(), ImmOp));
521   return buildAnd(Res, Op, Mask);
522 }
523 
524 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
525                                                 const SrcOp &Src) {
526   LLT SrcTy = Src.getLLTTy(*getMRI());
527   LLT DstTy = Dst.getLLTTy(*getMRI());
528   if (SrcTy == DstTy)
529     return buildCopy(Dst, Src);
530 
531   unsigned Opcode;
532   if (SrcTy.isPointer() && DstTy.isScalar())
533     Opcode = TargetOpcode::G_PTRTOINT;
534   else if (DstTy.isPointer() && SrcTy.isScalar())
535     Opcode = TargetOpcode::G_INTTOPTR;
536   else {
537     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
538     Opcode = TargetOpcode::G_BITCAST;
539   }
540 
541   return buildInstr(Opcode, Dst, Src);
542 }
543 
544 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
545                                                    const SrcOp &Src,
546                                                    uint64_t Index) {
547   LLT SrcTy = Src.getLLTTy(*getMRI());
548   LLT DstTy = Dst.getLLTTy(*getMRI());
549 
550 #ifndef NDEBUG
551   assert(SrcTy.isValid() && "invalid operand type");
552   assert(DstTy.isValid() && "invalid operand type");
553   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
554          "extracting off end of register");
555 #endif
556 
557   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
558     assert(Index == 0 && "insertion past the end of a register");
559     return buildCast(Dst, Src);
560   }
561 
562   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
563   Dst.addDefToMIB(*getMRI(), Extract);
564   Src.addSrcToMIB(Extract);
565   Extract.addImm(Index);
566   return Extract;
567 }
568 
569 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
570                                      ArrayRef<uint64_t> Indices) {
571 #ifndef NDEBUG
572   assert(Ops.size() == Indices.size() && "incompatible args");
573   assert(!Ops.empty() && "invalid trivial sequence");
574   assert(llvm::is_sorted(Indices) &&
575          "sequence offsets must be in ascending order");
576 
577   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
578   for (auto Op : Ops)
579     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
580 #endif
581 
582   LLT ResTy = getMRI()->getType(Res);
583   LLT OpTy = getMRI()->getType(Ops[0]);
584   unsigned OpSize = OpTy.getSizeInBits();
585   bool MaybeMerge = true;
586   for (unsigned i = 0; i < Ops.size(); ++i) {
587     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
588       MaybeMerge = false;
589       break;
590     }
591   }
592 
593   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
594     buildMerge(Res, Ops);
595     return;
596   }
597 
598   Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
599   buildUndef(ResIn);
600 
601   for (unsigned i = 0; i < Ops.size(); ++i) {
602     Register ResOut = i + 1 == Ops.size()
603                           ? Res
604                           : getMRI()->createGenericVirtualRegister(ResTy);
605     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
606     ResIn = ResOut;
607   }
608 }
609 
610 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
611   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
612 }
613 
614 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
615                                                  ArrayRef<Register> Ops) {
616   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
617   // we need some temporary storage for the DstOp objects. Here we use a
618   // sufficiently large SmallVector to not go through the heap.
619   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
620   assert(TmpVec.size() > 1);
621   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
622 }
623 
624 MachineInstrBuilder
625 MachineIRBuilder::buildMerge(const DstOp &Res,
626                              std::initializer_list<SrcOp> Ops) {
627   assert(Ops.size() > 1);
628   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
629 }
630 
631 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
632                                                    const SrcOp &Op) {
633   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
634   // we need some temporary storage for the DstOp objects. Here we use a
635   // sufficiently large SmallVector to not go through the heap.
636   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
637   assert(TmpVec.size() > 1);
638   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
639 }
640 
641 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
642                                                    const SrcOp &Op) {
643   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
644   SmallVector<DstOp, 8> TmpVec(NumReg, Res);
645   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
646 }
647 
648 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
649                                                    const SrcOp &Op) {
650   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
651   // we need some temporary storage for the DstOp objects. Here we use a
652   // sufficiently large SmallVector to not go through the heap.
653   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
654   assert(TmpVec.size() > 1);
655   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
656 }
657 
658 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
659                                                        ArrayRef<Register> Ops) {
660   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
661   // we need some temporary storage for the DstOp objects. Here we use a
662   // sufficiently large SmallVector to not go through the heap.
663   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
664   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
665 }
666 
667 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
668                                                        const SrcOp &Src) {
669   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
670   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
671 }
672 
673 MachineInstrBuilder
674 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
675                                         ArrayRef<Register> Ops) {
676   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
677   // we need some temporary storage for the DstOp objects. Here we use a
678   // sufficiently large SmallVector to not go through the heap.
679   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
680   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
681 }
682 
683 MachineInstrBuilder MachineIRBuilder::buildShuffleSplat(const DstOp &Res,
684                                                         const SrcOp &Src) {
685   LLT DstTy = Res.getLLTTy(*getMRI());
686   assert(Src.getLLTTy(*getMRI()) == DstTy.getElementType() &&
687          "Expected Src to match Dst elt ty");
688   auto UndefVec = buildUndef(DstTy);
689   auto Zero = buildConstant(LLT::scalar(64), 0);
690   auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero);
691   SmallVector<int, 16> ZeroMask(DstTy.getNumElements());
692   return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
693 }
694 
695 MachineInstrBuilder MachineIRBuilder::buildShuffleVector(const DstOp &Res,
696                                                          const SrcOp &Src1,
697                                                          const SrcOp &Src2,
698                                                          ArrayRef<int> Mask) {
699   LLT DstTy = Res.getLLTTy(*getMRI());
700   LLT Src1Ty = Src1.getLLTTy(*getMRI());
701   LLT Src2Ty = Src2.getLLTTy(*getMRI());
702   assert((size_t)(Src1Ty.getNumElements() + Src2Ty.getNumElements()) >=
703          Mask.size());
704   assert(DstTy.getElementType() == Src1Ty.getElementType() &&
705          DstTy.getElementType() == Src2Ty.getElementType());
706   (void)DstTy;
707   (void)Src1Ty;
708   (void)Src2Ty;
709   ArrayRef<int> MaskAlloc = getMF().allocateShuffleMask(Mask);
710   return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})
711       .addShuffleMask(MaskAlloc);
712 }
713 
714 MachineInstrBuilder
715 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
716   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
717   // we need some temporary storage for the DstOp objects. Here we use a
718   // sufficiently large SmallVector to not go through the heap.
719   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
720   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
721 }
722 
723 MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
724                                                   const SrcOp &Src,
725                                                   const SrcOp &Op,
726                                                   unsigned Index) {
727   assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
728              Res.getLLTTy(*getMRI()).getSizeInBits() &&
729          "insertion past the end of a register");
730 
731   if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
732       Op.getLLTTy(*getMRI()).getSizeInBits()) {
733     return buildCast(Res, Op);
734   }
735 
736   return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
737 }
738 
739 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
740                                                      ArrayRef<Register> ResultRegs,
741                                                      bool HasSideEffects) {
742   auto MIB =
743       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
744                                 : TargetOpcode::G_INTRINSIC);
745   for (unsigned ResultReg : ResultRegs)
746     MIB.addDef(ResultReg);
747   MIB.addIntrinsicID(ID);
748   return MIB;
749 }
750 
751 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
752                                                      ArrayRef<DstOp> Results,
753                                                      bool HasSideEffects) {
754   auto MIB =
755       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
756                                 : TargetOpcode::G_INTRINSIC);
757   for (DstOp Result : Results)
758     Result.addDefToMIB(*getMRI(), MIB);
759   MIB.addIntrinsicID(ID);
760   return MIB;
761 }
762 
763 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
764                                                  const SrcOp &Op) {
765   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
766 }
767 
768 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
769                                                    const SrcOp &Op,
770                                                    Optional<unsigned> Flags) {
771   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
772 }
773 
774 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
775                                                 const DstOp &Res,
776                                                 const SrcOp &Op0,
777                                                 const SrcOp &Op1) {
778   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
779 }
780 
781 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
782                                                 const DstOp &Res,
783                                                 const SrcOp &Op0,
784                                                 const SrcOp &Op1,
785                                                 Optional<unsigned> Flags) {
786 
787   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
788 }
789 
790 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
791                                                   const SrcOp &Tst,
792                                                   const SrcOp &Op0,
793                                                   const SrcOp &Op1,
794                                                   Optional<unsigned> Flags) {
795 
796   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
797 }
798 
799 MachineInstrBuilder
800 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
801                                            const SrcOp &Elt, const SrcOp &Idx) {
802   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
803 }
804 
805 MachineInstrBuilder
806 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
807                                             const SrcOp &Idx) {
808   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
809 }
810 
811 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
812     Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
813     Register NewVal, MachineMemOperand &MMO) {
814 #ifndef NDEBUG
815   LLT OldValResTy = getMRI()->getType(OldValRes);
816   LLT SuccessResTy = getMRI()->getType(SuccessRes);
817   LLT AddrTy = getMRI()->getType(Addr);
818   LLT CmpValTy = getMRI()->getType(CmpVal);
819   LLT NewValTy = getMRI()->getType(NewVal);
820   assert(OldValResTy.isScalar() && "invalid operand type");
821   assert(SuccessResTy.isScalar() && "invalid operand type");
822   assert(AddrTy.isPointer() && "invalid operand type");
823   assert(CmpValTy.isValid() && "invalid operand type");
824   assert(NewValTy.isValid() && "invalid operand type");
825   assert(OldValResTy == CmpValTy && "type mismatch");
826   assert(OldValResTy == NewValTy && "type mismatch");
827 #endif
828 
829   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
830       .addDef(OldValRes)
831       .addDef(SuccessRes)
832       .addUse(Addr)
833       .addUse(CmpVal)
834       .addUse(NewVal)
835       .addMemOperand(&MMO);
836 }
837 
838 MachineInstrBuilder
839 MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
840                                      Register CmpVal, Register NewVal,
841                                      MachineMemOperand &MMO) {
842 #ifndef NDEBUG
843   LLT OldValResTy = getMRI()->getType(OldValRes);
844   LLT AddrTy = getMRI()->getType(Addr);
845   LLT CmpValTy = getMRI()->getType(CmpVal);
846   LLT NewValTy = getMRI()->getType(NewVal);
847   assert(OldValResTy.isScalar() && "invalid operand type");
848   assert(AddrTy.isPointer() && "invalid operand type");
849   assert(CmpValTy.isValid() && "invalid operand type");
850   assert(NewValTy.isValid() && "invalid operand type");
851   assert(OldValResTy == CmpValTy && "type mismatch");
852   assert(OldValResTy == NewValTy && "type mismatch");
853 #endif
854 
855   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
856       .addDef(OldValRes)
857       .addUse(Addr)
858       .addUse(CmpVal)
859       .addUse(NewVal)
860       .addMemOperand(&MMO);
861 }
862 
863 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(
864   unsigned Opcode, const DstOp &OldValRes,
865   const SrcOp &Addr, const SrcOp &Val,
866   MachineMemOperand &MMO) {
867 
868 #ifndef NDEBUG
869   LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
870   LLT AddrTy = Addr.getLLTTy(*getMRI());
871   LLT ValTy = Val.getLLTTy(*getMRI());
872   assert(OldValResTy.isScalar() && "invalid operand type");
873   assert(AddrTy.isPointer() && "invalid operand type");
874   assert(ValTy.isValid() && "invalid operand type");
875   assert(OldValResTy == ValTy && "type mismatch");
876   assert(MMO.isAtomic() && "not atomic mem operand");
877 #endif
878 
879   auto MIB = buildInstr(Opcode);
880   OldValRes.addDefToMIB(*getMRI(), MIB);
881   Addr.addSrcToMIB(MIB);
882   Val.addSrcToMIB(MIB);
883   MIB.addMemOperand(&MMO);
884   return MIB;
885 }
886 
887 MachineInstrBuilder
888 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
889                                      Register Val, MachineMemOperand &MMO) {
890   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
891                         MMO);
892 }
893 MachineInstrBuilder
894 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
895                                     Register Val, MachineMemOperand &MMO) {
896   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
897                         MMO);
898 }
899 MachineInstrBuilder
900 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
901                                     Register Val, MachineMemOperand &MMO) {
902   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
903                         MMO);
904 }
905 MachineInstrBuilder
906 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
907                                     Register Val, MachineMemOperand &MMO) {
908   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
909                         MMO);
910 }
911 MachineInstrBuilder
912 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
913                                      Register Val, MachineMemOperand &MMO) {
914   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
915                         MMO);
916 }
917 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
918                                                        Register Addr,
919                                                        Register Val,
920                                                        MachineMemOperand &MMO) {
921   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
922                         MMO);
923 }
924 MachineInstrBuilder
925 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
926                                     Register Val, MachineMemOperand &MMO) {
927   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
928                         MMO);
929 }
930 MachineInstrBuilder
931 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
932                                     Register Val, MachineMemOperand &MMO) {
933   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
934                         MMO);
935 }
936 MachineInstrBuilder
937 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
938                                     Register Val, MachineMemOperand &MMO) {
939   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
940                         MMO);
941 }
942 MachineInstrBuilder
943 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
944                                      Register Val, MachineMemOperand &MMO) {
945   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
946                         MMO);
947 }
948 MachineInstrBuilder
949 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
950                                      Register Val, MachineMemOperand &MMO) {
951   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
952                         MMO);
953 }
954 
955 MachineInstrBuilder
956 MachineIRBuilder::buildAtomicRMWFAdd(
957   const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
958   MachineMemOperand &MMO) {
959   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
960                         MMO);
961 }
962 
963 MachineInstrBuilder
964 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
965                                      MachineMemOperand &MMO) {
966   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
967                         MMO);
968 }
969 
970 MachineInstrBuilder
971 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
972   return buildInstr(TargetOpcode::G_FENCE)
973     .addImm(Ordering)
974     .addImm(Scope);
975 }
976 
977 MachineInstrBuilder
978 MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
979 #ifndef NDEBUG
980   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
981 #endif
982 
983   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
984 }
985 
986 void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
987                                         bool IsExtend) {
988 #ifndef NDEBUG
989   if (DstTy.isVector()) {
990     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
991     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
992            "different number of elements in a trunc/ext");
993   } else
994     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
995 
996   if (IsExtend)
997     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
998            "invalid narrowing extend");
999   else
1000     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
1001            "invalid widening trunc");
1002 #endif
1003 }
1004 
1005 void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
1006                                         const LLT Op0Ty, const LLT Op1Ty) {
1007 #ifndef NDEBUG
1008   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
1009          "invalid operand type");
1010   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
1011   if (ResTy.isScalar() || ResTy.isPointer())
1012     assert(TstTy.isScalar() && "type mismatch");
1013   else
1014     assert((TstTy.isScalar() ||
1015             (TstTy.isVector() &&
1016              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
1017            "type mismatch");
1018 #endif
1019 }
1020 
1021 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
1022                                                  ArrayRef<DstOp> DstOps,
1023                                                  ArrayRef<SrcOp> SrcOps,
1024                                                  Optional<unsigned> Flags) {
1025   switch (Opc) {
1026   default:
1027     break;
1028   case TargetOpcode::G_SELECT: {
1029     assert(DstOps.size() == 1 && "Invalid select");
1030     assert(SrcOps.size() == 3 && "Invalid select");
1031     validateSelectOp(
1032         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
1033         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
1034     break;
1035   }
1036   case TargetOpcode::G_FNEG:
1037   case TargetOpcode::G_ABS:
1038     // All these are unary ops.
1039     assert(DstOps.size() == 1 && "Invalid Dst");
1040     assert(SrcOps.size() == 1 && "Invalid Srcs");
1041     validateUnaryOp(DstOps[0].getLLTTy(*getMRI()),
1042                     SrcOps[0].getLLTTy(*getMRI()));
1043     break;
1044   case TargetOpcode::G_ADD:
1045   case TargetOpcode::G_AND:
1046   case TargetOpcode::G_MUL:
1047   case TargetOpcode::G_OR:
1048   case TargetOpcode::G_SUB:
1049   case TargetOpcode::G_XOR:
1050   case TargetOpcode::G_UDIV:
1051   case TargetOpcode::G_SDIV:
1052   case TargetOpcode::G_UREM:
1053   case TargetOpcode::G_SREM:
1054   case TargetOpcode::G_SMIN:
1055   case TargetOpcode::G_SMAX:
1056   case TargetOpcode::G_UMIN:
1057   case TargetOpcode::G_UMAX:
1058   case TargetOpcode::G_UADDSAT:
1059   case TargetOpcode::G_SADDSAT:
1060   case TargetOpcode::G_USUBSAT:
1061   case TargetOpcode::G_SSUBSAT: {
1062     // All these are binary ops.
1063     assert(DstOps.size() == 1 && "Invalid Dst");
1064     assert(SrcOps.size() == 2 && "Invalid Srcs");
1065     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
1066                      SrcOps[0].getLLTTy(*getMRI()),
1067                      SrcOps[1].getLLTTy(*getMRI()));
1068     break;
1069   }
1070   case TargetOpcode::G_SHL:
1071   case TargetOpcode::G_ASHR:
1072   case TargetOpcode::G_LSHR:
1073   case TargetOpcode::G_USHLSAT:
1074   case TargetOpcode::G_SSHLSAT: {
1075     assert(DstOps.size() == 1 && "Invalid Dst");
1076     assert(SrcOps.size() == 2 && "Invalid Srcs");
1077     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
1078                     SrcOps[0].getLLTTy(*getMRI()),
1079                     SrcOps[1].getLLTTy(*getMRI()));
1080     break;
1081   }
1082   case TargetOpcode::G_SEXT:
1083   case TargetOpcode::G_ZEXT:
1084   case TargetOpcode::G_ANYEXT:
1085     assert(DstOps.size() == 1 && "Invalid Dst");
1086     assert(SrcOps.size() == 1 && "Invalid Srcs");
1087     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1088                      SrcOps[0].getLLTTy(*getMRI()), true);
1089     break;
1090   case TargetOpcode::G_TRUNC:
1091   case TargetOpcode::G_FPTRUNC: {
1092     assert(DstOps.size() == 1 && "Invalid Dst");
1093     assert(SrcOps.size() == 1 && "Invalid Srcs");
1094     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1095                      SrcOps[0].getLLTTy(*getMRI()), false);
1096     break;
1097   }
1098   case TargetOpcode::G_BITCAST: {
1099     assert(DstOps.size() == 1 && "Invalid Dst");
1100     assert(SrcOps.size() == 1 && "Invalid Srcs");
1101     assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1102            SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
1103     break;
1104   }
1105   case TargetOpcode::COPY:
1106     assert(DstOps.size() == 1 && "Invalid Dst");
1107     // If the caller wants to add a subreg source it has to be done separately
1108     // so we may not have any SrcOps at this point yet.
1109     break;
1110   case TargetOpcode::G_FCMP:
1111   case TargetOpcode::G_ICMP: {
1112     assert(DstOps.size() == 1 && "Invalid Dst Operands");
1113     assert(SrcOps.size() == 3 && "Invalid Src Operands");
1114     // For F/ICMP, the first src operand is the predicate, followed by
1115     // the two comparands.
1116     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1117            "Expecting predicate");
1118     assert([&]() -> bool {
1119       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1120       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1121                                          : CmpInst::isFPPredicate(Pred);
1122     }() && "Invalid predicate");
1123     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1124            "Type mismatch");
1125     assert([&]() -> bool {
1126       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1127       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1128       if (Op0Ty.isScalar() || Op0Ty.isPointer())
1129         return DstTy.isScalar();
1130       else
1131         return DstTy.isVector() &&
1132                DstTy.getNumElements() == Op0Ty.getNumElements();
1133     }() && "Type Mismatch");
1134     break;
1135   }
1136   case TargetOpcode::G_UNMERGE_VALUES: {
1137     assert(!DstOps.empty() && "Invalid trivial sequence");
1138     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1139     assert(llvm::all_of(DstOps,
1140                         [&, this](const DstOp &Op) {
1141                           return Op.getLLTTy(*getMRI()) ==
1142                                  DstOps[0].getLLTTy(*getMRI());
1143                         }) &&
1144            "type mismatch in output list");
1145     assert((TypeSize::ScalarTy)DstOps.size() *
1146                    DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1147                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1148            "input operands do not cover output register");
1149     break;
1150   }
1151   case TargetOpcode::G_MERGE_VALUES: {
1152     assert(!SrcOps.empty() && "invalid trivial sequence");
1153     assert(DstOps.size() == 1 && "Invalid Dst");
1154     assert(llvm::all_of(SrcOps,
1155                         [&, this](const SrcOp &Op) {
1156                           return Op.getLLTTy(*getMRI()) ==
1157                                  SrcOps[0].getLLTTy(*getMRI());
1158                         }) &&
1159            "type mismatch in input list");
1160     assert((TypeSize::ScalarTy)SrcOps.size() *
1161                    SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1162                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1163            "input operands do not cover output register");
1164     if (SrcOps.size() == 1)
1165       return buildCast(DstOps[0], SrcOps[0]);
1166     if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
1167       if (SrcOps[0].getLLTTy(*getMRI()).isVector())
1168         return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1169       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1170     }
1171     break;
1172   }
1173   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1174     assert(DstOps.size() == 1 && "Invalid Dst size");
1175     assert(SrcOps.size() == 2 && "Invalid Src size");
1176     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1177     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1178             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1179            "Invalid operand type");
1180     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1181     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1182                DstOps[0].getLLTTy(*getMRI()) &&
1183            "Type mismatch");
1184     break;
1185   }
1186   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1187     assert(DstOps.size() == 1 && "Invalid dst size");
1188     assert(SrcOps.size() == 3 && "Invalid src size");
1189     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1190            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1191     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1192                SrcOps[1].getLLTTy(*getMRI()) &&
1193            "Type mismatch");
1194     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1195     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1196                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1197            "Type mismatch");
1198     break;
1199   }
1200   case TargetOpcode::G_BUILD_VECTOR: {
1201     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1202            "Must have at least 2 operands");
1203     assert(DstOps.size() == 1 && "Invalid DstOps");
1204     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1205            "Res type must be a vector");
1206     assert(llvm::all_of(SrcOps,
1207                         [&, this](const SrcOp &Op) {
1208                           return Op.getLLTTy(*getMRI()) ==
1209                                  SrcOps[0].getLLTTy(*getMRI());
1210                         }) &&
1211            "type mismatch in input list");
1212     assert((TypeSize::ScalarTy)SrcOps.size() *
1213                    SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1214                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1215            "input scalars do not exactly cover the output vector register");
1216     break;
1217   }
1218   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1219     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1220            "Must have at least 2 operands");
1221     assert(DstOps.size() == 1 && "Invalid DstOps");
1222     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1223            "Res type must be a vector");
1224     assert(llvm::all_of(SrcOps,
1225                         [&, this](const SrcOp &Op) {
1226                           return Op.getLLTTy(*getMRI()) ==
1227                                  SrcOps[0].getLLTTy(*getMRI());
1228                         }) &&
1229            "type mismatch in input list");
1230     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1231         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1232       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1233     break;
1234   }
1235   case TargetOpcode::G_CONCAT_VECTORS: {
1236     assert(DstOps.size() == 1 && "Invalid DstOps");
1237     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1238            "Must have at least 2 operands");
1239     assert(llvm::all_of(SrcOps,
1240                         [&, this](const SrcOp &Op) {
1241                           return (Op.getLLTTy(*getMRI()).isVector() &&
1242                                   Op.getLLTTy(*getMRI()) ==
1243                                       SrcOps[0].getLLTTy(*getMRI()));
1244                         }) &&
1245            "type mismatch in input list");
1246     assert((TypeSize::ScalarTy)SrcOps.size() *
1247                    SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1248                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1249            "input vectors do not exactly cover the output vector register");
1250     break;
1251   }
1252   case TargetOpcode::G_UADDE: {
1253     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1254     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1255     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1256     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1257            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1258            "Invalid operand");
1259     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1260     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1261            "type mismatch");
1262     break;
1263   }
1264   }
1265 
1266   auto MIB = buildInstr(Opc);
1267   for (const DstOp &Op : DstOps)
1268     Op.addDefToMIB(*getMRI(), MIB);
1269   for (const SrcOp &Op : SrcOps)
1270     Op.addSrcToMIB(MIB);
1271   if (Flags)
1272     MIB->setFlags(*Flags);
1273   return MIB;
1274 }
1275