1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res,
164                                                          const SrcOp &Size,
165                                                          Align Alignment) {
166   assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
167   auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
168   Res.addDefToMIB(*getMRI(), MIB);
169   Size.addSrcToMIB(MIB);
170   MIB.addImm(Alignment.value());
171   return MIB;
172 }
173 
174 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res,
175                                                       int Idx) {
176   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
177   auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
178   Res.addDefToMIB(*getMRI(), MIB);
179   MIB.addFrameIndex(Idx);
180   return MIB;
181 }
182 
183 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res,
184                                                        const GlobalValue *GV) {
185   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
186   assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
187              GV->getType()->getAddressSpace() &&
188          "address space mismatch");
189 
190   auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
191   Res.addDefToMIB(*getMRI(), MIB);
192   MIB.addGlobalAddress(GV);
193   return MIB;
194 }
195 
196 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
197                                                      unsigned JTI) {
198   return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
199       .addJumpTableIndex(JTI);
200 }
201 
202 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
203                                         const LLT Op1) {
204   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
205   assert((Res == Op0 && Res == Op1) && "type mismatch");
206 }
207 
208 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
209                                        const LLT Op1) {
210   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
211   assert((Res == Op0) && "type mismatch");
212 }
213 
214 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res,
215                                                   const SrcOp &Op0,
216                                                   const SrcOp &Op1) {
217   assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
218          Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
219   assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
220 
221   return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
222 }
223 
224 Optional<MachineInstrBuilder>
225 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
226                                     const LLT ValueTy, uint64_t Value) {
227   assert(Res == 0 && "Res is a result argument");
228   assert(ValueTy.isScalar()  && "invalid offset type");
229 
230   if (Value == 0) {
231     Res = Op0;
232     return None;
233   }
234 
235   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
236   auto Cst = buildConstant(ValueTy, Value);
237   return buildPtrAdd(Res, Op0, Cst.getReg(0));
238 }
239 
240 MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res,
241                                                           const SrcOp &Op0,
242                                                           uint32_t NumBits) {
243   LLT PtrTy = Res.getLLTTy(*getMRI());
244   LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
245   Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
246   buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
247   return buildPtrMask(Res, Op0, MaskReg);
248 }
249 
250 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
251   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
252 }
253 
254 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
255   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
256   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
257 }
258 
259 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
260                                                 unsigned JTI,
261                                                 Register IndexReg) {
262   assert(getMRI()->getType(TablePtr).isPointer() &&
263          "Table reg must be a pointer");
264   return buildInstr(TargetOpcode::G_BRJT)
265       .addUse(TablePtr)
266       .addJumpTableIndex(JTI)
267       .addUse(IndexReg);
268 }
269 
270 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
271                                                 const SrcOp &Op) {
272   return buildInstr(TargetOpcode::COPY, Res, Op);
273 }
274 
275 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
276                                                     const ConstantInt &Val) {
277   LLT Ty = Res.getLLTTy(*getMRI());
278   LLT EltTy = Ty.getScalarType();
279   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
280          "creating constant with the wrong size");
281 
282   if (Ty.isVector()) {
283     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
284     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
285     .addCImm(&Val);
286     return buildSplatVector(Res, Const);
287   }
288 
289   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
290   Const->setDebugLoc(DebugLoc());
291   Res.addDefToMIB(*getMRI(), Const);
292   Const.addCImm(&Val);
293   return Const;
294 }
295 
296 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
297                                                     int64_t Val) {
298   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
299                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
300   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
301   return buildConstant(Res, *CI);
302 }
303 
304 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
305                                                      const ConstantFP &Val) {
306   LLT Ty = Res.getLLTTy(*getMRI());
307   LLT EltTy = Ty.getScalarType();
308 
309   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
310          == EltTy.getSizeInBits() &&
311          "creating fconstant with the wrong size");
312 
313   assert(!Ty.isPointer() && "invalid operand type");
314 
315   if (Ty.isVector()) {
316     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
317     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
318     .addFPImm(&Val);
319 
320     return buildSplatVector(Res, Const);
321   }
322 
323   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
324   Const->setDebugLoc(DebugLoc());
325   Res.addDefToMIB(*getMRI(), Const);
326   Const.addFPImm(&Val);
327   return Const;
328 }
329 
330 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
331                                                     const APInt &Val) {
332   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
333   return buildConstant(Res, *CI);
334 }
335 
336 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
337                                                      double Val) {
338   LLT DstTy = Res.getLLTTy(*getMRI());
339   auto &Ctx = getMF().getFunction().getContext();
340   auto *CFP =
341       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
342   return buildFConstant(Res, *CFP);
343 }
344 
345 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
346                                                      const APFloat &Val) {
347   auto &Ctx = getMF().getFunction().getContext();
348   auto *CFP = ConstantFP::get(Ctx, Val);
349   return buildFConstant(Res, *CFP);
350 }
351 
352 MachineInstrBuilder MachineIRBuilder::buildBrCond(Register Tst,
353                                                   MachineBasicBlock &Dest) {
354   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
355 
356   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
357 }
358 
359 MachineInstrBuilder MachineIRBuilder::buildLoad(const DstOp &Res,
360                                                 const SrcOp &Addr,
361                                                 MachineMemOperand &MMO) {
362   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
363 }
364 
365 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
366                                                      const DstOp &Res,
367                                                      const SrcOp &Addr,
368                                                      MachineMemOperand &MMO) {
369   assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
370   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
371 
372   auto MIB = buildInstr(Opcode);
373   Res.addDefToMIB(*getMRI(), MIB);
374   Addr.addSrcToMIB(MIB);
375   MIB.addMemOperand(&MMO);
376   return MIB;
377 }
378 
379 MachineInstrBuilder MachineIRBuilder::buildLoadFromOffset(
380   const DstOp &Dst, const SrcOp &BasePtr,
381   MachineMemOperand &BaseMMO, int64_t Offset) {
382   LLT LoadTy = Dst.getLLTTy(*getMRI());
383   MachineMemOperand *OffsetMMO =
384     getMF().getMachineMemOperand(&BaseMMO, Offset, LoadTy.getSizeInBytes());
385 
386   if (Offset == 0) // This may be a size or type changing load.
387     return buildLoad(Dst, BasePtr, *OffsetMMO);
388 
389   LLT PtrTy = BasePtr.getLLTTy(*getMRI());
390   LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
391   auto ConstOffset = buildConstant(OffsetTy, Offset);
392   auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
393   return buildLoad(Dst, Ptr, *OffsetMMO);
394 }
395 
396 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
397                                                  const SrcOp &Addr,
398                                                  MachineMemOperand &MMO) {
399   assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
400   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
401 
402   auto MIB = buildInstr(TargetOpcode::G_STORE);
403   Val.addSrcToMIB(MIB);
404   Addr.addSrcToMIB(MIB);
405   MIB.addMemOperand(&MMO);
406   return MIB;
407 }
408 
409 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
410                                                   const SrcOp &Op) {
411   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
412 }
413 
414 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
415                                                 const SrcOp &Op) {
416   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
417 }
418 
419 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
420                                                 const SrcOp &Op) {
421   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
422 }
423 
424 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
425   const auto *TLI = getMF().getSubtarget().getTargetLowering();
426   switch (TLI->getBooleanContents(IsVec, IsFP)) {
427   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
428     return TargetOpcode::G_SEXT;
429   case TargetLoweringBase::ZeroOrOneBooleanContent:
430     return TargetOpcode::G_ZEXT;
431   default:
432     return TargetOpcode::G_ANYEXT;
433   }
434 }
435 
436 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
437                                                    const SrcOp &Op,
438                                                    bool IsFP) {
439   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
440   return buildInstr(ExtOp, Res, Op);
441 }
442 
443 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
444                                                       const DstOp &Res,
445                                                       const SrcOp &Op) {
446   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
447           TargetOpcode::G_SEXT == ExtOpc) &&
448          "Expecting Extending Opc");
449   assert(Res.getLLTTy(*getMRI()).isScalar() ||
450          Res.getLLTTy(*getMRI()).isVector());
451   assert(Res.getLLTTy(*getMRI()).isScalar() ==
452          Op.getLLTTy(*getMRI()).isScalar());
453 
454   unsigned Opcode = TargetOpcode::COPY;
455   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
456       Op.getLLTTy(*getMRI()).getSizeInBits())
457     Opcode = ExtOpc;
458   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
459            Op.getLLTTy(*getMRI()).getSizeInBits())
460     Opcode = TargetOpcode::G_TRUNC;
461   else
462     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
463 
464   return buildInstr(Opcode, Res, Op);
465 }
466 
467 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
468                                                        const SrcOp &Op) {
469   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
470 }
471 
472 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
473                                                        const SrcOp &Op) {
474   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
475 }
476 
477 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
478                                                          const SrcOp &Op) {
479   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
480 }
481 
482 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
483                                                 const SrcOp &Src) {
484   LLT SrcTy = Src.getLLTTy(*getMRI());
485   LLT DstTy = Dst.getLLTTy(*getMRI());
486   if (SrcTy == DstTy)
487     return buildCopy(Dst, Src);
488 
489   unsigned Opcode;
490   if (SrcTy.isPointer() && DstTy.isScalar())
491     Opcode = TargetOpcode::G_PTRTOINT;
492   else if (DstTy.isPointer() && SrcTy.isScalar())
493     Opcode = TargetOpcode::G_INTTOPTR;
494   else {
495     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
496     Opcode = TargetOpcode::G_BITCAST;
497   }
498 
499   return buildInstr(Opcode, Dst, Src);
500 }
501 
502 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
503                                                    const SrcOp &Src,
504                                                    uint64_t Index) {
505   LLT SrcTy = Src.getLLTTy(*getMRI());
506   LLT DstTy = Dst.getLLTTy(*getMRI());
507 
508 #ifndef NDEBUG
509   assert(SrcTy.isValid() && "invalid operand type");
510   assert(DstTy.isValid() && "invalid operand type");
511   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
512          "extracting off end of register");
513 #endif
514 
515   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
516     assert(Index == 0 && "insertion past the end of a register");
517     return buildCast(Dst, Src);
518   }
519 
520   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
521   Dst.addDefToMIB(*getMRI(), Extract);
522   Src.addSrcToMIB(Extract);
523   Extract.addImm(Index);
524   return Extract;
525 }
526 
527 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
528                                      ArrayRef<uint64_t> Indices) {
529 #ifndef NDEBUG
530   assert(Ops.size() == Indices.size() && "incompatible args");
531   assert(!Ops.empty() && "invalid trivial sequence");
532   assert(llvm::is_sorted(Indices) &&
533          "sequence offsets must be in ascending order");
534 
535   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
536   for (auto Op : Ops)
537     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
538 #endif
539 
540   LLT ResTy = getMRI()->getType(Res);
541   LLT OpTy = getMRI()->getType(Ops[0]);
542   unsigned OpSize = OpTy.getSizeInBits();
543   bool MaybeMerge = true;
544   for (unsigned i = 0; i < Ops.size(); ++i) {
545     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
546       MaybeMerge = false;
547       break;
548     }
549   }
550 
551   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
552     buildMerge(Res, Ops);
553     return;
554   }
555 
556   Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
557   buildUndef(ResIn);
558 
559   for (unsigned i = 0; i < Ops.size(); ++i) {
560     Register ResOut = i + 1 == Ops.size()
561                           ? Res
562                           : getMRI()->createGenericVirtualRegister(ResTy);
563     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
564     ResIn = ResOut;
565   }
566 }
567 
568 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
569   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
570 }
571 
572 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
573                                                  ArrayRef<Register> Ops) {
574   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
575   // we need some temporary storage for the DstOp objects. Here we use a
576   // sufficiently large SmallVector to not go through the heap.
577   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
578   assert(TmpVec.size() > 1);
579   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
580 }
581 
582 MachineInstrBuilder
583 MachineIRBuilder::buildMerge(const DstOp &Res,
584                              std::initializer_list<SrcOp> Ops) {
585   assert(Ops.size() > 1);
586   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
587 }
588 
589 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
590                                                    const SrcOp &Op) {
591   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
592   // we need some temporary storage for the DstOp objects. Here we use a
593   // sufficiently large SmallVector to not go through the heap.
594   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
595   assert(TmpVec.size() > 1);
596   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
597 }
598 
599 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
600                                                    const SrcOp &Op) {
601   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
602   SmallVector<Register, 8> TmpVec;
603   for (unsigned I = 0; I != NumReg; ++I)
604     TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
605   return buildUnmerge(TmpVec, Op);
606 }
607 
608 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
609                                                    const SrcOp &Op) {
610   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
611   // we need some temporary storage for the DstOp objects. Here we use a
612   // sufficiently large SmallVector to not go through the heap.
613   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
614   assert(TmpVec.size() > 1);
615   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
616 }
617 
618 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
619                                                        ArrayRef<Register> Ops) {
620   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
621   // we need some temporary storage for the DstOp objects. Here we use a
622   // sufficiently large SmallVector to not go through the heap.
623   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
624   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
625 }
626 
627 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
628                                                        const SrcOp &Src) {
629   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
630   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
631 }
632 
633 MachineInstrBuilder
634 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
635                                         ArrayRef<Register> Ops) {
636   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
637   // we need some temporary storage for the DstOp objects. Here we use a
638   // sufficiently large SmallVector to not go through the heap.
639   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
640   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
641 }
642 
643 MachineInstrBuilder
644 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
645   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
646   // we need some temporary storage for the DstOp objects. Here we use a
647   // sufficiently large SmallVector to not go through the heap.
648   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
649   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
650 }
651 
652 MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
653                                                   const SrcOp &Src,
654                                                   const SrcOp &Op,
655                                                   unsigned Index) {
656   assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
657              Res.getLLTTy(*getMRI()).getSizeInBits() &&
658          "insertion past the end of a register");
659 
660   if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
661       Op.getLLTTy(*getMRI()).getSizeInBits()) {
662     return buildCast(Res, Op);
663   }
664 
665   return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
666 }
667 
668 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
669                                                      ArrayRef<Register> ResultRegs,
670                                                      bool HasSideEffects) {
671   auto MIB =
672       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
673                                 : TargetOpcode::G_INTRINSIC);
674   for (unsigned ResultReg : ResultRegs)
675     MIB.addDef(ResultReg);
676   MIB.addIntrinsicID(ID);
677   return MIB;
678 }
679 
680 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
681                                                      ArrayRef<DstOp> Results,
682                                                      bool HasSideEffects) {
683   auto MIB =
684       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
685                                 : TargetOpcode::G_INTRINSIC);
686   for (DstOp Result : Results)
687     Result.addDefToMIB(*getMRI(), MIB);
688   MIB.addIntrinsicID(ID);
689   return MIB;
690 }
691 
692 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
693                                                  const SrcOp &Op) {
694   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
695 }
696 
697 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
698                                                    const SrcOp &Op,
699                                                    Optional<unsigned> Flags) {
700   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
701 }
702 
703 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
704                                                 const DstOp &Res,
705                                                 const SrcOp &Op0,
706                                                 const SrcOp &Op1) {
707   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
708 }
709 
710 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
711                                                 const DstOp &Res,
712                                                 const SrcOp &Op0,
713                                                 const SrcOp &Op1,
714                                                 Optional<unsigned> Flags) {
715 
716   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
717 }
718 
719 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
720                                                   const SrcOp &Tst,
721                                                   const SrcOp &Op0,
722                                                   const SrcOp &Op1,
723                                                   Optional<unsigned> Flags) {
724 
725   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
726 }
727 
728 MachineInstrBuilder
729 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
730                                            const SrcOp &Elt, const SrcOp &Idx) {
731   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
732 }
733 
734 MachineInstrBuilder
735 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
736                                             const SrcOp &Idx) {
737   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
738 }
739 
740 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
741     Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
742     Register NewVal, MachineMemOperand &MMO) {
743 #ifndef NDEBUG
744   LLT OldValResTy = getMRI()->getType(OldValRes);
745   LLT SuccessResTy = getMRI()->getType(SuccessRes);
746   LLT AddrTy = getMRI()->getType(Addr);
747   LLT CmpValTy = getMRI()->getType(CmpVal);
748   LLT NewValTy = getMRI()->getType(NewVal);
749   assert(OldValResTy.isScalar() && "invalid operand type");
750   assert(SuccessResTy.isScalar() && "invalid operand type");
751   assert(AddrTy.isPointer() && "invalid operand type");
752   assert(CmpValTy.isValid() && "invalid operand type");
753   assert(NewValTy.isValid() && "invalid operand type");
754   assert(OldValResTy == CmpValTy && "type mismatch");
755   assert(OldValResTy == NewValTy && "type mismatch");
756 #endif
757 
758   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
759       .addDef(OldValRes)
760       .addDef(SuccessRes)
761       .addUse(Addr)
762       .addUse(CmpVal)
763       .addUse(NewVal)
764       .addMemOperand(&MMO);
765 }
766 
767 MachineInstrBuilder
768 MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
769                                      Register CmpVal, Register NewVal,
770                                      MachineMemOperand &MMO) {
771 #ifndef NDEBUG
772   LLT OldValResTy = getMRI()->getType(OldValRes);
773   LLT AddrTy = getMRI()->getType(Addr);
774   LLT CmpValTy = getMRI()->getType(CmpVal);
775   LLT NewValTy = getMRI()->getType(NewVal);
776   assert(OldValResTy.isScalar() && "invalid operand type");
777   assert(AddrTy.isPointer() && "invalid operand type");
778   assert(CmpValTy.isValid() && "invalid operand type");
779   assert(NewValTy.isValid() && "invalid operand type");
780   assert(OldValResTy == CmpValTy && "type mismatch");
781   assert(OldValResTy == NewValTy && "type mismatch");
782 #endif
783 
784   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
785       .addDef(OldValRes)
786       .addUse(Addr)
787       .addUse(CmpVal)
788       .addUse(NewVal)
789       .addMemOperand(&MMO);
790 }
791 
792 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(
793   unsigned Opcode, const DstOp &OldValRes,
794   const SrcOp &Addr, const SrcOp &Val,
795   MachineMemOperand &MMO) {
796 
797 #ifndef NDEBUG
798   LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
799   LLT AddrTy = Addr.getLLTTy(*getMRI());
800   LLT ValTy = Val.getLLTTy(*getMRI());
801   assert(OldValResTy.isScalar() && "invalid operand type");
802   assert(AddrTy.isPointer() && "invalid operand type");
803   assert(ValTy.isValid() && "invalid operand type");
804   assert(OldValResTy == ValTy && "type mismatch");
805   assert(MMO.isAtomic() && "not atomic mem operand");
806 #endif
807 
808   auto MIB = buildInstr(Opcode);
809   OldValRes.addDefToMIB(*getMRI(), MIB);
810   Addr.addSrcToMIB(MIB);
811   Val.addSrcToMIB(MIB);
812   MIB.addMemOperand(&MMO);
813   return MIB;
814 }
815 
816 MachineInstrBuilder
817 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
818                                      Register Val, MachineMemOperand &MMO) {
819   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
820                         MMO);
821 }
822 MachineInstrBuilder
823 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
824                                     Register Val, MachineMemOperand &MMO) {
825   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
826                         MMO);
827 }
828 MachineInstrBuilder
829 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
830                                     Register Val, MachineMemOperand &MMO) {
831   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
832                         MMO);
833 }
834 MachineInstrBuilder
835 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
836                                     Register Val, MachineMemOperand &MMO) {
837   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
838                         MMO);
839 }
840 MachineInstrBuilder
841 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
842                                      Register Val, MachineMemOperand &MMO) {
843   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
844                         MMO);
845 }
846 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
847                                                        Register Addr,
848                                                        Register Val,
849                                                        MachineMemOperand &MMO) {
850   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
851                         MMO);
852 }
853 MachineInstrBuilder
854 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
855                                     Register Val, MachineMemOperand &MMO) {
856   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
857                         MMO);
858 }
859 MachineInstrBuilder
860 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
861                                     Register Val, MachineMemOperand &MMO) {
862   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
863                         MMO);
864 }
865 MachineInstrBuilder
866 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
867                                     Register Val, MachineMemOperand &MMO) {
868   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
869                         MMO);
870 }
871 MachineInstrBuilder
872 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
873                                      Register Val, MachineMemOperand &MMO) {
874   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
875                         MMO);
876 }
877 MachineInstrBuilder
878 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
879                                      Register Val, MachineMemOperand &MMO) {
880   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
881                         MMO);
882 }
883 
884 MachineInstrBuilder
885 MachineIRBuilder::buildAtomicRMWFAdd(
886   const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
887   MachineMemOperand &MMO) {
888   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
889                         MMO);
890 }
891 
892 MachineInstrBuilder
893 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
894                                      MachineMemOperand &MMO) {
895   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
896                         MMO);
897 }
898 
899 MachineInstrBuilder
900 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
901   return buildInstr(TargetOpcode::G_FENCE)
902     .addImm(Ordering)
903     .addImm(Scope);
904 }
905 
906 MachineInstrBuilder
907 MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
908 #ifndef NDEBUG
909   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
910 #endif
911 
912   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
913 }
914 
915 void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
916                                         bool IsExtend) {
917 #ifndef NDEBUG
918   if (DstTy.isVector()) {
919     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
920     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
921            "different number of elements in a trunc/ext");
922   } else
923     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
924 
925   if (IsExtend)
926     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
927            "invalid narrowing extend");
928   else
929     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
930            "invalid widening trunc");
931 #endif
932 }
933 
934 void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
935                                         const LLT Op0Ty, const LLT Op1Ty) {
936 #ifndef NDEBUG
937   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
938          "invalid operand type");
939   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
940   if (ResTy.isScalar() || ResTy.isPointer())
941     assert(TstTy.isScalar() && "type mismatch");
942   else
943     assert((TstTy.isScalar() ||
944             (TstTy.isVector() &&
945              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
946            "type mismatch");
947 #endif
948 }
949 
950 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
951                                                  ArrayRef<DstOp> DstOps,
952                                                  ArrayRef<SrcOp> SrcOps,
953                                                  Optional<unsigned> Flags) {
954   switch (Opc) {
955   default:
956     break;
957   case TargetOpcode::G_SELECT: {
958     assert(DstOps.size() == 1 && "Invalid select");
959     assert(SrcOps.size() == 3 && "Invalid select");
960     validateSelectOp(
961         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
962         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
963     break;
964   }
965   case TargetOpcode::G_ADD:
966   case TargetOpcode::G_AND:
967   case TargetOpcode::G_MUL:
968   case TargetOpcode::G_OR:
969   case TargetOpcode::G_SUB:
970   case TargetOpcode::G_XOR:
971   case TargetOpcode::G_UDIV:
972   case TargetOpcode::G_SDIV:
973   case TargetOpcode::G_UREM:
974   case TargetOpcode::G_SREM:
975   case TargetOpcode::G_SMIN:
976   case TargetOpcode::G_SMAX:
977   case TargetOpcode::G_UMIN:
978   case TargetOpcode::G_UMAX:
979   case TargetOpcode::G_UADDSAT:
980   case TargetOpcode::G_SADDSAT:
981   case TargetOpcode::G_USUBSAT:
982   case TargetOpcode::G_SSUBSAT: {
983     // All these are binary ops.
984     assert(DstOps.size() == 1 && "Invalid Dst");
985     assert(SrcOps.size() == 2 && "Invalid Srcs");
986     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
987                      SrcOps[0].getLLTTy(*getMRI()),
988                      SrcOps[1].getLLTTy(*getMRI()));
989     break;
990   }
991   case TargetOpcode::G_SHL:
992   case TargetOpcode::G_ASHR:
993   case TargetOpcode::G_LSHR: {
994     assert(DstOps.size() == 1 && "Invalid Dst");
995     assert(SrcOps.size() == 2 && "Invalid Srcs");
996     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
997                     SrcOps[0].getLLTTy(*getMRI()),
998                     SrcOps[1].getLLTTy(*getMRI()));
999     break;
1000   }
1001   case TargetOpcode::G_SEXT:
1002   case TargetOpcode::G_ZEXT:
1003   case TargetOpcode::G_ANYEXT:
1004     assert(DstOps.size() == 1 && "Invalid Dst");
1005     assert(SrcOps.size() == 1 && "Invalid Srcs");
1006     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1007                      SrcOps[0].getLLTTy(*getMRI()), true);
1008     break;
1009   case TargetOpcode::G_TRUNC:
1010   case TargetOpcode::G_FPTRUNC: {
1011     assert(DstOps.size() == 1 && "Invalid Dst");
1012     assert(SrcOps.size() == 1 && "Invalid Srcs");
1013     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1014                      SrcOps[0].getLLTTy(*getMRI()), false);
1015     break;
1016   }
1017   case TargetOpcode::G_BITCAST: {
1018     assert(DstOps.size() == 1 && "Invalid Dst");
1019     assert(SrcOps.size() == 1 && "Invalid Srcs");
1020     assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1021            SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
1022     break;
1023   }
1024   case TargetOpcode::COPY:
1025     assert(DstOps.size() == 1 && "Invalid Dst");
1026     // If the caller wants to add a subreg source it has to be done separately
1027     // so we may not have any SrcOps at this point yet.
1028     break;
1029   case TargetOpcode::G_FCMP:
1030   case TargetOpcode::G_ICMP: {
1031     assert(DstOps.size() == 1 && "Invalid Dst Operands");
1032     assert(SrcOps.size() == 3 && "Invalid Src Operands");
1033     // For F/ICMP, the first src operand is the predicate, followed by
1034     // the two comparands.
1035     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1036            "Expecting predicate");
1037     assert([&]() -> bool {
1038       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1039       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1040                                          : CmpInst::isFPPredicate(Pred);
1041     }() && "Invalid predicate");
1042     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1043            "Type mismatch");
1044     assert([&]() -> bool {
1045       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1046       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1047       if (Op0Ty.isScalar() || Op0Ty.isPointer())
1048         return DstTy.isScalar();
1049       else
1050         return DstTy.isVector() &&
1051                DstTy.getNumElements() == Op0Ty.getNumElements();
1052     }() && "Type Mismatch");
1053     break;
1054   }
1055   case TargetOpcode::G_UNMERGE_VALUES: {
1056     assert(!DstOps.empty() && "Invalid trivial sequence");
1057     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1058     assert(std::all_of(DstOps.begin(), DstOps.end(),
1059                        [&, this](const DstOp &Op) {
1060                          return Op.getLLTTy(*getMRI()) ==
1061                                 DstOps[0].getLLTTy(*getMRI());
1062                        }) &&
1063            "type mismatch in output list");
1064     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1065                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1066            "input operands do not cover output register");
1067     break;
1068   }
1069   case TargetOpcode::G_MERGE_VALUES: {
1070     assert(!SrcOps.empty() && "invalid trivial sequence");
1071     assert(DstOps.size() == 1 && "Invalid Dst");
1072     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1073                        [&, this](const SrcOp &Op) {
1074                          return Op.getLLTTy(*getMRI()) ==
1075                                 SrcOps[0].getLLTTy(*getMRI());
1076                        }) &&
1077            "type mismatch in input list");
1078     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1079                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1080            "input operands do not cover output register");
1081     if (SrcOps.size() == 1)
1082       return buildCast(DstOps[0], SrcOps[0]);
1083     if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
1084       if (SrcOps[0].getLLTTy(*getMRI()).isVector())
1085         return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1086       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1087     }
1088     break;
1089   }
1090   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1091     assert(DstOps.size() == 1 && "Invalid Dst size");
1092     assert(SrcOps.size() == 2 && "Invalid Src size");
1093     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1094     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1095             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1096            "Invalid operand type");
1097     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1098     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1099                DstOps[0].getLLTTy(*getMRI()) &&
1100            "Type mismatch");
1101     break;
1102   }
1103   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1104     assert(DstOps.size() == 1 && "Invalid dst size");
1105     assert(SrcOps.size() == 3 && "Invalid src size");
1106     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1107            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1108     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1109                SrcOps[1].getLLTTy(*getMRI()) &&
1110            "Type mismatch");
1111     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1112     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1113                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1114            "Type mismatch");
1115     break;
1116   }
1117   case TargetOpcode::G_BUILD_VECTOR: {
1118     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1119            "Must have at least 2 operands");
1120     assert(DstOps.size() == 1 && "Invalid DstOps");
1121     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1122            "Res type must be a vector");
1123     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1124                        [&, this](const SrcOp &Op) {
1125                          return Op.getLLTTy(*getMRI()) ==
1126                                 SrcOps[0].getLLTTy(*getMRI());
1127                        }) &&
1128            "type mismatch in input list");
1129     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1130                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1131            "input scalars do not exactly cover the output vector register");
1132     break;
1133   }
1134   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1135     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1136            "Must have at least 2 operands");
1137     assert(DstOps.size() == 1 && "Invalid DstOps");
1138     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1139            "Res type must be a vector");
1140     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1141                        [&, this](const SrcOp &Op) {
1142                          return Op.getLLTTy(*getMRI()) ==
1143                                 SrcOps[0].getLLTTy(*getMRI());
1144                        }) &&
1145            "type mismatch in input list");
1146     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1147         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1148       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1149     break;
1150   }
1151   case TargetOpcode::G_CONCAT_VECTORS: {
1152     assert(DstOps.size() == 1 && "Invalid DstOps");
1153     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1154            "Must have at least 2 operands");
1155     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1156                        [&, this](const SrcOp &Op) {
1157                          return (Op.getLLTTy(*getMRI()).isVector() &&
1158                                  Op.getLLTTy(*getMRI()) ==
1159                                      SrcOps[0].getLLTTy(*getMRI()));
1160                        }) &&
1161            "type mismatch in input list");
1162     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1163                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1164            "input vectors do not exactly cover the output vector register");
1165     break;
1166   }
1167   case TargetOpcode::G_UADDE: {
1168     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1169     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1170     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1171     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1172            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1173            "Invalid operand");
1174     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1175     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1176            "type mismatch");
1177     break;
1178   }
1179   }
1180 
1181   auto MIB = buildInstr(Opc);
1182   for (const DstOp &Op : DstOps)
1183     Op.addDefToMIB(*getMRI(), MIB);
1184   for (const SrcOp &Op : SrcOps)
1185     Op.addSrcToMIB(MIB);
1186   if (Flags)
1187     MIB->setFlags(*Flags);
1188   return MIB;
1189 }
1190