1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/Analysis/MemoryLocation.h"
13 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 //------------------------------------------------------------------------------
37 // Build instruction variants.
38 //------------------------------------------------------------------------------
39 
40 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
41   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
42   return MIB;
43 }
44 
45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
46   getMBB().insert(getInsertPt(), MIB);
47   recordInsertion(MIB);
48   return MIB;
49 }
50 
51 MachineInstrBuilder
52 MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable,
53                                       const MDNode *Expr) {
54   assert(isa<DILocalVariable>(Variable) && "not a variable");
55   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
56   assert(
57       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
58       "Expected inlined-at fields to agree");
59   return insertInstr(BuildMI(getMF(), getDL(),
60                              getTII().get(TargetOpcode::DBG_VALUE),
61                              /*IsIndirect*/ false, Reg, Variable, Expr));
62 }
63 
64 MachineInstrBuilder
65 MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable,
66                                         const MDNode *Expr) {
67   assert(isa<DILocalVariable>(Variable) && "not a variable");
68   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
69   assert(
70       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
71       "Expected inlined-at fields to agree");
72   return insertInstr(BuildMI(getMF(), getDL(),
73                              getTII().get(TargetOpcode::DBG_VALUE),
74                              /*IsIndirect*/ true, Reg, Variable, Expr));
75 }
76 
77 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
78                                                       const MDNode *Variable,
79                                                       const MDNode *Expr) {
80   assert(isa<DILocalVariable>(Variable) && "not a variable");
81   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
82   assert(
83       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
84       "Expected inlined-at fields to agree");
85   return buildInstr(TargetOpcode::DBG_VALUE)
86       .addFrameIndex(FI)
87       .addImm(0)
88       .addMetadata(Variable)
89       .addMetadata(Expr);
90 }
91 
92 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
93                                                          const MDNode *Variable,
94                                                          const MDNode *Expr) {
95   assert(isa<DILocalVariable>(Variable) && "not a variable");
96   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
97   assert(
98       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
99       "Expected inlined-at fields to agree");
100   auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE);
101   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
102     if (CI->getBitWidth() > 64)
103       MIB.addCImm(CI);
104     else
105       MIB.addImm(CI->getZExtValue());
106   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
107     MIB.addFPImm(CFP);
108   } else {
109     // Insert $noreg if we didn't find a usable constant and had to drop it.
110     MIB.addReg(Register());
111   }
112 
113   MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
114   return insertInstr(MIB);
115 }
116 
117 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
118   assert(isa<DILabel>(Label) && "not a label");
119   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
120          "Expected inlined-at fields to agree");
121   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
122 
123   return MIB.addMetadata(Label);
124 }
125 
126 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res,
127                                                          const SrcOp &Size,
128                                                          Align Alignment) {
129   assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
130   auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
131   Res.addDefToMIB(*getMRI(), MIB);
132   Size.addSrcToMIB(MIB);
133   MIB.addImm(Alignment.value());
134   return MIB;
135 }
136 
137 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res,
138                                                       int Idx) {
139   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
140   auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
141   Res.addDefToMIB(*getMRI(), MIB);
142   MIB.addFrameIndex(Idx);
143   return MIB;
144 }
145 
146 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res,
147                                                        const GlobalValue *GV) {
148   assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
149   assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
150              GV->getType()->getAddressSpace() &&
151          "address space mismatch");
152 
153   auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
154   Res.addDefToMIB(*getMRI(), MIB);
155   MIB.addGlobalAddress(GV);
156   return MIB;
157 }
158 
159 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
160                                                      unsigned JTI) {
161   return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
162       .addJumpTableIndex(JTI);
163 }
164 
165 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) {
166   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
167   assert((Res == Op0) && "type mismatch");
168 }
169 
170 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
171                                         const LLT Op1) {
172   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
173   assert((Res == Op0 && Res == Op1) && "type mismatch");
174 }
175 
176 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
177                                        const LLT Op1) {
178   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
179   assert((Res == Op0) && "type mismatch");
180 }
181 
182 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res,
183                                                   const SrcOp &Op0,
184                                                   const SrcOp &Op1) {
185   assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
186          Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
187   assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
188 
189   return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
190 }
191 
192 Optional<MachineInstrBuilder>
193 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
194                                     const LLT ValueTy, uint64_t Value) {
195   assert(Res == 0 && "Res is a result argument");
196   assert(ValueTy.isScalar()  && "invalid offset type");
197 
198   if (Value == 0) {
199     Res = Op0;
200     return None;
201   }
202 
203   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
204   auto Cst = buildConstant(ValueTy, Value);
205   return buildPtrAdd(Res, Op0, Cst.getReg(0));
206 }
207 
208 MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res,
209                                                           const SrcOp &Op0,
210                                                           uint32_t NumBits) {
211   LLT PtrTy = Res.getLLTTy(*getMRI());
212   LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
213   Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
214   buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
215   return buildPtrMask(Res, Op0, MaskReg);
216 }
217 
218 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
219   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
220 }
221 
222 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
223   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
224   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
225 }
226 
227 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
228                                                 unsigned JTI,
229                                                 Register IndexReg) {
230   assert(getMRI()->getType(TablePtr).isPointer() &&
231          "Table reg must be a pointer");
232   return buildInstr(TargetOpcode::G_BRJT)
233       .addUse(TablePtr)
234       .addJumpTableIndex(JTI)
235       .addUse(IndexReg);
236 }
237 
238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
239                                                 const SrcOp &Op) {
240   return buildInstr(TargetOpcode::COPY, Res, Op);
241 }
242 
243 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
244                                                     const ConstantInt &Val) {
245   LLT Ty = Res.getLLTTy(*getMRI());
246   LLT EltTy = Ty.getScalarType();
247   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
248          "creating constant with the wrong size");
249 
250   if (Ty.isVector()) {
251     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
252     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
253     .addCImm(&Val);
254     return buildSplatVector(Res, Const);
255   }
256 
257   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
258   Const->setDebugLoc(DebugLoc());
259   Res.addDefToMIB(*getMRI(), Const);
260   Const.addCImm(&Val);
261   return Const;
262 }
263 
264 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
265                                                     int64_t Val) {
266   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
267                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
268   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
269   return buildConstant(Res, *CI);
270 }
271 
272 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
273                                                      const ConstantFP &Val) {
274   LLT Ty = Res.getLLTTy(*getMRI());
275   LLT EltTy = Ty.getScalarType();
276 
277   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
278          == EltTy.getSizeInBits() &&
279          "creating fconstant with the wrong size");
280 
281   assert(!Ty.isPointer() && "invalid operand type");
282 
283   if (Ty.isVector()) {
284     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
285     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
286     .addFPImm(&Val);
287 
288     return buildSplatVector(Res, Const);
289   }
290 
291   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
292   Const->setDebugLoc(DebugLoc());
293   Res.addDefToMIB(*getMRI(), Const);
294   Const.addFPImm(&Val);
295   return Const;
296 }
297 
298 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
299                                                     const APInt &Val) {
300   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
301   return buildConstant(Res, *CI);
302 }
303 
304 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
305                                                      double Val) {
306   LLT DstTy = Res.getLLTTy(*getMRI());
307   auto &Ctx = getMF().getFunction().getContext();
308   auto *CFP =
309       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
310   return buildFConstant(Res, *CFP);
311 }
312 
313 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
314                                                      const APFloat &Val) {
315   auto &Ctx = getMF().getFunction().getContext();
316   auto *CFP = ConstantFP::get(Ctx, Val);
317   return buildFConstant(Res, *CFP);
318 }
319 
320 MachineInstrBuilder MachineIRBuilder::buildBrCond(const SrcOp &Tst,
321                                                   MachineBasicBlock &Dest) {
322   assert(Tst.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
323 
324   auto MIB = buildInstr(TargetOpcode::G_BRCOND);
325   Tst.addSrcToMIB(MIB);
326   MIB.addMBB(&Dest);
327   return MIB;
328 }
329 
330 MachineInstrBuilder
331 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr,
332                             MachinePointerInfo PtrInfo, Align Alignment,
333                             MachineMemOperand::Flags MMOFlags,
334                             const AAMDNodes &AAInfo) {
335   MMOFlags |= MachineMemOperand::MOLoad;
336   assert((MMOFlags & MachineMemOperand::MOStore) == 0);
337 
338   uint64_t Size = MemoryLocation::getSizeOrUnknown(
339       TypeSize::Fixed(Dst.getLLTTy(*getMRI()).getSizeInBytes()));
340   MachineMemOperand *MMO =
341       getMF().getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
342   return buildLoad(Dst, Addr, *MMO);
343 }
344 
345 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
346                                                      const DstOp &Res,
347                                                      const SrcOp &Addr,
348                                                      MachineMemOperand &MMO) {
349   assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
350   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
351 
352   auto MIB = buildInstr(Opcode);
353   Res.addDefToMIB(*getMRI(), MIB);
354   Addr.addSrcToMIB(MIB);
355   MIB.addMemOperand(&MMO);
356   return MIB;
357 }
358 
359 MachineInstrBuilder MachineIRBuilder::buildLoadFromOffset(
360   const DstOp &Dst, const SrcOp &BasePtr,
361   MachineMemOperand &BaseMMO, int64_t Offset) {
362   LLT LoadTy = Dst.getLLTTy(*getMRI());
363   MachineMemOperand *OffsetMMO =
364     getMF().getMachineMemOperand(&BaseMMO, Offset, LoadTy.getSizeInBytes());
365 
366   if (Offset == 0) // This may be a size or type changing load.
367     return buildLoad(Dst, BasePtr, *OffsetMMO);
368 
369   LLT PtrTy = BasePtr.getLLTTy(*getMRI());
370   LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
371   auto ConstOffset = buildConstant(OffsetTy, Offset);
372   auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
373   return buildLoad(Dst, Ptr, *OffsetMMO);
374 }
375 
376 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
377                                                  const SrcOp &Addr,
378                                                  MachineMemOperand &MMO) {
379   assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
380   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
381 
382   auto MIB = buildInstr(TargetOpcode::G_STORE);
383   Val.addSrcToMIB(MIB);
384   Addr.addSrcToMIB(MIB);
385   MIB.addMemOperand(&MMO);
386   return MIB;
387 }
388 
389 MachineInstrBuilder
390 MachineIRBuilder::buildStore(const SrcOp &Val, const SrcOp &Addr,
391                              MachinePointerInfo PtrInfo, Align Alignment,
392                              MachineMemOperand::Flags MMOFlags,
393                              const AAMDNodes &AAInfo) {
394   MMOFlags |= MachineMemOperand::MOStore;
395   assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
396 
397   uint64_t Size = MemoryLocation::getSizeOrUnknown(
398       TypeSize::Fixed(Val.getLLTTy(*getMRI()).getSizeInBytes()));
399   MachineMemOperand *MMO =
400       getMF().getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
401   return buildStore(Val, Addr, *MMO);
402 }
403 
404 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
405                                                   const SrcOp &Op) {
406   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
407 }
408 
409 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
410                                                 const SrcOp &Op) {
411   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
412 }
413 
414 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
415                                                 const SrcOp &Op) {
416   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
417 }
418 
419 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
420   const auto *TLI = getMF().getSubtarget().getTargetLowering();
421   switch (TLI->getBooleanContents(IsVec, IsFP)) {
422   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
423     return TargetOpcode::G_SEXT;
424   case TargetLoweringBase::ZeroOrOneBooleanContent:
425     return TargetOpcode::G_ZEXT;
426   default:
427     return TargetOpcode::G_ANYEXT;
428   }
429 }
430 
431 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
432                                                    const SrcOp &Op,
433                                                    bool IsFP) {
434   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
435   return buildInstr(ExtOp, Res, Op);
436 }
437 
438 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
439                                                       const DstOp &Res,
440                                                       const SrcOp &Op) {
441   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
442           TargetOpcode::G_SEXT == ExtOpc) &&
443          "Expecting Extending Opc");
444   assert(Res.getLLTTy(*getMRI()).isScalar() ||
445          Res.getLLTTy(*getMRI()).isVector());
446   assert(Res.getLLTTy(*getMRI()).isScalar() ==
447          Op.getLLTTy(*getMRI()).isScalar());
448 
449   unsigned Opcode = TargetOpcode::COPY;
450   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
451       Op.getLLTTy(*getMRI()).getSizeInBits())
452     Opcode = ExtOpc;
453   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
454            Op.getLLTTy(*getMRI()).getSizeInBits())
455     Opcode = TargetOpcode::G_TRUNC;
456   else
457     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
458 
459   return buildInstr(Opcode, Res, Op);
460 }
461 
462 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
463                                                        const SrcOp &Op) {
464   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
465 }
466 
467 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
468                                                        const SrcOp &Op) {
469   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
470 }
471 
472 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
473                                                          const SrcOp &Op) {
474   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
475 }
476 
477 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
478                                                 const SrcOp &Src) {
479   LLT SrcTy = Src.getLLTTy(*getMRI());
480   LLT DstTy = Dst.getLLTTy(*getMRI());
481   if (SrcTy == DstTy)
482     return buildCopy(Dst, Src);
483 
484   unsigned Opcode;
485   if (SrcTy.isPointer() && DstTy.isScalar())
486     Opcode = TargetOpcode::G_PTRTOINT;
487   else if (DstTy.isPointer() && SrcTy.isScalar())
488     Opcode = TargetOpcode::G_INTTOPTR;
489   else {
490     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
491     Opcode = TargetOpcode::G_BITCAST;
492   }
493 
494   return buildInstr(Opcode, Dst, Src);
495 }
496 
497 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
498                                                    const SrcOp &Src,
499                                                    uint64_t Index) {
500   LLT SrcTy = Src.getLLTTy(*getMRI());
501   LLT DstTy = Dst.getLLTTy(*getMRI());
502 
503 #ifndef NDEBUG
504   assert(SrcTy.isValid() && "invalid operand type");
505   assert(DstTy.isValid() && "invalid operand type");
506   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
507          "extracting off end of register");
508 #endif
509 
510   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
511     assert(Index == 0 && "insertion past the end of a register");
512     return buildCast(Dst, Src);
513   }
514 
515   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
516   Dst.addDefToMIB(*getMRI(), Extract);
517   Src.addSrcToMIB(Extract);
518   Extract.addImm(Index);
519   return Extract;
520 }
521 
522 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
523                                      ArrayRef<uint64_t> Indices) {
524 #ifndef NDEBUG
525   assert(Ops.size() == Indices.size() && "incompatible args");
526   assert(!Ops.empty() && "invalid trivial sequence");
527   assert(llvm::is_sorted(Indices) &&
528          "sequence offsets must be in ascending order");
529 
530   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
531   for (auto Op : Ops)
532     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
533 #endif
534 
535   LLT ResTy = getMRI()->getType(Res);
536   LLT OpTy = getMRI()->getType(Ops[0]);
537   unsigned OpSize = OpTy.getSizeInBits();
538   bool MaybeMerge = true;
539   for (unsigned i = 0; i < Ops.size(); ++i) {
540     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
541       MaybeMerge = false;
542       break;
543     }
544   }
545 
546   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
547     buildMerge(Res, Ops);
548     return;
549   }
550 
551   Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
552   buildUndef(ResIn);
553 
554   for (unsigned i = 0; i < Ops.size(); ++i) {
555     Register ResOut = i + 1 == Ops.size()
556                           ? Res
557                           : getMRI()->createGenericVirtualRegister(ResTy);
558     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
559     ResIn = ResOut;
560   }
561 }
562 
563 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
564   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
565 }
566 
567 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
568                                                  ArrayRef<Register> Ops) {
569   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
570   // we need some temporary storage for the DstOp objects. Here we use a
571   // sufficiently large SmallVector to not go through the heap.
572   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
573   assert(TmpVec.size() > 1);
574   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
575 }
576 
577 MachineInstrBuilder
578 MachineIRBuilder::buildMerge(const DstOp &Res,
579                              std::initializer_list<SrcOp> Ops) {
580   assert(Ops.size() > 1);
581   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
582 }
583 
584 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
585                                                    const SrcOp &Op) {
586   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
587   // we need some temporary storage for the DstOp objects. Here we use a
588   // sufficiently large SmallVector to not go through the heap.
589   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
590   assert(TmpVec.size() > 1);
591   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
592 }
593 
594 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
595                                                    const SrcOp &Op) {
596   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
597   SmallVector<Register, 8> TmpVec;
598   for (unsigned I = 0; I != NumReg; ++I)
599     TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
600   return buildUnmerge(TmpVec, Op);
601 }
602 
603 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
604                                                    const SrcOp &Op) {
605   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
606   // we need some temporary storage for the DstOp objects. Here we use a
607   // sufficiently large SmallVector to not go through the heap.
608   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
609   assert(TmpVec.size() > 1);
610   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
611 }
612 
613 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
614                                                        ArrayRef<Register> Ops) {
615   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
616   // we need some temporary storage for the DstOp objects. Here we use a
617   // sufficiently large SmallVector to not go through the heap.
618   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
619   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
620 }
621 
622 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
623                                                        const SrcOp &Src) {
624   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
625   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
626 }
627 
628 MachineInstrBuilder
629 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
630                                         ArrayRef<Register> Ops) {
631   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
632   // we need some temporary storage for the DstOp objects. Here we use a
633   // sufficiently large SmallVector to not go through the heap.
634   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
635   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
636 }
637 
638 MachineInstrBuilder MachineIRBuilder::buildShuffleSplat(const DstOp &Res,
639                                                         const SrcOp &Src) {
640   LLT DstTy = Res.getLLTTy(*getMRI());
641   LLT SrcTy = Src.getLLTTy(*getMRI());
642   assert(SrcTy == DstTy.getElementType() && "Expected Src to match Dst elt ty");
643   auto UndefVec = buildUndef(DstTy);
644   auto Zero = buildConstant(LLT::scalar(64), 0);
645   auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero);
646   SmallVector<int, 16> ZeroMask(DstTy.getNumElements());
647   return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
648 }
649 
650 MachineInstrBuilder MachineIRBuilder::buildShuffleVector(const DstOp &Res,
651                                                          const SrcOp &Src1,
652                                                          const SrcOp &Src2,
653                                                          ArrayRef<int> Mask) {
654   LLT DstTy = Res.getLLTTy(*getMRI());
655   LLT Src1Ty = Src1.getLLTTy(*getMRI());
656   LLT Src2Ty = Src2.getLLTTy(*getMRI());
657   assert(Src1Ty.getNumElements() + Src2Ty.getNumElements() >= Mask.size());
658   assert(DstTy.getElementType() == Src1Ty.getElementType() &&
659          DstTy.getElementType() == Src2Ty.getElementType());
660   ArrayRef<int> MaskAlloc = getMF().allocateShuffleMask(Mask);
661   return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {DstTy}, {Src1, Src2})
662       .addShuffleMask(MaskAlloc);
663 }
664 
665 MachineInstrBuilder
666 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
667   // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
668   // we need some temporary storage for the DstOp objects. Here we use a
669   // sufficiently large SmallVector to not go through the heap.
670   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
671   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
672 }
673 
674 MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
675                                                   const SrcOp &Src,
676                                                   const SrcOp &Op,
677                                                   unsigned Index) {
678   assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
679              Res.getLLTTy(*getMRI()).getSizeInBits() &&
680          "insertion past the end of a register");
681 
682   if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
683       Op.getLLTTy(*getMRI()).getSizeInBits()) {
684     return buildCast(Res, Op);
685   }
686 
687   return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
688 }
689 
690 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
691                                                      ArrayRef<Register> ResultRegs,
692                                                      bool HasSideEffects) {
693   auto MIB =
694       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
695                                 : TargetOpcode::G_INTRINSIC);
696   for (unsigned ResultReg : ResultRegs)
697     MIB.addDef(ResultReg);
698   MIB.addIntrinsicID(ID);
699   return MIB;
700 }
701 
702 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
703                                                      ArrayRef<DstOp> Results,
704                                                      bool HasSideEffects) {
705   auto MIB =
706       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
707                                 : TargetOpcode::G_INTRINSIC);
708   for (DstOp Result : Results)
709     Result.addDefToMIB(*getMRI(), MIB);
710   MIB.addIntrinsicID(ID);
711   return MIB;
712 }
713 
714 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
715                                                  const SrcOp &Op) {
716   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
717 }
718 
719 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
720                                                    const SrcOp &Op,
721                                                    Optional<unsigned> Flags) {
722   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
723 }
724 
725 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
726                                                 const DstOp &Res,
727                                                 const SrcOp &Op0,
728                                                 const SrcOp &Op1) {
729   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
730 }
731 
732 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
733                                                 const DstOp &Res,
734                                                 const SrcOp &Op0,
735                                                 const SrcOp &Op1,
736                                                 Optional<unsigned> Flags) {
737 
738   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
739 }
740 
741 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
742                                                   const SrcOp &Tst,
743                                                   const SrcOp &Op0,
744                                                   const SrcOp &Op1,
745                                                   Optional<unsigned> Flags) {
746 
747   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
748 }
749 
750 MachineInstrBuilder
751 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
752                                            const SrcOp &Elt, const SrcOp &Idx) {
753   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
754 }
755 
756 MachineInstrBuilder
757 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
758                                             const SrcOp &Idx) {
759   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
760 }
761 
762 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
763     Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
764     Register NewVal, MachineMemOperand &MMO) {
765 #ifndef NDEBUG
766   LLT OldValResTy = getMRI()->getType(OldValRes);
767   LLT SuccessResTy = getMRI()->getType(SuccessRes);
768   LLT AddrTy = getMRI()->getType(Addr);
769   LLT CmpValTy = getMRI()->getType(CmpVal);
770   LLT NewValTy = getMRI()->getType(NewVal);
771   assert(OldValResTy.isScalar() && "invalid operand type");
772   assert(SuccessResTy.isScalar() && "invalid operand type");
773   assert(AddrTy.isPointer() && "invalid operand type");
774   assert(CmpValTy.isValid() && "invalid operand type");
775   assert(NewValTy.isValid() && "invalid operand type");
776   assert(OldValResTy == CmpValTy && "type mismatch");
777   assert(OldValResTy == NewValTy && "type mismatch");
778 #endif
779 
780   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
781       .addDef(OldValRes)
782       .addDef(SuccessRes)
783       .addUse(Addr)
784       .addUse(CmpVal)
785       .addUse(NewVal)
786       .addMemOperand(&MMO);
787 }
788 
789 MachineInstrBuilder
790 MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
791                                      Register CmpVal, Register NewVal,
792                                      MachineMemOperand &MMO) {
793 #ifndef NDEBUG
794   LLT OldValResTy = getMRI()->getType(OldValRes);
795   LLT AddrTy = getMRI()->getType(Addr);
796   LLT CmpValTy = getMRI()->getType(CmpVal);
797   LLT NewValTy = getMRI()->getType(NewVal);
798   assert(OldValResTy.isScalar() && "invalid operand type");
799   assert(AddrTy.isPointer() && "invalid operand type");
800   assert(CmpValTy.isValid() && "invalid operand type");
801   assert(NewValTy.isValid() && "invalid operand type");
802   assert(OldValResTy == CmpValTy && "type mismatch");
803   assert(OldValResTy == NewValTy && "type mismatch");
804 #endif
805 
806   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
807       .addDef(OldValRes)
808       .addUse(Addr)
809       .addUse(CmpVal)
810       .addUse(NewVal)
811       .addMemOperand(&MMO);
812 }
813 
814 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(
815   unsigned Opcode, const DstOp &OldValRes,
816   const SrcOp &Addr, const SrcOp &Val,
817   MachineMemOperand &MMO) {
818 
819 #ifndef NDEBUG
820   LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
821   LLT AddrTy = Addr.getLLTTy(*getMRI());
822   LLT ValTy = Val.getLLTTy(*getMRI());
823   assert(OldValResTy.isScalar() && "invalid operand type");
824   assert(AddrTy.isPointer() && "invalid operand type");
825   assert(ValTy.isValid() && "invalid operand type");
826   assert(OldValResTy == ValTy && "type mismatch");
827   assert(MMO.isAtomic() && "not atomic mem operand");
828 #endif
829 
830   auto MIB = buildInstr(Opcode);
831   OldValRes.addDefToMIB(*getMRI(), MIB);
832   Addr.addSrcToMIB(MIB);
833   Val.addSrcToMIB(MIB);
834   MIB.addMemOperand(&MMO);
835   return MIB;
836 }
837 
838 MachineInstrBuilder
839 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
840                                      Register Val, MachineMemOperand &MMO) {
841   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
842                         MMO);
843 }
844 MachineInstrBuilder
845 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
846                                     Register Val, MachineMemOperand &MMO) {
847   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
848                         MMO);
849 }
850 MachineInstrBuilder
851 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
852                                     Register Val, MachineMemOperand &MMO) {
853   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
854                         MMO);
855 }
856 MachineInstrBuilder
857 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
858                                     Register Val, MachineMemOperand &MMO) {
859   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
860                         MMO);
861 }
862 MachineInstrBuilder
863 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
864                                      Register Val, MachineMemOperand &MMO) {
865   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
866                         MMO);
867 }
868 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
869                                                        Register Addr,
870                                                        Register Val,
871                                                        MachineMemOperand &MMO) {
872   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
873                         MMO);
874 }
875 MachineInstrBuilder
876 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
877                                     Register Val, MachineMemOperand &MMO) {
878   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
879                         MMO);
880 }
881 MachineInstrBuilder
882 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
883                                     Register Val, MachineMemOperand &MMO) {
884   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
885                         MMO);
886 }
887 MachineInstrBuilder
888 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
889                                     Register Val, MachineMemOperand &MMO) {
890   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
891                         MMO);
892 }
893 MachineInstrBuilder
894 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
895                                      Register Val, MachineMemOperand &MMO) {
896   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
897                         MMO);
898 }
899 MachineInstrBuilder
900 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
901                                      Register Val, MachineMemOperand &MMO) {
902   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
903                         MMO);
904 }
905 
906 MachineInstrBuilder
907 MachineIRBuilder::buildAtomicRMWFAdd(
908   const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
909   MachineMemOperand &MMO) {
910   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
911                         MMO);
912 }
913 
914 MachineInstrBuilder
915 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
916                                      MachineMemOperand &MMO) {
917   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
918                         MMO);
919 }
920 
921 MachineInstrBuilder
922 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
923   return buildInstr(TargetOpcode::G_FENCE)
924     .addImm(Ordering)
925     .addImm(Scope);
926 }
927 
928 MachineInstrBuilder
929 MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
930 #ifndef NDEBUG
931   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
932 #endif
933 
934   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
935 }
936 
937 void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
938                                         bool IsExtend) {
939 #ifndef NDEBUG
940   if (DstTy.isVector()) {
941     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
942     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
943            "different number of elements in a trunc/ext");
944   } else
945     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
946 
947   if (IsExtend)
948     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
949            "invalid narrowing extend");
950   else
951     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
952            "invalid widening trunc");
953 #endif
954 }
955 
956 void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
957                                         const LLT Op0Ty, const LLT Op1Ty) {
958 #ifndef NDEBUG
959   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
960          "invalid operand type");
961   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
962   if (ResTy.isScalar() || ResTy.isPointer())
963     assert(TstTy.isScalar() && "type mismatch");
964   else
965     assert((TstTy.isScalar() ||
966             (TstTy.isVector() &&
967              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
968            "type mismatch");
969 #endif
970 }
971 
972 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
973                                                  ArrayRef<DstOp> DstOps,
974                                                  ArrayRef<SrcOp> SrcOps,
975                                                  Optional<unsigned> Flags) {
976   switch (Opc) {
977   default:
978     break;
979   case TargetOpcode::G_SELECT: {
980     assert(DstOps.size() == 1 && "Invalid select");
981     assert(SrcOps.size() == 3 && "Invalid select");
982     validateSelectOp(
983         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
984         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
985     break;
986   }
987   case TargetOpcode::G_FNEG:
988   case TargetOpcode::G_ABS:
989     // All these are unary ops.
990     assert(DstOps.size() == 1 && "Invalid Dst");
991     assert(SrcOps.size() == 1 && "Invalid Srcs");
992     validateUnaryOp(DstOps[0].getLLTTy(*getMRI()),
993                     SrcOps[0].getLLTTy(*getMRI()));
994     break;
995   case TargetOpcode::G_ADD:
996   case TargetOpcode::G_AND:
997   case TargetOpcode::G_MUL:
998   case TargetOpcode::G_OR:
999   case TargetOpcode::G_SUB:
1000   case TargetOpcode::G_XOR:
1001   case TargetOpcode::G_UDIV:
1002   case TargetOpcode::G_SDIV:
1003   case TargetOpcode::G_UREM:
1004   case TargetOpcode::G_SREM:
1005   case TargetOpcode::G_SMIN:
1006   case TargetOpcode::G_SMAX:
1007   case TargetOpcode::G_UMIN:
1008   case TargetOpcode::G_UMAX:
1009   case TargetOpcode::G_UADDSAT:
1010   case TargetOpcode::G_SADDSAT:
1011   case TargetOpcode::G_USUBSAT:
1012   case TargetOpcode::G_SSUBSAT: {
1013     // All these are binary ops.
1014     assert(DstOps.size() == 1 && "Invalid Dst");
1015     assert(SrcOps.size() == 2 && "Invalid Srcs");
1016     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
1017                      SrcOps[0].getLLTTy(*getMRI()),
1018                      SrcOps[1].getLLTTy(*getMRI()));
1019     break;
1020   }
1021   case TargetOpcode::G_SHL:
1022   case TargetOpcode::G_ASHR:
1023   case TargetOpcode::G_LSHR:
1024   case TargetOpcode::G_USHLSAT:
1025   case TargetOpcode::G_SSHLSAT: {
1026     assert(DstOps.size() == 1 && "Invalid Dst");
1027     assert(SrcOps.size() == 2 && "Invalid Srcs");
1028     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
1029                     SrcOps[0].getLLTTy(*getMRI()),
1030                     SrcOps[1].getLLTTy(*getMRI()));
1031     break;
1032   }
1033   case TargetOpcode::G_SEXT:
1034   case TargetOpcode::G_ZEXT:
1035   case TargetOpcode::G_ANYEXT:
1036     assert(DstOps.size() == 1 && "Invalid Dst");
1037     assert(SrcOps.size() == 1 && "Invalid Srcs");
1038     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1039                      SrcOps[0].getLLTTy(*getMRI()), true);
1040     break;
1041   case TargetOpcode::G_TRUNC:
1042   case TargetOpcode::G_FPTRUNC: {
1043     assert(DstOps.size() == 1 && "Invalid Dst");
1044     assert(SrcOps.size() == 1 && "Invalid Srcs");
1045     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1046                      SrcOps[0].getLLTTy(*getMRI()), false);
1047     break;
1048   }
1049   case TargetOpcode::G_BITCAST: {
1050     assert(DstOps.size() == 1 && "Invalid Dst");
1051     assert(SrcOps.size() == 1 && "Invalid Srcs");
1052     assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1053            SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
1054     break;
1055   }
1056   case TargetOpcode::COPY:
1057     assert(DstOps.size() == 1 && "Invalid Dst");
1058     // If the caller wants to add a subreg source it has to be done separately
1059     // so we may not have any SrcOps at this point yet.
1060     break;
1061   case TargetOpcode::G_FCMP:
1062   case TargetOpcode::G_ICMP: {
1063     assert(DstOps.size() == 1 && "Invalid Dst Operands");
1064     assert(SrcOps.size() == 3 && "Invalid Src Operands");
1065     // For F/ICMP, the first src operand is the predicate, followed by
1066     // the two comparands.
1067     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1068            "Expecting predicate");
1069     assert([&]() -> bool {
1070       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1071       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1072                                          : CmpInst::isFPPredicate(Pred);
1073     }() && "Invalid predicate");
1074     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1075            "Type mismatch");
1076     assert([&]() -> bool {
1077       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1078       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1079       if (Op0Ty.isScalar() || Op0Ty.isPointer())
1080         return DstTy.isScalar();
1081       else
1082         return DstTy.isVector() &&
1083                DstTy.getNumElements() == Op0Ty.getNumElements();
1084     }() && "Type Mismatch");
1085     break;
1086   }
1087   case TargetOpcode::G_UNMERGE_VALUES: {
1088     assert(!DstOps.empty() && "Invalid trivial sequence");
1089     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1090     assert(std::all_of(DstOps.begin(), DstOps.end(),
1091                        [&, this](const DstOp &Op) {
1092                          return Op.getLLTTy(*getMRI()) ==
1093                                 DstOps[0].getLLTTy(*getMRI());
1094                        }) &&
1095            "type mismatch in output list");
1096     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1097                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1098            "input operands do not cover output register");
1099     break;
1100   }
1101   case TargetOpcode::G_MERGE_VALUES: {
1102     assert(!SrcOps.empty() && "invalid trivial sequence");
1103     assert(DstOps.size() == 1 && "Invalid Dst");
1104     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1105                        [&, this](const SrcOp &Op) {
1106                          return Op.getLLTTy(*getMRI()) ==
1107                                 SrcOps[0].getLLTTy(*getMRI());
1108                        }) &&
1109            "type mismatch in input list");
1110     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1111                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1112            "input operands do not cover output register");
1113     if (SrcOps.size() == 1)
1114       return buildCast(DstOps[0], SrcOps[0]);
1115     if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
1116       if (SrcOps[0].getLLTTy(*getMRI()).isVector())
1117         return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1118       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1119     }
1120     break;
1121   }
1122   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1123     assert(DstOps.size() == 1 && "Invalid Dst size");
1124     assert(SrcOps.size() == 2 && "Invalid Src size");
1125     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1126     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1127             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1128            "Invalid operand type");
1129     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1130     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1131                DstOps[0].getLLTTy(*getMRI()) &&
1132            "Type mismatch");
1133     break;
1134   }
1135   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1136     assert(DstOps.size() == 1 && "Invalid dst size");
1137     assert(SrcOps.size() == 3 && "Invalid src size");
1138     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1139            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1140     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1141                SrcOps[1].getLLTTy(*getMRI()) &&
1142            "Type mismatch");
1143     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1144     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1145                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1146            "Type mismatch");
1147     break;
1148   }
1149   case TargetOpcode::G_BUILD_VECTOR: {
1150     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1151            "Must have at least 2 operands");
1152     assert(DstOps.size() == 1 && "Invalid DstOps");
1153     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1154            "Res type must be a vector");
1155     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1156                        [&, this](const SrcOp &Op) {
1157                          return Op.getLLTTy(*getMRI()) ==
1158                                 SrcOps[0].getLLTTy(*getMRI());
1159                        }) &&
1160            "type mismatch in input list");
1161     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1162                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1163            "input scalars do not exactly cover the output vector register");
1164     break;
1165   }
1166   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1167     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1168            "Must have at least 2 operands");
1169     assert(DstOps.size() == 1 && "Invalid DstOps");
1170     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1171            "Res type must be a vector");
1172     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1173                        [&, this](const SrcOp &Op) {
1174                          return Op.getLLTTy(*getMRI()) ==
1175                                 SrcOps[0].getLLTTy(*getMRI());
1176                        }) &&
1177            "type mismatch in input list");
1178     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1179         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1180       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1181     break;
1182   }
1183   case TargetOpcode::G_CONCAT_VECTORS: {
1184     assert(DstOps.size() == 1 && "Invalid DstOps");
1185     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1186            "Must have at least 2 operands");
1187     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1188                        [&, this](const SrcOp &Op) {
1189                          return (Op.getLLTTy(*getMRI()).isVector() &&
1190                                  Op.getLLTTy(*getMRI()) ==
1191                                      SrcOps[0].getLLTTy(*getMRI()));
1192                        }) &&
1193            "type mismatch in input list");
1194     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1195                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1196            "input vectors do not exactly cover the output vector register");
1197     break;
1198   }
1199   case TargetOpcode::G_UADDE: {
1200     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1201     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1202     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1203     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1204            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1205            "Invalid operand");
1206     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1207     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1208            "type mismatch");
1209     break;
1210   }
1211   }
1212 
1213   auto MIB = buildInstr(Opc);
1214   for (const DstOp &Op : DstOps)
1215     Op.addDefToMIB(*getMRI(), MIB);
1216   for (const SrcOp &Op : SrcOps)
1217     Op.addSrcToMIB(MIB);
1218   if (Flags)
1219     MIB->setFlags(*Flags);
1220   return MIB;
1221 }
1222