1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
164   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165   return buildInstr(TargetOpcode::G_FRAME_INDEX)
166       .addDef(Res)
167       .addFrameIndex(Idx);
168 }
169 
170 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
171                                                        const GlobalValue *GV) {
172   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173   assert(getMRI()->getType(Res).getAddressSpace() ==
174              GV->getType()->getAddressSpace() &&
175          "address space mismatch");
176 
177   return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178       .addDef(Res)
179       .addGlobalAddress(GV);
180 }
181 
182 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
183                                         const LLT &Op1) {
184   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
185   assert((Res == Op0 && Res == Op1) && "type mismatch");
186 }
187 
188 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
189                                        const LLT &Op1) {
190   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
191   assert((Res == Op0) && "type mismatch");
192 }
193 
194 MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
195                                                unsigned Op1) {
196   assert(getMRI()->getType(Res).isPointer() &&
197          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
198   assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
199 
200   return buildInstr(TargetOpcode::G_GEP)
201       .addDef(Res)
202       .addUse(Op0)
203       .addUse(Op1);
204 }
205 
206 Optional<MachineInstrBuilder>
207 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
208                                  const LLT &ValueTy, uint64_t Value) {
209   assert(Res == 0 && "Res is a result argument");
210   assert(ValueTy.isScalar()  && "invalid offset type");
211 
212   if (Value == 0) {
213     Res = Op0;
214     return None;
215   }
216 
217   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
218   unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
219 
220   buildConstant(TmpReg, Value);
221   return buildGEP(Res, Op0, TmpReg);
222 }
223 
224 MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
225                                                    uint32_t NumBits) {
226   assert(getMRI()->getType(Res).isPointer() &&
227          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
228 
229   return buildInstr(TargetOpcode::G_PTR_MASK)
230       .addDef(Res)
231       .addUse(Op0)
232       .addImm(NumBits);
233 }
234 
235 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
236   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
237 }
238 
239 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
240   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
241   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
242 }
243 
244 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
245                                                 const SrcOp &Op) {
246   return buildInstr(TargetOpcode::COPY, Res, Op);
247 }
248 
249 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
250                                                     const ConstantInt &Val) {
251   LLT Ty = Res.getLLTTy(*getMRI());
252   LLT EltTy = Ty.getScalarType();
253   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
254          "creating constant with the wrong size");
255 
256   if (Ty.isVector()) {
257     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
258     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
259     .addCImm(&Val);
260     return buildSplatVector(Res, Const);
261   }
262 
263   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
264   Res.addDefToMIB(*getMRI(), Const);
265   Const.addCImm(&Val);
266   return Const;
267 }
268 
269 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
270                                                     int64_t Val) {
271   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
272                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
273   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
274   return buildConstant(Res, *CI);
275 }
276 
277 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
278                                                      const ConstantFP &Val) {
279   LLT Ty = Res.getLLTTy(*getMRI());
280   LLT EltTy = Ty.getScalarType();
281 
282   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
283          == EltTy.getSizeInBits() &&
284          "creating fconstant with the wrong size");
285 
286   assert(!Ty.isPointer() && "invalid operand type");
287 
288   if (Ty.isVector()) {
289     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
290     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
291     .addFPImm(&Val);
292 
293     return buildSplatVector(Res, Const);
294   }
295 
296   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
297   Res.addDefToMIB(*getMRI(), Const);
298   Const.addFPImm(&Val);
299   return Const;
300 }
301 
302 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
303                                                     const APInt &Val) {
304   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
305   return buildConstant(Res, *CI);
306 }
307 
308 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
309                                                      double Val) {
310   LLT DstTy = Res.getLLTTy(*getMRI());
311   auto &Ctx = getMF().getFunction().getContext();
312   auto *CFP =
313       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
314   return buildFConstant(Res, *CFP);
315 }
316 
317 MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
318                                                   MachineBasicBlock &Dest) {
319   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
320 
321   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
322 }
323 
324 MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
325                                                 MachineMemOperand &MMO) {
326   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
327 }
328 
329 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
330                                                      unsigned Res,
331                                                      unsigned Addr,
332                                                      MachineMemOperand &MMO) {
333   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
334   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
335 
336   return buildInstr(Opcode)
337       .addDef(Res)
338       .addUse(Addr)
339       .addMemOperand(&MMO);
340 }
341 
342 MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
343                                                  MachineMemOperand &MMO) {
344   assert(getMRI()->getType(Val).isValid() && "invalid operand type");
345   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
346 
347   return buildInstr(TargetOpcode::G_STORE)
348       .addUse(Val)
349       .addUse(Addr)
350       .addMemOperand(&MMO);
351 }
352 
353 MachineInstrBuilder MachineIRBuilder::buildUAddo(const DstOp &Res,
354                                                  const DstOp &CarryOut,
355                                                  const SrcOp &Op0,
356                                                  const SrcOp &Op1) {
357   return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
358 }
359 
360 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
361                                                  const DstOp &CarryOut,
362                                                  const SrcOp &Op0,
363                                                  const SrcOp &Op1,
364                                                  const SrcOp &CarryIn) {
365   return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
366                     {Op0, Op1, CarryIn});
367 }
368 
369 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
370                                                   const SrcOp &Op) {
371   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
372 }
373 
374 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
375                                                 const SrcOp &Op) {
376   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
377 }
378 
379 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
380                                                 const SrcOp &Op) {
381   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
382 }
383 
384 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
385   const auto *TLI = getMF().getSubtarget().getTargetLowering();
386   switch (TLI->getBooleanContents(IsVec, IsFP)) {
387   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
388     return TargetOpcode::G_SEXT;
389   case TargetLoweringBase::ZeroOrOneBooleanContent:
390     return TargetOpcode::G_ZEXT;
391   default:
392     return TargetOpcode::G_ANYEXT;
393   }
394 }
395 
396 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
397                                                    const SrcOp &Op,
398                                                    bool IsFP) {
399   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
400   return buildInstr(ExtOp, Res, Op);
401 }
402 
403 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
404                                                       const DstOp &Res,
405                                                       const SrcOp &Op) {
406   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
407           TargetOpcode::G_SEXT == ExtOpc) &&
408          "Expecting Extending Opc");
409   assert(Res.getLLTTy(*getMRI()).isScalar() ||
410          Res.getLLTTy(*getMRI()).isVector());
411   assert(Res.getLLTTy(*getMRI()).isScalar() ==
412          Op.getLLTTy(*getMRI()).isScalar());
413 
414   unsigned Opcode = TargetOpcode::COPY;
415   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
416       Op.getLLTTy(*getMRI()).getSizeInBits())
417     Opcode = ExtOpc;
418   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
419            Op.getLLTTy(*getMRI()).getSizeInBits())
420     Opcode = TargetOpcode::G_TRUNC;
421   else
422     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
423 
424   return buildInstr(Opcode, Res, Op);
425 }
426 
427 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
428                                                        const SrcOp &Op) {
429   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
430 }
431 
432 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
433                                                        const SrcOp &Op) {
434   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
435 }
436 
437 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
438                                                          const SrcOp &Op) {
439   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
440 }
441 
442 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
443                                                 const SrcOp &Src) {
444   LLT SrcTy = Src.getLLTTy(*getMRI());
445   LLT DstTy = Dst.getLLTTy(*getMRI());
446   if (SrcTy == DstTy)
447     return buildCopy(Dst, Src);
448 
449   unsigned Opcode;
450   if (SrcTy.isPointer() && DstTy.isScalar())
451     Opcode = TargetOpcode::G_PTRTOINT;
452   else if (DstTy.isPointer() && SrcTy.isScalar())
453     Opcode = TargetOpcode::G_INTTOPTR;
454   else {
455     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
456     Opcode = TargetOpcode::G_BITCAST;
457   }
458 
459   return buildInstr(Opcode, Dst, Src);
460 }
461 
462 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
463                                                    const SrcOp &Src,
464                                                    uint64_t Index) {
465   LLT SrcTy = Src.getLLTTy(*getMRI());
466   LLT DstTy = Dst.getLLTTy(*getMRI());
467 
468 #ifndef NDEBUG
469   assert(SrcTy.isValid() && "invalid operand type");
470   assert(DstTy.isValid() && "invalid operand type");
471   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
472          "extracting off end of register");
473 #endif
474 
475   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
476     assert(Index == 0 && "insertion past the end of a register");
477     return buildCast(Dst, Src);
478   }
479 
480   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
481   Dst.addDefToMIB(*getMRI(), Extract);
482   Src.addSrcToMIB(Extract);
483   Extract.addImm(Index);
484   return Extract;
485 }
486 
487 void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
488                                      ArrayRef<uint64_t> Indices) {
489 #ifndef NDEBUG
490   assert(Ops.size() == Indices.size() && "incompatible args");
491   assert(!Ops.empty() && "invalid trivial sequence");
492   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
493          "sequence offsets must be in ascending order");
494 
495   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
496   for (auto Op : Ops)
497     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
498 #endif
499 
500   LLT ResTy = getMRI()->getType(Res);
501   LLT OpTy = getMRI()->getType(Ops[0]);
502   unsigned OpSize = OpTy.getSizeInBits();
503   bool MaybeMerge = true;
504   for (unsigned i = 0; i < Ops.size(); ++i) {
505     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
506       MaybeMerge = false;
507       break;
508     }
509   }
510 
511   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
512     buildMerge(Res, Ops);
513     return;
514   }
515 
516   unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
517   buildUndef(ResIn);
518 
519   for (unsigned i = 0; i < Ops.size(); ++i) {
520     unsigned ResOut = i + 1 == Ops.size()
521                           ? Res
522                           : getMRI()->createGenericVirtualRegister(ResTy);
523     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
524     ResIn = ResOut;
525   }
526 }
527 
528 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
529   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
530 }
531 
532 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
533                                                  ArrayRef<unsigned> Ops) {
534   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
535   // we need some temporary storage for the DstOp objects. Here we use a
536   // sufficiently large SmallVector to not go through the heap.
537   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
538   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
539 }
540 
541 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
542                                                    const SrcOp &Op) {
543   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
544   // we need some temporary storage for the DstOp objects. Here we use a
545   // sufficiently large SmallVector to not go through the heap.
546   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
547   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
548 }
549 
550 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
551                                                    const SrcOp &Op) {
552   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
553   SmallVector<unsigned, 8> TmpVec;
554   for (unsigned I = 0; I != NumReg; ++I)
555     TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
556   return buildUnmerge(TmpVec, Op);
557 }
558 
559 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
560                                                    const SrcOp &Op) {
561   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
562   // we need some temporary storage for the DstOp objects. Here we use a
563   // sufficiently large SmallVector to not go through the heap.
564   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
565   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
566 }
567 
568 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
569                                                        ArrayRef<unsigned> Ops) {
570   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
571   // we need some temporary storage for the DstOp objects. Here we use a
572   // sufficiently large SmallVector to not go through the heap.
573   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
574   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
575 }
576 
577 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
578                                                        const SrcOp &Src) {
579   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
580   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
581 }
582 
583 MachineInstrBuilder
584 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
585                                         ArrayRef<unsigned> Ops) {
586   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
587   // we need some temporary storage for the DstOp objects. Here we use a
588   // sufficiently large SmallVector to not go through the heap.
589   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
590   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
591 }
592 
593 MachineInstrBuilder
594 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
595   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
596   // we need some temporary storage for the DstOp objects. Here we use a
597   // sufficiently large SmallVector to not go through the heap.
598   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
599   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
600 }
601 
602 MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
603                                                   unsigned Op, unsigned Index) {
604   assert(Index + getMRI()->getType(Op).getSizeInBits() <=
605              getMRI()->getType(Res).getSizeInBits() &&
606          "insertion past the end of a register");
607 
608   if (getMRI()->getType(Res).getSizeInBits() ==
609       getMRI()->getType(Op).getSizeInBits()) {
610     return buildCast(Res, Op);
611   }
612 
613   return buildInstr(TargetOpcode::G_INSERT)
614       .addDef(Res)
615       .addUse(Src)
616       .addUse(Op)
617       .addImm(Index);
618 }
619 
620 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
621                                                      ArrayRef<unsigned> ResultRegs,
622                                                      bool HasSideEffects) {
623   auto MIB =
624       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
625                                 : TargetOpcode::G_INTRINSIC);
626   for (unsigned ResultReg : ResultRegs)
627     MIB.addDef(ResultReg);
628   MIB.addIntrinsicID(ID);
629   return MIB;
630 }
631 
632 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
633                                                  const SrcOp &Op) {
634   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
635 }
636 
637 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
638                                                    const SrcOp &Op) {
639   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
640 }
641 
642 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
643                                                 const DstOp &Res,
644                                                 const SrcOp &Op0,
645                                                 const SrcOp &Op1) {
646   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
647 }
648 
649 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
650                                                 const DstOp &Res,
651                                                 const SrcOp &Op0,
652                                                 const SrcOp &Op1) {
653 
654   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
655 }
656 
657 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
658                                                   const SrcOp &Tst,
659                                                   const SrcOp &Op0,
660                                                   const SrcOp &Op1) {
661 
662   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
663 }
664 
665 MachineInstrBuilder
666 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
667                                            const SrcOp &Elt, const SrcOp &Idx) {
668   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
669 }
670 
671 MachineInstrBuilder
672 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
673                                             const SrcOp &Idx) {
674   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
675 }
676 
677 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
678     unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
679     unsigned NewVal, MachineMemOperand &MMO) {
680 #ifndef NDEBUG
681   LLT OldValResTy = getMRI()->getType(OldValRes);
682   LLT SuccessResTy = getMRI()->getType(SuccessRes);
683   LLT AddrTy = getMRI()->getType(Addr);
684   LLT CmpValTy = getMRI()->getType(CmpVal);
685   LLT NewValTy = getMRI()->getType(NewVal);
686   assert(OldValResTy.isScalar() && "invalid operand type");
687   assert(SuccessResTy.isScalar() && "invalid operand type");
688   assert(AddrTy.isPointer() && "invalid operand type");
689   assert(CmpValTy.isValid() && "invalid operand type");
690   assert(NewValTy.isValid() && "invalid operand type");
691   assert(OldValResTy == CmpValTy && "type mismatch");
692   assert(OldValResTy == NewValTy && "type mismatch");
693 #endif
694 
695   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
696       .addDef(OldValRes)
697       .addDef(SuccessRes)
698       .addUse(Addr)
699       .addUse(CmpVal)
700       .addUse(NewVal)
701       .addMemOperand(&MMO);
702 }
703 
704 MachineInstrBuilder
705 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
706                                      unsigned CmpVal, unsigned NewVal,
707                                      MachineMemOperand &MMO) {
708 #ifndef NDEBUG
709   LLT OldValResTy = getMRI()->getType(OldValRes);
710   LLT AddrTy = getMRI()->getType(Addr);
711   LLT CmpValTy = getMRI()->getType(CmpVal);
712   LLT NewValTy = getMRI()->getType(NewVal);
713   assert(OldValResTy.isScalar() && "invalid operand type");
714   assert(AddrTy.isPointer() && "invalid operand type");
715   assert(CmpValTy.isValid() && "invalid operand type");
716   assert(NewValTy.isValid() && "invalid operand type");
717   assert(OldValResTy == CmpValTy && "type mismatch");
718   assert(OldValResTy == NewValTy && "type mismatch");
719 #endif
720 
721   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
722       .addDef(OldValRes)
723       .addUse(Addr)
724       .addUse(CmpVal)
725       .addUse(NewVal)
726       .addMemOperand(&MMO);
727 }
728 
729 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
730                                                      unsigned OldValRes,
731                                                      unsigned Addr,
732                                                      unsigned Val,
733                                                      MachineMemOperand &MMO) {
734 #ifndef NDEBUG
735   LLT OldValResTy = getMRI()->getType(OldValRes);
736   LLT AddrTy = getMRI()->getType(Addr);
737   LLT ValTy = getMRI()->getType(Val);
738   assert(OldValResTy.isScalar() && "invalid operand type");
739   assert(AddrTy.isPointer() && "invalid operand type");
740   assert(ValTy.isValid() && "invalid operand type");
741   assert(OldValResTy == ValTy && "type mismatch");
742 #endif
743 
744   return buildInstr(Opcode)
745       .addDef(OldValRes)
746       .addUse(Addr)
747       .addUse(Val)
748       .addMemOperand(&MMO);
749 }
750 
751 MachineInstrBuilder
752 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
753                                      unsigned Val, MachineMemOperand &MMO) {
754   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
755                         MMO);
756 }
757 MachineInstrBuilder
758 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
759                                     unsigned Val, MachineMemOperand &MMO) {
760   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
761                         MMO);
762 }
763 MachineInstrBuilder
764 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
765                                     unsigned Val, MachineMemOperand &MMO) {
766   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
767                         MMO);
768 }
769 MachineInstrBuilder
770 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
771                                     unsigned Val, MachineMemOperand &MMO) {
772   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
773                         MMO);
774 }
775 MachineInstrBuilder
776 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
777                                      unsigned Val, MachineMemOperand &MMO) {
778   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
779                         MMO);
780 }
781 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
782                                                        unsigned Addr,
783                                                        unsigned Val,
784                                                        MachineMemOperand &MMO) {
785   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
786                         MMO);
787 }
788 MachineInstrBuilder
789 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
790                                     unsigned Val, MachineMemOperand &MMO) {
791   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
792                         MMO);
793 }
794 MachineInstrBuilder
795 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
796                                     unsigned Val, MachineMemOperand &MMO) {
797   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
798                         MMO);
799 }
800 MachineInstrBuilder
801 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
802                                     unsigned Val, MachineMemOperand &MMO) {
803   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
804                         MMO);
805 }
806 MachineInstrBuilder
807 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
808                                      unsigned Val, MachineMemOperand &MMO) {
809   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
810                         MMO);
811 }
812 MachineInstrBuilder
813 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
814                                      unsigned Val, MachineMemOperand &MMO) {
815   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
816                         MMO);
817 }
818 
819 MachineInstrBuilder
820 MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
821 #ifndef NDEBUG
822   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
823 #endif
824 
825   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
826 }
827 
828 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
829                                         bool IsExtend) {
830 #ifndef NDEBUG
831   if (DstTy.isVector()) {
832     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
833     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
834            "different number of elements in a trunc/ext");
835   } else
836     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
837 
838   if (IsExtend)
839     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
840            "invalid narrowing extend");
841   else
842     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
843            "invalid widening trunc");
844 #endif
845 }
846 
847 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
848                                         const LLT &Op0Ty, const LLT &Op1Ty) {
849 #ifndef NDEBUG
850   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
851          "invalid operand type");
852   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
853   if (ResTy.isScalar() || ResTy.isPointer())
854     assert(TstTy.isScalar() && "type mismatch");
855   else
856     assert((TstTy.isScalar() ||
857             (TstTy.isVector() &&
858              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
859            "type mismatch");
860 #endif
861 }
862 
863 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
864                                                  ArrayRef<DstOp> DstOps,
865                                                  ArrayRef<SrcOp> SrcOps,
866                                                  Optional<unsigned> Flags) {
867   switch (Opc) {
868   default:
869     break;
870   case TargetOpcode::G_SELECT: {
871     assert(DstOps.size() == 1 && "Invalid select");
872     assert(SrcOps.size() == 3 && "Invalid select");
873     validateSelectOp(
874         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
875         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
876     break;
877   }
878   case TargetOpcode::G_ADD:
879   case TargetOpcode::G_AND:
880   case TargetOpcode::G_MUL:
881   case TargetOpcode::G_OR:
882   case TargetOpcode::G_SUB:
883   case TargetOpcode::G_XOR:
884   case TargetOpcode::G_UDIV:
885   case TargetOpcode::G_SDIV:
886   case TargetOpcode::G_UREM:
887   case TargetOpcode::G_SREM: {
888     // All these are binary ops.
889     assert(DstOps.size() == 1 && "Invalid Dst");
890     assert(SrcOps.size() == 2 && "Invalid Srcs");
891     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
892                      SrcOps[0].getLLTTy(*getMRI()),
893                      SrcOps[1].getLLTTy(*getMRI()));
894     break;
895   }
896   case TargetOpcode::G_SHL:
897   case TargetOpcode::G_ASHR:
898   case TargetOpcode::G_LSHR: {
899     assert(DstOps.size() == 1 && "Invalid Dst");
900     assert(SrcOps.size() == 2 && "Invalid Srcs");
901     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
902                     SrcOps[0].getLLTTy(*getMRI()),
903                     SrcOps[1].getLLTTy(*getMRI()));
904     break;
905   }
906   case TargetOpcode::G_SEXT:
907   case TargetOpcode::G_ZEXT:
908   case TargetOpcode::G_ANYEXT:
909     assert(DstOps.size() == 1 && "Invalid Dst");
910     assert(SrcOps.size() == 1 && "Invalid Srcs");
911     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
912                      SrcOps[0].getLLTTy(*getMRI()), true);
913     break;
914   case TargetOpcode::G_TRUNC:
915   case TargetOpcode::G_FPTRUNC: {
916     assert(DstOps.size() == 1 && "Invalid Dst");
917     assert(SrcOps.size() == 1 && "Invalid Srcs");
918     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
919                      SrcOps[0].getLLTTy(*getMRI()), false);
920     break;
921   }
922   case TargetOpcode::COPY:
923     assert(DstOps.size() == 1 && "Invalid Dst");
924     // If the caller wants to add a subreg source it has to be done separately
925     // so we may not have any SrcOps at this point yet.
926     break;
927   case TargetOpcode::G_FCMP:
928   case TargetOpcode::G_ICMP: {
929     assert(DstOps.size() == 1 && "Invalid Dst Operands");
930     assert(SrcOps.size() == 3 && "Invalid Src Operands");
931     // For F/ICMP, the first src operand is the predicate, followed by
932     // the two comparands.
933     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
934            "Expecting predicate");
935     assert([&]() -> bool {
936       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
937       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
938                                          : CmpInst::isFPPredicate(Pred);
939     }() && "Invalid predicate");
940     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
941            "Type mismatch");
942     assert([&]() -> bool {
943       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
944       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
945       if (Op0Ty.isScalar() || Op0Ty.isPointer())
946         return DstTy.isScalar();
947       else
948         return DstTy.isVector() &&
949                DstTy.getNumElements() == Op0Ty.getNumElements();
950     }() && "Type Mismatch");
951     break;
952   }
953   case TargetOpcode::G_UNMERGE_VALUES: {
954     assert(!DstOps.empty() && "Invalid trivial sequence");
955     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
956     assert(std::all_of(DstOps.begin(), DstOps.end(),
957                        [&, this](const DstOp &Op) {
958                          return Op.getLLTTy(*getMRI()) ==
959                                 DstOps[0].getLLTTy(*getMRI());
960                        }) &&
961            "type mismatch in output list");
962     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
963                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
964            "input operands do not cover output register");
965     break;
966   }
967   case TargetOpcode::G_MERGE_VALUES: {
968     assert(!SrcOps.empty() && "invalid trivial sequence");
969     assert(DstOps.size() == 1 && "Invalid Dst");
970     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
971                        [&, this](const SrcOp &Op) {
972                          return Op.getLLTTy(*getMRI()) ==
973                                 SrcOps[0].getLLTTy(*getMRI());
974                        }) &&
975            "type mismatch in input list");
976     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
977                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
978            "input operands do not cover output register");
979     if (SrcOps.size() == 1)
980       return buildCast(DstOps[0], SrcOps[0]);
981     if (DstOps[0].getLLTTy(*getMRI()).isVector())
982       return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
983     break;
984   }
985   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
986     assert(DstOps.size() == 1 && "Invalid Dst size");
987     assert(SrcOps.size() == 2 && "Invalid Src size");
988     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
989     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
990             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
991            "Invalid operand type");
992     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
993     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
994                DstOps[0].getLLTTy(*getMRI()) &&
995            "Type mismatch");
996     break;
997   }
998   case TargetOpcode::G_INSERT_VECTOR_ELT: {
999     assert(DstOps.size() == 1 && "Invalid dst size");
1000     assert(SrcOps.size() == 3 && "Invalid src size");
1001     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1002            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1003     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1004                SrcOps[1].getLLTTy(*getMRI()) &&
1005            "Type mismatch");
1006     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1007     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1008                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1009            "Type mismatch");
1010     break;
1011   }
1012   case TargetOpcode::G_BUILD_VECTOR: {
1013     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1014            "Must have at least 2 operands");
1015     assert(DstOps.size() == 1 && "Invalid DstOps");
1016     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1017            "Res type must be a vector");
1018     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1019                        [&, this](const SrcOp &Op) {
1020                          return Op.getLLTTy(*getMRI()) ==
1021                                 SrcOps[0].getLLTTy(*getMRI());
1022                        }) &&
1023            "type mismatch in input list");
1024     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1025                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1026            "input scalars do not exactly cover the output vector register");
1027     break;
1028   }
1029   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1030     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1031            "Must have at least 2 operands");
1032     assert(DstOps.size() == 1 && "Invalid DstOps");
1033     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1034            "Res type must be a vector");
1035     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1036                        [&, this](const SrcOp &Op) {
1037                          return Op.getLLTTy(*getMRI()) ==
1038                                 SrcOps[0].getLLTTy(*getMRI());
1039                        }) &&
1040            "type mismatch in input list");
1041     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1042         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1043       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1044     break;
1045   }
1046   case TargetOpcode::G_CONCAT_VECTORS: {
1047     assert(DstOps.size() == 1 && "Invalid DstOps");
1048     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1049            "Must have at least 2 operands");
1050     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1051                        [&, this](const SrcOp &Op) {
1052                          return (Op.getLLTTy(*getMRI()).isVector() &&
1053                                  Op.getLLTTy(*getMRI()) ==
1054                                      SrcOps[0].getLLTTy(*getMRI()));
1055                        }) &&
1056            "type mismatch in input list");
1057     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1058                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1059            "input vectors do not exactly cover the output vector register");
1060     break;
1061   }
1062   case TargetOpcode::G_UADDE: {
1063     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1064     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1065     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1066     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1067            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1068            "Invalid operand");
1069     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1070     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1071            "type mismatch");
1072     break;
1073   }
1074   }
1075 
1076   auto MIB = buildInstr(Opc);
1077   for (const DstOp &Op : DstOps)
1078     Op.addDefToMIB(*getMRI(), MIB);
1079   for (const SrcOp &Op : SrcOps)
1080     Op.addSrcToMIB(MIB);
1081   if (Flags)
1082     MIB->setFlags(*Flags);
1083   return MIB;
1084 }
1085