1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
164   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165   return buildInstr(TargetOpcode::G_FRAME_INDEX)
166       .addDef(Res)
167       .addFrameIndex(Idx);
168 }
169 
170 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
171                                                        const GlobalValue *GV) {
172   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173   assert(getMRI()->getType(Res).getAddressSpace() ==
174              GV->getType()->getAddressSpace() &&
175          "address space mismatch");
176 
177   return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178       .addDef(Res)
179       .addGlobalAddress(GV);
180 }
181 
182 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
183                                         const LLT &Op1) {
184   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
185   assert((Res == Op0 && Res == Op1) && "type mismatch");
186 }
187 
188 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
189                                        const LLT &Op1) {
190   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
191   assert((Res == Op0) && "type mismatch");
192 }
193 
194 MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
195                                                unsigned Op1) {
196   assert(getMRI()->getType(Res).isPointer() &&
197          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
198   assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
199 
200   return buildInstr(TargetOpcode::G_GEP)
201       .addDef(Res)
202       .addUse(Op0)
203       .addUse(Op1);
204 }
205 
206 Optional<MachineInstrBuilder>
207 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
208                                  const LLT &ValueTy, uint64_t Value) {
209   assert(Res == 0 && "Res is a result argument");
210   assert(ValueTy.isScalar()  && "invalid offset type");
211 
212   if (Value == 0) {
213     Res = Op0;
214     return None;
215   }
216 
217   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
218   auto Cst = buildConstant(ValueTy, Value);
219   return buildGEP(Res, Op0, Cst.getReg(0));
220 }
221 
222 MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
223                                                    uint32_t NumBits) {
224   assert(getMRI()->getType(Res).isPointer() &&
225          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
226 
227   return buildInstr(TargetOpcode::G_PTR_MASK)
228       .addDef(Res)
229       .addUse(Op0)
230       .addImm(NumBits);
231 }
232 
233 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
234   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
235 }
236 
237 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
238   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
239   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
240 }
241 
242 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
243                                                 const SrcOp &Op) {
244   return buildInstr(TargetOpcode::COPY, Res, Op);
245 }
246 
247 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
248                                                     const ConstantInt &Val) {
249   LLT Ty = Res.getLLTTy(*getMRI());
250   LLT EltTy = Ty.getScalarType();
251   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
252          "creating constant with the wrong size");
253 
254   if (Ty.isVector()) {
255     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
256     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
257     .addCImm(&Val);
258     return buildSplatVector(Res, Const);
259   }
260 
261   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
262   Res.addDefToMIB(*getMRI(), Const);
263   Const.addCImm(&Val);
264   return Const;
265 }
266 
267 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
268                                                     int64_t Val) {
269   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
270                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
271   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
272   return buildConstant(Res, *CI);
273 }
274 
275 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
276                                                      const ConstantFP &Val) {
277   LLT Ty = Res.getLLTTy(*getMRI());
278   LLT EltTy = Ty.getScalarType();
279 
280   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
281          == EltTy.getSizeInBits() &&
282          "creating fconstant with the wrong size");
283 
284   assert(!Ty.isPointer() && "invalid operand type");
285 
286   if (Ty.isVector()) {
287     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
288     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
289     .addFPImm(&Val);
290 
291     return buildSplatVector(Res, Const);
292   }
293 
294   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
295   Res.addDefToMIB(*getMRI(), Const);
296   Const.addFPImm(&Val);
297   return Const;
298 }
299 
300 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
301                                                     const APInt &Val) {
302   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
303   return buildConstant(Res, *CI);
304 }
305 
306 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
307                                                      double Val) {
308   LLT DstTy = Res.getLLTTy(*getMRI());
309   auto &Ctx = getMF().getFunction().getContext();
310   auto *CFP =
311       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
312   return buildFConstant(Res, *CFP);
313 }
314 
315 MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
316                                                   MachineBasicBlock &Dest) {
317   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
318 
319   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
320 }
321 
322 MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
323                                                 MachineMemOperand &MMO) {
324   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
325 }
326 
327 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
328                                                      unsigned Res,
329                                                      unsigned Addr,
330                                                      MachineMemOperand &MMO) {
331   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
332   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
333 
334   return buildInstr(Opcode)
335       .addDef(Res)
336       .addUse(Addr)
337       .addMemOperand(&MMO);
338 }
339 
340 MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
341                                                  MachineMemOperand &MMO) {
342   assert(getMRI()->getType(Val).isValid() && "invalid operand type");
343   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
344 
345   return buildInstr(TargetOpcode::G_STORE)
346       .addUse(Val)
347       .addUse(Addr)
348       .addMemOperand(&MMO);
349 }
350 
351 MachineInstrBuilder MachineIRBuilder::buildUAddo(const DstOp &Res,
352                                                  const DstOp &CarryOut,
353                                                  const SrcOp &Op0,
354                                                  const SrcOp &Op1) {
355   return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
356 }
357 
358 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
359                                                  const DstOp &CarryOut,
360                                                  const SrcOp &Op0,
361                                                  const SrcOp &Op1,
362                                                  const SrcOp &CarryIn) {
363   return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
364                     {Op0, Op1, CarryIn});
365 }
366 
367 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
368                                                   const SrcOp &Op) {
369   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
370 }
371 
372 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
373                                                 const SrcOp &Op) {
374   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
375 }
376 
377 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
378                                                 const SrcOp &Op) {
379   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
380 }
381 
382 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
383   const auto *TLI = getMF().getSubtarget().getTargetLowering();
384   switch (TLI->getBooleanContents(IsVec, IsFP)) {
385   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
386     return TargetOpcode::G_SEXT;
387   case TargetLoweringBase::ZeroOrOneBooleanContent:
388     return TargetOpcode::G_ZEXT;
389   default:
390     return TargetOpcode::G_ANYEXT;
391   }
392 }
393 
394 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
395                                                    const SrcOp &Op,
396                                                    bool IsFP) {
397   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
398   return buildInstr(ExtOp, Res, Op);
399 }
400 
401 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
402                                                       const DstOp &Res,
403                                                       const SrcOp &Op) {
404   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
405           TargetOpcode::G_SEXT == ExtOpc) &&
406          "Expecting Extending Opc");
407   assert(Res.getLLTTy(*getMRI()).isScalar() ||
408          Res.getLLTTy(*getMRI()).isVector());
409   assert(Res.getLLTTy(*getMRI()).isScalar() ==
410          Op.getLLTTy(*getMRI()).isScalar());
411 
412   unsigned Opcode = TargetOpcode::COPY;
413   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
414       Op.getLLTTy(*getMRI()).getSizeInBits())
415     Opcode = ExtOpc;
416   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
417            Op.getLLTTy(*getMRI()).getSizeInBits())
418     Opcode = TargetOpcode::G_TRUNC;
419   else
420     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
421 
422   return buildInstr(Opcode, Res, Op);
423 }
424 
425 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
426                                                        const SrcOp &Op) {
427   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
428 }
429 
430 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
431                                                        const SrcOp &Op) {
432   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
433 }
434 
435 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
436                                                          const SrcOp &Op) {
437   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
438 }
439 
440 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
441                                                 const SrcOp &Src) {
442   LLT SrcTy = Src.getLLTTy(*getMRI());
443   LLT DstTy = Dst.getLLTTy(*getMRI());
444   if (SrcTy == DstTy)
445     return buildCopy(Dst, Src);
446 
447   unsigned Opcode;
448   if (SrcTy.isPointer() && DstTy.isScalar())
449     Opcode = TargetOpcode::G_PTRTOINT;
450   else if (DstTy.isPointer() && SrcTy.isScalar())
451     Opcode = TargetOpcode::G_INTTOPTR;
452   else {
453     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
454     Opcode = TargetOpcode::G_BITCAST;
455   }
456 
457   return buildInstr(Opcode, Dst, Src);
458 }
459 
460 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
461                                                    const SrcOp &Src,
462                                                    uint64_t Index) {
463   LLT SrcTy = Src.getLLTTy(*getMRI());
464   LLT DstTy = Dst.getLLTTy(*getMRI());
465 
466 #ifndef NDEBUG
467   assert(SrcTy.isValid() && "invalid operand type");
468   assert(DstTy.isValid() && "invalid operand type");
469   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
470          "extracting off end of register");
471 #endif
472 
473   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
474     assert(Index == 0 && "insertion past the end of a register");
475     return buildCast(Dst, Src);
476   }
477 
478   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
479   Dst.addDefToMIB(*getMRI(), Extract);
480   Src.addSrcToMIB(Extract);
481   Extract.addImm(Index);
482   return Extract;
483 }
484 
485 void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
486                                      ArrayRef<uint64_t> Indices) {
487 #ifndef NDEBUG
488   assert(Ops.size() == Indices.size() && "incompatible args");
489   assert(!Ops.empty() && "invalid trivial sequence");
490   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
491          "sequence offsets must be in ascending order");
492 
493   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
494   for (auto Op : Ops)
495     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
496 #endif
497 
498   LLT ResTy = getMRI()->getType(Res);
499   LLT OpTy = getMRI()->getType(Ops[0]);
500   unsigned OpSize = OpTy.getSizeInBits();
501   bool MaybeMerge = true;
502   for (unsigned i = 0; i < Ops.size(); ++i) {
503     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
504       MaybeMerge = false;
505       break;
506     }
507   }
508 
509   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
510     buildMerge(Res, Ops);
511     return;
512   }
513 
514   unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
515   buildUndef(ResIn);
516 
517   for (unsigned i = 0; i < Ops.size(); ++i) {
518     unsigned ResOut = i + 1 == Ops.size()
519                           ? Res
520                           : getMRI()->createGenericVirtualRegister(ResTy);
521     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
522     ResIn = ResOut;
523   }
524 }
525 
526 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
527   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
528 }
529 
530 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
531                                                  ArrayRef<unsigned> Ops) {
532   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
533   // we need some temporary storage for the DstOp objects. Here we use a
534   // sufficiently large SmallVector to not go through the heap.
535   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
536   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
537 }
538 
539 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
540                                                    const SrcOp &Op) {
541   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
542   // we need some temporary storage for the DstOp objects. Here we use a
543   // sufficiently large SmallVector to not go through the heap.
544   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
545   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
546 }
547 
548 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
549                                                    const SrcOp &Op) {
550   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
551   SmallVector<unsigned, 8> TmpVec;
552   for (unsigned I = 0; I != NumReg; ++I)
553     TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
554   return buildUnmerge(TmpVec, Op);
555 }
556 
557 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
558                                                    const SrcOp &Op) {
559   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
560   // we need some temporary storage for the DstOp objects. Here we use a
561   // sufficiently large SmallVector to not go through the heap.
562   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
563   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
564 }
565 
566 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
567                                                        ArrayRef<unsigned> Ops) {
568   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
569   // we need some temporary storage for the DstOp objects. Here we use a
570   // sufficiently large SmallVector to not go through the heap.
571   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
572   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
573 }
574 
575 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
576                                                        const SrcOp &Src) {
577   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
578   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
579 }
580 
581 MachineInstrBuilder
582 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
583                                         ArrayRef<unsigned> Ops) {
584   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
585   // we need some temporary storage for the DstOp objects. Here we use a
586   // sufficiently large SmallVector to not go through the heap.
587   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
588   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
589 }
590 
591 MachineInstrBuilder
592 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
593   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
594   // we need some temporary storage for the DstOp objects. Here we use a
595   // sufficiently large SmallVector to not go through the heap.
596   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
597   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
598 }
599 
600 MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
601                                                   unsigned Op, unsigned Index) {
602   assert(Index + getMRI()->getType(Op).getSizeInBits() <=
603              getMRI()->getType(Res).getSizeInBits() &&
604          "insertion past the end of a register");
605 
606   if (getMRI()->getType(Res).getSizeInBits() ==
607       getMRI()->getType(Op).getSizeInBits()) {
608     return buildCast(Res, Op);
609   }
610 
611   return buildInstr(TargetOpcode::G_INSERT)
612       .addDef(Res)
613       .addUse(Src)
614       .addUse(Op)
615       .addImm(Index);
616 }
617 
618 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
619                                                      ArrayRef<unsigned> ResultRegs,
620                                                      bool HasSideEffects) {
621   auto MIB =
622       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
623                                 : TargetOpcode::G_INTRINSIC);
624   for (unsigned ResultReg : ResultRegs)
625     MIB.addDef(ResultReg);
626   MIB.addIntrinsicID(ID);
627   return MIB;
628 }
629 
630 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
631                                                  const SrcOp &Op) {
632   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
633 }
634 
635 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
636                                                    const SrcOp &Op) {
637   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
638 }
639 
640 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
641                                                 const DstOp &Res,
642                                                 const SrcOp &Op0,
643                                                 const SrcOp &Op1) {
644   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
645 }
646 
647 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
648                                                 const DstOp &Res,
649                                                 const SrcOp &Op0,
650                                                 const SrcOp &Op1) {
651 
652   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
653 }
654 
655 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
656                                                   const SrcOp &Tst,
657                                                   const SrcOp &Op0,
658                                                   const SrcOp &Op1) {
659 
660   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
661 }
662 
663 MachineInstrBuilder
664 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
665                                            const SrcOp &Elt, const SrcOp &Idx) {
666   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
667 }
668 
669 MachineInstrBuilder
670 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
671                                             const SrcOp &Idx) {
672   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
673 }
674 
675 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
676     unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
677     unsigned NewVal, MachineMemOperand &MMO) {
678 #ifndef NDEBUG
679   LLT OldValResTy = getMRI()->getType(OldValRes);
680   LLT SuccessResTy = getMRI()->getType(SuccessRes);
681   LLT AddrTy = getMRI()->getType(Addr);
682   LLT CmpValTy = getMRI()->getType(CmpVal);
683   LLT NewValTy = getMRI()->getType(NewVal);
684   assert(OldValResTy.isScalar() && "invalid operand type");
685   assert(SuccessResTy.isScalar() && "invalid operand type");
686   assert(AddrTy.isPointer() && "invalid operand type");
687   assert(CmpValTy.isValid() && "invalid operand type");
688   assert(NewValTy.isValid() && "invalid operand type");
689   assert(OldValResTy == CmpValTy && "type mismatch");
690   assert(OldValResTy == NewValTy && "type mismatch");
691 #endif
692 
693   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
694       .addDef(OldValRes)
695       .addDef(SuccessRes)
696       .addUse(Addr)
697       .addUse(CmpVal)
698       .addUse(NewVal)
699       .addMemOperand(&MMO);
700 }
701 
702 MachineInstrBuilder
703 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
704                                      unsigned CmpVal, unsigned NewVal,
705                                      MachineMemOperand &MMO) {
706 #ifndef NDEBUG
707   LLT OldValResTy = getMRI()->getType(OldValRes);
708   LLT AddrTy = getMRI()->getType(Addr);
709   LLT CmpValTy = getMRI()->getType(CmpVal);
710   LLT NewValTy = getMRI()->getType(NewVal);
711   assert(OldValResTy.isScalar() && "invalid operand type");
712   assert(AddrTy.isPointer() && "invalid operand type");
713   assert(CmpValTy.isValid() && "invalid operand type");
714   assert(NewValTy.isValid() && "invalid operand type");
715   assert(OldValResTy == CmpValTy && "type mismatch");
716   assert(OldValResTy == NewValTy && "type mismatch");
717 #endif
718 
719   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
720       .addDef(OldValRes)
721       .addUse(Addr)
722       .addUse(CmpVal)
723       .addUse(NewVal)
724       .addMemOperand(&MMO);
725 }
726 
727 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
728                                                      unsigned OldValRes,
729                                                      unsigned Addr,
730                                                      unsigned Val,
731                                                      MachineMemOperand &MMO) {
732 #ifndef NDEBUG
733   LLT OldValResTy = getMRI()->getType(OldValRes);
734   LLT AddrTy = getMRI()->getType(Addr);
735   LLT ValTy = getMRI()->getType(Val);
736   assert(OldValResTy.isScalar() && "invalid operand type");
737   assert(AddrTy.isPointer() && "invalid operand type");
738   assert(ValTy.isValid() && "invalid operand type");
739   assert(OldValResTy == ValTy && "type mismatch");
740 #endif
741 
742   return buildInstr(Opcode)
743       .addDef(OldValRes)
744       .addUse(Addr)
745       .addUse(Val)
746       .addMemOperand(&MMO);
747 }
748 
749 MachineInstrBuilder
750 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
751                                      unsigned Val, MachineMemOperand &MMO) {
752   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
753                         MMO);
754 }
755 MachineInstrBuilder
756 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
757                                     unsigned Val, MachineMemOperand &MMO) {
758   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
759                         MMO);
760 }
761 MachineInstrBuilder
762 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
763                                     unsigned Val, MachineMemOperand &MMO) {
764   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
765                         MMO);
766 }
767 MachineInstrBuilder
768 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
769                                     unsigned Val, MachineMemOperand &MMO) {
770   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
771                         MMO);
772 }
773 MachineInstrBuilder
774 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
775                                      unsigned Val, MachineMemOperand &MMO) {
776   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
777                         MMO);
778 }
779 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
780                                                        unsigned Addr,
781                                                        unsigned Val,
782                                                        MachineMemOperand &MMO) {
783   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
784                         MMO);
785 }
786 MachineInstrBuilder
787 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
788                                     unsigned Val, MachineMemOperand &MMO) {
789   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
790                         MMO);
791 }
792 MachineInstrBuilder
793 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
794                                     unsigned Val, MachineMemOperand &MMO) {
795   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
796                         MMO);
797 }
798 MachineInstrBuilder
799 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
800                                     unsigned Val, MachineMemOperand &MMO) {
801   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
802                         MMO);
803 }
804 MachineInstrBuilder
805 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
806                                      unsigned Val, MachineMemOperand &MMO) {
807   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
808                         MMO);
809 }
810 MachineInstrBuilder
811 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
812                                      unsigned Val, MachineMemOperand &MMO) {
813   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
814                         MMO);
815 }
816 
817 MachineInstrBuilder
818 MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
819 #ifndef NDEBUG
820   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
821 #endif
822 
823   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
824 }
825 
826 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
827                                         bool IsExtend) {
828 #ifndef NDEBUG
829   if (DstTy.isVector()) {
830     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
831     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
832            "different number of elements in a trunc/ext");
833   } else
834     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
835 
836   if (IsExtend)
837     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
838            "invalid narrowing extend");
839   else
840     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
841            "invalid widening trunc");
842 #endif
843 }
844 
845 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
846                                         const LLT &Op0Ty, const LLT &Op1Ty) {
847 #ifndef NDEBUG
848   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
849          "invalid operand type");
850   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
851   if (ResTy.isScalar() || ResTy.isPointer())
852     assert(TstTy.isScalar() && "type mismatch");
853   else
854     assert((TstTy.isScalar() ||
855             (TstTy.isVector() &&
856              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
857            "type mismatch");
858 #endif
859 }
860 
861 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
862                                                  ArrayRef<DstOp> DstOps,
863                                                  ArrayRef<SrcOp> SrcOps,
864                                                  Optional<unsigned> Flags) {
865   switch (Opc) {
866   default:
867     break;
868   case TargetOpcode::G_SELECT: {
869     assert(DstOps.size() == 1 && "Invalid select");
870     assert(SrcOps.size() == 3 && "Invalid select");
871     validateSelectOp(
872         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
873         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
874     break;
875   }
876   case TargetOpcode::G_ADD:
877   case TargetOpcode::G_AND:
878   case TargetOpcode::G_MUL:
879   case TargetOpcode::G_OR:
880   case TargetOpcode::G_SUB:
881   case TargetOpcode::G_XOR:
882   case TargetOpcode::G_UDIV:
883   case TargetOpcode::G_SDIV:
884   case TargetOpcode::G_UREM:
885   case TargetOpcode::G_SREM: {
886     // All these are binary ops.
887     assert(DstOps.size() == 1 && "Invalid Dst");
888     assert(SrcOps.size() == 2 && "Invalid Srcs");
889     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
890                      SrcOps[0].getLLTTy(*getMRI()),
891                      SrcOps[1].getLLTTy(*getMRI()));
892     break;
893   }
894   case TargetOpcode::G_SHL:
895   case TargetOpcode::G_ASHR:
896   case TargetOpcode::G_LSHR: {
897     assert(DstOps.size() == 1 && "Invalid Dst");
898     assert(SrcOps.size() == 2 && "Invalid Srcs");
899     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
900                     SrcOps[0].getLLTTy(*getMRI()),
901                     SrcOps[1].getLLTTy(*getMRI()));
902     break;
903   }
904   case TargetOpcode::G_SEXT:
905   case TargetOpcode::G_ZEXT:
906   case TargetOpcode::G_ANYEXT:
907     assert(DstOps.size() == 1 && "Invalid Dst");
908     assert(SrcOps.size() == 1 && "Invalid Srcs");
909     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
910                      SrcOps[0].getLLTTy(*getMRI()), true);
911     break;
912   case TargetOpcode::G_TRUNC:
913   case TargetOpcode::G_FPTRUNC: {
914     assert(DstOps.size() == 1 && "Invalid Dst");
915     assert(SrcOps.size() == 1 && "Invalid Srcs");
916     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
917                      SrcOps[0].getLLTTy(*getMRI()), false);
918     break;
919   }
920   case TargetOpcode::COPY:
921     assert(DstOps.size() == 1 && "Invalid Dst");
922     // If the caller wants to add a subreg source it has to be done separately
923     // so we may not have any SrcOps at this point yet.
924     break;
925   case TargetOpcode::G_FCMP:
926   case TargetOpcode::G_ICMP: {
927     assert(DstOps.size() == 1 && "Invalid Dst Operands");
928     assert(SrcOps.size() == 3 && "Invalid Src Operands");
929     // For F/ICMP, the first src operand is the predicate, followed by
930     // the two comparands.
931     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
932            "Expecting predicate");
933     assert([&]() -> bool {
934       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
935       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
936                                          : CmpInst::isFPPredicate(Pred);
937     }() && "Invalid predicate");
938     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
939            "Type mismatch");
940     assert([&]() -> bool {
941       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
942       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
943       if (Op0Ty.isScalar() || Op0Ty.isPointer())
944         return DstTy.isScalar();
945       else
946         return DstTy.isVector() &&
947                DstTy.getNumElements() == Op0Ty.getNumElements();
948     }() && "Type Mismatch");
949     break;
950   }
951   case TargetOpcode::G_UNMERGE_VALUES: {
952     assert(!DstOps.empty() && "Invalid trivial sequence");
953     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
954     assert(std::all_of(DstOps.begin(), DstOps.end(),
955                        [&, this](const DstOp &Op) {
956                          return Op.getLLTTy(*getMRI()) ==
957                                 DstOps[0].getLLTTy(*getMRI());
958                        }) &&
959            "type mismatch in output list");
960     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
961                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
962            "input operands do not cover output register");
963     break;
964   }
965   case TargetOpcode::G_MERGE_VALUES: {
966     assert(!SrcOps.empty() && "invalid trivial sequence");
967     assert(DstOps.size() == 1 && "Invalid Dst");
968     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
969                        [&, this](const SrcOp &Op) {
970                          return Op.getLLTTy(*getMRI()) ==
971                                 SrcOps[0].getLLTTy(*getMRI());
972                        }) &&
973            "type mismatch in input list");
974     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
975                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
976            "input operands do not cover output register");
977     if (SrcOps.size() == 1)
978       return buildCast(DstOps[0], SrcOps[0]);
979     if (DstOps[0].getLLTTy(*getMRI()).isVector())
980       return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
981     break;
982   }
983   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
984     assert(DstOps.size() == 1 && "Invalid Dst size");
985     assert(SrcOps.size() == 2 && "Invalid Src size");
986     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
987     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
988             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
989            "Invalid operand type");
990     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
991     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
992                DstOps[0].getLLTTy(*getMRI()) &&
993            "Type mismatch");
994     break;
995   }
996   case TargetOpcode::G_INSERT_VECTOR_ELT: {
997     assert(DstOps.size() == 1 && "Invalid dst size");
998     assert(SrcOps.size() == 3 && "Invalid src size");
999     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1000            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1001     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1002                SrcOps[1].getLLTTy(*getMRI()) &&
1003            "Type mismatch");
1004     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1005     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1006                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1007            "Type mismatch");
1008     break;
1009   }
1010   case TargetOpcode::G_BUILD_VECTOR: {
1011     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1012            "Must have at least 2 operands");
1013     assert(DstOps.size() == 1 && "Invalid DstOps");
1014     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1015            "Res type must be a vector");
1016     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1017                        [&, this](const SrcOp &Op) {
1018                          return Op.getLLTTy(*getMRI()) ==
1019                                 SrcOps[0].getLLTTy(*getMRI());
1020                        }) &&
1021            "type mismatch in input list");
1022     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1023                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1024            "input scalars do not exactly cover the output vector register");
1025     break;
1026   }
1027   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1028     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1029            "Must have at least 2 operands");
1030     assert(DstOps.size() == 1 && "Invalid DstOps");
1031     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1032            "Res type must be a vector");
1033     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1034                        [&, this](const SrcOp &Op) {
1035                          return Op.getLLTTy(*getMRI()) ==
1036                                 SrcOps[0].getLLTTy(*getMRI());
1037                        }) &&
1038            "type mismatch in input list");
1039     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1040         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1041       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1042     break;
1043   }
1044   case TargetOpcode::G_CONCAT_VECTORS: {
1045     assert(DstOps.size() == 1 && "Invalid DstOps");
1046     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1047            "Must have at least 2 operands");
1048     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1049                        [&, this](const SrcOp &Op) {
1050                          return (Op.getLLTTy(*getMRI()).isVector() &&
1051                                  Op.getLLTTy(*getMRI()) ==
1052                                      SrcOps[0].getLLTTy(*getMRI()));
1053                        }) &&
1054            "type mismatch in input list");
1055     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1056                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1057            "input vectors do not exactly cover the output vector register");
1058     break;
1059   }
1060   case TargetOpcode::G_UADDE: {
1061     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1062     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1063     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1064     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1065            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1066            "Invalid operand");
1067     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1068     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1069            "type mismatch");
1070     break;
1071   }
1072   }
1073 
1074   auto MIB = buildInstr(Opc);
1075   for (const DstOp &Op : DstOps)
1076     Op.addDefToMIB(*getMRI(), MIB);
1077   for (const SrcOp &Op : SrcOps)
1078     Op.addSrcToMIB(MIB);
1079   if (Flags)
1080     MIB->setFlags(*Flags);
1081   return MIB;
1082 }
1083