1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the MachineIRBuidler class.
11 //===----------------------------------------------------------------------===//
12 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetOpcodes.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
20 
21 using namespace llvm;
22 
23 void MachineIRBuilder::setMF(MachineFunction &MF) {
24   this->MF = &MF;
25   this->MBB = nullptr;
26   this->TII = MF.getSubtarget().getInstrInfo();
27   this->DL = DebugLoc();
28   this->MI = nullptr;
29 }
30 
31 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
32   this->MBB = &MBB;
33   Before = Beginning;
34   assert(&getMF() == MBB.getParent() &&
35          "Basic block is in a different function");
36 }
37 
38 void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
39   assert(MI.getParent() && "Instruction is not part of a basic block");
40   setMBB(*MI.getParent());
41   this->MI = &MI;
42   this->Before = Before;
43 }
44 
45 MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
46   if (MI) {
47     if (Before)
48       return MI;
49     if (!MI->getNextNode())
50       return getMBB().end();
51     return MI->getNextNode();
52   }
53   return Before ? getMBB().begin() : getMBB().end();
54 }
55 
56 //------------------------------------------------------------------------------
57 // Build instruction variants.
58 //------------------------------------------------------------------------------
59 
60 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode,
61                                                   ArrayRef<LLT> Tys) {
62   MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
63   if (Tys.size() > 0) {
64     assert(isPreISelGenericOpcode(Opcode) &&
65            "Only generic instruction can have a type");
66     for (unsigned i = 0; i < Tys.size(); ++i)
67       MIB->setType(Tys[i], i);
68   } else
69     assert(!isPreISelGenericOpcode(Opcode) &&
70            "Generic instruction must have a type");
71   getMBB().insert(getInsertPt(), MIB);
72   return MIB;
73 }
74 
75 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(LLT Ty, unsigned Res,
76                                                        int Idx) {
77   return buildInstr(TargetOpcode::G_FRAME_INDEX, Ty)
78       .addDef(Res)
79       .addFrameIndex(Idx);
80 }
81 
82 MachineInstrBuilder MachineIRBuilder::buildAdd(LLT Ty, unsigned Res,
83                                                 unsigned Op0, unsigned Op1) {
84   return buildInstr(TargetOpcode::G_ADD, Ty)
85       .addDef(Res)
86       .addUse(Op0)
87       .addUse(Op1);
88 }
89 
90 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
91   return buildInstr(TargetOpcode::G_BR, LLT::unsized()).addMBB(&Dest);
92 }
93 
94 MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
95   return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
96 }
97 
98 MachineInstrBuilder MachineIRBuilder::buildBrCond(LLT Ty, unsigned Tst,
99                                                   MachineBasicBlock &Dest) {
100   return buildInstr(TargetOpcode::G_BRCOND, Ty).addUse(Tst).addMBB(&Dest);
101 }
102 
103 
104  MachineInstrBuilder MachineIRBuilder::buildLoad(LLT VTy, LLT PTy, unsigned Res,
105                                                  unsigned Addr,
106                                                  MachineMemOperand &MMO) {
107   return buildInstr(TargetOpcode::G_LOAD, {VTy, PTy})
108       .addDef(Res)
109       .addUse(Addr)
110       .addMemOperand(&MMO);
111 }
112 
113 MachineInstrBuilder MachineIRBuilder::buildStore(LLT VTy, LLT PTy,
114                                                   unsigned Val, unsigned Addr,
115                                                   MachineMemOperand &MMO) {
116   return buildInstr(TargetOpcode::G_STORE, {VTy, PTy})
117       .addUse(Val)
118       .addUse(Addr)
119       .addMemOperand(&MMO);
120 }
121 
122 MachineInstrBuilder
123 MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results, unsigned Src,
124                                ArrayRef<unsigned> Indexes) {
125   assert(Results.size() == Indexes.size() && "inconsistent number of regs");
126 
127   MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_EXTRACT, Ty);
128   for (auto Res : Results)
129     MIB.addDef(Res);
130 
131   MIB.addUse(Src);
132 
133   for (auto Idx : Indexes)
134     MIB.addImm(Idx);
135   return MIB;
136 }
137 
138 MachineInstrBuilder MachineIRBuilder::buildSequence(LLT Ty, unsigned Res,
139                                               ArrayRef<unsigned> Ops) {
140   MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE, Ty);
141   MIB.addDef(Res);
142   for (auto Op : Ops)
143     MIB.addUse(Op);
144   return MIB;
145 }
146 
147 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(ArrayRef<LLT> Tys,
148                                                      Intrinsic::ID ID,
149                                                      unsigned Res,
150                                                      bool HasSideEffects) {
151   auto MIB =
152       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
153                                 : TargetOpcode::G_INTRINSIC,
154                  Tys);
155   if (Res)
156     MIB.addDef(Res);
157   MIB.addIntrinsicID(ID);
158   return MIB;
159 }
160