1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
164   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165   return buildInstr(TargetOpcode::G_FRAME_INDEX)
166       .addDef(Res)
167       .addFrameIndex(Idx);
168 }
169 
170 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
171                                                        const GlobalValue *GV) {
172   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173   assert(getMRI()->getType(Res).getAddressSpace() ==
174              GV->getType()->getAddressSpace() &&
175          "address space mismatch");
176 
177   return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178       .addDef(Res)
179       .addGlobalAddress(GV);
180 }
181 
182 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
183                                                      unsigned JTI) {
184   return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
185       .addJumpTableIndex(JTI);
186 }
187 
188 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
189                                         const LLT &Op1) {
190   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
191   assert((Res == Op0 && Res == Op1) && "type mismatch");
192 }
193 
194 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
195                                        const LLT &Op1) {
196   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
197   assert((Res == Op0) && "type mismatch");
198 }
199 
200 MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
201                                                unsigned Op1) {
202   assert(getMRI()->getType(Res).isPointer() &&
203          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
204   assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
205 
206   return buildInstr(TargetOpcode::G_GEP)
207       .addDef(Res)
208       .addUse(Op0)
209       .addUse(Op1);
210 }
211 
212 Optional<MachineInstrBuilder>
213 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
214                                  const LLT &ValueTy, uint64_t Value) {
215   assert(Res == 0 && "Res is a result argument");
216   assert(ValueTy.isScalar()  && "invalid offset type");
217 
218   if (Value == 0) {
219     Res = Op0;
220     return None;
221   }
222 
223   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
224   auto Cst = buildConstant(ValueTy, Value);
225   return buildGEP(Res, Op0, Cst.getReg(0));
226 }
227 
228 MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
229                                                    uint32_t NumBits) {
230   assert(getMRI()->getType(Res).isPointer() &&
231          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
232 
233   return buildInstr(TargetOpcode::G_PTR_MASK)
234       .addDef(Res)
235       .addUse(Op0)
236       .addImm(NumBits);
237 }
238 
239 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
240   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
241 }
242 
243 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
244   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
245   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
246 }
247 
248 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
249                                                 const SrcOp &Op) {
250   return buildInstr(TargetOpcode::COPY, Res, Op);
251 }
252 
253 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
254                                                     const ConstantInt &Val) {
255   LLT Ty = Res.getLLTTy(*getMRI());
256   LLT EltTy = Ty.getScalarType();
257   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
258          "creating constant with the wrong size");
259 
260   if (Ty.isVector()) {
261     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
262     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
263     .addCImm(&Val);
264     return buildSplatVector(Res, Const);
265   }
266 
267   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
268   Res.addDefToMIB(*getMRI(), Const);
269   Const.addCImm(&Val);
270   return Const;
271 }
272 
273 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
274                                                     int64_t Val) {
275   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
276                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
277   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
278   return buildConstant(Res, *CI);
279 }
280 
281 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
282                                                      const ConstantFP &Val) {
283   LLT Ty = Res.getLLTTy(*getMRI());
284   LLT EltTy = Ty.getScalarType();
285 
286   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
287          == EltTy.getSizeInBits() &&
288          "creating fconstant with the wrong size");
289 
290   assert(!Ty.isPointer() && "invalid operand type");
291 
292   if (Ty.isVector()) {
293     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
294     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
295     .addFPImm(&Val);
296 
297     return buildSplatVector(Res, Const);
298   }
299 
300   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
301   Res.addDefToMIB(*getMRI(), Const);
302   Const.addFPImm(&Val);
303   return Const;
304 }
305 
306 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
307                                                     const APInt &Val) {
308   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
309   return buildConstant(Res, *CI);
310 }
311 
312 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
313                                                      double Val) {
314   LLT DstTy = Res.getLLTTy(*getMRI());
315   auto &Ctx = getMF().getFunction().getContext();
316   auto *CFP =
317       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
318   return buildFConstant(Res, *CFP);
319 }
320 
321 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
322                                                      const APFloat &Val) {
323   auto &Ctx = getMF().getFunction().getContext();
324   auto *CFP = ConstantFP::get(Ctx, Val);
325   return buildFConstant(Res, *CFP);
326 }
327 
328 MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
329                                                   MachineBasicBlock &Dest) {
330   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
331 
332   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
333 }
334 
335 MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
336                                                 MachineMemOperand &MMO) {
337   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
338 }
339 
340 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
341                                                      unsigned Res,
342                                                      unsigned Addr,
343                                                      MachineMemOperand &MMO) {
344   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
345   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
346 
347   return buildInstr(Opcode)
348       .addDef(Res)
349       .addUse(Addr)
350       .addMemOperand(&MMO);
351 }
352 
353 MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
354                                                  MachineMemOperand &MMO) {
355   assert(getMRI()->getType(Val).isValid() && "invalid operand type");
356   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
357 
358   return buildInstr(TargetOpcode::G_STORE)
359       .addUse(Val)
360       .addUse(Addr)
361       .addMemOperand(&MMO);
362 }
363 
364 MachineInstrBuilder MachineIRBuilder::buildUAddo(const DstOp &Res,
365                                                  const DstOp &CarryOut,
366                                                  const SrcOp &Op0,
367                                                  const SrcOp &Op1) {
368   return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
369 }
370 
371 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
372                                                  const DstOp &CarryOut,
373                                                  const SrcOp &Op0,
374                                                  const SrcOp &Op1,
375                                                  const SrcOp &CarryIn) {
376   return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
377                     {Op0, Op1, CarryIn});
378 }
379 
380 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
381                                                   const SrcOp &Op) {
382   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
383 }
384 
385 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
386                                                 const SrcOp &Op) {
387   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
388 }
389 
390 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
391                                                 const SrcOp &Op) {
392   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
393 }
394 
395 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
396   const auto *TLI = getMF().getSubtarget().getTargetLowering();
397   switch (TLI->getBooleanContents(IsVec, IsFP)) {
398   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
399     return TargetOpcode::G_SEXT;
400   case TargetLoweringBase::ZeroOrOneBooleanContent:
401     return TargetOpcode::G_ZEXT;
402   default:
403     return TargetOpcode::G_ANYEXT;
404   }
405 }
406 
407 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
408                                                    const SrcOp &Op,
409                                                    bool IsFP) {
410   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
411   return buildInstr(ExtOp, Res, Op);
412 }
413 
414 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
415                                                       const DstOp &Res,
416                                                       const SrcOp &Op) {
417   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
418           TargetOpcode::G_SEXT == ExtOpc) &&
419          "Expecting Extending Opc");
420   assert(Res.getLLTTy(*getMRI()).isScalar() ||
421          Res.getLLTTy(*getMRI()).isVector());
422   assert(Res.getLLTTy(*getMRI()).isScalar() ==
423          Op.getLLTTy(*getMRI()).isScalar());
424 
425   unsigned Opcode = TargetOpcode::COPY;
426   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
427       Op.getLLTTy(*getMRI()).getSizeInBits())
428     Opcode = ExtOpc;
429   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
430            Op.getLLTTy(*getMRI()).getSizeInBits())
431     Opcode = TargetOpcode::G_TRUNC;
432   else
433     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
434 
435   return buildInstr(Opcode, Res, Op);
436 }
437 
438 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
439                                                        const SrcOp &Op) {
440   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
441 }
442 
443 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
444                                                        const SrcOp &Op) {
445   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
446 }
447 
448 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
449                                                          const SrcOp &Op) {
450   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
451 }
452 
453 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
454                                                 const SrcOp &Src) {
455   LLT SrcTy = Src.getLLTTy(*getMRI());
456   LLT DstTy = Dst.getLLTTy(*getMRI());
457   if (SrcTy == DstTy)
458     return buildCopy(Dst, Src);
459 
460   unsigned Opcode;
461   if (SrcTy.isPointer() && DstTy.isScalar())
462     Opcode = TargetOpcode::G_PTRTOINT;
463   else if (DstTy.isPointer() && SrcTy.isScalar())
464     Opcode = TargetOpcode::G_INTTOPTR;
465   else {
466     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
467     Opcode = TargetOpcode::G_BITCAST;
468   }
469 
470   return buildInstr(Opcode, Dst, Src);
471 }
472 
473 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
474                                                    const SrcOp &Src,
475                                                    uint64_t Index) {
476   LLT SrcTy = Src.getLLTTy(*getMRI());
477   LLT DstTy = Dst.getLLTTy(*getMRI());
478 
479 #ifndef NDEBUG
480   assert(SrcTy.isValid() && "invalid operand type");
481   assert(DstTy.isValid() && "invalid operand type");
482   assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
483          "extracting off end of register");
484 #endif
485 
486   if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
487     assert(Index == 0 && "insertion past the end of a register");
488     return buildCast(Dst, Src);
489   }
490 
491   auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
492   Dst.addDefToMIB(*getMRI(), Extract);
493   Src.addSrcToMIB(Extract);
494   Extract.addImm(Index);
495   return Extract;
496 }
497 
498 void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
499                                      ArrayRef<uint64_t> Indices) {
500 #ifndef NDEBUG
501   assert(Ops.size() == Indices.size() && "incompatible args");
502   assert(!Ops.empty() && "invalid trivial sequence");
503   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
504          "sequence offsets must be in ascending order");
505 
506   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
507   for (auto Op : Ops)
508     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
509 #endif
510 
511   LLT ResTy = getMRI()->getType(Res);
512   LLT OpTy = getMRI()->getType(Ops[0]);
513   unsigned OpSize = OpTy.getSizeInBits();
514   bool MaybeMerge = true;
515   for (unsigned i = 0; i < Ops.size(); ++i) {
516     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
517       MaybeMerge = false;
518       break;
519     }
520   }
521 
522   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
523     buildMerge(Res, Ops);
524     return;
525   }
526 
527   unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
528   buildUndef(ResIn);
529 
530   for (unsigned i = 0; i < Ops.size(); ++i) {
531     unsigned ResOut = i + 1 == Ops.size()
532                           ? Res
533                           : getMRI()->createGenericVirtualRegister(ResTy);
534     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
535     ResIn = ResOut;
536   }
537 }
538 
539 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
540   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
541 }
542 
543 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
544                                                  ArrayRef<unsigned> Ops) {
545   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
546   // we need some temporary storage for the DstOp objects. Here we use a
547   // sufficiently large SmallVector to not go through the heap.
548   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
549   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
550 }
551 
552 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
553                                                    const SrcOp &Op) {
554   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
555   // we need some temporary storage for the DstOp objects. Here we use a
556   // sufficiently large SmallVector to not go through the heap.
557   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
558   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
559 }
560 
561 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
562                                                    const SrcOp &Op) {
563   unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
564   SmallVector<unsigned, 8> TmpVec;
565   for (unsigned I = 0; I != NumReg; ++I)
566     TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
567   return buildUnmerge(TmpVec, Op);
568 }
569 
570 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
571                                                    const SrcOp &Op) {
572   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
573   // we need some temporary storage for the DstOp objects. Here we use a
574   // sufficiently large SmallVector to not go through the heap.
575   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
576   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
577 }
578 
579 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
580                                                        ArrayRef<unsigned> Ops) {
581   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
582   // we need some temporary storage for the DstOp objects. Here we use a
583   // sufficiently large SmallVector to not go through the heap.
584   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
585   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
586 }
587 
588 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
589                                                        const SrcOp &Src) {
590   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
591   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
592 }
593 
594 MachineInstrBuilder
595 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
596                                         ArrayRef<unsigned> Ops) {
597   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
598   // we need some temporary storage for the DstOp objects. Here we use a
599   // sufficiently large SmallVector to not go through the heap.
600   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
601   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
602 }
603 
604 MachineInstrBuilder
605 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
606   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
607   // we need some temporary storage for the DstOp objects. Here we use a
608   // sufficiently large SmallVector to not go through the heap.
609   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
610   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
611 }
612 
613 MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
614                                                   unsigned Op, unsigned Index) {
615   assert(Index + getMRI()->getType(Op).getSizeInBits() <=
616              getMRI()->getType(Res).getSizeInBits() &&
617          "insertion past the end of a register");
618 
619   if (getMRI()->getType(Res).getSizeInBits() ==
620       getMRI()->getType(Op).getSizeInBits()) {
621     return buildCast(Res, Op);
622   }
623 
624   return buildInstr(TargetOpcode::G_INSERT)
625       .addDef(Res)
626       .addUse(Src)
627       .addUse(Op)
628       .addImm(Index);
629 }
630 
631 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
632                                                      ArrayRef<unsigned> ResultRegs,
633                                                      bool HasSideEffects) {
634   auto MIB =
635       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
636                                 : TargetOpcode::G_INTRINSIC);
637   for (unsigned ResultReg : ResultRegs)
638     MIB.addDef(ResultReg);
639   MIB.addIntrinsicID(ID);
640   return MIB;
641 }
642 
643 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
644                                                      ArrayRef<DstOp> Results,
645                                                      bool HasSideEffects) {
646   auto MIB =
647       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
648                                 : TargetOpcode::G_INTRINSIC);
649   for (DstOp Result : Results)
650     Result.addDefToMIB(*getMRI(), MIB);
651   MIB.addIntrinsicID(ID);
652   return MIB;
653 }
654 
655 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
656                                                  const SrcOp &Op) {
657   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
658 }
659 
660 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
661                                                    const SrcOp &Op) {
662   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
663 }
664 
665 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
666                                                 const DstOp &Res,
667                                                 const SrcOp &Op0,
668                                                 const SrcOp &Op1) {
669   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
670 }
671 
672 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
673                                                 const DstOp &Res,
674                                                 const SrcOp &Op0,
675                                                 const SrcOp &Op1) {
676 
677   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
678 }
679 
680 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
681                                                   const SrcOp &Tst,
682                                                   const SrcOp &Op0,
683                                                   const SrcOp &Op1) {
684 
685   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
686 }
687 
688 MachineInstrBuilder
689 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
690                                            const SrcOp &Elt, const SrcOp &Idx) {
691   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
692 }
693 
694 MachineInstrBuilder
695 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
696                                             const SrcOp &Idx) {
697   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
698 }
699 
700 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
701     unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
702     unsigned NewVal, MachineMemOperand &MMO) {
703 #ifndef NDEBUG
704   LLT OldValResTy = getMRI()->getType(OldValRes);
705   LLT SuccessResTy = getMRI()->getType(SuccessRes);
706   LLT AddrTy = getMRI()->getType(Addr);
707   LLT CmpValTy = getMRI()->getType(CmpVal);
708   LLT NewValTy = getMRI()->getType(NewVal);
709   assert(OldValResTy.isScalar() && "invalid operand type");
710   assert(SuccessResTy.isScalar() && "invalid operand type");
711   assert(AddrTy.isPointer() && "invalid operand type");
712   assert(CmpValTy.isValid() && "invalid operand type");
713   assert(NewValTy.isValid() && "invalid operand type");
714   assert(OldValResTy == CmpValTy && "type mismatch");
715   assert(OldValResTy == NewValTy && "type mismatch");
716 #endif
717 
718   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
719       .addDef(OldValRes)
720       .addDef(SuccessRes)
721       .addUse(Addr)
722       .addUse(CmpVal)
723       .addUse(NewVal)
724       .addMemOperand(&MMO);
725 }
726 
727 MachineInstrBuilder
728 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
729                                      unsigned CmpVal, unsigned NewVal,
730                                      MachineMemOperand &MMO) {
731 #ifndef NDEBUG
732   LLT OldValResTy = getMRI()->getType(OldValRes);
733   LLT AddrTy = getMRI()->getType(Addr);
734   LLT CmpValTy = getMRI()->getType(CmpVal);
735   LLT NewValTy = getMRI()->getType(NewVal);
736   assert(OldValResTy.isScalar() && "invalid operand type");
737   assert(AddrTy.isPointer() && "invalid operand type");
738   assert(CmpValTy.isValid() && "invalid operand type");
739   assert(NewValTy.isValid() && "invalid operand type");
740   assert(OldValResTy == CmpValTy && "type mismatch");
741   assert(OldValResTy == NewValTy && "type mismatch");
742 #endif
743 
744   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
745       .addDef(OldValRes)
746       .addUse(Addr)
747       .addUse(CmpVal)
748       .addUse(NewVal)
749       .addMemOperand(&MMO);
750 }
751 
752 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
753                                                      unsigned OldValRes,
754                                                      unsigned Addr,
755                                                      unsigned Val,
756                                                      MachineMemOperand &MMO) {
757 #ifndef NDEBUG
758   LLT OldValResTy = getMRI()->getType(OldValRes);
759   LLT AddrTy = getMRI()->getType(Addr);
760   LLT ValTy = getMRI()->getType(Val);
761   assert(OldValResTy.isScalar() && "invalid operand type");
762   assert(AddrTy.isPointer() && "invalid operand type");
763   assert(ValTy.isValid() && "invalid operand type");
764   assert(OldValResTy == ValTy && "type mismatch");
765 #endif
766 
767   return buildInstr(Opcode)
768       .addDef(OldValRes)
769       .addUse(Addr)
770       .addUse(Val)
771       .addMemOperand(&MMO);
772 }
773 
774 MachineInstrBuilder
775 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
776                                      unsigned Val, MachineMemOperand &MMO) {
777   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
778                         MMO);
779 }
780 MachineInstrBuilder
781 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
782                                     unsigned Val, MachineMemOperand &MMO) {
783   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
784                         MMO);
785 }
786 MachineInstrBuilder
787 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
788                                     unsigned Val, MachineMemOperand &MMO) {
789   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
790                         MMO);
791 }
792 MachineInstrBuilder
793 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
794                                     unsigned Val, MachineMemOperand &MMO) {
795   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
796                         MMO);
797 }
798 MachineInstrBuilder
799 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
800                                      unsigned Val, MachineMemOperand &MMO) {
801   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
802                         MMO);
803 }
804 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
805                                                        unsigned Addr,
806                                                        unsigned Val,
807                                                        MachineMemOperand &MMO) {
808   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
809                         MMO);
810 }
811 MachineInstrBuilder
812 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
813                                     unsigned Val, MachineMemOperand &MMO) {
814   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
815                         MMO);
816 }
817 MachineInstrBuilder
818 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
819                                     unsigned Val, MachineMemOperand &MMO) {
820   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
821                         MMO);
822 }
823 MachineInstrBuilder
824 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
825                                     unsigned Val, MachineMemOperand &MMO) {
826   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
827                         MMO);
828 }
829 MachineInstrBuilder
830 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
831                                      unsigned Val, MachineMemOperand &MMO) {
832   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
833                         MMO);
834 }
835 MachineInstrBuilder
836 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
837                                      unsigned Val, MachineMemOperand &MMO) {
838   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
839                         MMO);
840 }
841 
842 MachineInstrBuilder
843 MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
844 #ifndef NDEBUG
845   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
846 #endif
847 
848   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
849 }
850 
851 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
852                                         bool IsExtend) {
853 #ifndef NDEBUG
854   if (DstTy.isVector()) {
855     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
856     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
857            "different number of elements in a trunc/ext");
858   } else
859     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
860 
861   if (IsExtend)
862     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
863            "invalid narrowing extend");
864   else
865     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
866            "invalid widening trunc");
867 #endif
868 }
869 
870 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
871                                         const LLT &Op0Ty, const LLT &Op1Ty) {
872 #ifndef NDEBUG
873   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
874          "invalid operand type");
875   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
876   if (ResTy.isScalar() || ResTy.isPointer())
877     assert(TstTy.isScalar() && "type mismatch");
878   else
879     assert((TstTy.isScalar() ||
880             (TstTy.isVector() &&
881              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
882            "type mismatch");
883 #endif
884 }
885 
886 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
887                                                  ArrayRef<DstOp> DstOps,
888                                                  ArrayRef<SrcOp> SrcOps,
889                                                  Optional<unsigned> Flags) {
890   switch (Opc) {
891   default:
892     break;
893   case TargetOpcode::G_SELECT: {
894     assert(DstOps.size() == 1 && "Invalid select");
895     assert(SrcOps.size() == 3 && "Invalid select");
896     validateSelectOp(
897         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
898         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
899     break;
900   }
901   case TargetOpcode::G_ADD:
902   case TargetOpcode::G_AND:
903   case TargetOpcode::G_MUL:
904   case TargetOpcode::G_OR:
905   case TargetOpcode::G_SUB:
906   case TargetOpcode::G_XOR:
907   case TargetOpcode::G_UDIV:
908   case TargetOpcode::G_SDIV:
909   case TargetOpcode::G_UREM:
910   case TargetOpcode::G_SREM:
911   case TargetOpcode::G_SMIN:
912   case TargetOpcode::G_SMAX:
913   case TargetOpcode::G_UMIN:
914   case TargetOpcode::G_UMAX: {
915     // All these are binary ops.
916     assert(DstOps.size() == 1 && "Invalid Dst");
917     assert(SrcOps.size() == 2 && "Invalid Srcs");
918     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
919                      SrcOps[0].getLLTTy(*getMRI()),
920                      SrcOps[1].getLLTTy(*getMRI()));
921     break;
922   }
923   case TargetOpcode::G_SHL:
924   case TargetOpcode::G_ASHR:
925   case TargetOpcode::G_LSHR: {
926     assert(DstOps.size() == 1 && "Invalid Dst");
927     assert(SrcOps.size() == 2 && "Invalid Srcs");
928     validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
929                     SrcOps[0].getLLTTy(*getMRI()),
930                     SrcOps[1].getLLTTy(*getMRI()));
931     break;
932   }
933   case TargetOpcode::G_SEXT:
934   case TargetOpcode::G_ZEXT:
935   case TargetOpcode::G_ANYEXT:
936     assert(DstOps.size() == 1 && "Invalid Dst");
937     assert(SrcOps.size() == 1 && "Invalid Srcs");
938     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
939                      SrcOps[0].getLLTTy(*getMRI()), true);
940     break;
941   case TargetOpcode::G_TRUNC:
942   case TargetOpcode::G_FPTRUNC: {
943     assert(DstOps.size() == 1 && "Invalid Dst");
944     assert(SrcOps.size() == 1 && "Invalid Srcs");
945     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
946                      SrcOps[0].getLLTTy(*getMRI()), false);
947     break;
948   }
949   case TargetOpcode::COPY:
950     assert(DstOps.size() == 1 && "Invalid Dst");
951     // If the caller wants to add a subreg source it has to be done separately
952     // so we may not have any SrcOps at this point yet.
953     break;
954   case TargetOpcode::G_FCMP:
955   case TargetOpcode::G_ICMP: {
956     assert(DstOps.size() == 1 && "Invalid Dst Operands");
957     assert(SrcOps.size() == 3 && "Invalid Src Operands");
958     // For F/ICMP, the first src operand is the predicate, followed by
959     // the two comparands.
960     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
961            "Expecting predicate");
962     assert([&]() -> bool {
963       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
964       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
965                                          : CmpInst::isFPPredicate(Pred);
966     }() && "Invalid predicate");
967     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
968            "Type mismatch");
969     assert([&]() -> bool {
970       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
971       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
972       if (Op0Ty.isScalar() || Op0Ty.isPointer())
973         return DstTy.isScalar();
974       else
975         return DstTy.isVector() &&
976                DstTy.getNumElements() == Op0Ty.getNumElements();
977     }() && "Type Mismatch");
978     break;
979   }
980   case TargetOpcode::G_UNMERGE_VALUES: {
981     assert(!DstOps.empty() && "Invalid trivial sequence");
982     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
983     assert(std::all_of(DstOps.begin(), DstOps.end(),
984                        [&, this](const DstOp &Op) {
985                          return Op.getLLTTy(*getMRI()) ==
986                                 DstOps[0].getLLTTy(*getMRI());
987                        }) &&
988            "type mismatch in output list");
989     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
990                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
991            "input operands do not cover output register");
992     break;
993   }
994   case TargetOpcode::G_MERGE_VALUES: {
995     assert(!SrcOps.empty() && "invalid trivial sequence");
996     assert(DstOps.size() == 1 && "Invalid Dst");
997     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
998                        [&, this](const SrcOp &Op) {
999                          return Op.getLLTTy(*getMRI()) ==
1000                                 SrcOps[0].getLLTTy(*getMRI());
1001                        }) &&
1002            "type mismatch in input list");
1003     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1004                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1005            "input operands do not cover output register");
1006     if (SrcOps.size() == 1)
1007       return buildCast(DstOps[0], SrcOps[0]);
1008     if (DstOps[0].getLLTTy(*getMRI()).isVector())
1009       return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1010     break;
1011   }
1012   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1013     assert(DstOps.size() == 1 && "Invalid Dst size");
1014     assert(SrcOps.size() == 2 && "Invalid Src size");
1015     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1016     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1017             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1018            "Invalid operand type");
1019     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1020     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1021                DstOps[0].getLLTTy(*getMRI()) &&
1022            "Type mismatch");
1023     break;
1024   }
1025   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1026     assert(DstOps.size() == 1 && "Invalid dst size");
1027     assert(SrcOps.size() == 3 && "Invalid src size");
1028     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1029            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1030     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1031                SrcOps[1].getLLTTy(*getMRI()) &&
1032            "Type mismatch");
1033     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1034     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1035                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1036            "Type mismatch");
1037     break;
1038   }
1039   case TargetOpcode::G_BUILD_VECTOR: {
1040     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1041            "Must have at least 2 operands");
1042     assert(DstOps.size() == 1 && "Invalid DstOps");
1043     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1044            "Res type must be a vector");
1045     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1046                        [&, this](const SrcOp &Op) {
1047                          return Op.getLLTTy(*getMRI()) ==
1048                                 SrcOps[0].getLLTTy(*getMRI());
1049                        }) &&
1050            "type mismatch in input list");
1051     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1052                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1053            "input scalars do not exactly cover the output vector register");
1054     break;
1055   }
1056   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1057     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1058            "Must have at least 2 operands");
1059     assert(DstOps.size() == 1 && "Invalid DstOps");
1060     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1061            "Res type must be a vector");
1062     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1063                        [&, this](const SrcOp &Op) {
1064                          return Op.getLLTTy(*getMRI()) ==
1065                                 SrcOps[0].getLLTTy(*getMRI());
1066                        }) &&
1067            "type mismatch in input list");
1068     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1069         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1070       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1071     break;
1072   }
1073   case TargetOpcode::G_CONCAT_VECTORS: {
1074     assert(DstOps.size() == 1 && "Invalid DstOps");
1075     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1076            "Must have at least 2 operands");
1077     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1078                        [&, this](const SrcOp &Op) {
1079                          return (Op.getLLTTy(*getMRI()).isVector() &&
1080                                  Op.getLLTTy(*getMRI()) ==
1081                                      SrcOps[0].getLLTTy(*getMRI()));
1082                        }) &&
1083            "type mismatch in input list");
1084     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1085                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1086            "input vectors do not exactly cover the output vector register");
1087     break;
1088   }
1089   case TargetOpcode::G_UADDE: {
1090     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1091     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1092     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1093     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1094            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1095            "Invalid operand");
1096     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1097     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1098            "type mismatch");
1099     break;
1100   }
1101   }
1102 
1103   auto MIB = buildInstr(Opc);
1104   for (const DstOp &Op : DstOps)
1105     Op.addDefToMIB(*getMRI(), MIB);
1106   for (const SrcOp &Op : SrcOps)
1107     Op.addSrcToMIB(MIB);
1108   if (Flags)
1109     MIB->setFlags(*Flags);
1110   return MIB;
1111 }
1112