1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
164   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165   return buildInstr(TargetOpcode::G_FRAME_INDEX)
166       .addDef(Res)
167       .addFrameIndex(Idx);
168 }
169 
170 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
171                                                        const GlobalValue *GV) {
172   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173   assert(getMRI()->getType(Res).getAddressSpace() ==
174              GV->getType()->getAddressSpace() &&
175          "address space mismatch");
176 
177   return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178       .addDef(Res)
179       .addGlobalAddress(GV);
180 }
181 
182 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
183                                         const LLT &Op1) {
184   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
185   assert((Res == Op0 && Res == Op1) && "type mismatch");
186 }
187 
188 MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
189                                                unsigned Op1) {
190   assert(getMRI()->getType(Res).isPointer() &&
191          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
192   assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
193 
194   return buildInstr(TargetOpcode::G_GEP)
195       .addDef(Res)
196       .addUse(Op0)
197       .addUse(Op1);
198 }
199 
200 Optional<MachineInstrBuilder>
201 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
202                                  const LLT &ValueTy, uint64_t Value) {
203   assert(Res == 0 && "Res is a result argument");
204   assert(ValueTy.isScalar()  && "invalid offset type");
205 
206   if (Value == 0) {
207     Res = Op0;
208     return None;
209   }
210 
211   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
212   unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
213 
214   buildConstant(TmpReg, Value);
215   return buildGEP(Res, Op0, TmpReg);
216 }
217 
218 MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
219                                                    uint32_t NumBits) {
220   assert(getMRI()->getType(Res).isPointer() &&
221          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
222 
223   return buildInstr(TargetOpcode::G_PTR_MASK)
224       .addDef(Res)
225       .addUse(Op0)
226       .addImm(NumBits);
227 }
228 
229 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
230   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
231 }
232 
233 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
234   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
235   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
236 }
237 
238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
239                                                 const SrcOp &Op) {
240   return buildInstr(TargetOpcode::COPY, Res, Op);
241 }
242 
243 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
244                                                     const ConstantInt &Val) {
245   LLT Ty = Res.getLLTTy(*getMRI());
246   LLT EltTy = Ty.getScalarType();
247 
248   const ConstantInt *NewVal = &Val;
249   if (EltTy.getSizeInBits() != Val.getBitWidth()) {
250     NewVal = ConstantInt::get(
251       getMF().getFunction().getContext(),
252       Val.getValue().sextOrTrunc(EltTy.getSizeInBits()));
253   }
254 
255   if (Ty.isVector()) {
256     unsigned EltReg = getMRI()->createGenericVirtualRegister(EltTy);
257     buildInstr(TargetOpcode::G_CONSTANT)
258       .addDef(EltReg)
259       .addCImm(NewVal);
260 
261     auto MIB = buildInstr(TargetOpcode::G_BUILD_VECTOR);
262     Res.addDefToMIB(*getMRI(), MIB);
263 
264     for (unsigned I = 0, E = Ty.getNumElements(); I != E; ++I)
265       MIB.addUse(EltReg);
266     return MIB;
267   }
268 
269   auto MIB = buildInstr(TargetOpcode::G_CONSTANT);
270   Res.addDefToMIB(*getMRI(), MIB);
271   MIB.addCImm(NewVal);
272   return MIB;
273 }
274 
275 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
276                                                     int64_t Val) {
277   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
278                                Res.getLLTTy(*getMRI()).getSizeInBits());
279   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
280   return buildConstant(Res, *CI);
281 }
282 
283 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
284                                                      const ConstantFP &Val) {
285   LLT Ty = Res.getLLTTy(*getMRI());
286 
287   assert(!Ty.isPointer() && "invalid operand type");
288 
289   if (Ty.isVector()) {
290     unsigned EltReg
291       = getMRI()->createGenericVirtualRegister(Ty.getElementType());
292     buildInstr(TargetOpcode::G_FCONSTANT)
293       .addDef(EltReg)
294       .addFPImm(&Val);
295 
296     auto MIB = buildInstr(TargetOpcode::G_BUILD_VECTOR);
297     Res.addDefToMIB(*getMRI(), MIB);
298 
299     for (unsigned I = 0, E = Ty.getNumElements(); I != E; ++I)
300       MIB.addUse(EltReg);
301     return MIB;
302   }
303 
304   auto MIB = buildInstr(TargetOpcode::G_FCONSTANT);
305   Res.addDefToMIB(*getMRI(), MIB);
306   MIB.addFPImm(&Val);
307   return MIB;
308 }
309 
310 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
311                                                      double Val) {
312   LLT DstTy = Res.getLLTTy(*getMRI());
313   auto &Ctx = getMF().getFunction().getContext();
314   auto *CFP =
315       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getSizeInBits()));
316   return buildFConstant(Res, *CFP);
317 }
318 
319 MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
320                                                   MachineBasicBlock &Dest) {
321   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
322 
323   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
324 }
325 
326 MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
327                                                 MachineMemOperand &MMO) {
328   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
329 }
330 
331 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
332                                                      unsigned Res,
333                                                      unsigned Addr,
334                                                      MachineMemOperand &MMO) {
335   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
336   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
337 
338   return buildInstr(Opcode)
339       .addDef(Res)
340       .addUse(Addr)
341       .addMemOperand(&MMO);
342 }
343 
344 MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
345                                                  MachineMemOperand &MMO) {
346   assert(getMRI()->getType(Val).isValid() && "invalid operand type");
347   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
348 
349   return buildInstr(TargetOpcode::G_STORE)
350       .addUse(Val)
351       .addUse(Addr)
352       .addMemOperand(&MMO);
353 }
354 
355 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
356                                                  const DstOp &CarryOut,
357                                                  const SrcOp &Op0,
358                                                  const SrcOp &Op1,
359                                                  const SrcOp &CarryIn) {
360   return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
361                     {Op0, Op1, CarryIn});
362 }
363 
364 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
365                                                   const SrcOp &Op) {
366   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
367 }
368 
369 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
370                                                 const SrcOp &Op) {
371   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
372 }
373 
374 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
375                                                 const SrcOp &Op) {
376   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
377 }
378 
379 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
380   const auto *TLI = getMF().getSubtarget().getTargetLowering();
381   switch (TLI->getBooleanContents(IsVec, IsFP)) {
382   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
383     return TargetOpcode::G_SEXT;
384   case TargetLoweringBase::ZeroOrOneBooleanContent:
385     return TargetOpcode::G_ZEXT;
386   default:
387     return TargetOpcode::G_ANYEXT;
388   }
389 }
390 
391 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
392                                                    const SrcOp &Op,
393                                                    bool IsFP) {
394   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
395   return buildInstr(ExtOp, Res, Op);
396 }
397 
398 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
399                                                       const DstOp &Res,
400                                                       const SrcOp &Op) {
401   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
402           TargetOpcode::G_SEXT == ExtOpc) &&
403          "Expecting Extending Opc");
404   assert(Res.getLLTTy(*getMRI()).isScalar() ||
405          Res.getLLTTy(*getMRI()).isVector());
406   assert(Res.getLLTTy(*getMRI()).isScalar() ==
407          Op.getLLTTy(*getMRI()).isScalar());
408 
409   unsigned Opcode = TargetOpcode::COPY;
410   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
411       Op.getLLTTy(*getMRI()).getSizeInBits())
412     Opcode = ExtOpc;
413   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
414            Op.getLLTTy(*getMRI()).getSizeInBits())
415     Opcode = TargetOpcode::G_TRUNC;
416   else
417     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
418 
419   return buildInstr(Opcode, Res, Op);
420 }
421 
422 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
423                                                        const SrcOp &Op) {
424   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
425 }
426 
427 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
428                                                        const SrcOp &Op) {
429   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
430 }
431 
432 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
433                                                          const SrcOp &Op) {
434   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
435 }
436 
437 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
438                                                 const SrcOp &Src) {
439   LLT SrcTy = Src.getLLTTy(*getMRI());
440   LLT DstTy = Dst.getLLTTy(*getMRI());
441   if (SrcTy == DstTy)
442     return buildCopy(Dst, Src);
443 
444   unsigned Opcode;
445   if (SrcTy.isPointer() && DstTy.isScalar())
446     Opcode = TargetOpcode::G_PTRTOINT;
447   else if (DstTy.isPointer() && SrcTy.isScalar())
448     Opcode = TargetOpcode::G_INTTOPTR;
449   else {
450     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
451     Opcode = TargetOpcode::G_BITCAST;
452   }
453 
454   return buildInstr(Opcode, Dst, Src);
455 }
456 
457 MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
458                                                    uint64_t Index) {
459 #ifndef NDEBUG
460   assert(getMRI()->getType(Src).isValid() && "invalid operand type");
461   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
462   assert(Index + getMRI()->getType(Res).getSizeInBits() <=
463              getMRI()->getType(Src).getSizeInBits() &&
464          "extracting off end of register");
465 #endif
466 
467   if (getMRI()->getType(Res).getSizeInBits() ==
468       getMRI()->getType(Src).getSizeInBits()) {
469     assert(Index == 0 && "insertion past the end of a register");
470     return buildCast(Res, Src);
471   }
472 
473   return buildInstr(TargetOpcode::G_EXTRACT)
474       .addDef(Res)
475       .addUse(Src)
476       .addImm(Index);
477 }
478 
479 void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
480                                      ArrayRef<uint64_t> Indices) {
481 #ifndef NDEBUG
482   assert(Ops.size() == Indices.size() && "incompatible args");
483   assert(!Ops.empty() && "invalid trivial sequence");
484   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
485          "sequence offsets must be in ascending order");
486 
487   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
488   for (auto Op : Ops)
489     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
490 #endif
491 
492   LLT ResTy = getMRI()->getType(Res);
493   LLT OpTy = getMRI()->getType(Ops[0]);
494   unsigned OpSize = OpTy.getSizeInBits();
495   bool MaybeMerge = true;
496   for (unsigned i = 0; i < Ops.size(); ++i) {
497     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
498       MaybeMerge = false;
499       break;
500     }
501   }
502 
503   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
504     buildMerge(Res, Ops);
505     return;
506   }
507 
508   unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
509   buildUndef(ResIn);
510 
511   for (unsigned i = 0; i < Ops.size(); ++i) {
512     unsigned ResOut = i + 1 == Ops.size()
513                           ? Res
514                           : getMRI()->createGenericVirtualRegister(ResTy);
515     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
516     ResIn = ResOut;
517   }
518 }
519 
520 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
521   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
522 }
523 
524 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
525                                                  ArrayRef<unsigned> Ops) {
526   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
527   // we need some temporary storage for the DstOp objects. Here we use a
528   // sufficiently large SmallVector to not go through the heap.
529   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
530   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
531 }
532 
533 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
534                                                    const SrcOp &Op) {
535   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
536   // we need some temporary storage for the DstOp objects. Here we use a
537   // sufficiently large SmallVector to not go through the heap.
538   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
539   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
540 }
541 
542 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
543                                                    const SrcOp &Op) {
544   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
545   // we need some temporary storage for the DstOp objects. Here we use a
546   // sufficiently large SmallVector to not go through the heap.
547   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
548   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
549 }
550 
551 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
552                                                        ArrayRef<unsigned> Ops) {
553   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
554   // we need some temporary storage for the DstOp objects. Here we use a
555   // sufficiently large SmallVector to not go through the heap.
556   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
557   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
558 }
559 
560 MachineInstrBuilder
561 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
562                                         ArrayRef<unsigned> Ops) {
563   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
564   // we need some temporary storage for the DstOp objects. Here we use a
565   // sufficiently large SmallVector to not go through the heap.
566   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
567   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
568 }
569 
570 MachineInstrBuilder
571 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
572   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
573   // we need some temporary storage for the DstOp objects. Here we use a
574   // sufficiently large SmallVector to not go through the heap.
575   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
576   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
577 }
578 
579 MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
580                                                   unsigned Op, unsigned Index) {
581   assert(Index + getMRI()->getType(Op).getSizeInBits() <=
582              getMRI()->getType(Res).getSizeInBits() &&
583          "insertion past the end of a register");
584 
585   if (getMRI()->getType(Res).getSizeInBits() ==
586       getMRI()->getType(Op).getSizeInBits()) {
587     return buildCast(Res, Op);
588   }
589 
590   return buildInstr(TargetOpcode::G_INSERT)
591       .addDef(Res)
592       .addUse(Src)
593       .addUse(Op)
594       .addImm(Index);
595 }
596 
597 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
598                                                      unsigned Res,
599                                                      bool HasSideEffects) {
600   auto MIB =
601       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
602                                 : TargetOpcode::G_INTRINSIC);
603   if (Res)
604     MIB.addDef(Res);
605   MIB.addIntrinsicID(ID);
606   return MIB;
607 }
608 
609 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
610                                                  const SrcOp &Op) {
611   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
612 }
613 
614 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
615                                                    const SrcOp &Op) {
616   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
617 }
618 
619 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
620                                                 const DstOp &Res,
621                                                 const SrcOp &Op0,
622                                                 const SrcOp &Op1) {
623   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
624 }
625 
626 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
627                                                 const DstOp &Res,
628                                                 const SrcOp &Op0,
629                                                 const SrcOp &Op1) {
630 
631   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
632 }
633 
634 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
635                                                   const SrcOp &Tst,
636                                                   const SrcOp &Op0,
637                                                   const SrcOp &Op1) {
638 
639   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
640 }
641 
642 MachineInstrBuilder
643 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
644                                            const SrcOp &Elt, const SrcOp &Idx) {
645   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
646 }
647 
648 MachineInstrBuilder
649 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
650                                             const SrcOp &Idx) {
651   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
652 }
653 
654 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
655     unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
656     unsigned NewVal, MachineMemOperand &MMO) {
657 #ifndef NDEBUG
658   LLT OldValResTy = getMRI()->getType(OldValRes);
659   LLT SuccessResTy = getMRI()->getType(SuccessRes);
660   LLT AddrTy = getMRI()->getType(Addr);
661   LLT CmpValTy = getMRI()->getType(CmpVal);
662   LLT NewValTy = getMRI()->getType(NewVal);
663   assert(OldValResTy.isScalar() && "invalid operand type");
664   assert(SuccessResTy.isScalar() && "invalid operand type");
665   assert(AddrTy.isPointer() && "invalid operand type");
666   assert(CmpValTy.isValid() && "invalid operand type");
667   assert(NewValTy.isValid() && "invalid operand type");
668   assert(OldValResTy == CmpValTy && "type mismatch");
669   assert(OldValResTy == NewValTy && "type mismatch");
670 #endif
671 
672   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
673       .addDef(OldValRes)
674       .addDef(SuccessRes)
675       .addUse(Addr)
676       .addUse(CmpVal)
677       .addUse(NewVal)
678       .addMemOperand(&MMO);
679 }
680 
681 MachineInstrBuilder
682 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
683                                      unsigned CmpVal, unsigned NewVal,
684                                      MachineMemOperand &MMO) {
685 #ifndef NDEBUG
686   LLT OldValResTy = getMRI()->getType(OldValRes);
687   LLT AddrTy = getMRI()->getType(Addr);
688   LLT CmpValTy = getMRI()->getType(CmpVal);
689   LLT NewValTy = getMRI()->getType(NewVal);
690   assert(OldValResTy.isScalar() && "invalid operand type");
691   assert(AddrTy.isPointer() && "invalid operand type");
692   assert(CmpValTy.isValid() && "invalid operand type");
693   assert(NewValTy.isValid() && "invalid operand type");
694   assert(OldValResTy == CmpValTy && "type mismatch");
695   assert(OldValResTy == NewValTy && "type mismatch");
696 #endif
697 
698   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
699       .addDef(OldValRes)
700       .addUse(Addr)
701       .addUse(CmpVal)
702       .addUse(NewVal)
703       .addMemOperand(&MMO);
704 }
705 
706 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
707                                                      unsigned OldValRes,
708                                                      unsigned Addr,
709                                                      unsigned Val,
710                                                      MachineMemOperand &MMO) {
711 #ifndef NDEBUG
712   LLT OldValResTy = getMRI()->getType(OldValRes);
713   LLT AddrTy = getMRI()->getType(Addr);
714   LLT ValTy = getMRI()->getType(Val);
715   assert(OldValResTy.isScalar() && "invalid operand type");
716   assert(AddrTy.isPointer() && "invalid operand type");
717   assert(ValTy.isValid() && "invalid operand type");
718   assert(OldValResTy == ValTy && "type mismatch");
719 #endif
720 
721   return buildInstr(Opcode)
722       .addDef(OldValRes)
723       .addUse(Addr)
724       .addUse(Val)
725       .addMemOperand(&MMO);
726 }
727 
728 MachineInstrBuilder
729 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
730                                      unsigned Val, MachineMemOperand &MMO) {
731   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
732                         MMO);
733 }
734 MachineInstrBuilder
735 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
736                                     unsigned Val, MachineMemOperand &MMO) {
737   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
738                         MMO);
739 }
740 MachineInstrBuilder
741 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
742                                     unsigned Val, MachineMemOperand &MMO) {
743   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
744                         MMO);
745 }
746 MachineInstrBuilder
747 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
748                                     unsigned Val, MachineMemOperand &MMO) {
749   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
750                         MMO);
751 }
752 MachineInstrBuilder
753 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
754                                      unsigned Val, MachineMemOperand &MMO) {
755   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
756                         MMO);
757 }
758 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
759                                                        unsigned Addr,
760                                                        unsigned Val,
761                                                        MachineMemOperand &MMO) {
762   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
763                         MMO);
764 }
765 MachineInstrBuilder
766 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
767                                     unsigned Val, MachineMemOperand &MMO) {
768   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
769                         MMO);
770 }
771 MachineInstrBuilder
772 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
773                                     unsigned Val, MachineMemOperand &MMO) {
774   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
775                         MMO);
776 }
777 MachineInstrBuilder
778 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
779                                     unsigned Val, MachineMemOperand &MMO) {
780   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
781                         MMO);
782 }
783 MachineInstrBuilder
784 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
785                                      unsigned Val, MachineMemOperand &MMO) {
786   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
787                         MMO);
788 }
789 MachineInstrBuilder
790 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
791                                      unsigned Val, MachineMemOperand &MMO) {
792   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
793                         MMO);
794 }
795 
796 MachineInstrBuilder
797 MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
798 #ifndef NDEBUG
799   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
800 #endif
801 
802   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
803 }
804 
805 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
806                                         bool IsExtend) {
807 #ifndef NDEBUG
808   if (DstTy.isVector()) {
809     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
810     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
811            "different number of elements in a trunc/ext");
812   } else
813     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
814 
815   if (IsExtend)
816     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
817            "invalid narrowing extend");
818   else
819     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
820            "invalid widening trunc");
821 #endif
822 }
823 
824 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
825                                         const LLT &Op0Ty, const LLT &Op1Ty) {
826 #ifndef NDEBUG
827   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
828          "invalid operand type");
829   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
830   if (ResTy.isScalar() || ResTy.isPointer())
831     assert(TstTy.isScalar() && "type mismatch");
832   else
833     assert((TstTy.isScalar() ||
834             (TstTy.isVector() &&
835              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
836            "type mismatch");
837 #endif
838 }
839 
840 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
841                                                  ArrayRef<DstOp> DstOps,
842                                                  ArrayRef<SrcOp> SrcOps,
843                                                  Optional<unsigned> Flags) {
844   switch (Opc) {
845   default:
846     break;
847   case TargetOpcode::G_SELECT: {
848     assert(DstOps.size() == 1 && "Invalid select");
849     assert(SrcOps.size() == 3 && "Invalid select");
850     validateSelectOp(
851         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
852         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
853     break;
854   }
855   case TargetOpcode::G_ADD:
856   case TargetOpcode::G_AND:
857   case TargetOpcode::G_ASHR:
858   case TargetOpcode::G_LSHR:
859   case TargetOpcode::G_MUL:
860   case TargetOpcode::G_OR:
861   case TargetOpcode::G_SHL:
862   case TargetOpcode::G_SUB:
863   case TargetOpcode::G_XOR:
864   case TargetOpcode::G_UDIV:
865   case TargetOpcode::G_SDIV:
866   case TargetOpcode::G_UREM:
867   case TargetOpcode::G_SREM: {
868     // All these are binary ops.
869     assert(DstOps.size() == 1 && "Invalid Dst");
870     assert(SrcOps.size() == 2 && "Invalid Srcs");
871     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
872                      SrcOps[0].getLLTTy(*getMRI()),
873                      SrcOps[1].getLLTTy(*getMRI()));
874     break;
875   case TargetOpcode::G_SEXT:
876   case TargetOpcode::G_ZEXT:
877   case TargetOpcode::G_ANYEXT:
878     assert(DstOps.size() == 1 && "Invalid Dst");
879     assert(SrcOps.size() == 1 && "Invalid Srcs");
880     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
881                      SrcOps[0].getLLTTy(*getMRI()), true);
882     break;
883   case TargetOpcode::G_TRUNC:
884   case TargetOpcode::G_FPTRUNC:
885     assert(DstOps.size() == 1 && "Invalid Dst");
886     assert(SrcOps.size() == 1 && "Invalid Srcs");
887     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
888                      SrcOps[0].getLLTTy(*getMRI()), false);
889     break;
890   }
891   case TargetOpcode::COPY:
892     assert(DstOps.size() == 1 && "Invalid Dst");
893     assert(SrcOps.size() == 1 && "Invalid Srcs");
894     assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
895            SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
896            DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
897     break;
898   case TargetOpcode::G_FCMP:
899   case TargetOpcode::G_ICMP: {
900     assert(DstOps.size() == 1 && "Invalid Dst Operands");
901     assert(SrcOps.size() == 3 && "Invalid Src Operands");
902     // For F/ICMP, the first src operand is the predicate, followed by
903     // the two comparands.
904     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
905            "Expecting predicate");
906     assert([&]() -> bool {
907       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
908       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
909                                          : CmpInst::isFPPredicate(Pred);
910     }() && "Invalid predicate");
911     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
912            "Type mismatch");
913     assert([&]() -> bool {
914       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
915       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
916       if (Op0Ty.isScalar() || Op0Ty.isPointer())
917         return DstTy.isScalar();
918       else
919         return DstTy.isVector() &&
920                DstTy.getNumElements() == Op0Ty.getNumElements();
921     }() && "Type Mismatch");
922     break;
923   }
924   case TargetOpcode::G_UNMERGE_VALUES: {
925     assert(!DstOps.empty() && "Invalid trivial sequence");
926     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
927     assert(std::all_of(DstOps.begin(), DstOps.end(),
928                        [&, this](const DstOp &Op) {
929                          return Op.getLLTTy(*getMRI()) ==
930                                 DstOps[0].getLLTTy(*getMRI());
931                        }) &&
932            "type mismatch in output list");
933     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
934                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
935            "input operands do not cover output register");
936     break;
937   }
938   case TargetOpcode::G_MERGE_VALUES: {
939     assert(!SrcOps.empty() && "invalid trivial sequence");
940     assert(DstOps.size() == 1 && "Invalid Dst");
941     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
942                        [&, this](const SrcOp &Op) {
943                          return Op.getLLTTy(*getMRI()) ==
944                                 SrcOps[0].getLLTTy(*getMRI());
945                        }) &&
946            "type mismatch in input list");
947     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
948                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
949            "input operands do not cover output register");
950     if (SrcOps.size() == 1)
951       return buildCast(DstOps[0], SrcOps[0]);
952     if (DstOps[0].getLLTTy(*getMRI()).isVector())
953       return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
954     break;
955   }
956   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
957     assert(DstOps.size() == 1 && "Invalid Dst size");
958     assert(SrcOps.size() == 2 && "Invalid Src size");
959     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
960     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
961             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
962            "Invalid operand type");
963     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
964     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
965                DstOps[0].getLLTTy(*getMRI()) &&
966            "Type mismatch");
967     break;
968   }
969   case TargetOpcode::G_INSERT_VECTOR_ELT: {
970     assert(DstOps.size() == 1 && "Invalid dst size");
971     assert(SrcOps.size() == 3 && "Invalid src size");
972     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
973            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
974     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
975                SrcOps[1].getLLTTy(*getMRI()) &&
976            "Type mismatch");
977     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
978     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
979                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
980            "Type mismatch");
981     break;
982   }
983   case TargetOpcode::G_BUILD_VECTOR: {
984     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
985            "Must have at least 2 operands");
986     assert(DstOps.size() == 1 && "Invalid DstOps");
987     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
988            "Res type must be a vector");
989     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
990                        [&, this](const SrcOp &Op) {
991                          return Op.getLLTTy(*getMRI()) ==
992                                 SrcOps[0].getLLTTy(*getMRI());
993                        }) &&
994            "type mismatch in input list");
995     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
996                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
997            "input scalars do not exactly cover the output vector register");
998     break;
999   }
1000   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1001     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1002            "Must have at least 2 operands");
1003     assert(DstOps.size() == 1 && "Invalid DstOps");
1004     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1005            "Res type must be a vector");
1006     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1007                        [&, this](const SrcOp &Op) {
1008                          return Op.getLLTTy(*getMRI()) ==
1009                                 SrcOps[0].getLLTTy(*getMRI());
1010                        }) &&
1011            "type mismatch in input list");
1012     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1013         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1014       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1015     break;
1016   }
1017   case TargetOpcode::G_CONCAT_VECTORS: {
1018     assert(DstOps.size() == 1 && "Invalid DstOps");
1019     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1020            "Must have at least 2 operands");
1021     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1022                        [&, this](const SrcOp &Op) {
1023                          return (Op.getLLTTy(*getMRI()).isVector() &&
1024                                  Op.getLLTTy(*getMRI()) ==
1025                                      SrcOps[0].getLLTTy(*getMRI()));
1026                        }) &&
1027            "type mismatch in input list");
1028     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1029                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1030            "input vectors do not exactly cover the output vector register");
1031     break;
1032   }
1033   case TargetOpcode::G_UADDE: {
1034     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1035     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1036     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1037     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1038            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1039            "Invalid operand");
1040     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1041     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1042            "type mismatch");
1043     break;
1044   }
1045   }
1046 
1047   auto MIB = buildInstr(Opc);
1048   for (const DstOp &Op : DstOps)
1049     Op.addDefToMIB(*getMRI(), MIB);
1050   for (const SrcOp &Op : SrcOps)
1051     Op.addSrcToMIB(MIB);
1052   if (Flags)
1053     MIB->setFlags(*Flags);
1054   return MIB;
1055 }
1056