1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/CodeGen/TargetOpcodes.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
26 void MachineIRBuilder::setMF(MachineFunction &MF) {
27   State.MF = &MF;
28   State.MBB = nullptr;
29   State.MRI = &MF.getRegInfo();
30   State.TII = MF.getSubtarget().getInstrInfo();
31   State.DL = DebugLoc();
32   State.II = MachineBasicBlock::iterator();
33   State.Observer = nullptr;
34 }
35 
36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
37   State.MBB = &MBB;
38   State.II = MBB.end();
39   assert(&getMF() == MBB.getParent() &&
40          "Basic block is in a different function");
41 }
42 
43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
44   assert(MI.getParent() && "Instruction is not part of a basic block");
45   setMBB(*MI.getParent());
46   State.II = MI.getIterator();
47 }
48 
49 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
50 
51 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
52                                    MachineBasicBlock::iterator II) {
53   assert(MBB.getParent() == &getMF() &&
54          "Basic block is in a different function");
55   State.MBB = &MBB;
56   State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60   if (State.Observer)
61     State.Observer->createdInstr(*InsertedInstr);
62 }
63 
64 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
65   State.Observer = &Observer;
66 }
67 
68 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
75   return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80   return MIB;
81 }
82 
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
84   getMBB().insert(getInsertPt(), MIB);
85   recordInsertion(MIB);
86   return MIB;
87 }
88 
89 MachineInstrBuilder
90 MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
91                                       const MDNode *Expr) {
92   assert(isa<DILocalVariable>(Variable) && "not a variable");
93   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94   assert(
95       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96       "Expected inlined-at fields to agree");
97   return insertInstr(BuildMI(getMF(), getDL(),
98                              getTII().get(TargetOpcode::DBG_VALUE),
99                              /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
102 MachineInstrBuilder
103 MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
104                                         const MDNode *Expr) {
105   assert(isa<DILocalVariable>(Variable) && "not a variable");
106   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107   assert(
108       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109       "Expected inlined-at fields to agree");
110   return insertInstr(BuildMI(getMF(), getDL(),
111                              getTII().get(TargetOpcode::DBG_VALUE),
112                              /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
115 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
116                                                       const MDNode *Variable,
117                                                       const MDNode *Expr) {
118   assert(isa<DILocalVariable>(Variable) && "not a variable");
119   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120   assert(
121       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122       "Expected inlined-at fields to agree");
123   return buildInstr(TargetOpcode::DBG_VALUE)
124       .addFrameIndex(FI)
125       .addImm(0)
126       .addMetadata(Variable)
127       .addMetadata(Expr);
128 }
129 
130 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
131                                                          const MDNode *Variable,
132                                                          const MDNode *Expr) {
133   assert(isa<DILocalVariable>(Variable) && "not a variable");
134   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135   assert(
136       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137       "Expected inlined-at fields to agree");
138   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140     if (CI->getBitWidth() > 64)
141       MIB.addCImm(CI);
142     else
143       MIB.addImm(CI->getZExtValue());
144   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145     MIB.addFPImm(CFP);
146   } else {
147     // Insert %noreg if we didn't find a usable constant and had to drop it.
148     MIB.addReg(0U);
149   }
150 
151   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
154 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
155   assert(isa<DILabel>(Label) && "not a label");
156   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157          "Expected inlined-at fields to agree");
158   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160   return MIB.addMetadata(Label);
161 }
162 
163 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
164   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165   return buildInstr(TargetOpcode::G_FRAME_INDEX)
166       .addDef(Res)
167       .addFrameIndex(Idx);
168 }
169 
170 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
171                                                        const GlobalValue *GV) {
172   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173   assert(getMRI()->getType(Res).getAddressSpace() ==
174              GV->getType()->getAddressSpace() &&
175          "address space mismatch");
176 
177   return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178       .addDef(Res)
179       .addGlobalAddress(GV);
180 }
181 
182 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
183                                         const LLT &Op1) {
184   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
185   assert((Res == Op0 && Res == Op1) && "type mismatch");
186 }
187 
188 MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
189                                                unsigned Op1) {
190   assert(getMRI()->getType(Res).isPointer() &&
191          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
192   assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
193 
194   return buildInstr(TargetOpcode::G_GEP)
195       .addDef(Res)
196       .addUse(Op0)
197       .addUse(Op1);
198 }
199 
200 Optional<MachineInstrBuilder>
201 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
202                                  const LLT &ValueTy, uint64_t Value) {
203   assert(Res == 0 && "Res is a result argument");
204   assert(ValueTy.isScalar()  && "invalid offset type");
205 
206   if (Value == 0) {
207     Res = Op0;
208     return None;
209   }
210 
211   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
212   unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
213 
214   buildConstant(TmpReg, Value);
215   return buildGEP(Res, Op0, TmpReg);
216 }
217 
218 MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
219                                                    uint32_t NumBits) {
220   assert(getMRI()->getType(Res).isPointer() &&
221          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
222 
223   return buildInstr(TargetOpcode::G_PTR_MASK)
224       .addDef(Res)
225       .addUse(Op0)
226       .addImm(NumBits);
227 }
228 
229 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
230   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
231 }
232 
233 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
234   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
235   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
236 }
237 
238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
239                                                 const SrcOp &Op) {
240   return buildInstr(TargetOpcode::COPY, Res, Op);
241 }
242 
243 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
244                                                     const ConstantInt &Val) {
245   LLT Ty = Res.getLLTTy(*getMRI());
246   LLT EltTy = Ty.getScalarType();
247   assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
248          "creating constant with the wrong size");
249 
250   if (Ty.isVector()) {
251     auto Const = buildInstr(TargetOpcode::G_CONSTANT)
252     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
253     .addCImm(&Val);
254     return buildSplatVector(Res, Const);
255   }
256 
257   auto Const = buildInstr(TargetOpcode::G_CONSTANT);
258   Res.addDefToMIB(*getMRI(), Const);
259   Const.addCImm(&Val);
260   return Const;
261 }
262 
263 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
264                                                     int64_t Val) {
265   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
266                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
267   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
268   return buildConstant(Res, *CI);
269 }
270 
271 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
272                                                      const ConstantFP &Val) {
273   LLT Ty = Res.getLLTTy(*getMRI());
274   LLT EltTy = Ty.getScalarType();
275 
276   assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
277          == EltTy.getSizeInBits() &&
278          "creating fconstant with the wrong size");
279 
280   assert(!Ty.isPointer() && "invalid operand type");
281 
282   if (Ty.isVector()) {
283     auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
284     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
285     .addFPImm(&Val);
286 
287     return buildSplatVector(Res, Const);
288   }
289 
290   auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
291   Res.addDefToMIB(*getMRI(), Const);
292   Const.addFPImm(&Val);
293   return Const;
294 }
295 
296 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
297                                                     const APInt &Val) {
298   ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
299   return buildConstant(Res, *CI);
300 }
301 
302 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
303                                                      double Val) {
304   LLT DstTy = Res.getLLTTy(*getMRI());
305   auto &Ctx = getMF().getFunction().getContext();
306   auto *CFP =
307       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
308   return buildFConstant(Res, *CFP);
309 }
310 
311 MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
312                                                   MachineBasicBlock &Dest) {
313   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
314 
315   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
316 }
317 
318 MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
319                                                 MachineMemOperand &MMO) {
320   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
321 }
322 
323 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
324                                                      unsigned Res,
325                                                      unsigned Addr,
326                                                      MachineMemOperand &MMO) {
327   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
328   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
329 
330   return buildInstr(Opcode)
331       .addDef(Res)
332       .addUse(Addr)
333       .addMemOperand(&MMO);
334 }
335 
336 MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
337                                                  MachineMemOperand &MMO) {
338   assert(getMRI()->getType(Val).isValid() && "invalid operand type");
339   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
340 
341   return buildInstr(TargetOpcode::G_STORE)
342       .addUse(Val)
343       .addUse(Addr)
344       .addMemOperand(&MMO);
345 }
346 
347 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
348                                                  const DstOp &CarryOut,
349                                                  const SrcOp &Op0,
350                                                  const SrcOp &Op1,
351                                                  const SrcOp &CarryIn) {
352   return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
353                     {Op0, Op1, CarryIn});
354 }
355 
356 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
357                                                   const SrcOp &Op) {
358   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
359 }
360 
361 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
362                                                 const SrcOp &Op) {
363   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
364 }
365 
366 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
367                                                 const SrcOp &Op) {
368   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
369 }
370 
371 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
372   const auto *TLI = getMF().getSubtarget().getTargetLowering();
373   switch (TLI->getBooleanContents(IsVec, IsFP)) {
374   case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
375     return TargetOpcode::G_SEXT;
376   case TargetLoweringBase::ZeroOrOneBooleanContent:
377     return TargetOpcode::G_ZEXT;
378   default:
379     return TargetOpcode::G_ANYEXT;
380   }
381 }
382 
383 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
384                                                    const SrcOp &Op,
385                                                    bool IsFP) {
386   unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
387   return buildInstr(ExtOp, Res, Op);
388 }
389 
390 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
391                                                       const DstOp &Res,
392                                                       const SrcOp &Op) {
393   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
394           TargetOpcode::G_SEXT == ExtOpc) &&
395          "Expecting Extending Opc");
396   assert(Res.getLLTTy(*getMRI()).isScalar() ||
397          Res.getLLTTy(*getMRI()).isVector());
398   assert(Res.getLLTTy(*getMRI()).isScalar() ==
399          Op.getLLTTy(*getMRI()).isScalar());
400 
401   unsigned Opcode = TargetOpcode::COPY;
402   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
403       Op.getLLTTy(*getMRI()).getSizeInBits())
404     Opcode = ExtOpc;
405   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
406            Op.getLLTTy(*getMRI()).getSizeInBits())
407     Opcode = TargetOpcode::G_TRUNC;
408   else
409     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
410 
411   return buildInstr(Opcode, Res, Op);
412 }
413 
414 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
415                                                        const SrcOp &Op) {
416   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
417 }
418 
419 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
420                                                        const SrcOp &Op) {
421   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
422 }
423 
424 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
425                                                          const SrcOp &Op) {
426   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
427 }
428 
429 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
430                                                 const SrcOp &Src) {
431   LLT SrcTy = Src.getLLTTy(*getMRI());
432   LLT DstTy = Dst.getLLTTy(*getMRI());
433   if (SrcTy == DstTy)
434     return buildCopy(Dst, Src);
435 
436   unsigned Opcode;
437   if (SrcTy.isPointer() && DstTy.isScalar())
438     Opcode = TargetOpcode::G_PTRTOINT;
439   else if (DstTy.isPointer() && SrcTy.isScalar())
440     Opcode = TargetOpcode::G_INTTOPTR;
441   else {
442     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
443     Opcode = TargetOpcode::G_BITCAST;
444   }
445 
446   return buildInstr(Opcode, Dst, Src);
447 }
448 
449 MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
450                                                    uint64_t Index) {
451 #ifndef NDEBUG
452   assert(getMRI()->getType(Src).isValid() && "invalid operand type");
453   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
454   assert(Index + getMRI()->getType(Res).getSizeInBits() <=
455              getMRI()->getType(Src).getSizeInBits() &&
456          "extracting off end of register");
457 #endif
458 
459   if (getMRI()->getType(Res).getSizeInBits() ==
460       getMRI()->getType(Src).getSizeInBits()) {
461     assert(Index == 0 && "insertion past the end of a register");
462     return buildCast(Res, Src);
463   }
464 
465   return buildInstr(TargetOpcode::G_EXTRACT)
466       .addDef(Res)
467       .addUse(Src)
468       .addImm(Index);
469 }
470 
471 void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
472                                      ArrayRef<uint64_t> Indices) {
473 #ifndef NDEBUG
474   assert(Ops.size() == Indices.size() && "incompatible args");
475   assert(!Ops.empty() && "invalid trivial sequence");
476   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
477          "sequence offsets must be in ascending order");
478 
479   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
480   for (auto Op : Ops)
481     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
482 #endif
483 
484   LLT ResTy = getMRI()->getType(Res);
485   LLT OpTy = getMRI()->getType(Ops[0]);
486   unsigned OpSize = OpTy.getSizeInBits();
487   bool MaybeMerge = true;
488   for (unsigned i = 0; i < Ops.size(); ++i) {
489     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
490       MaybeMerge = false;
491       break;
492     }
493   }
494 
495   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
496     buildMerge(Res, Ops);
497     return;
498   }
499 
500   unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
501   buildUndef(ResIn);
502 
503   for (unsigned i = 0; i < Ops.size(); ++i) {
504     unsigned ResOut = i + 1 == Ops.size()
505                           ? Res
506                           : getMRI()->createGenericVirtualRegister(ResTy);
507     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
508     ResIn = ResOut;
509   }
510 }
511 
512 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
513   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
514 }
515 
516 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
517                                                  ArrayRef<unsigned> Ops) {
518   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
519   // we need some temporary storage for the DstOp objects. Here we use a
520   // sufficiently large SmallVector to not go through the heap.
521   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
522   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
523 }
524 
525 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
526                                                    const SrcOp &Op) {
527   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
528   // we need some temporary storage for the DstOp objects. Here we use a
529   // sufficiently large SmallVector to not go through the heap.
530   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
531   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
532 }
533 
534 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
535                                                    const SrcOp &Op) {
536   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
537   // we need some temporary storage for the DstOp objects. Here we use a
538   // sufficiently large SmallVector to not go through the heap.
539   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
540   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
541 }
542 
543 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
544                                                        ArrayRef<unsigned> Ops) {
545   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
546   // we need some temporary storage for the DstOp objects. Here we use a
547   // sufficiently large SmallVector to not go through the heap.
548   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
549   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
550 }
551 
552 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
553                                                        const SrcOp &Src) {
554   SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
555   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
556 }
557 
558 MachineInstrBuilder
559 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
560                                         ArrayRef<unsigned> Ops) {
561   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
562   // we need some temporary storage for the DstOp objects. Here we use a
563   // sufficiently large SmallVector to not go through the heap.
564   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
565   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
566 }
567 
568 MachineInstrBuilder
569 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
570   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
571   // we need some temporary storage for the DstOp objects. Here we use a
572   // sufficiently large SmallVector to not go through the heap.
573   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
574   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
575 }
576 
577 MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
578                                                   unsigned Op, unsigned Index) {
579   assert(Index + getMRI()->getType(Op).getSizeInBits() <=
580              getMRI()->getType(Res).getSizeInBits() &&
581          "insertion past the end of a register");
582 
583   if (getMRI()->getType(Res).getSizeInBits() ==
584       getMRI()->getType(Op).getSizeInBits()) {
585     return buildCast(Res, Op);
586   }
587 
588   return buildInstr(TargetOpcode::G_INSERT)
589       .addDef(Res)
590       .addUse(Src)
591       .addUse(Op)
592       .addImm(Index);
593 }
594 
595 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
596                                                      unsigned Res,
597                                                      bool HasSideEffects) {
598   auto MIB =
599       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
600                                 : TargetOpcode::G_INTRINSIC);
601   if (Res)
602     MIB.addDef(Res);
603   MIB.addIntrinsicID(ID);
604   return MIB;
605 }
606 
607 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
608                                                  const SrcOp &Op) {
609   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
610 }
611 
612 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
613                                                    const SrcOp &Op) {
614   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
615 }
616 
617 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
618                                                 const DstOp &Res,
619                                                 const SrcOp &Op0,
620                                                 const SrcOp &Op1) {
621   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
622 }
623 
624 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
625                                                 const DstOp &Res,
626                                                 const SrcOp &Op0,
627                                                 const SrcOp &Op1) {
628 
629   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
630 }
631 
632 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
633                                                   const SrcOp &Tst,
634                                                   const SrcOp &Op0,
635                                                   const SrcOp &Op1) {
636 
637   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
638 }
639 
640 MachineInstrBuilder
641 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
642                                            const SrcOp &Elt, const SrcOp &Idx) {
643   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
644 }
645 
646 MachineInstrBuilder
647 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
648                                             const SrcOp &Idx) {
649   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
650 }
651 
652 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
653     unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
654     unsigned NewVal, MachineMemOperand &MMO) {
655 #ifndef NDEBUG
656   LLT OldValResTy = getMRI()->getType(OldValRes);
657   LLT SuccessResTy = getMRI()->getType(SuccessRes);
658   LLT AddrTy = getMRI()->getType(Addr);
659   LLT CmpValTy = getMRI()->getType(CmpVal);
660   LLT NewValTy = getMRI()->getType(NewVal);
661   assert(OldValResTy.isScalar() && "invalid operand type");
662   assert(SuccessResTy.isScalar() && "invalid operand type");
663   assert(AddrTy.isPointer() && "invalid operand type");
664   assert(CmpValTy.isValid() && "invalid operand type");
665   assert(NewValTy.isValid() && "invalid operand type");
666   assert(OldValResTy == CmpValTy && "type mismatch");
667   assert(OldValResTy == NewValTy && "type mismatch");
668 #endif
669 
670   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
671       .addDef(OldValRes)
672       .addDef(SuccessRes)
673       .addUse(Addr)
674       .addUse(CmpVal)
675       .addUse(NewVal)
676       .addMemOperand(&MMO);
677 }
678 
679 MachineInstrBuilder
680 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
681                                      unsigned CmpVal, unsigned NewVal,
682                                      MachineMemOperand &MMO) {
683 #ifndef NDEBUG
684   LLT OldValResTy = getMRI()->getType(OldValRes);
685   LLT AddrTy = getMRI()->getType(Addr);
686   LLT CmpValTy = getMRI()->getType(CmpVal);
687   LLT NewValTy = getMRI()->getType(NewVal);
688   assert(OldValResTy.isScalar() && "invalid operand type");
689   assert(AddrTy.isPointer() && "invalid operand type");
690   assert(CmpValTy.isValid() && "invalid operand type");
691   assert(NewValTy.isValid() && "invalid operand type");
692   assert(OldValResTy == CmpValTy && "type mismatch");
693   assert(OldValResTy == NewValTy && "type mismatch");
694 #endif
695 
696   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
697       .addDef(OldValRes)
698       .addUse(Addr)
699       .addUse(CmpVal)
700       .addUse(NewVal)
701       .addMemOperand(&MMO);
702 }
703 
704 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
705                                                      unsigned OldValRes,
706                                                      unsigned Addr,
707                                                      unsigned Val,
708                                                      MachineMemOperand &MMO) {
709 #ifndef NDEBUG
710   LLT OldValResTy = getMRI()->getType(OldValRes);
711   LLT AddrTy = getMRI()->getType(Addr);
712   LLT ValTy = getMRI()->getType(Val);
713   assert(OldValResTy.isScalar() && "invalid operand type");
714   assert(AddrTy.isPointer() && "invalid operand type");
715   assert(ValTy.isValid() && "invalid operand type");
716   assert(OldValResTy == ValTy && "type mismatch");
717 #endif
718 
719   return buildInstr(Opcode)
720       .addDef(OldValRes)
721       .addUse(Addr)
722       .addUse(Val)
723       .addMemOperand(&MMO);
724 }
725 
726 MachineInstrBuilder
727 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
728                                      unsigned Val, MachineMemOperand &MMO) {
729   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
730                         MMO);
731 }
732 MachineInstrBuilder
733 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
734                                     unsigned Val, MachineMemOperand &MMO) {
735   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
736                         MMO);
737 }
738 MachineInstrBuilder
739 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
740                                     unsigned Val, MachineMemOperand &MMO) {
741   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
742                         MMO);
743 }
744 MachineInstrBuilder
745 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
746                                     unsigned Val, MachineMemOperand &MMO) {
747   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
748                         MMO);
749 }
750 MachineInstrBuilder
751 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
752                                      unsigned Val, MachineMemOperand &MMO) {
753   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
754                         MMO);
755 }
756 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
757                                                        unsigned Addr,
758                                                        unsigned Val,
759                                                        MachineMemOperand &MMO) {
760   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
761                         MMO);
762 }
763 MachineInstrBuilder
764 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
765                                     unsigned Val, MachineMemOperand &MMO) {
766   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
767                         MMO);
768 }
769 MachineInstrBuilder
770 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
771                                     unsigned Val, MachineMemOperand &MMO) {
772   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
773                         MMO);
774 }
775 MachineInstrBuilder
776 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
777                                     unsigned Val, MachineMemOperand &MMO) {
778   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
779                         MMO);
780 }
781 MachineInstrBuilder
782 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
783                                      unsigned Val, MachineMemOperand &MMO) {
784   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
785                         MMO);
786 }
787 MachineInstrBuilder
788 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
789                                      unsigned Val, MachineMemOperand &MMO) {
790   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
791                         MMO);
792 }
793 
794 MachineInstrBuilder
795 MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
796 #ifndef NDEBUG
797   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
798 #endif
799 
800   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
801 }
802 
803 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
804                                         bool IsExtend) {
805 #ifndef NDEBUG
806   if (DstTy.isVector()) {
807     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
808     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
809            "different number of elements in a trunc/ext");
810   } else
811     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
812 
813   if (IsExtend)
814     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
815            "invalid narrowing extend");
816   else
817     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
818            "invalid widening trunc");
819 #endif
820 }
821 
822 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
823                                         const LLT &Op0Ty, const LLT &Op1Ty) {
824 #ifndef NDEBUG
825   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
826          "invalid operand type");
827   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
828   if (ResTy.isScalar() || ResTy.isPointer())
829     assert(TstTy.isScalar() && "type mismatch");
830   else
831     assert((TstTy.isScalar() ||
832             (TstTy.isVector() &&
833              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
834            "type mismatch");
835 #endif
836 }
837 
838 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
839                                                  ArrayRef<DstOp> DstOps,
840                                                  ArrayRef<SrcOp> SrcOps,
841                                                  Optional<unsigned> Flags) {
842   switch (Opc) {
843   default:
844     break;
845   case TargetOpcode::G_SELECT: {
846     assert(DstOps.size() == 1 && "Invalid select");
847     assert(SrcOps.size() == 3 && "Invalid select");
848     validateSelectOp(
849         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
850         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
851     break;
852   }
853   case TargetOpcode::G_ADD:
854   case TargetOpcode::G_AND:
855   case TargetOpcode::G_ASHR:
856   case TargetOpcode::G_LSHR:
857   case TargetOpcode::G_MUL:
858   case TargetOpcode::G_OR:
859   case TargetOpcode::G_SHL:
860   case TargetOpcode::G_SUB:
861   case TargetOpcode::G_XOR:
862   case TargetOpcode::G_UDIV:
863   case TargetOpcode::G_SDIV:
864   case TargetOpcode::G_UREM:
865   case TargetOpcode::G_SREM: {
866     // All these are binary ops.
867     assert(DstOps.size() == 1 && "Invalid Dst");
868     assert(SrcOps.size() == 2 && "Invalid Srcs");
869     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
870                      SrcOps[0].getLLTTy(*getMRI()),
871                      SrcOps[1].getLLTTy(*getMRI()));
872     break;
873   case TargetOpcode::G_SEXT:
874   case TargetOpcode::G_ZEXT:
875   case TargetOpcode::G_ANYEXT:
876     assert(DstOps.size() == 1 && "Invalid Dst");
877     assert(SrcOps.size() == 1 && "Invalid Srcs");
878     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
879                      SrcOps[0].getLLTTy(*getMRI()), true);
880     break;
881   case TargetOpcode::G_TRUNC:
882   case TargetOpcode::G_FPTRUNC:
883     assert(DstOps.size() == 1 && "Invalid Dst");
884     assert(SrcOps.size() == 1 && "Invalid Srcs");
885     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
886                      SrcOps[0].getLLTTy(*getMRI()), false);
887     break;
888   }
889   case TargetOpcode::COPY:
890     assert(DstOps.size() == 1 && "Invalid Dst");
891     assert(SrcOps.size() == 1 && "Invalid Srcs");
892     assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
893            SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
894            DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
895     break;
896   case TargetOpcode::G_FCMP:
897   case TargetOpcode::G_ICMP: {
898     assert(DstOps.size() == 1 && "Invalid Dst Operands");
899     assert(SrcOps.size() == 3 && "Invalid Src Operands");
900     // For F/ICMP, the first src operand is the predicate, followed by
901     // the two comparands.
902     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
903            "Expecting predicate");
904     assert([&]() -> bool {
905       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
906       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
907                                          : CmpInst::isFPPredicate(Pred);
908     }() && "Invalid predicate");
909     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
910            "Type mismatch");
911     assert([&]() -> bool {
912       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
913       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
914       if (Op0Ty.isScalar() || Op0Ty.isPointer())
915         return DstTy.isScalar();
916       else
917         return DstTy.isVector() &&
918                DstTy.getNumElements() == Op0Ty.getNumElements();
919     }() && "Type Mismatch");
920     break;
921   }
922   case TargetOpcode::G_UNMERGE_VALUES: {
923     assert(!DstOps.empty() && "Invalid trivial sequence");
924     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
925     assert(std::all_of(DstOps.begin(), DstOps.end(),
926                        [&, this](const DstOp &Op) {
927                          return Op.getLLTTy(*getMRI()) ==
928                                 DstOps[0].getLLTTy(*getMRI());
929                        }) &&
930            "type mismatch in output list");
931     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
932                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
933            "input operands do not cover output register");
934     break;
935   }
936   case TargetOpcode::G_MERGE_VALUES: {
937     assert(!SrcOps.empty() && "invalid trivial sequence");
938     assert(DstOps.size() == 1 && "Invalid Dst");
939     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
940                        [&, this](const SrcOp &Op) {
941                          return Op.getLLTTy(*getMRI()) ==
942                                 SrcOps[0].getLLTTy(*getMRI());
943                        }) &&
944            "type mismatch in input list");
945     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
946                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
947            "input operands do not cover output register");
948     if (SrcOps.size() == 1)
949       return buildCast(DstOps[0], SrcOps[0]);
950     if (DstOps[0].getLLTTy(*getMRI()).isVector())
951       return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
952     break;
953   }
954   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
955     assert(DstOps.size() == 1 && "Invalid Dst size");
956     assert(SrcOps.size() == 2 && "Invalid Src size");
957     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
958     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
959             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
960            "Invalid operand type");
961     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
962     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
963                DstOps[0].getLLTTy(*getMRI()) &&
964            "Type mismatch");
965     break;
966   }
967   case TargetOpcode::G_INSERT_VECTOR_ELT: {
968     assert(DstOps.size() == 1 && "Invalid dst size");
969     assert(SrcOps.size() == 3 && "Invalid src size");
970     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
971            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
972     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
973                SrcOps[1].getLLTTy(*getMRI()) &&
974            "Type mismatch");
975     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
976     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
977                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
978            "Type mismatch");
979     break;
980   }
981   case TargetOpcode::G_BUILD_VECTOR: {
982     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
983            "Must have at least 2 operands");
984     assert(DstOps.size() == 1 && "Invalid DstOps");
985     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
986            "Res type must be a vector");
987     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
988                        [&, this](const SrcOp &Op) {
989                          return Op.getLLTTy(*getMRI()) ==
990                                 SrcOps[0].getLLTTy(*getMRI());
991                        }) &&
992            "type mismatch in input list");
993     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
994                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
995            "input scalars do not exactly cover the output vector register");
996     break;
997   }
998   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
999     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1000            "Must have at least 2 operands");
1001     assert(DstOps.size() == 1 && "Invalid DstOps");
1002     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1003            "Res type must be a vector");
1004     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1005                        [&, this](const SrcOp &Op) {
1006                          return Op.getLLTTy(*getMRI()) ==
1007                                 SrcOps[0].getLLTTy(*getMRI());
1008                        }) &&
1009            "type mismatch in input list");
1010     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1011         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1012       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1013     break;
1014   }
1015   case TargetOpcode::G_CONCAT_VECTORS: {
1016     assert(DstOps.size() == 1 && "Invalid DstOps");
1017     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1018            "Must have at least 2 operands");
1019     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1020                        [&, this](const SrcOp &Op) {
1021                          return (Op.getLLTTy(*getMRI()).isVector() &&
1022                                  Op.getLLTTy(*getMRI()) ==
1023                                      SrcOps[0].getLLTTy(*getMRI()));
1024                        }) &&
1025            "type mismatch in input list");
1026     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1027                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1028            "input vectors do not exactly cover the output vector register");
1029     break;
1030   }
1031   case TargetOpcode::G_UADDE: {
1032     assert(DstOps.size() == 2 && "Invalid no of dst operands");
1033     assert(SrcOps.size() == 3 && "Invalid no of src operands");
1034     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1035     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1036            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1037            "Invalid operand");
1038     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1039     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1040            "type mismatch");
1041     break;
1042   }
1043   }
1044 
1045   auto MIB = buildInstr(Opc);
1046   for (const DstOp &Op : DstOps)
1047     Op.addDefToMIB(*getMRI(), MIB);
1048   for (const SrcOp &Op : SrcOps)
1049     Op.addSrcToMIB(MIB);
1050   if (Flags)
1051     MIB->setFlags(*Flags);
1052   return MIB;
1053 }
1054