1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
13 
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/TargetOpcodes.h"
20 #include "llvm/CodeGen/TargetSubtargetInfo.h"
21 #include "llvm/IR/DebugInfo.h"
22 
23 using namespace llvm;
24 
25 void MachineIRBuilder::setMF(MachineFunction &MF) {
26   State.MF = &MF;
27   State.MBB = nullptr;
28   State.MRI = &MF.getRegInfo();
29   State.TII = MF.getSubtarget().getInstrInfo();
30   State.DL = DebugLoc();
31   State.II = MachineBasicBlock::iterator();
32   State.Observer = nullptr;
33 }
34 
35 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
36   State.MBB = &MBB;
37   State.II = MBB.end();
38   assert(&getMF() == MBB.getParent() &&
39          "Basic block is in a different function");
40 }
41 
42 void MachineIRBuilder::setInstr(MachineInstr &MI) {
43   assert(MI.getParent() && "Instruction is not part of a basic block");
44   setMBB(*MI.getParent());
45   State.II = MI.getIterator();
46 }
47 
48 void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
49 
50 void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
51                                    MachineBasicBlock::iterator II) {
52   assert(MBB.getParent() == &getMF() &&
53          "Basic block is in a different function");
54   State.MBB = &MBB;
55   State.II = II;
56 }
57 
58 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
59   if (State.Observer)
60     State.Observer->createdInstr(*InsertedInstr);
61 }
62 
63 void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) {
64   State.Observer = &Observer;
65 }
66 
67 void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; }
68 
69 //------------------------------------------------------------------------------
70 // Build instruction variants.
71 //------------------------------------------------------------------------------
72 
73 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
74   return insertInstr(buildInstrNoInsert(Opcode));
75 }
76 
77 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
78   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
79   return MIB;
80 }
81 
82 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
83   getMBB().insert(getInsertPt(), MIB);
84   recordInsertion(MIB);
85   return MIB;
86 }
87 
88 MachineInstrBuilder
89 MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
90                                       const MDNode *Expr) {
91   assert(isa<DILocalVariable>(Variable) && "not a variable");
92   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
93   assert(
94       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
95       "Expected inlined-at fields to agree");
96   return insertInstr(BuildMI(getMF(), getDL(),
97                              getTII().get(TargetOpcode::DBG_VALUE),
98                              /*IsIndirect*/ false, Reg, Variable, Expr));
99 }
100 
101 MachineInstrBuilder
102 MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
103                                         const MDNode *Expr) {
104   assert(isa<DILocalVariable>(Variable) && "not a variable");
105   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
106   assert(
107       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
108       "Expected inlined-at fields to agree");
109   return insertInstr(BuildMI(getMF(), getDL(),
110                              getTII().get(TargetOpcode::DBG_VALUE),
111                              /*IsIndirect*/ true, Reg, Variable, Expr));
112 }
113 
114 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
115                                                       const MDNode *Variable,
116                                                       const MDNode *Expr) {
117   assert(isa<DILocalVariable>(Variable) && "not a variable");
118   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
119   assert(
120       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
121       "Expected inlined-at fields to agree");
122   return buildInstr(TargetOpcode::DBG_VALUE)
123       .addFrameIndex(FI)
124       .addImm(0)
125       .addMetadata(Variable)
126       .addMetadata(Expr);
127 }
128 
129 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
130                                                          const MDNode *Variable,
131                                                          const MDNode *Expr) {
132   assert(isa<DILocalVariable>(Variable) && "not a variable");
133   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
134   assert(
135       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
136       "Expected inlined-at fields to agree");
137   auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
138   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
139     if (CI->getBitWidth() > 64)
140       MIB.addCImm(CI);
141     else
142       MIB.addImm(CI->getZExtValue());
143   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
144     MIB.addFPImm(CFP);
145   } else {
146     // Insert %noreg if we didn't find a usable constant and had to drop it.
147     MIB.addReg(0U);
148   }
149 
150   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
151 }
152 
153 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
154   assert(isa<DILabel>(Label) && "not a label");
155   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
156          "Expected inlined-at fields to agree");
157   auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
158 
159   return MIB.addMetadata(Label);
160 }
161 
162 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
163   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
164   return buildInstr(TargetOpcode::G_FRAME_INDEX)
165       .addDef(Res)
166       .addFrameIndex(Idx);
167 }
168 
169 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
170                                                        const GlobalValue *GV) {
171   assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
172   assert(getMRI()->getType(Res).getAddressSpace() ==
173              GV->getType()->getAddressSpace() &&
174          "address space mismatch");
175 
176   return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
177       .addDef(Res)
178       .addGlobalAddress(GV);
179 }
180 
181 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
182                                         const LLT &Op1) {
183   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
184   assert((Res == Op0 && Res == Op1) && "type mismatch");
185 }
186 
187 MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
188                                                unsigned Op1) {
189   assert(getMRI()->getType(Res).isPointer() &&
190          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
191   assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
192 
193   return buildInstr(TargetOpcode::G_GEP)
194       .addDef(Res)
195       .addUse(Op0)
196       .addUse(Op1);
197 }
198 
199 Optional<MachineInstrBuilder>
200 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
201                                  const LLT &ValueTy, uint64_t Value) {
202   assert(Res == 0 && "Res is a result argument");
203   assert(ValueTy.isScalar()  && "invalid offset type");
204 
205   if (Value == 0) {
206     Res = Op0;
207     return None;
208   }
209 
210   Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
211   unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
212 
213   buildConstant(TmpReg, Value);
214   return buildGEP(Res, Op0, TmpReg);
215 }
216 
217 MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
218                                                    uint32_t NumBits) {
219   assert(getMRI()->getType(Res).isPointer() &&
220          getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
221 
222   return buildInstr(TargetOpcode::G_PTR_MASK)
223       .addDef(Res)
224       .addUse(Op0)
225       .addImm(NumBits);
226 }
227 
228 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
229   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
230 }
231 
232 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
233   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
234   return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
235 }
236 
237 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
238                                                 const SrcOp &Op) {
239   return buildInstr(TargetOpcode::COPY, Res, Op);
240 }
241 
242 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
243                                                     const ConstantInt &Val) {
244   LLT Ty = Res.getLLTTy(*getMRI());
245 
246   assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
247 
248   const ConstantInt *NewVal = &Val;
249   if (Ty.getSizeInBits() != Val.getBitWidth())
250     NewVal = ConstantInt::get(getMF().getFunction().getContext(),
251                               Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
252 
253   auto MIB = buildInstr(TargetOpcode::G_CONSTANT);
254   Res.addDefToMIB(*getMRI(), MIB);
255   MIB.addCImm(NewVal);
256   return MIB;
257 }
258 
259 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
260                                                     int64_t Val) {
261   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
262                                Res.getLLTTy(*getMRI()).getSizeInBits());
263   ConstantInt *CI = ConstantInt::get(IntN, Val, true);
264   return buildConstant(Res, *CI);
265 }
266 
267 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
268                                                      const ConstantFP &Val) {
269   assert(Res.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
270 
271   auto MIB = buildInstr(TargetOpcode::G_FCONSTANT);
272   Res.addDefToMIB(*getMRI(), MIB);
273   MIB.addFPImm(&Val);
274   return MIB;
275 }
276 
277 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
278                                                      double Val) {
279   LLT DstTy = Res.getLLTTy(*getMRI());
280   auto &Ctx = getMF().getFunction().getContext();
281   auto *CFP =
282       ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getSizeInBits()));
283   return buildFConstant(Res, *CFP);
284 }
285 
286 MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
287                                                   MachineBasicBlock &Dest) {
288   assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
289 
290   return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
291 }
292 
293 MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
294                                                 MachineMemOperand &MMO) {
295   return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
296 }
297 
298 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
299                                                      unsigned Res,
300                                                      unsigned Addr,
301                                                      MachineMemOperand &MMO) {
302   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
303   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
304 
305   return buildInstr(Opcode)
306       .addDef(Res)
307       .addUse(Addr)
308       .addMemOperand(&MMO);
309 }
310 
311 MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
312                                                  MachineMemOperand &MMO) {
313   assert(getMRI()->getType(Val).isValid() && "invalid operand type");
314   assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
315 
316   return buildInstr(TargetOpcode::G_STORE)
317       .addUse(Val)
318       .addUse(Addr)
319       .addMemOperand(&MMO);
320 }
321 
322 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
323                                                  const DstOp &CarryOut,
324                                                  const SrcOp &Op0,
325                                                  const SrcOp &Op1,
326                                                  const SrcOp &CarryIn) {
327   return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
328                     {Op0, Op1, CarryIn});
329 }
330 
331 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
332                                                   const SrcOp &Op) {
333   return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
334 }
335 
336 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
337                                                 const SrcOp &Op) {
338   return buildInstr(TargetOpcode::G_SEXT, Res, Op);
339 }
340 
341 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
342                                                 const SrcOp &Op) {
343   return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
344 }
345 
346 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
347                                                       const DstOp &Res,
348                                                       const SrcOp &Op) {
349   assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
350           TargetOpcode::G_SEXT == ExtOpc) &&
351          "Expecting Extending Opc");
352   assert(Res.getLLTTy(*getMRI()).isScalar() ||
353          Res.getLLTTy(*getMRI()).isVector());
354   assert(Res.getLLTTy(*getMRI()).isScalar() ==
355          Op.getLLTTy(*getMRI()).isScalar());
356 
357   unsigned Opcode = TargetOpcode::COPY;
358   if (Res.getLLTTy(*getMRI()).getSizeInBits() >
359       Op.getLLTTy(*getMRI()).getSizeInBits())
360     Opcode = ExtOpc;
361   else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
362            Op.getLLTTy(*getMRI()).getSizeInBits())
363     Opcode = TargetOpcode::G_TRUNC;
364   else
365     assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
366 
367   return buildInstr(Opcode, Res, Op);
368 }
369 
370 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
371                                                        const SrcOp &Op) {
372   return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
373 }
374 
375 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
376                                                        const SrcOp &Op) {
377   return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
378 }
379 
380 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
381                                                          const SrcOp &Op) {
382   return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
383 }
384 
385 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
386                                                 const SrcOp &Src) {
387   LLT SrcTy = Src.getLLTTy(*getMRI());
388   LLT DstTy = Dst.getLLTTy(*getMRI());
389   if (SrcTy == DstTy)
390     return buildCopy(Dst, Src);
391 
392   unsigned Opcode;
393   if (SrcTy.isPointer() && DstTy.isScalar())
394     Opcode = TargetOpcode::G_PTRTOINT;
395   else if (DstTy.isPointer() && SrcTy.isScalar())
396     Opcode = TargetOpcode::G_INTTOPTR;
397   else {
398     assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
399     Opcode = TargetOpcode::G_BITCAST;
400   }
401 
402   return buildInstr(Opcode, Dst, Src);
403 }
404 
405 MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
406                                                    uint64_t Index) {
407 #ifndef NDEBUG
408   assert(getMRI()->getType(Src).isValid() && "invalid operand type");
409   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
410   assert(Index + getMRI()->getType(Res).getSizeInBits() <=
411              getMRI()->getType(Src).getSizeInBits() &&
412          "extracting off end of register");
413 #endif
414 
415   if (getMRI()->getType(Res).getSizeInBits() ==
416       getMRI()->getType(Src).getSizeInBits()) {
417     assert(Index == 0 && "insertion past the end of a register");
418     return buildCast(Res, Src);
419   }
420 
421   return buildInstr(TargetOpcode::G_EXTRACT)
422       .addDef(Res)
423       .addUse(Src)
424       .addImm(Index);
425 }
426 
427 void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
428                                      ArrayRef<uint64_t> Indices) {
429 #ifndef NDEBUG
430   assert(Ops.size() == Indices.size() && "incompatible args");
431   assert(!Ops.empty() && "invalid trivial sequence");
432   assert(std::is_sorted(Indices.begin(), Indices.end()) &&
433          "sequence offsets must be in ascending order");
434 
435   assert(getMRI()->getType(Res).isValid() && "invalid operand type");
436   for (auto Op : Ops)
437     assert(getMRI()->getType(Op).isValid() && "invalid operand type");
438 #endif
439 
440   LLT ResTy = getMRI()->getType(Res);
441   LLT OpTy = getMRI()->getType(Ops[0]);
442   unsigned OpSize = OpTy.getSizeInBits();
443   bool MaybeMerge = true;
444   for (unsigned i = 0; i < Ops.size(); ++i) {
445     if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
446       MaybeMerge = false;
447       break;
448     }
449   }
450 
451   if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
452     buildMerge(Res, Ops);
453     return;
454   }
455 
456   unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
457   buildUndef(ResIn);
458 
459   for (unsigned i = 0; i < Ops.size(); ++i) {
460     unsigned ResOut = i + 1 == Ops.size()
461                           ? Res
462                           : getMRI()->createGenericVirtualRegister(ResTy);
463     buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
464     ResIn = ResOut;
465   }
466 }
467 
468 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
469   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
470 }
471 
472 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
473                                                  ArrayRef<unsigned> Ops) {
474   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
475   // we need some temporary storage for the DstOp objects. Here we use a
476   // sufficiently large SmallVector to not go through the heap.
477   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
478   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
479 }
480 
481 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
482                                                    const SrcOp &Op) {
483   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
484   // we need some temporary storage for the DstOp objects. Here we use a
485   // sufficiently large SmallVector to not go through the heap.
486   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
487   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
488 }
489 
490 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
491                                                    const SrcOp &Op) {
492   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
493   // we need some temporary storage for the DstOp objects. Here we use a
494   // sufficiently large SmallVector to not go through the heap.
495   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
496   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
497 }
498 
499 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
500                                                        ArrayRef<unsigned> Ops) {
501   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
502   // we need some temporary storage for the DstOp objects. Here we use a
503   // sufficiently large SmallVector to not go through the heap.
504   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
505   return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
506 }
507 
508 MachineInstrBuilder
509 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
510                                         ArrayRef<unsigned> Ops) {
511   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
512   // we need some temporary storage for the DstOp objects. Here we use a
513   // sufficiently large SmallVector to not go through the heap.
514   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
515   return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
516 }
517 
518 MachineInstrBuilder
519 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
520   // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
521   // we need some temporary storage for the DstOp objects. Here we use a
522   // sufficiently large SmallVector to not go through the heap.
523   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
524   return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
525 }
526 
527 MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
528                                                   unsigned Op, unsigned Index) {
529   assert(Index + getMRI()->getType(Op).getSizeInBits() <=
530              getMRI()->getType(Res).getSizeInBits() &&
531          "insertion past the end of a register");
532 
533   if (getMRI()->getType(Res).getSizeInBits() ==
534       getMRI()->getType(Op).getSizeInBits()) {
535     return buildCast(Res, Op);
536   }
537 
538   return buildInstr(TargetOpcode::G_INSERT)
539       .addDef(Res)
540       .addUse(Src)
541       .addUse(Op)
542       .addImm(Index);
543 }
544 
545 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
546                                                      unsigned Res,
547                                                      bool HasSideEffects) {
548   auto MIB =
549       buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
550                                 : TargetOpcode::G_INTRINSIC);
551   if (Res)
552     MIB.addDef(Res);
553   MIB.addIntrinsicID(ID);
554   return MIB;
555 }
556 
557 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
558                                                  const SrcOp &Op) {
559   return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
560 }
561 
562 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
563                                                    const SrcOp &Op) {
564   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
565 }
566 
567 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
568                                                 const DstOp &Res,
569                                                 const SrcOp &Op0,
570                                                 const SrcOp &Op1) {
571   return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
572 }
573 
574 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
575                                                 const DstOp &Res,
576                                                 const SrcOp &Op0,
577                                                 const SrcOp &Op1) {
578 
579   return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
580 }
581 
582 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
583                                                   const SrcOp &Tst,
584                                                   const SrcOp &Op0,
585                                                   const SrcOp &Op1) {
586 
587   return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
588 }
589 
590 MachineInstrBuilder
591 MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
592                                            const SrcOp &Elt, const SrcOp &Idx) {
593   return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
594 }
595 
596 MachineInstrBuilder
597 MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
598                                             const SrcOp &Idx) {
599   return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
600 }
601 
602 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
603     unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
604     unsigned NewVal, MachineMemOperand &MMO) {
605 #ifndef NDEBUG
606   LLT OldValResTy = getMRI()->getType(OldValRes);
607   LLT SuccessResTy = getMRI()->getType(SuccessRes);
608   LLT AddrTy = getMRI()->getType(Addr);
609   LLT CmpValTy = getMRI()->getType(CmpVal);
610   LLT NewValTy = getMRI()->getType(NewVal);
611   assert(OldValResTy.isScalar() && "invalid operand type");
612   assert(SuccessResTy.isScalar() && "invalid operand type");
613   assert(AddrTy.isPointer() && "invalid operand type");
614   assert(CmpValTy.isValid() && "invalid operand type");
615   assert(NewValTy.isValid() && "invalid operand type");
616   assert(OldValResTy == CmpValTy && "type mismatch");
617   assert(OldValResTy == NewValTy && "type mismatch");
618 #endif
619 
620   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
621       .addDef(OldValRes)
622       .addDef(SuccessRes)
623       .addUse(Addr)
624       .addUse(CmpVal)
625       .addUse(NewVal)
626       .addMemOperand(&MMO);
627 }
628 
629 MachineInstrBuilder
630 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
631                                      unsigned CmpVal, unsigned NewVal,
632                                      MachineMemOperand &MMO) {
633 #ifndef NDEBUG
634   LLT OldValResTy = getMRI()->getType(OldValRes);
635   LLT AddrTy = getMRI()->getType(Addr);
636   LLT CmpValTy = getMRI()->getType(CmpVal);
637   LLT NewValTy = getMRI()->getType(NewVal);
638   assert(OldValResTy.isScalar() && "invalid operand type");
639   assert(AddrTy.isPointer() && "invalid operand type");
640   assert(CmpValTy.isValid() && "invalid operand type");
641   assert(NewValTy.isValid() && "invalid operand type");
642   assert(OldValResTy == CmpValTy && "type mismatch");
643   assert(OldValResTy == NewValTy && "type mismatch");
644 #endif
645 
646   return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
647       .addDef(OldValRes)
648       .addUse(Addr)
649       .addUse(CmpVal)
650       .addUse(NewVal)
651       .addMemOperand(&MMO);
652 }
653 
654 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode,
655                                                      unsigned OldValRes,
656                                                      unsigned Addr,
657                                                      unsigned Val,
658                                                      MachineMemOperand &MMO) {
659 #ifndef NDEBUG
660   LLT OldValResTy = getMRI()->getType(OldValRes);
661   LLT AddrTy = getMRI()->getType(Addr);
662   LLT ValTy = getMRI()->getType(Val);
663   assert(OldValResTy.isScalar() && "invalid operand type");
664   assert(AddrTy.isPointer() && "invalid operand type");
665   assert(ValTy.isValid() && "invalid operand type");
666   assert(OldValResTy == ValTy && "type mismatch");
667 #endif
668 
669   return buildInstr(Opcode)
670       .addDef(OldValRes)
671       .addUse(Addr)
672       .addUse(Val)
673       .addMemOperand(&MMO);
674 }
675 
676 MachineInstrBuilder
677 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
678                                      unsigned Val, MachineMemOperand &MMO) {
679   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
680                         MMO);
681 }
682 MachineInstrBuilder
683 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
684                                     unsigned Val, MachineMemOperand &MMO) {
685   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
686                         MMO);
687 }
688 MachineInstrBuilder
689 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
690                                     unsigned Val, MachineMemOperand &MMO) {
691   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
692                         MMO);
693 }
694 MachineInstrBuilder
695 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
696                                     unsigned Val, MachineMemOperand &MMO) {
697   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
698                         MMO);
699 }
700 MachineInstrBuilder
701 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
702                                      unsigned Val, MachineMemOperand &MMO) {
703   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
704                         MMO);
705 }
706 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes,
707                                                        unsigned Addr,
708                                                        unsigned Val,
709                                                        MachineMemOperand &MMO) {
710   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
711                         MMO);
712 }
713 MachineInstrBuilder
714 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
715                                     unsigned Val, MachineMemOperand &MMO) {
716   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
717                         MMO);
718 }
719 MachineInstrBuilder
720 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
721                                     unsigned Val, MachineMemOperand &MMO) {
722   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
723                         MMO);
724 }
725 MachineInstrBuilder
726 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
727                                     unsigned Val, MachineMemOperand &MMO) {
728   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
729                         MMO);
730 }
731 MachineInstrBuilder
732 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
733                                      unsigned Val, MachineMemOperand &MMO) {
734   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
735                         MMO);
736 }
737 MachineInstrBuilder
738 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
739                                      unsigned Val, MachineMemOperand &MMO) {
740   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
741                         MMO);
742 }
743 
744 MachineInstrBuilder
745 MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
746 #ifndef NDEBUG
747   assert(getMRI()->getType(Res).isPointer() && "invalid res type");
748 #endif
749 
750   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
751 }
752 
753 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
754                                         bool IsExtend) {
755 #ifndef NDEBUG
756   if (DstTy.isVector()) {
757     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
758     assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
759            "different number of elements in a trunc/ext");
760   } else
761     assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
762 
763   if (IsExtend)
764     assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
765            "invalid narrowing extend");
766   else
767     assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
768            "invalid widening trunc");
769 #endif
770 }
771 
772 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
773                                         const LLT &Op0Ty, const LLT &Op1Ty) {
774 #ifndef NDEBUG
775   assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
776          "invalid operand type");
777   assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
778   if (ResTy.isScalar() || ResTy.isPointer())
779     assert(TstTy.isScalar() && "type mismatch");
780   else
781     assert((TstTy.isScalar() ||
782             (TstTy.isVector() &&
783              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
784            "type mismatch");
785 #endif
786 }
787 
788 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
789                                                  ArrayRef<DstOp> DstOps,
790                                                  ArrayRef<SrcOp> SrcOps,
791                                                  Optional<unsigned> Flags) {
792   switch (Opc) {
793   default:
794     break;
795   case TargetOpcode::G_SELECT: {
796     assert(DstOps.size() == 1 && "Invalid select");
797     assert(SrcOps.size() == 3 && "Invalid select");
798     validateSelectOp(
799         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
800         SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
801     break;
802   }
803   case TargetOpcode::G_ADD:
804   case TargetOpcode::G_AND:
805   case TargetOpcode::G_ASHR:
806   case TargetOpcode::G_LSHR:
807   case TargetOpcode::G_MUL:
808   case TargetOpcode::G_OR:
809   case TargetOpcode::G_SHL:
810   case TargetOpcode::G_SUB:
811   case TargetOpcode::G_XOR:
812   case TargetOpcode::G_UDIV:
813   case TargetOpcode::G_SDIV:
814   case TargetOpcode::G_UREM:
815   case TargetOpcode::G_SREM: {
816     // All these are binary ops.
817     assert(DstOps.size() == 1 && "Invalid Dst");
818     assert(SrcOps.size() == 2 && "Invalid Srcs");
819     validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
820                      SrcOps[0].getLLTTy(*getMRI()),
821                      SrcOps[1].getLLTTy(*getMRI()));
822     break;
823   case TargetOpcode::G_SEXT:
824   case TargetOpcode::G_ZEXT:
825   case TargetOpcode::G_ANYEXT:
826     assert(DstOps.size() == 1 && "Invalid Dst");
827     assert(SrcOps.size() == 1 && "Invalid Srcs");
828     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
829                      SrcOps[0].getLLTTy(*getMRI()), true);
830     break;
831   case TargetOpcode::G_TRUNC:
832   case TargetOpcode::G_FPTRUNC:
833     assert(DstOps.size() == 1 && "Invalid Dst");
834     assert(SrcOps.size() == 1 && "Invalid Srcs");
835     validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
836                      SrcOps[0].getLLTTy(*getMRI()), false);
837     break;
838   }
839   case TargetOpcode::COPY:
840     assert(DstOps.size() == 1 && "Invalid Dst");
841     assert(SrcOps.size() == 1 && "Invalid Srcs");
842     assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
843            SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
844            DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
845     break;
846   case TargetOpcode::G_FCMP:
847   case TargetOpcode::G_ICMP: {
848     assert(DstOps.size() == 1 && "Invalid Dst Operands");
849     assert(SrcOps.size() == 3 && "Invalid Src Operands");
850     // For F/ICMP, the first src operand is the predicate, followed by
851     // the two comparands.
852     assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
853            "Expecting predicate");
854     assert([&]() -> bool {
855       CmpInst::Predicate Pred = SrcOps[0].getPredicate();
856       return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
857                                          : CmpInst::isFPPredicate(Pred);
858     }() && "Invalid predicate");
859     assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
860            "Type mismatch");
861     assert([&]() -> bool {
862       LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
863       LLT DstTy = DstOps[0].getLLTTy(*getMRI());
864       if (Op0Ty.isScalar() || Op0Ty.isPointer())
865         return DstTy.isScalar();
866       else
867         return DstTy.isVector() &&
868                DstTy.getNumElements() == Op0Ty.getNumElements();
869     }() && "Type Mismatch");
870     break;
871   }
872   case TargetOpcode::G_UNMERGE_VALUES: {
873     assert(!DstOps.empty() && "Invalid trivial sequence");
874     assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
875     assert(std::all_of(DstOps.begin(), DstOps.end(),
876                        [&, this](const DstOp &Op) {
877                          return Op.getLLTTy(*getMRI()) ==
878                                 DstOps[0].getLLTTy(*getMRI());
879                        }) &&
880            "type mismatch in output list");
881     assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
882                SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
883            "input operands do not cover output register");
884     break;
885   }
886   case TargetOpcode::G_MERGE_VALUES: {
887     assert(!SrcOps.empty() && "invalid trivial sequence");
888     assert(DstOps.size() == 1 && "Invalid Dst");
889     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
890                        [&, this](const SrcOp &Op) {
891                          return Op.getLLTTy(*getMRI()) ==
892                                 SrcOps[0].getLLTTy(*getMRI());
893                        }) &&
894            "type mismatch in input list");
895     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
896                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
897            "input operands do not cover output register");
898     if (SrcOps.size() == 1)
899       return buildCast(DstOps[0], SrcOps[0]);
900     if (DstOps[0].getLLTTy(*getMRI()).isVector())
901       return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
902     break;
903   }
904   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
905     assert(DstOps.size() == 1 && "Invalid Dst size");
906     assert(SrcOps.size() == 2 && "Invalid Src size");
907     assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
908     assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
909             DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
910            "Invalid operand type");
911     assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
912     assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
913                DstOps[0].getLLTTy(*getMRI()) &&
914            "Type mismatch");
915     break;
916   }
917   case TargetOpcode::G_INSERT_VECTOR_ELT: {
918     assert(DstOps.size() == 1 && "Invalid dst size");
919     assert(SrcOps.size() == 3 && "Invalid src size");
920     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
921            SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
922     assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
923                SrcOps[1].getLLTTy(*getMRI()) &&
924            "Type mismatch");
925     assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
926     assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
927                SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
928            "Type mismatch");
929     break;
930   }
931   case TargetOpcode::G_BUILD_VECTOR: {
932     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
933            "Must have at least 2 operands");
934     assert(DstOps.size() == 1 && "Invalid DstOps");
935     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
936            "Res type must be a vector");
937     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
938                        [&, this](const SrcOp &Op) {
939                          return Op.getLLTTy(*getMRI()) ==
940                                 SrcOps[0].getLLTTy(*getMRI());
941                        }) &&
942            "type mismatch in input list");
943     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
944                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
945            "input scalars do not exactly cover the outpur vector register");
946     break;
947   }
948   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
949     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
950            "Must have at least 2 operands");
951     assert(DstOps.size() == 1 && "Invalid DstOps");
952     assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
953            "Res type must be a vector");
954     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
955                        [&, this](const SrcOp &Op) {
956                          return Op.getLLTTy(*getMRI()) ==
957                                 SrcOps[0].getLLTTy(*getMRI());
958                        }) &&
959            "type mismatch in input list");
960     if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
961         DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
962       return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
963     break;
964   }
965   case TargetOpcode::G_CONCAT_VECTORS: {
966     assert(DstOps.size() == 1 && "Invalid DstOps");
967     assert((!SrcOps.empty() || SrcOps.size() < 2) &&
968            "Must have at least 2 operands");
969     assert(std::all_of(SrcOps.begin(), SrcOps.end(),
970                        [&, this](const SrcOp &Op) {
971                          return (Op.getLLTTy(*getMRI()).isVector() &&
972                                  Op.getLLTTy(*getMRI()) ==
973                                      SrcOps[0].getLLTTy(*getMRI()));
974                        }) &&
975            "type mismatch in input list");
976     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
977                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
978            "input vectors do not exactly cover the outpur vector register");
979     break;
980   }
981   case TargetOpcode::G_UADDE: {
982     assert(DstOps.size() == 2 && "Invalid no of dst operands");
983     assert(SrcOps.size() == 3 && "Invalid no of src operands");
984     assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
985     assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
986            (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
987            "Invalid operand");
988     assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
989     assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
990            "type mismatch");
991     break;
992   }
993   }
994 
995   auto MIB = buildInstr(Opc);
996   for (const DstOp &Op : DstOps)
997     Op.addDefToMIB(*getMRI(), MIB);
998   for (const SrcOp &Op : SrcOps)
999     Op.addSrcToMIB(MIB);
1000   if (Flags)
1001     MIB->setFlags(*Flags);
1002   return MIB;
1003 }
1004