1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
67   if (OrigTy.isVector() && TargetTy.isVector()) {
68     assert(OrigTy.getElementType() == TargetTy.getElementType());
69     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
70                                     TargetTy.getNumElements());
71     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
72   }
73 
74   if (OrigTy.isVector() && !TargetTy.isVector()) {
75     assert(OrigTy.getElementType() == TargetTy);
76     return TargetTy;
77   }
78 
79   assert(!OrigTy.isVector() && !TargetTy.isVector() &&
80          "GCD type of vector and scalar not implemented");
81 
82   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
83                                   TargetTy.getSizeInBits());
84   return LLT::scalar(GCD);
85 }
86 
87 static LLT getLCMType(LLT Ty0, LLT Ty1) {
88   if (!Ty0.isVector() && !Ty1.isVector()) {
89     unsigned Mul = Ty0.getSizeInBits() * Ty1.getSizeInBits();
90     int GCDSize = greatestCommonDivisor(Ty0.getSizeInBits(),
91                                         Ty1.getSizeInBits());
92     return LLT::scalar(Mul / GCDSize);
93   }
94 
95   if (Ty0.isVector() && !Ty1.isVector()) {
96     assert(Ty0.getElementType() == Ty1 && "not yet handled");
97     return Ty0;
98   }
99 
100   if (Ty1.isVector() && !Ty0.isVector()) {
101     assert(Ty1.getElementType() == Ty0 && "not yet handled");
102     return Ty1;
103   }
104 
105   if (Ty0.isVector() && Ty1.isVector()) {
106     assert(Ty0.getElementType() == Ty1.getElementType() && "not yet handled");
107 
108     int GCDElts = greatestCommonDivisor(Ty0.getNumElements(),
109                                         Ty1.getNumElements());
110 
111     int Mul = Ty0.getNumElements() * Ty1.getNumElements();
112     return LLT::vector(Mul / GCDElts, Ty0.getElementType());
113   }
114 
115   llvm_unreachable("not yet handled");
116 }
117 
118 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) {
119 
120   if (!Ty.isScalar())
121     return nullptr;
122 
123   switch (Ty.getSizeInBits()) {
124   case 16:
125     return Type::getHalfTy(Ctx);
126   case 32:
127     return Type::getFloatTy(Ctx);
128   case 64:
129     return Type::getDoubleTy(Ctx);
130   case 128:
131     return Type::getFP128Ty(Ctx);
132   default:
133     return nullptr;
134   }
135 }
136 
137 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
138                                  GISelChangeObserver &Observer,
139                                  MachineIRBuilder &Builder)
140     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
141       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
142   MIRBuilder.setMF(MF);
143   MIRBuilder.setChangeObserver(Observer);
144 }
145 
146 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
147                                  GISelChangeObserver &Observer,
148                                  MachineIRBuilder &B)
149     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
150   MIRBuilder.setMF(MF);
151   MIRBuilder.setChangeObserver(Observer);
152 }
153 LegalizerHelper::LegalizeResult
154 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
155   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
156 
157   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
158       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
159     return LI.legalizeIntrinsic(MI, MIRBuilder, Observer) ? Legalized
160                                                           : UnableToLegalize;
161   auto Step = LI.getAction(MI, MRI);
162   switch (Step.Action) {
163   case Legal:
164     LLVM_DEBUG(dbgs() << ".. Already legal\n");
165     return AlreadyLegal;
166   case Libcall:
167     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
168     return libcall(MI);
169   case NarrowScalar:
170     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
171     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
172   case WidenScalar:
173     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
174     return widenScalar(MI, Step.TypeIdx, Step.NewType);
175   case Lower:
176     LLVM_DEBUG(dbgs() << ".. Lower\n");
177     return lower(MI, Step.TypeIdx, Step.NewType);
178   case FewerElements:
179     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
180     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
181   case MoreElements:
182     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
183     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
184   case Custom:
185     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
186     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
187                                                             : UnableToLegalize;
188   default:
189     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
190     return UnableToLegalize;
191   }
192 }
193 
194 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
195                                    SmallVectorImpl<Register> &VRegs) {
196   for (int i = 0; i < NumParts; ++i)
197     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
198   MIRBuilder.buildUnmerge(VRegs, Reg);
199 }
200 
201 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
202                                    LLT MainTy, LLT &LeftoverTy,
203                                    SmallVectorImpl<Register> &VRegs,
204                                    SmallVectorImpl<Register> &LeftoverRegs) {
205   assert(!LeftoverTy.isValid() && "this is an out argument");
206 
207   unsigned RegSize = RegTy.getSizeInBits();
208   unsigned MainSize = MainTy.getSizeInBits();
209   unsigned NumParts = RegSize / MainSize;
210   unsigned LeftoverSize = RegSize - NumParts * MainSize;
211 
212   // Use an unmerge when possible.
213   if (LeftoverSize == 0) {
214     for (unsigned I = 0; I < NumParts; ++I)
215       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
216     MIRBuilder.buildUnmerge(VRegs, Reg);
217     return true;
218   }
219 
220   if (MainTy.isVector()) {
221     unsigned EltSize = MainTy.getScalarSizeInBits();
222     if (LeftoverSize % EltSize != 0)
223       return false;
224     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
225   } else {
226     LeftoverTy = LLT::scalar(LeftoverSize);
227   }
228 
229   // For irregular sizes, extract the individual parts.
230   for (unsigned I = 0; I != NumParts; ++I) {
231     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
232     VRegs.push_back(NewReg);
233     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
234   }
235 
236   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
237        Offset += LeftoverSize) {
238     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
239     LeftoverRegs.push_back(NewReg);
240     MIRBuilder.buildExtract(NewReg, Reg, Offset);
241   }
242 
243   return true;
244 }
245 
246 void LegalizerHelper::insertParts(Register DstReg,
247                                   LLT ResultTy, LLT PartTy,
248                                   ArrayRef<Register> PartRegs,
249                                   LLT LeftoverTy,
250                                   ArrayRef<Register> LeftoverRegs) {
251   if (!LeftoverTy.isValid()) {
252     assert(LeftoverRegs.empty());
253 
254     if (!ResultTy.isVector()) {
255       MIRBuilder.buildMerge(DstReg, PartRegs);
256       return;
257     }
258 
259     if (PartTy.isVector())
260       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
261     else
262       MIRBuilder.buildBuildVector(DstReg, PartRegs);
263     return;
264   }
265 
266   unsigned PartSize = PartTy.getSizeInBits();
267   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
268 
269   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
270   MIRBuilder.buildUndef(CurResultReg);
271 
272   unsigned Offset = 0;
273   for (Register PartReg : PartRegs) {
274     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
275     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
276     CurResultReg = NewResultReg;
277     Offset += PartSize;
278   }
279 
280   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
281     // Use the original output register for the final insert to avoid a copy.
282     Register NewResultReg = (I + 1 == E) ?
283       DstReg : MRI.createGenericVirtualRegister(ResultTy);
284 
285     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
286     CurResultReg = NewResultReg;
287     Offset += LeftoverPartSize;
288   }
289 }
290 
291 /// Return the result registers of G_UNMERGE_VALUES \p MI in \p Regs
292 static void getUnmergeResults(SmallVectorImpl<Register> &Regs,
293                               const MachineInstr &MI) {
294   assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
295 
296   const int NumResults = MI.getNumOperands() - 1;
297   Regs.resize(NumResults);
298   for (int I = 0; I != NumResults; ++I)
299     Regs[I] = MI.getOperand(I).getReg();
300 }
301 
302 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
303                                     LLT NarrowTy, Register SrcReg) {
304   LLT SrcTy = MRI.getType(SrcReg);
305 
306   LLT GCDTy = getGCDType(DstTy, getGCDType(SrcTy, NarrowTy));
307   if (SrcTy == GCDTy) {
308     // If the source already evenly divides the result type, we don't need to do
309     // anything.
310     Parts.push_back(SrcReg);
311   } else {
312     // Need to split into common type sized pieces.
313     auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
314     getUnmergeResults(Parts, *Unmerge);
315   }
316 
317   return GCDTy;
318 }
319 
320 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
321                                          SmallVectorImpl<Register> &VRegs,
322                                          unsigned PadStrategy) {
323   LLT LCMTy = getLCMType(DstTy, NarrowTy);
324 
325   int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits();
326   int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits();
327   int NumOrigSrc = VRegs.size();
328 
329   Register PadReg;
330 
331   // Get a value we can use to pad the source value if the sources won't evenly
332   // cover the result type.
333   if (NumOrigSrc < NumParts * NumSubParts) {
334     if (PadStrategy == TargetOpcode::G_ZEXT)
335       PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0);
336     else if (PadStrategy == TargetOpcode::G_ANYEXT)
337       PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
338     else {
339       assert(PadStrategy == TargetOpcode::G_SEXT);
340 
341       // Shift the sign bit of the low register through the high register.
342       auto ShiftAmt =
343         MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1);
344       PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0);
345     }
346   }
347 
348   // Registers for the final merge to be produced.
349   SmallVector<Register, 4> Remerge(NumParts);
350 
351   // Registers needed for intermediate merges, which will be merged into a
352   // source for Remerge.
353   SmallVector<Register, 4> SubMerge(NumSubParts);
354 
355   // Once we've fully read off the end of the original source bits, we can reuse
356   // the same high bits for remaining padding elements.
357   Register AllPadReg;
358 
359   // Build merges to the LCM type to cover the original result type.
360   for (int I = 0; I != NumParts; ++I) {
361     bool AllMergePartsArePadding = true;
362 
363     // Build the requested merges to the requested type.
364     for (int J = 0; J != NumSubParts; ++J) {
365       int Idx = I * NumSubParts + J;
366       if (Idx >= NumOrigSrc) {
367         SubMerge[J] = PadReg;
368         continue;
369       }
370 
371       SubMerge[J] = VRegs[Idx];
372 
373       // There are meaningful bits here we can't reuse later.
374       AllMergePartsArePadding = false;
375     }
376 
377     // If we've filled up a complete piece with padding bits, we can directly
378     // emit the natural sized constant if applicable, rather than a merge of
379     // smaller constants.
380     if (AllMergePartsArePadding && !AllPadReg) {
381       if (PadStrategy == TargetOpcode::G_ANYEXT)
382         AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);
383       else if (PadStrategy == TargetOpcode::G_ZEXT)
384         AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
385 
386       // If this is a sign extension, we can't materialize a trivial constant
387       // with the right type and have to produce a merge.
388     }
389 
390     if (AllPadReg) {
391       // Avoid creating additional instructions if we're just adding additional
392       // copies of padding bits.
393       Remerge[I] = AllPadReg;
394       continue;
395     }
396 
397     if (NumSubParts == 1)
398       Remerge[I] = SubMerge[0];
399     else
400       Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0);
401 
402     // In the sign extend padding case, re-use the first all-signbit merge.
403     if (AllMergePartsArePadding && !AllPadReg)
404       AllPadReg = Remerge[I];
405   }
406 
407   VRegs = std::move(Remerge);
408   return LCMTy;
409 }
410 
411 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
412                                                ArrayRef<Register> RemergeRegs) {
413   LLT DstTy = MRI.getType(DstReg);
414 
415   // Create the merge to the widened source, and extract the relevant bits into
416   // the result.
417 
418   if (DstTy == LCMTy) {
419     MIRBuilder.buildMerge(DstReg, RemergeRegs);
420     return;
421   }
422 
423   auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs);
424   if (DstTy.isScalar() && LCMTy.isScalar()) {
425     MIRBuilder.buildTrunc(DstReg, Remerge);
426     return;
427   }
428 
429   if (LCMTy.isVector()) {
430     MIRBuilder.buildExtract(DstReg, Remerge, 0);
431     return;
432   }
433 
434   llvm_unreachable("unhandled case");
435 }
436 
437 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
438   switch (Opcode) {
439   case TargetOpcode::G_SDIV:
440     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
441     switch (Size) {
442     case 32:
443       return RTLIB::SDIV_I32;
444     case 64:
445       return RTLIB::SDIV_I64;
446     case 128:
447       return RTLIB::SDIV_I128;
448     default:
449       llvm_unreachable("unexpected size");
450     }
451   case TargetOpcode::G_UDIV:
452     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
453     switch (Size) {
454     case 32:
455       return RTLIB::UDIV_I32;
456     case 64:
457       return RTLIB::UDIV_I64;
458     case 128:
459       return RTLIB::UDIV_I128;
460     default:
461       llvm_unreachable("unexpected size");
462     }
463   case TargetOpcode::G_SREM:
464     assert((Size == 32 || Size == 64) && "Unsupported size");
465     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
466   case TargetOpcode::G_UREM:
467     assert((Size == 32 || Size == 64) && "Unsupported size");
468     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
469   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
470     assert(Size == 32 && "Unsupported size");
471     return RTLIB::CTLZ_I32;
472   case TargetOpcode::G_FADD:
473     assert((Size == 32 || Size == 64) && "Unsupported size");
474     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
475   case TargetOpcode::G_FSUB:
476     assert((Size == 32 || Size == 64) && "Unsupported size");
477     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
478   case TargetOpcode::G_FMUL:
479     assert((Size == 32 || Size == 64) && "Unsupported size");
480     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
481   case TargetOpcode::G_FDIV:
482     assert((Size == 32 || Size == 64) && "Unsupported size");
483     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
484   case TargetOpcode::G_FEXP:
485     assert((Size == 32 || Size == 64) && "Unsupported size");
486     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
487   case TargetOpcode::G_FEXP2:
488     assert((Size == 32 || Size == 64) && "Unsupported size");
489     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
490   case TargetOpcode::G_FREM:
491     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
492   case TargetOpcode::G_FPOW:
493     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
494   case TargetOpcode::G_FMA:
495     assert((Size == 32 || Size == 64) && "Unsupported size");
496     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
497   case TargetOpcode::G_FSIN:
498     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
499     return Size == 128 ? RTLIB::SIN_F128
500                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
501   case TargetOpcode::G_FCOS:
502     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
503     return Size == 128 ? RTLIB::COS_F128
504                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
505   case TargetOpcode::G_FLOG10:
506     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
507     return Size == 128 ? RTLIB::LOG10_F128
508                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
509   case TargetOpcode::G_FLOG:
510     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
511     return Size == 128 ? RTLIB::LOG_F128
512                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
513   case TargetOpcode::G_FLOG2:
514     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
515     return Size == 128 ? RTLIB::LOG2_F128
516                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
517   case TargetOpcode::G_FCEIL:
518     assert((Size == 32 || Size == 64) && "Unsupported size");
519     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
520   case TargetOpcode::G_FFLOOR:
521     assert((Size == 32 || Size == 64) && "Unsupported size");
522     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
523   }
524   llvm_unreachable("Unknown libcall function");
525 }
526 
527 /// True if an instruction is in tail position in its caller. Intended for
528 /// legalizing libcalls as tail calls when possible.
529 static bool isLibCallInTailPosition(MachineInstr &MI) {
530   const Function &F = MI.getParent()->getParent()->getFunction();
531 
532   // Conservatively require the attributes of the call to match those of
533   // the return. Ignore NoAlias and NonNull because they don't affect the
534   // call sequence.
535   AttributeList CallerAttrs = F.getAttributes();
536   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
537           .removeAttribute(Attribute::NoAlias)
538           .removeAttribute(Attribute::NonNull)
539           .hasAttributes())
540     return false;
541 
542   // It's not safe to eliminate the sign / zero extension of the return value.
543   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
544       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
545     return false;
546 
547   // Only tail call if the following instruction is a standard return.
548   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
549   MachineInstr *Next = MI.getNextNode();
550   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
551     return false;
552 
553   return true;
554 }
555 
556 LegalizerHelper::LegalizeResult
557 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
558                     const CallLowering::ArgInfo &Result,
559                     ArrayRef<CallLowering::ArgInfo> Args) {
560   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
561   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
562   const char *Name = TLI.getLibcallName(Libcall);
563 
564   CallLowering::CallLoweringInfo Info;
565   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
566   Info.Callee = MachineOperand::CreateES(Name);
567   Info.OrigRet = Result;
568   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
569   if (!CLI.lowerCall(MIRBuilder, Info))
570     return LegalizerHelper::UnableToLegalize;
571 
572   return LegalizerHelper::Legalized;
573 }
574 
575 // Useful for libcalls where all operands have the same type.
576 static LegalizerHelper::LegalizeResult
577 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
578               Type *OpType) {
579   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
580 
581   SmallVector<CallLowering::ArgInfo, 3> Args;
582   for (unsigned i = 1; i < MI.getNumOperands(); i++)
583     Args.push_back({MI.getOperand(i).getReg(), OpType});
584   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
585                        Args);
586 }
587 
588 LegalizerHelper::LegalizeResult
589 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
590                        MachineInstr &MI) {
591   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
592   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
593 
594   SmallVector<CallLowering::ArgInfo, 3> Args;
595   // Add all the args, except for the last which is an imm denoting 'tail'.
596   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
597     Register Reg = MI.getOperand(i).getReg();
598 
599     // Need derive an IR type for call lowering.
600     LLT OpLLT = MRI.getType(Reg);
601     Type *OpTy = nullptr;
602     if (OpLLT.isPointer())
603       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
604     else
605       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
606     Args.push_back({Reg, OpTy});
607   }
608 
609   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
610   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
611   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
612   RTLIB::Libcall RTLibcall;
613   switch (ID) {
614   case Intrinsic::memcpy:
615     RTLibcall = RTLIB::MEMCPY;
616     break;
617   case Intrinsic::memset:
618     RTLibcall = RTLIB::MEMSET;
619     break;
620   case Intrinsic::memmove:
621     RTLibcall = RTLIB::MEMMOVE;
622     break;
623   default:
624     return LegalizerHelper::UnableToLegalize;
625   }
626   const char *Name = TLI.getLibcallName(RTLibcall);
627 
628   MIRBuilder.setInstr(MI);
629 
630   CallLowering::CallLoweringInfo Info;
631   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
632   Info.Callee = MachineOperand::CreateES(Name);
633   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
634   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
635                     isLibCallInTailPosition(MI);
636 
637   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
638   if (!CLI.lowerCall(MIRBuilder, Info))
639     return LegalizerHelper::UnableToLegalize;
640 
641   if (Info.LoweredTailCall) {
642     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
643     // We must have a return following the call to get past
644     // isLibCallInTailPosition.
645     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
646            "Expected instr following MI to be a return?");
647 
648     // We lowered a tail call, so the call is now the return from the block.
649     // Delete the old return.
650     MI.getNextNode()->eraseFromParent();
651   }
652 
653   return LegalizerHelper::Legalized;
654 }
655 
656 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
657                                        Type *FromType) {
658   auto ToMVT = MVT::getVT(ToType);
659   auto FromMVT = MVT::getVT(FromType);
660 
661   switch (Opcode) {
662   case TargetOpcode::G_FPEXT:
663     return RTLIB::getFPEXT(FromMVT, ToMVT);
664   case TargetOpcode::G_FPTRUNC:
665     return RTLIB::getFPROUND(FromMVT, ToMVT);
666   case TargetOpcode::G_FPTOSI:
667     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
668   case TargetOpcode::G_FPTOUI:
669     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
670   case TargetOpcode::G_SITOFP:
671     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
672   case TargetOpcode::G_UITOFP:
673     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
674   }
675   llvm_unreachable("Unsupported libcall function");
676 }
677 
678 static LegalizerHelper::LegalizeResult
679 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
680                   Type *FromType) {
681   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
682   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
683                        {{MI.getOperand(1).getReg(), FromType}});
684 }
685 
686 LegalizerHelper::LegalizeResult
687 LegalizerHelper::libcall(MachineInstr &MI) {
688   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
689   unsigned Size = LLTy.getSizeInBits();
690   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
691 
692   MIRBuilder.setInstr(MI);
693 
694   switch (MI.getOpcode()) {
695   default:
696     return UnableToLegalize;
697   case TargetOpcode::G_SDIV:
698   case TargetOpcode::G_UDIV:
699   case TargetOpcode::G_SREM:
700   case TargetOpcode::G_UREM:
701   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
702     Type *HLTy = IntegerType::get(Ctx, Size);
703     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
704     if (Status != Legalized)
705       return Status;
706     break;
707   }
708   case TargetOpcode::G_FADD:
709   case TargetOpcode::G_FSUB:
710   case TargetOpcode::G_FMUL:
711   case TargetOpcode::G_FDIV:
712   case TargetOpcode::G_FMA:
713   case TargetOpcode::G_FPOW:
714   case TargetOpcode::G_FREM:
715   case TargetOpcode::G_FCOS:
716   case TargetOpcode::G_FSIN:
717   case TargetOpcode::G_FLOG10:
718   case TargetOpcode::G_FLOG:
719   case TargetOpcode::G_FLOG2:
720   case TargetOpcode::G_FEXP:
721   case TargetOpcode::G_FEXP2:
722   case TargetOpcode::G_FCEIL:
723   case TargetOpcode::G_FFLOOR: {
724     Type *HLTy = getFloatTypeForLLT(Ctx, LLTy);
725     if (!HLTy || (Size != 32 && Size != 64)) {
726       LLVM_DEBUG(dbgs() << "No libcall available for size " << Size << ".\n");
727       return UnableToLegalize;
728     }
729     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
730     if (Status != Legalized)
731       return Status;
732     break;
733   }
734   case TargetOpcode::G_FPEXT:
735   case TargetOpcode::G_FPTRUNC: {
736     Type *FromTy = getFloatTypeForLLT(Ctx,  MRI.getType(MI.getOperand(1).getReg()));
737     Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg()));
738     if (!FromTy || !ToTy)
739       return UnableToLegalize;
740     LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy );
741     if (Status != Legalized)
742       return Status;
743     break;
744   }
745   case TargetOpcode::G_FPTOSI:
746   case TargetOpcode::G_FPTOUI: {
747     // FIXME: Support other types
748     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
749     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
750     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
751       return UnableToLegalize;
752     LegalizeResult Status = conversionLibcall(
753         MI, MIRBuilder,
754         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
755         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
756     if (Status != Legalized)
757       return Status;
758     break;
759   }
760   case TargetOpcode::G_SITOFP:
761   case TargetOpcode::G_UITOFP: {
762     // FIXME: Support other types
763     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
764     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
765     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
766       return UnableToLegalize;
767     LegalizeResult Status = conversionLibcall(
768         MI, MIRBuilder,
769         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
770         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
771     if (Status != Legalized)
772       return Status;
773     break;
774   }
775   }
776 
777   MI.eraseFromParent();
778   return Legalized;
779 }
780 
781 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
782                                                               unsigned TypeIdx,
783                                                               LLT NarrowTy) {
784   MIRBuilder.setInstr(MI);
785 
786   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
787   uint64_t NarrowSize = NarrowTy.getSizeInBits();
788 
789   switch (MI.getOpcode()) {
790   default:
791     return UnableToLegalize;
792   case TargetOpcode::G_IMPLICIT_DEF: {
793     // FIXME: add support for when SizeOp0 isn't an exact multiple of
794     // NarrowSize.
795     if (SizeOp0 % NarrowSize != 0)
796       return UnableToLegalize;
797     int NumParts = SizeOp0 / NarrowSize;
798 
799     SmallVector<Register, 2> DstRegs;
800     for (int i = 0; i < NumParts; ++i)
801       DstRegs.push_back(
802           MIRBuilder.buildUndef(NarrowTy).getReg(0));
803 
804     Register DstReg = MI.getOperand(0).getReg();
805     if(MRI.getType(DstReg).isVector())
806       MIRBuilder.buildBuildVector(DstReg, DstRegs);
807     else
808       MIRBuilder.buildMerge(DstReg, DstRegs);
809     MI.eraseFromParent();
810     return Legalized;
811   }
812   case TargetOpcode::G_CONSTANT: {
813     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
814     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
815     unsigned TotalSize = Ty.getSizeInBits();
816     unsigned NarrowSize = NarrowTy.getSizeInBits();
817     int NumParts = TotalSize / NarrowSize;
818 
819     SmallVector<Register, 4> PartRegs;
820     for (int I = 0; I != NumParts; ++I) {
821       unsigned Offset = I * NarrowSize;
822       auto K = MIRBuilder.buildConstant(NarrowTy,
823                                         Val.lshr(Offset).trunc(NarrowSize));
824       PartRegs.push_back(K.getReg(0));
825     }
826 
827     LLT LeftoverTy;
828     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
829     SmallVector<Register, 1> LeftoverRegs;
830     if (LeftoverBits != 0) {
831       LeftoverTy = LLT::scalar(LeftoverBits);
832       auto K = MIRBuilder.buildConstant(
833         LeftoverTy,
834         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
835       LeftoverRegs.push_back(K.getReg(0));
836     }
837 
838     insertParts(MI.getOperand(0).getReg(),
839                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
840 
841     MI.eraseFromParent();
842     return Legalized;
843   }
844   case TargetOpcode::G_SEXT:
845   case TargetOpcode::G_ZEXT:
846   case TargetOpcode::G_ANYEXT:
847     return narrowScalarExt(MI, TypeIdx, NarrowTy);
848   case TargetOpcode::G_TRUNC: {
849     if (TypeIdx != 1)
850       return UnableToLegalize;
851 
852     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
853     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
854       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
855       return UnableToLegalize;
856     }
857 
858     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
859     MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0));
860     MI.eraseFromParent();
861     return Legalized;
862   }
863 
864   case TargetOpcode::G_ADD: {
865     // FIXME: add support for when SizeOp0 isn't an exact multiple of
866     // NarrowSize.
867     if (SizeOp0 % NarrowSize != 0)
868       return UnableToLegalize;
869     // Expand in terms of carry-setting/consuming G_ADDE instructions.
870     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
871 
872     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
873     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
874     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
875 
876     Register CarryIn;
877     for (int i = 0; i < NumParts; ++i) {
878       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
879       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
880 
881       if (i == 0)
882         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
883       else {
884         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
885                               Src2Regs[i], CarryIn);
886       }
887 
888       DstRegs.push_back(DstReg);
889       CarryIn = CarryOut;
890     }
891     Register DstReg = MI.getOperand(0).getReg();
892     if(MRI.getType(DstReg).isVector())
893       MIRBuilder.buildBuildVector(DstReg, DstRegs);
894     else
895       MIRBuilder.buildMerge(DstReg, DstRegs);
896     MI.eraseFromParent();
897     return Legalized;
898   }
899   case TargetOpcode::G_SUB: {
900     // FIXME: add support for when SizeOp0 isn't an exact multiple of
901     // NarrowSize.
902     if (SizeOp0 % NarrowSize != 0)
903       return UnableToLegalize;
904 
905     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
906 
907     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
908     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
909     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
910 
911     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
912     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
913     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
914                           {Src1Regs[0], Src2Regs[0]});
915     DstRegs.push_back(DstReg);
916     Register BorrowIn = BorrowOut;
917     for (int i = 1; i < NumParts; ++i) {
918       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
919       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
920 
921       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
922                             {Src1Regs[i], Src2Regs[i], BorrowIn});
923 
924       DstRegs.push_back(DstReg);
925       BorrowIn = BorrowOut;
926     }
927     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
928     MI.eraseFromParent();
929     return Legalized;
930   }
931   case TargetOpcode::G_MUL:
932   case TargetOpcode::G_UMULH:
933     return narrowScalarMul(MI, NarrowTy);
934   case TargetOpcode::G_EXTRACT:
935     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
936   case TargetOpcode::G_INSERT:
937     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
938   case TargetOpcode::G_LOAD: {
939     const auto &MMO = **MI.memoperands_begin();
940     Register DstReg = MI.getOperand(0).getReg();
941     LLT DstTy = MRI.getType(DstReg);
942     if (DstTy.isVector())
943       return UnableToLegalize;
944 
945     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
946       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
947       auto &MMO = **MI.memoperands_begin();
948       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO);
949       MIRBuilder.buildAnyExt(DstReg, TmpReg);
950       MI.eraseFromParent();
951       return Legalized;
952     }
953 
954     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
955   }
956   case TargetOpcode::G_ZEXTLOAD:
957   case TargetOpcode::G_SEXTLOAD: {
958     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
959     Register DstReg = MI.getOperand(0).getReg();
960     Register PtrReg = MI.getOperand(1).getReg();
961 
962     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
963     auto &MMO = **MI.memoperands_begin();
964     if (MMO.getSizeInBits() == NarrowSize) {
965       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
966     } else {
967       MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO);
968     }
969 
970     if (ZExt)
971       MIRBuilder.buildZExt(DstReg, TmpReg);
972     else
973       MIRBuilder.buildSExt(DstReg, TmpReg);
974 
975     MI.eraseFromParent();
976     return Legalized;
977   }
978   case TargetOpcode::G_STORE: {
979     const auto &MMO = **MI.memoperands_begin();
980 
981     Register SrcReg = MI.getOperand(0).getReg();
982     LLT SrcTy = MRI.getType(SrcReg);
983     if (SrcTy.isVector())
984       return UnableToLegalize;
985 
986     int NumParts = SizeOp0 / NarrowSize;
987     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
988     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
989     if (SrcTy.isVector() && LeftoverBits != 0)
990       return UnableToLegalize;
991 
992     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
993       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
994       auto &MMO = **MI.memoperands_begin();
995       MIRBuilder.buildTrunc(TmpReg, SrcReg);
996       MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO);
997       MI.eraseFromParent();
998       return Legalized;
999     }
1000 
1001     return reduceLoadStoreWidth(MI, 0, NarrowTy);
1002   }
1003   case TargetOpcode::G_SELECT:
1004     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
1005   case TargetOpcode::G_AND:
1006   case TargetOpcode::G_OR:
1007   case TargetOpcode::G_XOR: {
1008     // Legalize bitwise operation:
1009     // A = BinOp<Ty> B, C
1010     // into:
1011     // B1, ..., BN = G_UNMERGE_VALUES B
1012     // C1, ..., CN = G_UNMERGE_VALUES C
1013     // A1 = BinOp<Ty/N> B1, C2
1014     // ...
1015     // AN = BinOp<Ty/N> BN, CN
1016     // A = G_MERGE_VALUES A1, ..., AN
1017     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
1018   }
1019   case TargetOpcode::G_SHL:
1020   case TargetOpcode::G_LSHR:
1021   case TargetOpcode::G_ASHR:
1022     return narrowScalarShift(MI, TypeIdx, NarrowTy);
1023   case TargetOpcode::G_CTLZ:
1024   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1025   case TargetOpcode::G_CTTZ:
1026   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1027   case TargetOpcode::G_CTPOP:
1028     if (TypeIdx == 1)
1029       switch (MI.getOpcode()) {
1030       case TargetOpcode::G_CTLZ:
1031       case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1032         return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);
1033       case TargetOpcode::G_CTTZ:
1034       case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1035         return narrowScalarCTTZ(MI, TypeIdx, NarrowTy);
1036       case TargetOpcode::G_CTPOP:
1037         return narrowScalarCTPOP(MI, TypeIdx, NarrowTy);
1038       default:
1039         return UnableToLegalize;
1040       }
1041 
1042     Observer.changingInstr(MI);
1043     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1044     Observer.changedInstr(MI);
1045     return Legalized;
1046   case TargetOpcode::G_INTTOPTR:
1047     if (TypeIdx != 1)
1048       return UnableToLegalize;
1049 
1050     Observer.changingInstr(MI);
1051     narrowScalarSrc(MI, NarrowTy, 1);
1052     Observer.changedInstr(MI);
1053     return Legalized;
1054   case TargetOpcode::G_PTRTOINT:
1055     if (TypeIdx != 0)
1056       return UnableToLegalize;
1057 
1058     Observer.changingInstr(MI);
1059     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1060     Observer.changedInstr(MI);
1061     return Legalized;
1062   case TargetOpcode::G_PHI: {
1063     unsigned NumParts = SizeOp0 / NarrowSize;
1064     SmallVector<Register, 2> DstRegs(NumParts);
1065     SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2);
1066     Observer.changingInstr(MI);
1067     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
1068       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
1069       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1070       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
1071                    SrcRegs[i / 2]);
1072     }
1073     MachineBasicBlock &MBB = *MI.getParent();
1074     MIRBuilder.setInsertPt(MBB, MI);
1075     for (unsigned i = 0; i < NumParts; ++i) {
1076       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
1077       MachineInstrBuilder MIB =
1078           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
1079       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
1080         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
1081     }
1082     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
1083     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1084     Observer.changedInstr(MI);
1085     MI.eraseFromParent();
1086     return Legalized;
1087   }
1088   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1089   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1090     if (TypeIdx != 2)
1091       return UnableToLegalize;
1092 
1093     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
1094     Observer.changingInstr(MI);
1095     narrowScalarSrc(MI, NarrowTy, OpIdx);
1096     Observer.changedInstr(MI);
1097     return Legalized;
1098   }
1099   case TargetOpcode::G_ICMP: {
1100     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
1101     if (NarrowSize * 2 != SrcSize)
1102       return UnableToLegalize;
1103 
1104     Observer.changingInstr(MI);
1105     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
1106     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
1107     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2));
1108 
1109     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
1110     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
1111     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3));
1112 
1113     CmpInst::Predicate Pred =
1114         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1115     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
1116 
1117     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
1118       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
1119       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
1120       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
1121       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
1122       MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero);
1123     } else {
1124       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
1125       MachineInstrBuilder CmpHEQ =
1126           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
1127       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
1128           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
1129       MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH);
1130     }
1131     Observer.changedInstr(MI);
1132     MI.eraseFromParent();
1133     return Legalized;
1134   }
1135   case TargetOpcode::G_SEXT_INREG: {
1136     if (TypeIdx != 0)
1137       return UnableToLegalize;
1138 
1139     int64_t SizeInBits = MI.getOperand(2).getImm();
1140 
1141     // So long as the new type has more bits than the bits we're extending we
1142     // don't need to break it apart.
1143     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
1144       Observer.changingInstr(MI);
1145       // We don't lose any non-extension bits by truncating the src and
1146       // sign-extending the dst.
1147       MachineOperand &MO1 = MI.getOperand(1);
1148       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
1149       MO1.setReg(TruncMIB.getReg(0));
1150 
1151       MachineOperand &MO2 = MI.getOperand(0);
1152       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1153       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1154       MIRBuilder.buildSExt(MO2, DstExt);
1155       MO2.setReg(DstExt);
1156       Observer.changedInstr(MI);
1157       return Legalized;
1158     }
1159 
1160     // Break it apart. Components below the extension point are unmodified. The
1161     // component containing the extension point becomes a narrower SEXT_INREG.
1162     // Components above it are ashr'd from the component containing the
1163     // extension point.
1164     if (SizeOp0 % NarrowSize != 0)
1165       return UnableToLegalize;
1166     int NumParts = SizeOp0 / NarrowSize;
1167 
1168     // List the registers where the destination will be scattered.
1169     SmallVector<Register, 2> DstRegs;
1170     // List the registers where the source will be split.
1171     SmallVector<Register, 2> SrcRegs;
1172 
1173     // Create all the temporary registers.
1174     for (int i = 0; i < NumParts; ++i) {
1175       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1176 
1177       SrcRegs.push_back(SrcReg);
1178     }
1179 
1180     // Explode the big arguments into smaller chunks.
1181     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1));
1182 
1183     Register AshrCstReg =
1184         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1185             .getReg(0);
1186     Register FullExtensionReg = 0;
1187     Register PartialExtensionReg = 0;
1188 
1189     // Do the operation on each small part.
1190     for (int i = 0; i < NumParts; ++i) {
1191       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1192         DstRegs.push_back(SrcRegs[i]);
1193       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1194         assert(PartialExtensionReg &&
1195                "Expected to visit partial extension before full");
1196         if (FullExtensionReg) {
1197           DstRegs.push_back(FullExtensionReg);
1198           continue;
1199         }
1200         DstRegs.push_back(
1201             MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
1202                 .getReg(0));
1203         FullExtensionReg = DstRegs.back();
1204       } else {
1205         DstRegs.push_back(
1206             MIRBuilder
1207                 .buildInstr(
1208                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1209                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1210                 .getReg(0));
1211         PartialExtensionReg = DstRegs.back();
1212       }
1213     }
1214 
1215     // Gather the destination registers into the final destination.
1216     Register DstReg = MI.getOperand(0).getReg();
1217     MIRBuilder.buildMerge(DstReg, DstRegs);
1218     MI.eraseFromParent();
1219     return Legalized;
1220   }
1221   case TargetOpcode::G_BSWAP:
1222   case TargetOpcode::G_BITREVERSE: {
1223     if (SizeOp0 % NarrowSize != 0)
1224       return UnableToLegalize;
1225 
1226     Observer.changingInstr(MI);
1227     SmallVector<Register, 2> SrcRegs, DstRegs;
1228     unsigned NumParts = SizeOp0 / NarrowSize;
1229     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1230 
1231     for (unsigned i = 0; i < NumParts; ++i) {
1232       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1233                                            {SrcRegs[NumParts - 1 - i]});
1234       DstRegs.push_back(DstPart.getReg(0));
1235     }
1236 
1237     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1238 
1239     Observer.changedInstr(MI);
1240     MI.eraseFromParent();
1241     return Legalized;
1242   }
1243   }
1244 }
1245 
1246 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1247                                      unsigned OpIdx, unsigned ExtOpcode) {
1248   MachineOperand &MO = MI.getOperand(OpIdx);
1249   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1250   MO.setReg(ExtB.getReg(0));
1251 }
1252 
1253 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1254                                       unsigned OpIdx) {
1255   MachineOperand &MO = MI.getOperand(OpIdx);
1256   auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
1257   MO.setReg(ExtB.getReg(0));
1258 }
1259 
1260 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1261                                      unsigned OpIdx, unsigned TruncOpcode) {
1262   MachineOperand &MO = MI.getOperand(OpIdx);
1263   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1264   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1265   MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
1266   MO.setReg(DstExt);
1267 }
1268 
1269 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1270                                       unsigned OpIdx, unsigned ExtOpcode) {
1271   MachineOperand &MO = MI.getOperand(OpIdx);
1272   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1273   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1274   MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
1275   MO.setReg(DstTrunc);
1276 }
1277 
1278 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1279                                             unsigned OpIdx) {
1280   MachineOperand &MO = MI.getOperand(OpIdx);
1281   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1282   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1283   MIRBuilder.buildExtract(MO, DstExt, 0);
1284   MO.setReg(DstExt);
1285 }
1286 
1287 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1288                                             unsigned OpIdx) {
1289   MachineOperand &MO = MI.getOperand(OpIdx);
1290 
1291   LLT OldTy = MRI.getType(MO.getReg());
1292   unsigned OldElts = OldTy.getNumElements();
1293   unsigned NewElts = MoreTy.getNumElements();
1294 
1295   unsigned NumParts = NewElts / OldElts;
1296 
1297   // Use concat_vectors if the result is a multiple of the number of elements.
1298   if (NumParts * OldElts == NewElts) {
1299     SmallVector<Register, 8> Parts;
1300     Parts.push_back(MO.getReg());
1301 
1302     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1303     for (unsigned I = 1; I != NumParts; ++I)
1304       Parts.push_back(ImpDef);
1305 
1306     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1307     MO.setReg(Concat.getReg(0));
1308     return;
1309   }
1310 
1311   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1312   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1313   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1314   MO.setReg(MoreReg);
1315 }
1316 
1317 LegalizerHelper::LegalizeResult
1318 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1319                                         LLT WideTy) {
1320   if (TypeIdx != 1)
1321     return UnableToLegalize;
1322 
1323   Register DstReg = MI.getOperand(0).getReg();
1324   LLT DstTy = MRI.getType(DstReg);
1325   if (DstTy.isVector())
1326     return UnableToLegalize;
1327 
1328   Register Src1 = MI.getOperand(1).getReg();
1329   LLT SrcTy = MRI.getType(Src1);
1330   const int DstSize = DstTy.getSizeInBits();
1331   const int SrcSize = SrcTy.getSizeInBits();
1332   const int WideSize = WideTy.getSizeInBits();
1333   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1334 
1335   unsigned NumOps = MI.getNumOperands();
1336   unsigned NumSrc = MI.getNumOperands() - 1;
1337   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1338 
1339   if (WideSize >= DstSize) {
1340     // Directly pack the bits in the target type.
1341     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1342 
1343     for (unsigned I = 2; I != NumOps; ++I) {
1344       const unsigned Offset = (I - 1) * PartSize;
1345 
1346       Register SrcReg = MI.getOperand(I).getReg();
1347       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1348 
1349       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1350 
1351       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1352         MRI.createGenericVirtualRegister(WideTy);
1353 
1354       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1355       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1356       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1357       ResultReg = NextResult;
1358     }
1359 
1360     if (WideSize > DstSize)
1361       MIRBuilder.buildTrunc(DstReg, ResultReg);
1362     else if (DstTy.isPointer())
1363       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1364 
1365     MI.eraseFromParent();
1366     return Legalized;
1367   }
1368 
1369   // Unmerge the original values to the GCD type, and recombine to the next
1370   // multiple greater than the original type.
1371   //
1372   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1373   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1374   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1375   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1376   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1377   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1378   // %12:_(s12) = G_MERGE_VALUES %10, %11
1379   //
1380   // Padding with undef if necessary:
1381   //
1382   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1383   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1384   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1385   // %7:_(s2) = G_IMPLICIT_DEF
1386   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1387   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1388   // %10:_(s12) = G_MERGE_VALUES %8, %9
1389 
1390   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1391   LLT GCDTy = LLT::scalar(GCD);
1392 
1393   SmallVector<Register, 8> Parts;
1394   SmallVector<Register, 8> NewMergeRegs;
1395   SmallVector<Register, 8> Unmerges;
1396   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1397 
1398   // Decompose the original operands if they don't evenly divide.
1399   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1400     Register SrcReg = MI.getOperand(I).getReg();
1401     if (GCD == SrcSize) {
1402       Unmerges.push_back(SrcReg);
1403     } else {
1404       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1405       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1406         Unmerges.push_back(Unmerge.getReg(J));
1407     }
1408   }
1409 
1410   // Pad with undef to the next size that is a multiple of the requested size.
1411   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1412     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1413     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1414       Unmerges.push_back(UndefReg);
1415   }
1416 
1417   const int PartsPerGCD = WideSize / GCD;
1418 
1419   // Build merges of each piece.
1420   ArrayRef<Register> Slicer(Unmerges);
1421   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1422     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1423     NewMergeRegs.push_back(Merge.getReg(0));
1424   }
1425 
1426   // A truncate may be necessary if the requested type doesn't evenly divide the
1427   // original result type.
1428   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1429     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1430   } else {
1431     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1432     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1433   }
1434 
1435   MI.eraseFromParent();
1436   return Legalized;
1437 }
1438 
1439 LegalizerHelper::LegalizeResult
1440 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1441                                           LLT WideTy) {
1442   if (TypeIdx != 0)
1443     return UnableToLegalize;
1444 
1445   int NumDst = MI.getNumOperands() - 1;
1446   Register SrcReg = MI.getOperand(NumDst).getReg();
1447   LLT SrcTy = MRI.getType(SrcReg);
1448   if (SrcTy.isVector())
1449     return UnableToLegalize;
1450 
1451   Register Dst0Reg = MI.getOperand(0).getReg();
1452   LLT DstTy = MRI.getType(Dst0Reg);
1453   if (!DstTy.isScalar())
1454     return UnableToLegalize;
1455 
1456   if (WideTy.getSizeInBits() == SrcTy.getSizeInBits()) {
1457     if (SrcTy.isPointer()) {
1458       const DataLayout &DL = MIRBuilder.getDataLayout();
1459       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) {
1460         LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
1461         return UnableToLegalize;
1462       }
1463 
1464       SrcTy = LLT::scalar(SrcTy.getSizeInBits());
1465       SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0);
1466     }
1467 
1468     // Theres no unmerge type to target. Directly extract the bits from the
1469     // source type
1470     unsigned DstSize = DstTy.getSizeInBits();
1471 
1472     MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
1473     for (int I = 1; I != NumDst; ++I) {
1474       auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
1475       auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);
1476       MIRBuilder.buildTrunc(MI.getOperand(I), Shr);
1477     }
1478 
1479     MI.eraseFromParent();
1480     return Legalized;
1481   }
1482 
1483   // TODO
1484   if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1485     return UnableToLegalize;
1486 
1487   // Extend the source to a wider type.
1488   LLT LCMTy = getLCMType(SrcTy, WideTy);
1489 
1490   Register WideSrc = SrcReg;
1491   if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) {
1492     // TODO: If this is an integral address space, cast to integer and anyext.
1493     if (SrcTy.isPointer()) {
1494       LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n");
1495       return UnableToLegalize;
1496     }
1497 
1498     WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);
1499   }
1500 
1501   auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);
1502 
1503   // Create a sequence of unmerges to the original results. since we may have
1504   // widened the source, we will need to pad the results with dead defs to cover
1505   // the source register.
1506   // e.g. widen s16 to s32:
1507   // %1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0:_(s48)
1508   //
1509   // =>
1510   //  %4:_(s64) = G_ANYEXT %0:_(s48)
1511   //  %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4 ; Requested unmerge
1512   //  %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %5 ; unpack to original regs
1513   //  %3:_(s16), dead %7 = G_UNMERGE_VALUES %6 ; original reg + extra dead def
1514 
1515   const int NumUnmerge = Unmerge->getNumOperands() - 1;
1516   const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
1517 
1518   for (int I = 0; I != NumUnmerge; ++I) {
1519     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
1520 
1521     for (int J = 0; J != PartsPerUnmerge; ++J) {
1522       int Idx = I * PartsPerUnmerge + J;
1523       if (Idx < NumDst)
1524         MIB.addDef(MI.getOperand(Idx).getReg());
1525       else {
1526         // Create dead def for excess components.
1527         MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
1528       }
1529     }
1530 
1531     MIB.addUse(Unmerge.getReg(I));
1532   }
1533 
1534   MI.eraseFromParent();
1535   return Legalized;
1536 }
1537 
1538 LegalizerHelper::LegalizeResult
1539 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1540                                     LLT WideTy) {
1541   Register DstReg = MI.getOperand(0).getReg();
1542   Register SrcReg = MI.getOperand(1).getReg();
1543   LLT SrcTy = MRI.getType(SrcReg);
1544 
1545   LLT DstTy = MRI.getType(DstReg);
1546   unsigned Offset = MI.getOperand(2).getImm();
1547 
1548   if (TypeIdx == 0) {
1549     if (SrcTy.isVector() || DstTy.isVector())
1550       return UnableToLegalize;
1551 
1552     SrcOp Src(SrcReg);
1553     if (SrcTy.isPointer()) {
1554       // Extracts from pointers can be handled only if they are really just
1555       // simple integers.
1556       const DataLayout &DL = MIRBuilder.getDataLayout();
1557       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1558         return UnableToLegalize;
1559 
1560       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1561       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1562       SrcTy = SrcAsIntTy;
1563     }
1564 
1565     if (DstTy.isPointer())
1566       return UnableToLegalize;
1567 
1568     if (Offset == 0) {
1569       // Avoid a shift in the degenerate case.
1570       MIRBuilder.buildTrunc(DstReg,
1571                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1572       MI.eraseFromParent();
1573       return Legalized;
1574     }
1575 
1576     // Do a shift in the source type.
1577     LLT ShiftTy = SrcTy;
1578     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1579       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1580       ShiftTy = WideTy;
1581     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1582       return UnableToLegalize;
1583 
1584     auto LShr = MIRBuilder.buildLShr(
1585       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1586     MIRBuilder.buildTrunc(DstReg, LShr);
1587     MI.eraseFromParent();
1588     return Legalized;
1589   }
1590 
1591   if (SrcTy.isScalar()) {
1592     Observer.changingInstr(MI);
1593     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1594     Observer.changedInstr(MI);
1595     return Legalized;
1596   }
1597 
1598   if (!SrcTy.isVector())
1599     return UnableToLegalize;
1600 
1601   if (DstTy != SrcTy.getElementType())
1602     return UnableToLegalize;
1603 
1604   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1605     return UnableToLegalize;
1606 
1607   Observer.changingInstr(MI);
1608   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1609 
1610   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1611                           Offset);
1612   widenScalarDst(MI, WideTy.getScalarType(), 0);
1613   Observer.changedInstr(MI);
1614   return Legalized;
1615 }
1616 
1617 LegalizerHelper::LegalizeResult
1618 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1619                                    LLT WideTy) {
1620   if (TypeIdx != 0)
1621     return UnableToLegalize;
1622   Observer.changingInstr(MI);
1623   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1624   widenScalarDst(MI, WideTy);
1625   Observer.changedInstr(MI);
1626   return Legalized;
1627 }
1628 
1629 LegalizerHelper::LegalizeResult
1630 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1631   MIRBuilder.setInstr(MI);
1632 
1633   switch (MI.getOpcode()) {
1634   default:
1635     return UnableToLegalize;
1636   case TargetOpcode::G_EXTRACT:
1637     return widenScalarExtract(MI, TypeIdx, WideTy);
1638   case TargetOpcode::G_INSERT:
1639     return widenScalarInsert(MI, TypeIdx, WideTy);
1640   case TargetOpcode::G_MERGE_VALUES:
1641     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1642   case TargetOpcode::G_UNMERGE_VALUES:
1643     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1644   case TargetOpcode::G_UADDO:
1645   case TargetOpcode::G_USUBO: {
1646     if (TypeIdx == 1)
1647       return UnableToLegalize; // TODO
1648     auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
1649     auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
1650     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1651                           ? TargetOpcode::G_ADD
1652                           : TargetOpcode::G_SUB;
1653     // Do the arithmetic in the larger type.
1654     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1655     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1656     APInt Mask =
1657         APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
1658     auto AndOp = MIRBuilder.buildAnd(
1659         WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
1660     // There is no overflow if the AndOp is the same as NewOp.
1661     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
1662     // Now trunc the NewOp to the original result.
1663     MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
1664     MI.eraseFromParent();
1665     return Legalized;
1666   }
1667   case TargetOpcode::G_CTTZ:
1668   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1669   case TargetOpcode::G_CTLZ:
1670   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1671   case TargetOpcode::G_CTPOP: {
1672     if (TypeIdx == 0) {
1673       Observer.changingInstr(MI);
1674       widenScalarDst(MI, WideTy, 0);
1675       Observer.changedInstr(MI);
1676       return Legalized;
1677     }
1678 
1679     Register SrcReg = MI.getOperand(1).getReg();
1680 
1681     // First ZEXT the input.
1682     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1683     LLT CurTy = MRI.getType(SrcReg);
1684     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1685       // The count is the same in the larger type except if the original
1686       // value was zero.  This can be handled by setting the bit just off
1687       // the top of the original type.
1688       auto TopBit =
1689           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1690       MIBSrc = MIRBuilder.buildOr(
1691         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1692     }
1693 
1694     // Perform the operation at the larger size.
1695     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1696     // This is already the correct result for CTPOP and CTTZs
1697     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1698         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1699       // The correct result is NewOp - (Difference in widety and current ty).
1700       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1701       MIBNewOp = MIRBuilder.buildSub(
1702           WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff));
1703     }
1704 
1705     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1706     MI.eraseFromParent();
1707     return Legalized;
1708   }
1709   case TargetOpcode::G_BSWAP: {
1710     Observer.changingInstr(MI);
1711     Register DstReg = MI.getOperand(0).getReg();
1712 
1713     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1714     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1715     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1716     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1717 
1718     MI.getOperand(0).setReg(DstExt);
1719 
1720     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1721 
1722     LLT Ty = MRI.getType(DstReg);
1723     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1724     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1725     MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg);
1726 
1727     MIRBuilder.buildTrunc(DstReg, ShrReg);
1728     Observer.changedInstr(MI);
1729     return Legalized;
1730   }
1731   case TargetOpcode::G_BITREVERSE: {
1732     Observer.changingInstr(MI);
1733 
1734     Register DstReg = MI.getOperand(0).getReg();
1735     LLT Ty = MRI.getType(DstReg);
1736     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1737 
1738     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1739     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1740     MI.getOperand(0).setReg(DstExt);
1741     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1742 
1743     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1744     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1745     MIRBuilder.buildTrunc(DstReg, Shift);
1746     Observer.changedInstr(MI);
1747     return Legalized;
1748   }
1749   case TargetOpcode::G_ADD:
1750   case TargetOpcode::G_AND:
1751   case TargetOpcode::G_MUL:
1752   case TargetOpcode::G_OR:
1753   case TargetOpcode::G_XOR:
1754   case TargetOpcode::G_SUB:
1755     // Perform operation at larger width (any extension is fines here, high bits
1756     // don't affect the result) and then truncate the result back to the
1757     // original type.
1758     Observer.changingInstr(MI);
1759     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1760     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1761     widenScalarDst(MI, WideTy);
1762     Observer.changedInstr(MI);
1763     return Legalized;
1764 
1765   case TargetOpcode::G_SHL:
1766     Observer.changingInstr(MI);
1767 
1768     if (TypeIdx == 0) {
1769       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1770       widenScalarDst(MI, WideTy);
1771     } else {
1772       assert(TypeIdx == 1);
1773       // The "number of bits to shift" operand must preserve its value as an
1774       // unsigned integer:
1775       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1776     }
1777 
1778     Observer.changedInstr(MI);
1779     return Legalized;
1780 
1781   case TargetOpcode::G_SDIV:
1782   case TargetOpcode::G_SREM:
1783   case TargetOpcode::G_SMIN:
1784   case TargetOpcode::G_SMAX:
1785     Observer.changingInstr(MI);
1786     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1787     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1788     widenScalarDst(MI, WideTy);
1789     Observer.changedInstr(MI);
1790     return Legalized;
1791 
1792   case TargetOpcode::G_ASHR:
1793   case TargetOpcode::G_LSHR:
1794     Observer.changingInstr(MI);
1795 
1796     if (TypeIdx == 0) {
1797       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1798         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1799 
1800       widenScalarSrc(MI, WideTy, 1, CvtOp);
1801       widenScalarDst(MI, WideTy);
1802     } else {
1803       assert(TypeIdx == 1);
1804       // The "number of bits to shift" operand must preserve its value as an
1805       // unsigned integer:
1806       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1807     }
1808 
1809     Observer.changedInstr(MI);
1810     return Legalized;
1811   case TargetOpcode::G_UDIV:
1812   case TargetOpcode::G_UREM:
1813   case TargetOpcode::G_UMIN:
1814   case TargetOpcode::G_UMAX:
1815     Observer.changingInstr(MI);
1816     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1817     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1818     widenScalarDst(MI, WideTy);
1819     Observer.changedInstr(MI);
1820     return Legalized;
1821 
1822   case TargetOpcode::G_SELECT:
1823     Observer.changingInstr(MI);
1824     if (TypeIdx == 0) {
1825       // Perform operation at larger width (any extension is fine here, high
1826       // bits don't affect the result) and then truncate the result back to the
1827       // original type.
1828       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1829       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1830       widenScalarDst(MI, WideTy);
1831     } else {
1832       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1833       // Explicit extension is required here since high bits affect the result.
1834       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1835     }
1836     Observer.changedInstr(MI);
1837     return Legalized;
1838 
1839   case TargetOpcode::G_FPTOSI:
1840   case TargetOpcode::G_FPTOUI:
1841     Observer.changingInstr(MI);
1842 
1843     if (TypeIdx == 0)
1844       widenScalarDst(MI, WideTy);
1845     else
1846       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1847 
1848     Observer.changedInstr(MI);
1849     return Legalized;
1850   case TargetOpcode::G_SITOFP:
1851     if (TypeIdx != 1)
1852       return UnableToLegalize;
1853     Observer.changingInstr(MI);
1854     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1855     Observer.changedInstr(MI);
1856     return Legalized;
1857 
1858   case TargetOpcode::G_UITOFP:
1859     if (TypeIdx != 1)
1860       return UnableToLegalize;
1861     Observer.changingInstr(MI);
1862     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1863     Observer.changedInstr(MI);
1864     return Legalized;
1865 
1866   case TargetOpcode::G_LOAD:
1867   case TargetOpcode::G_SEXTLOAD:
1868   case TargetOpcode::G_ZEXTLOAD:
1869     Observer.changingInstr(MI);
1870     widenScalarDst(MI, WideTy);
1871     Observer.changedInstr(MI);
1872     return Legalized;
1873 
1874   case TargetOpcode::G_STORE: {
1875     if (TypeIdx != 0)
1876       return UnableToLegalize;
1877 
1878     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1879     if (!isPowerOf2_32(Ty.getSizeInBits()))
1880       return UnableToLegalize;
1881 
1882     Observer.changingInstr(MI);
1883 
1884     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1885       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1886     widenScalarSrc(MI, WideTy, 0, ExtType);
1887 
1888     Observer.changedInstr(MI);
1889     return Legalized;
1890   }
1891   case TargetOpcode::G_CONSTANT: {
1892     MachineOperand &SrcMO = MI.getOperand(1);
1893     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1894     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1895         MRI.getType(MI.getOperand(0).getReg()));
1896     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1897             ExtOpc == TargetOpcode::G_ANYEXT) &&
1898            "Illegal Extend");
1899     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1900     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1901                            ? SrcVal.sext(WideTy.getSizeInBits())
1902                            : SrcVal.zext(WideTy.getSizeInBits());
1903     Observer.changingInstr(MI);
1904     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1905 
1906     widenScalarDst(MI, WideTy);
1907     Observer.changedInstr(MI);
1908     return Legalized;
1909   }
1910   case TargetOpcode::G_FCONSTANT: {
1911     MachineOperand &SrcMO = MI.getOperand(1);
1912     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1913     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1914     bool LosesInfo;
1915     switch (WideTy.getSizeInBits()) {
1916     case 32:
1917       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1918                   &LosesInfo);
1919       break;
1920     case 64:
1921       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1922                   &LosesInfo);
1923       break;
1924     default:
1925       return UnableToLegalize;
1926     }
1927 
1928     assert(!LosesInfo && "extend should always be lossless");
1929 
1930     Observer.changingInstr(MI);
1931     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1932 
1933     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1934     Observer.changedInstr(MI);
1935     return Legalized;
1936   }
1937   case TargetOpcode::G_IMPLICIT_DEF: {
1938     Observer.changingInstr(MI);
1939     widenScalarDst(MI, WideTy);
1940     Observer.changedInstr(MI);
1941     return Legalized;
1942   }
1943   case TargetOpcode::G_BRCOND:
1944     Observer.changingInstr(MI);
1945     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1946     Observer.changedInstr(MI);
1947     return Legalized;
1948 
1949   case TargetOpcode::G_FCMP:
1950     Observer.changingInstr(MI);
1951     if (TypeIdx == 0)
1952       widenScalarDst(MI, WideTy);
1953     else {
1954       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1955       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1956     }
1957     Observer.changedInstr(MI);
1958     return Legalized;
1959 
1960   case TargetOpcode::G_ICMP:
1961     Observer.changingInstr(MI);
1962     if (TypeIdx == 0)
1963       widenScalarDst(MI, WideTy);
1964     else {
1965       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1966                                MI.getOperand(1).getPredicate()))
1967                                ? TargetOpcode::G_SEXT
1968                                : TargetOpcode::G_ZEXT;
1969       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1970       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1971     }
1972     Observer.changedInstr(MI);
1973     return Legalized;
1974 
1975   case TargetOpcode::G_PTR_ADD:
1976     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1977     Observer.changingInstr(MI);
1978     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1979     Observer.changedInstr(MI);
1980     return Legalized;
1981 
1982   case TargetOpcode::G_PHI: {
1983     assert(TypeIdx == 0 && "Expecting only Idx 0");
1984 
1985     Observer.changingInstr(MI);
1986     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1987       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1988       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1989       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1990     }
1991 
1992     MachineBasicBlock &MBB = *MI.getParent();
1993     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1994     widenScalarDst(MI, WideTy);
1995     Observer.changedInstr(MI);
1996     return Legalized;
1997   }
1998   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1999     if (TypeIdx == 0) {
2000       Register VecReg = MI.getOperand(1).getReg();
2001       LLT VecTy = MRI.getType(VecReg);
2002       Observer.changingInstr(MI);
2003 
2004       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
2005                                      WideTy.getSizeInBits()),
2006                      1, TargetOpcode::G_SEXT);
2007 
2008       widenScalarDst(MI, WideTy, 0);
2009       Observer.changedInstr(MI);
2010       return Legalized;
2011     }
2012 
2013     if (TypeIdx != 2)
2014       return UnableToLegalize;
2015     Observer.changingInstr(MI);
2016     // TODO: Probably should be zext
2017     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
2018     Observer.changedInstr(MI);
2019     return Legalized;
2020   }
2021   case TargetOpcode::G_INSERT_VECTOR_ELT: {
2022     if (TypeIdx == 1) {
2023       Observer.changingInstr(MI);
2024 
2025       Register VecReg = MI.getOperand(1).getReg();
2026       LLT VecTy = MRI.getType(VecReg);
2027       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
2028 
2029       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
2030       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
2031       widenScalarDst(MI, WideVecTy, 0);
2032       Observer.changedInstr(MI);
2033       return Legalized;
2034     }
2035 
2036     if (TypeIdx == 2) {
2037       Observer.changingInstr(MI);
2038       // TODO: Probably should be zext
2039       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
2040       Observer.changedInstr(MI);
2041     }
2042 
2043     return Legalized;
2044   }
2045   case TargetOpcode::G_FADD:
2046   case TargetOpcode::G_FMUL:
2047   case TargetOpcode::G_FSUB:
2048   case TargetOpcode::G_FMA:
2049   case TargetOpcode::G_FMAD:
2050   case TargetOpcode::G_FNEG:
2051   case TargetOpcode::G_FABS:
2052   case TargetOpcode::G_FCANONICALIZE:
2053   case TargetOpcode::G_FMINNUM:
2054   case TargetOpcode::G_FMAXNUM:
2055   case TargetOpcode::G_FMINNUM_IEEE:
2056   case TargetOpcode::G_FMAXNUM_IEEE:
2057   case TargetOpcode::G_FMINIMUM:
2058   case TargetOpcode::G_FMAXIMUM:
2059   case TargetOpcode::G_FDIV:
2060   case TargetOpcode::G_FREM:
2061   case TargetOpcode::G_FCEIL:
2062   case TargetOpcode::G_FFLOOR:
2063   case TargetOpcode::G_FCOS:
2064   case TargetOpcode::G_FSIN:
2065   case TargetOpcode::G_FLOG10:
2066   case TargetOpcode::G_FLOG:
2067   case TargetOpcode::G_FLOG2:
2068   case TargetOpcode::G_FRINT:
2069   case TargetOpcode::G_FNEARBYINT:
2070   case TargetOpcode::G_FSQRT:
2071   case TargetOpcode::G_FEXP:
2072   case TargetOpcode::G_FEXP2:
2073   case TargetOpcode::G_FPOW:
2074   case TargetOpcode::G_INTRINSIC_TRUNC:
2075   case TargetOpcode::G_INTRINSIC_ROUND:
2076     assert(TypeIdx == 0);
2077     Observer.changingInstr(MI);
2078 
2079     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
2080       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
2081 
2082     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
2083     Observer.changedInstr(MI);
2084     return Legalized;
2085   case TargetOpcode::G_INTTOPTR:
2086     if (TypeIdx != 1)
2087       return UnableToLegalize;
2088 
2089     Observer.changingInstr(MI);
2090     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
2091     Observer.changedInstr(MI);
2092     return Legalized;
2093   case TargetOpcode::G_PTRTOINT:
2094     if (TypeIdx != 0)
2095       return UnableToLegalize;
2096 
2097     Observer.changingInstr(MI);
2098     widenScalarDst(MI, WideTy, 0);
2099     Observer.changedInstr(MI);
2100     return Legalized;
2101   case TargetOpcode::G_BUILD_VECTOR: {
2102     Observer.changingInstr(MI);
2103 
2104     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
2105     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
2106       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
2107 
2108     // Avoid changing the result vector type if the source element type was
2109     // requested.
2110     if (TypeIdx == 1) {
2111       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2112       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
2113     } else {
2114       widenScalarDst(MI, WideTy, 0);
2115     }
2116 
2117     Observer.changedInstr(MI);
2118     return Legalized;
2119   }
2120   case TargetOpcode::G_SEXT_INREG:
2121     if (TypeIdx != 0)
2122       return UnableToLegalize;
2123 
2124     Observer.changingInstr(MI);
2125     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
2126     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
2127     Observer.changedInstr(MI);
2128     return Legalized;
2129   }
2130 }
2131 
2132 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
2133                              MachineIRBuilder &B, Register Src, LLT Ty) {
2134   auto Unmerge = B.buildUnmerge(Ty, Src);
2135   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
2136     Pieces.push_back(Unmerge.getReg(I));
2137 }
2138 
2139 LegalizerHelper::LegalizeResult
2140 LegalizerHelper::lowerBitcast(MachineInstr &MI) {
2141   Register Dst = MI.getOperand(0).getReg();
2142   Register Src = MI.getOperand(1).getReg();
2143   LLT DstTy = MRI.getType(Dst);
2144   LLT SrcTy = MRI.getType(Src);
2145 
2146   if (SrcTy.isVector() && !DstTy.isVector()) {
2147     SmallVector<Register, 8> SrcRegs;
2148     getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcTy.getElementType());
2149     MIRBuilder.buildMerge(Dst, SrcRegs);
2150     MI.eraseFromParent();
2151     return Legalized;
2152   }
2153 
2154   if (DstTy.isVector() && !SrcTy.isVector()) {
2155     SmallVector<Register, 8> SrcRegs;
2156     getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
2157     MIRBuilder.buildMerge(Dst, SrcRegs);
2158     MI.eraseFromParent();
2159     return Legalized;
2160   }
2161 
2162   return UnableToLegalize;
2163 }
2164 
2165 LegalizerHelper::LegalizeResult
2166 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2167   using namespace TargetOpcode;
2168   MIRBuilder.setInstr(MI);
2169 
2170   switch(MI.getOpcode()) {
2171   default:
2172     return UnableToLegalize;
2173   case TargetOpcode::G_BITCAST:
2174     return lowerBitcast(MI);
2175   case TargetOpcode::G_SREM:
2176   case TargetOpcode::G_UREM: {
2177     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
2178     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg},
2179                           {MI.getOperand(1), MI.getOperand(2)});
2180 
2181     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
2182     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2));
2183     MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), ProdReg);
2184     MI.eraseFromParent();
2185     return Legalized;
2186   }
2187   case TargetOpcode::G_SADDO:
2188   case TargetOpcode::G_SSUBO:
2189     return lowerSADDO_SSUBO(MI);
2190   case TargetOpcode::G_SMULO:
2191   case TargetOpcode::G_UMULO: {
2192     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
2193     // result.
2194     Register Res = MI.getOperand(0).getReg();
2195     Register Overflow = MI.getOperand(1).getReg();
2196     Register LHS = MI.getOperand(2).getReg();
2197     Register RHS = MI.getOperand(3).getReg();
2198 
2199     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
2200                           ? TargetOpcode::G_SMULH
2201                           : TargetOpcode::G_UMULH;
2202 
2203     Observer.changingInstr(MI);
2204     const auto &TII = MIRBuilder.getTII();
2205     MI.setDesc(TII.get(TargetOpcode::G_MUL));
2206     MI.RemoveOperand(1);
2207     Observer.changedInstr(MI);
2208 
2209     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
2210 
2211     auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS});
2212 
2213     Register Zero = MRI.createGenericVirtualRegister(Ty);
2214     MIRBuilder.buildConstant(Zero, 0);
2215 
2216     // For *signed* multiply, overflow is detected by checking:
2217     // (hi != (lo >> bitwidth-1))
2218     if (Opcode == TargetOpcode::G_SMULH) {
2219       auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1);
2220       auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt);
2221       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
2222     } else {
2223       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2224     }
2225     return Legalized;
2226   }
2227   case TargetOpcode::G_FNEG: {
2228     // TODO: Handle vector types once we are able to
2229     // represent them.
2230     if (Ty.isVector())
2231       return UnableToLegalize;
2232     Register Res = MI.getOperand(0).getReg();
2233     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2234     Type *ZeroTy = getFloatTypeForLLT(Ctx, Ty);
2235     if (!ZeroTy)
2236       return UnableToLegalize;
2237     ConstantFP &ZeroForNegation =
2238         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2239     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2240     Register SubByReg = MI.getOperand(1).getReg();
2241     Register ZeroReg = Zero.getReg(0);
2242     MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
2243     MI.eraseFromParent();
2244     return Legalized;
2245   }
2246   case TargetOpcode::G_FSUB: {
2247     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2248     // First, check if G_FNEG is marked as Lower. If so, we may
2249     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2250     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2251       return UnableToLegalize;
2252     Register Res = MI.getOperand(0).getReg();
2253     Register LHS = MI.getOperand(1).getReg();
2254     Register RHS = MI.getOperand(2).getReg();
2255     Register Neg = MRI.createGenericVirtualRegister(Ty);
2256     MIRBuilder.buildFNeg(Neg, RHS);
2257     MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
2258     MI.eraseFromParent();
2259     return Legalized;
2260   }
2261   case TargetOpcode::G_FMAD:
2262     return lowerFMad(MI);
2263   case TargetOpcode::G_INTRINSIC_ROUND:
2264     return lowerIntrinsicRound(MI);
2265   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2266     Register OldValRes = MI.getOperand(0).getReg();
2267     Register SuccessRes = MI.getOperand(1).getReg();
2268     Register Addr = MI.getOperand(2).getReg();
2269     Register CmpVal = MI.getOperand(3).getReg();
2270     Register NewVal = MI.getOperand(4).getReg();
2271     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2272                                   **MI.memoperands_begin());
2273     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2274     MI.eraseFromParent();
2275     return Legalized;
2276   }
2277   case TargetOpcode::G_LOAD:
2278   case TargetOpcode::G_SEXTLOAD:
2279   case TargetOpcode::G_ZEXTLOAD: {
2280     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2281     Register DstReg = MI.getOperand(0).getReg();
2282     Register PtrReg = MI.getOperand(1).getReg();
2283     LLT DstTy = MRI.getType(DstReg);
2284     auto &MMO = **MI.memoperands_begin();
2285 
2286     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2287       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2288         // This load needs splitting into power of 2 sized loads.
2289         if (DstTy.isVector())
2290           return UnableToLegalize;
2291         if (isPowerOf2_32(DstTy.getSizeInBits()))
2292           return UnableToLegalize; // Don't know what we're being asked to do.
2293 
2294         // Our strategy here is to generate anyextending loads for the smaller
2295         // types up to next power-2 result type, and then combine the two larger
2296         // result values together, before truncating back down to the non-pow-2
2297         // type.
2298         // E.g. v1 = i24 load =>
2299         // v2 = i32 zextload (2 byte)
2300         // v3 = i32 load (1 byte)
2301         // v4 = i32 shl v3, 16
2302         // v5 = i32 or v4, v2
2303         // v1 = i24 trunc v5
2304         // By doing this we generate the correct truncate which should get
2305         // combined away as an artifact with a matching extend.
2306         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2307         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2308 
2309         MachineFunction &MF = MIRBuilder.getMF();
2310         MachineMemOperand *LargeMMO =
2311             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2312         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2313             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2314 
2315         LLT PtrTy = MRI.getType(PtrReg);
2316         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2317         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2318         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2319         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2320         auto LargeLoad = MIRBuilder.buildLoadInstr(
2321             TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO);
2322 
2323         auto OffsetCst = MIRBuilder.buildConstant(
2324             LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
2325         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2326         auto SmallPtr =
2327             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2328         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2329                                               *SmallMMO);
2330 
2331         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2332         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2333         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2334         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2335         MI.eraseFromParent();
2336         return Legalized;
2337       }
2338       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2339       MI.eraseFromParent();
2340       return Legalized;
2341     }
2342 
2343     if (DstTy.isScalar()) {
2344       Register TmpReg =
2345           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2346       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2347       switch (MI.getOpcode()) {
2348       default:
2349         llvm_unreachable("Unexpected opcode");
2350       case TargetOpcode::G_LOAD:
2351         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2352         break;
2353       case TargetOpcode::G_SEXTLOAD:
2354         MIRBuilder.buildSExt(DstReg, TmpReg);
2355         break;
2356       case TargetOpcode::G_ZEXTLOAD:
2357         MIRBuilder.buildZExt(DstReg, TmpReg);
2358         break;
2359       }
2360       MI.eraseFromParent();
2361       return Legalized;
2362     }
2363 
2364     return UnableToLegalize;
2365   }
2366   case TargetOpcode::G_STORE: {
2367     // Lower a non-power of 2 store into multiple pow-2 stores.
2368     // E.g. split an i24 store into an i16 store + i8 store.
2369     // We do this by first extending the stored value to the next largest power
2370     // of 2 type, and then using truncating stores to store the components.
2371     // By doing this, likewise with G_LOAD, generate an extend that can be
2372     // artifact-combined away instead of leaving behind extracts.
2373     Register SrcReg = MI.getOperand(0).getReg();
2374     Register PtrReg = MI.getOperand(1).getReg();
2375     LLT SrcTy = MRI.getType(SrcReg);
2376     MachineMemOperand &MMO = **MI.memoperands_begin();
2377     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2378       return UnableToLegalize;
2379     if (SrcTy.isVector())
2380       return UnableToLegalize;
2381     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2382       return UnableToLegalize; // Don't know what we're being asked to do.
2383 
2384     // Extend to the next pow-2.
2385     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2386     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2387 
2388     // Obtain the smaller value by shifting away the larger value.
2389     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2390     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2391     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2392     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2393 
2394     // Generate the PtrAdd and truncating stores.
2395     LLT PtrTy = MRI.getType(PtrReg);
2396     auto OffsetCst = MIRBuilder.buildConstant(
2397             LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
2398     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2399     auto SmallPtr =
2400         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2401 
2402     MachineFunction &MF = MIRBuilder.getMF();
2403     MachineMemOperand *LargeMMO =
2404         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2405     MachineMemOperand *SmallMMO =
2406         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2407     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2408     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2409     MI.eraseFromParent();
2410     return Legalized;
2411   }
2412   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2413   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2414   case TargetOpcode::G_CTLZ:
2415   case TargetOpcode::G_CTTZ:
2416   case TargetOpcode::G_CTPOP:
2417     return lowerBitCount(MI, TypeIdx, Ty);
2418   case G_UADDO: {
2419     Register Res = MI.getOperand(0).getReg();
2420     Register CarryOut = MI.getOperand(1).getReg();
2421     Register LHS = MI.getOperand(2).getReg();
2422     Register RHS = MI.getOperand(3).getReg();
2423 
2424     MIRBuilder.buildAdd(Res, LHS, RHS);
2425     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2426 
2427     MI.eraseFromParent();
2428     return Legalized;
2429   }
2430   case G_UADDE: {
2431     Register Res = MI.getOperand(0).getReg();
2432     Register CarryOut = MI.getOperand(1).getReg();
2433     Register LHS = MI.getOperand(2).getReg();
2434     Register RHS = MI.getOperand(3).getReg();
2435     Register CarryIn = MI.getOperand(4).getReg();
2436 
2437     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2438     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2439 
2440     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2441     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2442     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2443     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2444 
2445     MI.eraseFromParent();
2446     return Legalized;
2447   }
2448   case G_USUBO: {
2449     Register Res = MI.getOperand(0).getReg();
2450     Register BorrowOut = MI.getOperand(1).getReg();
2451     Register LHS = MI.getOperand(2).getReg();
2452     Register RHS = MI.getOperand(3).getReg();
2453 
2454     MIRBuilder.buildSub(Res, LHS, RHS);
2455     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2456 
2457     MI.eraseFromParent();
2458     return Legalized;
2459   }
2460   case G_USUBE: {
2461     Register Res = MI.getOperand(0).getReg();
2462     Register BorrowOut = MI.getOperand(1).getReg();
2463     Register LHS = MI.getOperand(2).getReg();
2464     Register RHS = MI.getOperand(3).getReg();
2465     Register BorrowIn = MI.getOperand(4).getReg();
2466 
2467     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2468     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2469     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2470     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2471 
2472     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2473     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2474     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2475     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2476     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2477     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2478 
2479     MI.eraseFromParent();
2480     return Legalized;
2481   }
2482   case G_UITOFP:
2483     return lowerUITOFP(MI, TypeIdx, Ty);
2484   case G_SITOFP:
2485     return lowerSITOFP(MI, TypeIdx, Ty);
2486   case G_FPTOUI:
2487     return lowerFPTOUI(MI, TypeIdx, Ty);
2488   case G_FPTOSI:
2489     return lowerFPTOSI(MI);
2490   case G_FPTRUNC:
2491     return lowerFPTRUNC(MI, TypeIdx, Ty);
2492   case G_SMIN:
2493   case G_SMAX:
2494   case G_UMIN:
2495   case G_UMAX:
2496     return lowerMinMax(MI, TypeIdx, Ty);
2497   case G_FCOPYSIGN:
2498     return lowerFCopySign(MI, TypeIdx, Ty);
2499   case G_FMINNUM:
2500   case G_FMAXNUM:
2501     return lowerFMinNumMaxNum(MI);
2502   case G_UNMERGE_VALUES:
2503     return lowerUnmergeValues(MI);
2504   case TargetOpcode::G_SEXT_INREG: {
2505     assert(MI.getOperand(2).isImm() && "Expected immediate");
2506     int64_t SizeInBits = MI.getOperand(2).getImm();
2507 
2508     Register DstReg = MI.getOperand(0).getReg();
2509     Register SrcReg = MI.getOperand(1).getReg();
2510     LLT DstTy = MRI.getType(DstReg);
2511     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2512 
2513     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2514     MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
2515     MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
2516     MI.eraseFromParent();
2517     return Legalized;
2518   }
2519   case G_SHUFFLE_VECTOR:
2520     return lowerShuffleVector(MI);
2521   case G_DYN_STACKALLOC:
2522     return lowerDynStackAlloc(MI);
2523   case G_EXTRACT:
2524     return lowerExtract(MI);
2525   case G_INSERT:
2526     return lowerInsert(MI);
2527   case G_BSWAP:
2528     return lowerBswap(MI);
2529   case G_BITREVERSE:
2530     return lowerBitreverse(MI);
2531   case G_READ_REGISTER:
2532   case G_WRITE_REGISTER:
2533     return lowerReadWriteRegister(MI);
2534   }
2535 }
2536 
2537 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2538     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2539   SmallVector<Register, 2> DstRegs;
2540 
2541   unsigned NarrowSize = NarrowTy.getSizeInBits();
2542   Register DstReg = MI.getOperand(0).getReg();
2543   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2544   int NumParts = Size / NarrowSize;
2545   // FIXME: Don't know how to handle the situation where the small vectors
2546   // aren't all the same size yet.
2547   if (Size % NarrowSize != 0)
2548     return UnableToLegalize;
2549 
2550   for (int i = 0; i < NumParts; ++i) {
2551     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2552     MIRBuilder.buildUndef(TmpReg);
2553     DstRegs.push_back(TmpReg);
2554   }
2555 
2556   if (NarrowTy.isVector())
2557     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2558   else
2559     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2560 
2561   MI.eraseFromParent();
2562   return Legalized;
2563 }
2564 
2565 LegalizerHelper::LegalizeResult
2566 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2567                                           LLT NarrowTy) {
2568   const unsigned Opc = MI.getOpcode();
2569   const unsigned NumOps = MI.getNumOperands() - 1;
2570   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2571   const Register DstReg = MI.getOperand(0).getReg();
2572   const unsigned Flags = MI.getFlags();
2573   const LLT DstTy = MRI.getType(DstReg);
2574   const unsigned Size = DstTy.getSizeInBits();
2575   const int NumParts = Size / NarrowSize;
2576   const LLT EltTy = DstTy.getElementType();
2577   const unsigned EltSize = EltTy.getSizeInBits();
2578   const unsigned BitsForNumParts = NarrowSize * NumParts;
2579 
2580   // Check if we have any leftovers. If we do, then only handle the case where
2581   // the leftover is one element.
2582   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2583     return UnableToLegalize;
2584 
2585   if (BitsForNumParts != Size) {
2586     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2587     MIRBuilder.buildUndef(AccumDstReg);
2588 
2589     // Handle the pieces which evenly divide into the requested type with
2590     // extract/op/insert sequence.
2591     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2592       SmallVector<SrcOp, 4> SrcOps;
2593       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2594         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2595         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I), Offset);
2596         SrcOps.push_back(PartOpReg);
2597       }
2598 
2599       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2600       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2601 
2602       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2603       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2604       AccumDstReg = PartInsertReg;
2605     }
2606 
2607     // Handle the remaining element sized leftover piece.
2608     SmallVector<SrcOp, 4> SrcOps;
2609     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2610       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2611       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I), BitsForNumParts);
2612       SrcOps.push_back(PartOpReg);
2613     }
2614 
2615     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2616     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2617     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2618     MI.eraseFromParent();
2619 
2620     return Legalized;
2621   }
2622 
2623   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2624 
2625   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2626 
2627   if (NumOps >= 2)
2628     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2629 
2630   if (NumOps >= 3)
2631     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2632 
2633   for (int i = 0; i < NumParts; ++i) {
2634     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2635 
2636     if (NumOps == 1)
2637       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2638     else if (NumOps == 2) {
2639       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2640     } else if (NumOps == 3) {
2641       MIRBuilder.buildInstr(Opc, {DstReg},
2642                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2643     }
2644 
2645     DstRegs.push_back(DstReg);
2646   }
2647 
2648   if (NarrowTy.isVector())
2649     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2650   else
2651     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2652 
2653   MI.eraseFromParent();
2654   return Legalized;
2655 }
2656 
2657 // Handle splitting vector operations which need to have the same number of
2658 // elements in each type index, but each type index may have a different element
2659 // type.
2660 //
2661 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2662 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2663 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2664 //
2665 // Also handles some irregular breakdown cases, e.g.
2666 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2667 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2668 //             s64 = G_SHL s64, s32
2669 LegalizerHelper::LegalizeResult
2670 LegalizerHelper::fewerElementsVectorMultiEltType(
2671   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2672   if (TypeIdx != 0)
2673     return UnableToLegalize;
2674 
2675   const LLT NarrowTy0 = NarrowTyArg;
2676   const unsigned NewNumElts =
2677       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2678 
2679   const Register DstReg = MI.getOperand(0).getReg();
2680   LLT DstTy = MRI.getType(DstReg);
2681   LLT LeftoverTy0;
2682 
2683   // All of the operands need to have the same number of elements, so if we can
2684   // determine a type breakdown for the result type, we can for all of the
2685   // source types.
2686   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2687   if (NumParts < 0)
2688     return UnableToLegalize;
2689 
2690   SmallVector<MachineInstrBuilder, 4> NewInsts;
2691 
2692   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2693   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2694 
2695   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2696     LLT LeftoverTy;
2697     Register SrcReg = MI.getOperand(I).getReg();
2698     LLT SrcTyI = MRI.getType(SrcReg);
2699     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2700     LLT LeftoverTyI;
2701 
2702     // Split this operand into the requested typed registers, and any leftover
2703     // required to reproduce the original type.
2704     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2705                       LeftoverRegs))
2706       return UnableToLegalize;
2707 
2708     if (I == 1) {
2709       // For the first operand, create an instruction for each part and setup
2710       // the result.
2711       for (Register PartReg : PartRegs) {
2712         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2713         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2714                                .addDef(PartDstReg)
2715                                .addUse(PartReg));
2716         DstRegs.push_back(PartDstReg);
2717       }
2718 
2719       for (Register LeftoverReg : LeftoverRegs) {
2720         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2721         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2722                                .addDef(PartDstReg)
2723                                .addUse(LeftoverReg));
2724         LeftoverDstRegs.push_back(PartDstReg);
2725       }
2726     } else {
2727       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2728 
2729       // Add the newly created operand splits to the existing instructions. The
2730       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2731       // pieces.
2732       unsigned InstCount = 0;
2733       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2734         NewInsts[InstCount++].addUse(PartRegs[J]);
2735       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2736         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2737     }
2738 
2739     PartRegs.clear();
2740     LeftoverRegs.clear();
2741   }
2742 
2743   // Insert the newly built operations and rebuild the result register.
2744   for (auto &MIB : NewInsts)
2745     MIRBuilder.insertInstr(MIB);
2746 
2747   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2748 
2749   MI.eraseFromParent();
2750   return Legalized;
2751 }
2752 
2753 LegalizerHelper::LegalizeResult
2754 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2755                                           LLT NarrowTy) {
2756   if (TypeIdx != 0)
2757     return UnableToLegalize;
2758 
2759   Register DstReg = MI.getOperand(0).getReg();
2760   Register SrcReg = MI.getOperand(1).getReg();
2761   LLT DstTy = MRI.getType(DstReg);
2762   LLT SrcTy = MRI.getType(SrcReg);
2763 
2764   LLT NarrowTy0 = NarrowTy;
2765   LLT NarrowTy1;
2766   unsigned NumParts;
2767 
2768   if (NarrowTy.isVector()) {
2769     // Uneven breakdown not handled.
2770     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2771     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2772       return UnableToLegalize;
2773 
2774     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2775   } else {
2776     NumParts = DstTy.getNumElements();
2777     NarrowTy1 = SrcTy.getElementType();
2778   }
2779 
2780   SmallVector<Register, 4> SrcRegs, DstRegs;
2781   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2782 
2783   for (unsigned I = 0; I < NumParts; ++I) {
2784     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2785     MachineInstr *NewInst =
2786         MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]});
2787 
2788     NewInst->setFlags(MI.getFlags());
2789     DstRegs.push_back(DstReg);
2790   }
2791 
2792   if (NarrowTy.isVector())
2793     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2794   else
2795     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2796 
2797   MI.eraseFromParent();
2798   return Legalized;
2799 }
2800 
2801 LegalizerHelper::LegalizeResult
2802 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2803                                         LLT NarrowTy) {
2804   Register DstReg = MI.getOperand(0).getReg();
2805   Register Src0Reg = MI.getOperand(2).getReg();
2806   LLT DstTy = MRI.getType(DstReg);
2807   LLT SrcTy = MRI.getType(Src0Reg);
2808 
2809   unsigned NumParts;
2810   LLT NarrowTy0, NarrowTy1;
2811 
2812   if (TypeIdx == 0) {
2813     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2814     unsigned OldElts = DstTy.getNumElements();
2815 
2816     NarrowTy0 = NarrowTy;
2817     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2818     NarrowTy1 = NarrowTy.isVector() ?
2819       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2820       SrcTy.getElementType();
2821 
2822   } else {
2823     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2824     unsigned OldElts = SrcTy.getNumElements();
2825 
2826     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2827       NarrowTy.getNumElements();
2828     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2829                             DstTy.getScalarSizeInBits());
2830     NarrowTy1 = NarrowTy;
2831   }
2832 
2833   // FIXME: Don't know how to handle the situation where the small vectors
2834   // aren't all the same size yet.
2835   if (NarrowTy1.isVector() &&
2836       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2837     return UnableToLegalize;
2838 
2839   CmpInst::Predicate Pred
2840     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2841 
2842   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2843   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2844   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2845 
2846   for (unsigned I = 0; I < NumParts; ++I) {
2847     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2848     DstRegs.push_back(DstReg);
2849 
2850     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2851       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2852     else {
2853       MachineInstr *NewCmp
2854         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2855       NewCmp->setFlags(MI.getFlags());
2856     }
2857   }
2858 
2859   if (NarrowTy1.isVector())
2860     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2861   else
2862     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2863 
2864   MI.eraseFromParent();
2865   return Legalized;
2866 }
2867 
2868 LegalizerHelper::LegalizeResult
2869 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2870                                            LLT NarrowTy) {
2871   Register DstReg = MI.getOperand(0).getReg();
2872   Register CondReg = MI.getOperand(1).getReg();
2873 
2874   unsigned NumParts = 0;
2875   LLT NarrowTy0, NarrowTy1;
2876 
2877   LLT DstTy = MRI.getType(DstReg);
2878   LLT CondTy = MRI.getType(CondReg);
2879   unsigned Size = DstTy.getSizeInBits();
2880 
2881   assert(TypeIdx == 0 || CondTy.isVector());
2882 
2883   if (TypeIdx == 0) {
2884     NarrowTy0 = NarrowTy;
2885     NarrowTy1 = CondTy;
2886 
2887     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2888     // FIXME: Don't know how to handle the situation where the small vectors
2889     // aren't all the same size yet.
2890     if (Size % NarrowSize != 0)
2891       return UnableToLegalize;
2892 
2893     NumParts = Size / NarrowSize;
2894 
2895     // Need to break down the condition type
2896     if (CondTy.isVector()) {
2897       if (CondTy.getNumElements() == NumParts)
2898         NarrowTy1 = CondTy.getElementType();
2899       else
2900         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2901                                 CondTy.getScalarSizeInBits());
2902     }
2903   } else {
2904     NumParts = CondTy.getNumElements();
2905     if (NarrowTy.isVector()) {
2906       // TODO: Handle uneven breakdown.
2907       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2908         return UnableToLegalize;
2909 
2910       return UnableToLegalize;
2911     } else {
2912       NarrowTy0 = DstTy.getElementType();
2913       NarrowTy1 = NarrowTy;
2914     }
2915   }
2916 
2917   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2918   if (CondTy.isVector())
2919     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2920 
2921   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2922   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2923 
2924   for (unsigned i = 0; i < NumParts; ++i) {
2925     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2926     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2927                            Src1Regs[i], Src2Regs[i]);
2928     DstRegs.push_back(DstReg);
2929   }
2930 
2931   if (NarrowTy0.isVector())
2932     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2933   else
2934     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2935 
2936   MI.eraseFromParent();
2937   return Legalized;
2938 }
2939 
2940 LegalizerHelper::LegalizeResult
2941 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2942                                         LLT NarrowTy) {
2943   const Register DstReg = MI.getOperand(0).getReg();
2944   LLT PhiTy = MRI.getType(DstReg);
2945   LLT LeftoverTy;
2946 
2947   // All of the operands need to have the same number of elements, so if we can
2948   // determine a type breakdown for the result type, we can for all of the
2949   // source types.
2950   int NumParts, NumLeftover;
2951   std::tie(NumParts, NumLeftover)
2952     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2953   if (NumParts < 0)
2954     return UnableToLegalize;
2955 
2956   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2957   SmallVector<MachineInstrBuilder, 4> NewInsts;
2958 
2959   const int TotalNumParts = NumParts + NumLeftover;
2960 
2961   // Insert the new phis in the result block first.
2962   for (int I = 0; I != TotalNumParts; ++I) {
2963     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2964     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2965     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2966                        .addDef(PartDstReg));
2967     if (I < NumParts)
2968       DstRegs.push_back(PartDstReg);
2969     else
2970       LeftoverDstRegs.push_back(PartDstReg);
2971   }
2972 
2973   MachineBasicBlock *MBB = MI.getParent();
2974   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2975   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2976 
2977   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2978 
2979   // Insert code to extract the incoming values in each predecessor block.
2980   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2981     PartRegs.clear();
2982     LeftoverRegs.clear();
2983 
2984     Register SrcReg = MI.getOperand(I).getReg();
2985     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2986     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2987 
2988     LLT Unused;
2989     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2990                       LeftoverRegs))
2991       return UnableToLegalize;
2992 
2993     // Add the newly created operand splits to the existing instructions. The
2994     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2995     // pieces.
2996     for (int J = 0; J != TotalNumParts; ++J) {
2997       MachineInstrBuilder MIB = NewInsts[J];
2998       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2999       MIB.addMBB(&OpMBB);
3000     }
3001   }
3002 
3003   MI.eraseFromParent();
3004   return Legalized;
3005 }
3006 
3007 LegalizerHelper::LegalizeResult
3008 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
3009                                                   unsigned TypeIdx,
3010                                                   LLT NarrowTy) {
3011   if (TypeIdx != 1)
3012     return UnableToLegalize;
3013 
3014   const int NumDst = MI.getNumOperands() - 1;
3015   const Register SrcReg = MI.getOperand(NumDst).getReg();
3016   LLT SrcTy = MRI.getType(SrcReg);
3017 
3018   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3019 
3020   // TODO: Create sequence of extracts.
3021   if (DstTy == NarrowTy)
3022     return UnableToLegalize;
3023 
3024   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
3025   if (DstTy == GCDTy) {
3026     // This would just be a copy of the same unmerge.
3027     // TODO: Create extracts, pad with undef and create intermediate merges.
3028     return UnableToLegalize;
3029   }
3030 
3031   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
3032   const int NumUnmerge = Unmerge->getNumOperands() - 1;
3033   const int PartsPerUnmerge = NumDst / NumUnmerge;
3034 
3035   for (int I = 0; I != NumUnmerge; ++I) {
3036     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3037 
3038     for (int J = 0; J != PartsPerUnmerge; ++J)
3039       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
3040     MIB.addUse(Unmerge.getReg(I));
3041   }
3042 
3043   MI.eraseFromParent();
3044   return Legalized;
3045 }
3046 
3047 LegalizerHelper::LegalizeResult
3048 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
3049                                                 unsigned TypeIdx,
3050                                                 LLT NarrowTy) {
3051   assert(TypeIdx == 0 && "not a vector type index");
3052   Register DstReg = MI.getOperand(0).getReg();
3053   LLT DstTy = MRI.getType(DstReg);
3054   LLT SrcTy = DstTy.getElementType();
3055 
3056   int DstNumElts = DstTy.getNumElements();
3057   int NarrowNumElts = NarrowTy.getNumElements();
3058   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
3059   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
3060 
3061   SmallVector<Register, 8> ConcatOps;
3062   SmallVector<Register, 8> SubBuildVector;
3063 
3064   Register UndefReg;
3065   if (WidenedDstTy != DstTy)
3066     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
3067 
3068   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
3069   // necessary.
3070   //
3071   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
3072   //   -> <2 x s16>
3073   //
3074   // %4:_(s16) = G_IMPLICIT_DEF
3075   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
3076   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
3077   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
3078   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
3079   for (int I = 0; I != NumConcat; ++I) {
3080     for (int J = 0; J != NarrowNumElts; ++J) {
3081       int SrcIdx = NarrowNumElts * I + J;
3082 
3083       if (SrcIdx < DstNumElts) {
3084         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
3085         SubBuildVector.push_back(SrcReg);
3086       } else
3087         SubBuildVector.push_back(UndefReg);
3088     }
3089 
3090     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
3091     ConcatOps.push_back(BuildVec.getReg(0));
3092     SubBuildVector.clear();
3093   }
3094 
3095   if (DstTy == WidenedDstTy)
3096     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
3097   else {
3098     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
3099     MIRBuilder.buildExtract(DstReg, Concat, 0);
3100   }
3101 
3102   MI.eraseFromParent();
3103   return Legalized;
3104 }
3105 
3106 LegalizerHelper::LegalizeResult
3107 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
3108                                       LLT NarrowTy) {
3109   // FIXME: Don't know how to handle secondary types yet.
3110   if (TypeIdx != 0)
3111     return UnableToLegalize;
3112 
3113   MachineMemOperand *MMO = *MI.memoperands_begin();
3114 
3115   // This implementation doesn't work for atomics. Give up instead of doing
3116   // something invalid.
3117   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
3118       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
3119     return UnableToLegalize;
3120 
3121   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
3122   Register ValReg = MI.getOperand(0).getReg();
3123   Register AddrReg = MI.getOperand(1).getReg();
3124   LLT ValTy = MRI.getType(ValReg);
3125 
3126   int NumParts = -1;
3127   int NumLeftover = -1;
3128   LLT LeftoverTy;
3129   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
3130   if (IsLoad) {
3131     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
3132   } else {
3133     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
3134                      NarrowLeftoverRegs)) {
3135       NumParts = NarrowRegs.size();
3136       NumLeftover = NarrowLeftoverRegs.size();
3137     }
3138   }
3139 
3140   if (NumParts == -1)
3141     return UnableToLegalize;
3142 
3143   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
3144 
3145   unsigned TotalSize = ValTy.getSizeInBits();
3146 
3147   // Split the load/store into PartTy sized pieces starting at Offset. If this
3148   // is a load, return the new registers in ValRegs. For a store, each elements
3149   // of ValRegs should be PartTy. Returns the next offset that needs to be
3150   // handled.
3151   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
3152                              unsigned Offset) -> unsigned {
3153     MachineFunction &MF = MIRBuilder.getMF();
3154     unsigned PartSize = PartTy.getSizeInBits();
3155     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
3156          Offset += PartSize, ++Idx) {
3157       unsigned ByteSize = PartSize / 8;
3158       unsigned ByteOffset = Offset / 8;
3159       Register NewAddrReg;
3160 
3161       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
3162 
3163       MachineMemOperand *NewMMO =
3164         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
3165 
3166       if (IsLoad) {
3167         Register Dst = MRI.createGenericVirtualRegister(PartTy);
3168         ValRegs.push_back(Dst);
3169         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
3170       } else {
3171         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
3172       }
3173     }
3174 
3175     return Offset;
3176   };
3177 
3178   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
3179 
3180   // Handle the rest of the register if this isn't an even type breakdown.
3181   if (LeftoverTy.isValid())
3182     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
3183 
3184   if (IsLoad) {
3185     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
3186                 LeftoverTy, NarrowLeftoverRegs);
3187   }
3188 
3189   MI.eraseFromParent();
3190   return Legalized;
3191 }
3192 
3193 LegalizerHelper::LegalizeResult
3194 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx,
3195                                               LLT NarrowTy) {
3196   Register DstReg = MI.getOperand(0).getReg();
3197   Register SrcReg = MI.getOperand(1).getReg();
3198   int64_t Imm = MI.getOperand(2).getImm();
3199 
3200   LLT DstTy = MRI.getType(DstReg);
3201 
3202   SmallVector<Register, 8> Parts;
3203   LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
3204   LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts);
3205 
3206   for (Register &R : Parts)
3207     R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0);
3208 
3209   buildWidenedRemergeToDst(DstReg, LCMTy, Parts);
3210 
3211   MI.eraseFromParent();
3212   return Legalized;
3213 }
3214 
3215 LegalizerHelper::LegalizeResult
3216 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
3217                                      LLT NarrowTy) {
3218   using namespace TargetOpcode;
3219 
3220   MIRBuilder.setInstr(MI);
3221   switch (MI.getOpcode()) {
3222   case G_IMPLICIT_DEF:
3223     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
3224   case G_AND:
3225   case G_OR:
3226   case G_XOR:
3227   case G_ADD:
3228   case G_SUB:
3229   case G_MUL:
3230   case G_SMULH:
3231   case G_UMULH:
3232   case G_FADD:
3233   case G_FMUL:
3234   case G_FSUB:
3235   case G_FNEG:
3236   case G_FABS:
3237   case G_FCANONICALIZE:
3238   case G_FDIV:
3239   case G_FREM:
3240   case G_FMA:
3241   case G_FMAD:
3242   case G_FPOW:
3243   case G_FEXP:
3244   case G_FEXP2:
3245   case G_FLOG:
3246   case G_FLOG2:
3247   case G_FLOG10:
3248   case G_FNEARBYINT:
3249   case G_FCEIL:
3250   case G_FFLOOR:
3251   case G_FRINT:
3252   case G_INTRINSIC_ROUND:
3253   case G_INTRINSIC_TRUNC:
3254   case G_FCOS:
3255   case G_FSIN:
3256   case G_FSQRT:
3257   case G_BSWAP:
3258   case G_BITREVERSE:
3259   case G_SDIV:
3260   case G_UDIV:
3261   case G_SREM:
3262   case G_UREM:
3263   case G_SMIN:
3264   case G_SMAX:
3265   case G_UMIN:
3266   case G_UMAX:
3267   case G_FMINNUM:
3268   case G_FMAXNUM:
3269   case G_FMINNUM_IEEE:
3270   case G_FMAXNUM_IEEE:
3271   case G_FMINIMUM:
3272   case G_FMAXIMUM:
3273     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3274   case G_SHL:
3275   case G_LSHR:
3276   case G_ASHR:
3277   case G_CTLZ:
3278   case G_CTLZ_ZERO_UNDEF:
3279   case G_CTTZ:
3280   case G_CTTZ_ZERO_UNDEF:
3281   case G_CTPOP:
3282   case G_FCOPYSIGN:
3283     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3284   case G_ZEXT:
3285   case G_SEXT:
3286   case G_ANYEXT:
3287   case G_FPEXT:
3288   case G_FPTRUNC:
3289   case G_SITOFP:
3290   case G_UITOFP:
3291   case G_FPTOSI:
3292   case G_FPTOUI:
3293   case G_INTTOPTR:
3294   case G_PTRTOINT:
3295   case G_ADDRSPACE_CAST:
3296     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3297   case G_ICMP:
3298   case G_FCMP:
3299     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3300   case G_SELECT:
3301     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3302   case G_PHI:
3303     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3304   case G_UNMERGE_VALUES:
3305     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3306   case G_BUILD_VECTOR:
3307     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3308   case G_LOAD:
3309   case G_STORE:
3310     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3311   case G_SEXT_INREG:
3312     return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy);
3313   default:
3314     return UnableToLegalize;
3315   }
3316 }
3317 
3318 LegalizerHelper::LegalizeResult
3319 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3320                                              const LLT HalfTy, const LLT AmtTy) {
3321 
3322   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3323   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3324   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
3325 
3326   if (Amt.isNullValue()) {
3327     MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
3328     MI.eraseFromParent();
3329     return Legalized;
3330   }
3331 
3332   LLT NVT = HalfTy;
3333   unsigned NVTBits = HalfTy.getSizeInBits();
3334   unsigned VTBits = 2 * NVTBits;
3335 
3336   SrcOp Lo(Register(0)), Hi(Register(0));
3337   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3338     if (Amt.ugt(VTBits)) {
3339       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3340     } else if (Amt.ugt(NVTBits)) {
3341       Lo = MIRBuilder.buildConstant(NVT, 0);
3342       Hi = MIRBuilder.buildShl(NVT, InL,
3343                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3344     } else if (Amt == NVTBits) {
3345       Lo = MIRBuilder.buildConstant(NVT, 0);
3346       Hi = InL;
3347     } else {
3348       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3349       auto OrLHS =
3350           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3351       auto OrRHS = MIRBuilder.buildLShr(
3352           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3353       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3354     }
3355   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3356     if (Amt.ugt(VTBits)) {
3357       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3358     } else if (Amt.ugt(NVTBits)) {
3359       Lo = MIRBuilder.buildLShr(NVT, InH,
3360                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3361       Hi = MIRBuilder.buildConstant(NVT, 0);
3362     } else if (Amt == NVTBits) {
3363       Lo = InH;
3364       Hi = MIRBuilder.buildConstant(NVT, 0);
3365     } else {
3366       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3367 
3368       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3369       auto OrRHS = MIRBuilder.buildShl(
3370           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3371 
3372       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3373       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3374     }
3375   } else {
3376     if (Amt.ugt(VTBits)) {
3377       Hi = Lo = MIRBuilder.buildAShr(
3378           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3379     } else if (Amt.ugt(NVTBits)) {
3380       Lo = MIRBuilder.buildAShr(NVT, InH,
3381                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3382       Hi = MIRBuilder.buildAShr(NVT, InH,
3383                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3384     } else if (Amt == NVTBits) {
3385       Lo = InH;
3386       Hi = MIRBuilder.buildAShr(NVT, InH,
3387                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3388     } else {
3389       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3390 
3391       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3392       auto OrRHS = MIRBuilder.buildShl(
3393           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3394 
3395       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3396       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3397     }
3398   }
3399 
3400   MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi});
3401   MI.eraseFromParent();
3402 
3403   return Legalized;
3404 }
3405 
3406 // TODO: Optimize if constant shift amount.
3407 LegalizerHelper::LegalizeResult
3408 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3409                                    LLT RequestedTy) {
3410   if (TypeIdx == 1) {
3411     Observer.changingInstr(MI);
3412     narrowScalarSrc(MI, RequestedTy, 2);
3413     Observer.changedInstr(MI);
3414     return Legalized;
3415   }
3416 
3417   Register DstReg = MI.getOperand(0).getReg();
3418   LLT DstTy = MRI.getType(DstReg);
3419   if (DstTy.isVector())
3420     return UnableToLegalize;
3421 
3422   Register Amt = MI.getOperand(2).getReg();
3423   LLT ShiftAmtTy = MRI.getType(Amt);
3424   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3425   if (DstEltSize % 2 != 0)
3426     return UnableToLegalize;
3427 
3428   // Ignore the input type. We can only go to exactly half the size of the
3429   // input. If that isn't small enough, the resulting pieces will be further
3430   // legalized.
3431   const unsigned NewBitSize = DstEltSize / 2;
3432   const LLT HalfTy = LLT::scalar(NewBitSize);
3433   const LLT CondTy = LLT::scalar(1);
3434 
3435   if (const MachineInstr *KShiftAmt =
3436           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3437     return narrowScalarShiftByConstant(
3438         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3439   }
3440 
3441   // TODO: Expand with known bits.
3442 
3443   // Handle the fully general expansion by an unknown amount.
3444   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3445 
3446   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3447   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3448   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
3449 
3450   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3451   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3452 
3453   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3454   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3455   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3456 
3457   Register ResultRegs[2];
3458   switch (MI.getOpcode()) {
3459   case TargetOpcode::G_SHL: {
3460     // Short: ShAmt < NewBitSize
3461     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3462 
3463     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3464     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3465     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3466 
3467     // Long: ShAmt >= NewBitSize
3468     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3469     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3470 
3471     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3472     auto Hi = MIRBuilder.buildSelect(
3473         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3474 
3475     ResultRegs[0] = Lo.getReg(0);
3476     ResultRegs[1] = Hi.getReg(0);
3477     break;
3478   }
3479   case TargetOpcode::G_LSHR:
3480   case TargetOpcode::G_ASHR: {
3481     // Short: ShAmt < NewBitSize
3482     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3483 
3484     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3485     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3486     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3487 
3488     // Long: ShAmt >= NewBitSize
3489     MachineInstrBuilder HiL;
3490     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3491       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3492     } else {
3493       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3494       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3495     }
3496     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3497                                      {InH, AmtExcess});     // Lo from Hi part.
3498 
3499     auto Lo = MIRBuilder.buildSelect(
3500         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3501 
3502     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3503 
3504     ResultRegs[0] = Lo.getReg(0);
3505     ResultRegs[1] = Hi.getReg(0);
3506     break;
3507   }
3508   default:
3509     llvm_unreachable("not a shift");
3510   }
3511 
3512   MIRBuilder.buildMerge(DstReg, ResultRegs);
3513   MI.eraseFromParent();
3514   return Legalized;
3515 }
3516 
3517 LegalizerHelper::LegalizeResult
3518 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3519                                        LLT MoreTy) {
3520   assert(TypeIdx == 0 && "Expecting only Idx 0");
3521 
3522   Observer.changingInstr(MI);
3523   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3524     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3525     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3526     moreElementsVectorSrc(MI, MoreTy, I);
3527   }
3528 
3529   MachineBasicBlock &MBB = *MI.getParent();
3530   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3531   moreElementsVectorDst(MI, MoreTy, 0);
3532   Observer.changedInstr(MI);
3533   return Legalized;
3534 }
3535 
3536 LegalizerHelper::LegalizeResult
3537 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3538                                     LLT MoreTy) {
3539   MIRBuilder.setInstr(MI);
3540   unsigned Opc = MI.getOpcode();
3541   switch (Opc) {
3542   case TargetOpcode::G_IMPLICIT_DEF:
3543   case TargetOpcode::G_LOAD: {
3544     if (TypeIdx != 0)
3545       return UnableToLegalize;
3546     Observer.changingInstr(MI);
3547     moreElementsVectorDst(MI, MoreTy, 0);
3548     Observer.changedInstr(MI);
3549     return Legalized;
3550   }
3551   case TargetOpcode::G_STORE:
3552     if (TypeIdx != 0)
3553       return UnableToLegalize;
3554     Observer.changingInstr(MI);
3555     moreElementsVectorSrc(MI, MoreTy, 0);
3556     Observer.changedInstr(MI);
3557     return Legalized;
3558   case TargetOpcode::G_AND:
3559   case TargetOpcode::G_OR:
3560   case TargetOpcode::G_XOR:
3561   case TargetOpcode::G_SMIN:
3562   case TargetOpcode::G_SMAX:
3563   case TargetOpcode::G_UMIN:
3564   case TargetOpcode::G_UMAX:
3565   case TargetOpcode::G_FMINNUM:
3566   case TargetOpcode::G_FMAXNUM:
3567   case TargetOpcode::G_FMINNUM_IEEE:
3568   case TargetOpcode::G_FMAXNUM_IEEE:
3569   case TargetOpcode::G_FMINIMUM:
3570   case TargetOpcode::G_FMAXIMUM: {
3571     Observer.changingInstr(MI);
3572     moreElementsVectorSrc(MI, MoreTy, 1);
3573     moreElementsVectorSrc(MI, MoreTy, 2);
3574     moreElementsVectorDst(MI, MoreTy, 0);
3575     Observer.changedInstr(MI);
3576     return Legalized;
3577   }
3578   case TargetOpcode::G_EXTRACT:
3579     if (TypeIdx != 1)
3580       return UnableToLegalize;
3581     Observer.changingInstr(MI);
3582     moreElementsVectorSrc(MI, MoreTy, 1);
3583     Observer.changedInstr(MI);
3584     return Legalized;
3585   case TargetOpcode::G_INSERT:
3586     if (TypeIdx != 0)
3587       return UnableToLegalize;
3588     Observer.changingInstr(MI);
3589     moreElementsVectorSrc(MI, MoreTy, 1);
3590     moreElementsVectorDst(MI, MoreTy, 0);
3591     Observer.changedInstr(MI);
3592     return Legalized;
3593   case TargetOpcode::G_SELECT:
3594     if (TypeIdx != 0)
3595       return UnableToLegalize;
3596     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3597       return UnableToLegalize;
3598 
3599     Observer.changingInstr(MI);
3600     moreElementsVectorSrc(MI, MoreTy, 2);
3601     moreElementsVectorSrc(MI, MoreTy, 3);
3602     moreElementsVectorDst(MI, MoreTy, 0);
3603     Observer.changedInstr(MI);
3604     return Legalized;
3605   case TargetOpcode::G_UNMERGE_VALUES: {
3606     if (TypeIdx != 1)
3607       return UnableToLegalize;
3608 
3609     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3610     int NumDst = MI.getNumOperands() - 1;
3611     moreElementsVectorSrc(MI, MoreTy, NumDst);
3612 
3613     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3614     for (int I = 0; I != NumDst; ++I)
3615       MIB.addDef(MI.getOperand(I).getReg());
3616 
3617     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3618     for (int I = NumDst; I != NewNumDst; ++I)
3619       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3620 
3621     MIB.addUse(MI.getOperand(NumDst).getReg());
3622     MI.eraseFromParent();
3623     return Legalized;
3624   }
3625   case TargetOpcode::G_PHI:
3626     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3627   default:
3628     return UnableToLegalize;
3629   }
3630 }
3631 
3632 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3633                                         ArrayRef<Register> Src1Regs,
3634                                         ArrayRef<Register> Src2Regs,
3635                                         LLT NarrowTy) {
3636   MachineIRBuilder &B = MIRBuilder;
3637   unsigned SrcParts = Src1Regs.size();
3638   unsigned DstParts = DstRegs.size();
3639 
3640   unsigned DstIdx = 0; // Low bits of the result.
3641   Register FactorSum =
3642       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3643   DstRegs[DstIdx] = FactorSum;
3644 
3645   unsigned CarrySumPrevDstIdx;
3646   SmallVector<Register, 4> Factors;
3647 
3648   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3649     // Collect low parts of muls for DstIdx.
3650     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3651          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3652       MachineInstrBuilder Mul =
3653           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3654       Factors.push_back(Mul.getReg(0));
3655     }
3656     // Collect high parts of muls from previous DstIdx.
3657     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3658          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3659       MachineInstrBuilder Umulh =
3660           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3661       Factors.push_back(Umulh.getReg(0));
3662     }
3663     // Add CarrySum from additions calculated for previous DstIdx.
3664     if (DstIdx != 1) {
3665       Factors.push_back(CarrySumPrevDstIdx);
3666     }
3667 
3668     Register CarrySum;
3669     // Add all factors and accumulate all carries into CarrySum.
3670     if (DstIdx != DstParts - 1) {
3671       MachineInstrBuilder Uaddo =
3672           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3673       FactorSum = Uaddo.getReg(0);
3674       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3675       for (unsigned i = 2; i < Factors.size(); ++i) {
3676         MachineInstrBuilder Uaddo =
3677             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3678         FactorSum = Uaddo.getReg(0);
3679         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3680         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3681       }
3682     } else {
3683       // Since value for the next index is not calculated, neither is CarrySum.
3684       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3685       for (unsigned i = 2; i < Factors.size(); ++i)
3686         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3687     }
3688 
3689     CarrySumPrevDstIdx = CarrySum;
3690     DstRegs[DstIdx] = FactorSum;
3691     Factors.clear();
3692   }
3693 }
3694 
3695 LegalizerHelper::LegalizeResult
3696 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3697   Register DstReg = MI.getOperand(0).getReg();
3698   Register Src1 = MI.getOperand(1).getReg();
3699   Register Src2 = MI.getOperand(2).getReg();
3700 
3701   LLT Ty = MRI.getType(DstReg);
3702   if (Ty.isVector())
3703     return UnableToLegalize;
3704 
3705   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3706   unsigned DstSize = Ty.getSizeInBits();
3707   unsigned NarrowSize = NarrowTy.getSizeInBits();
3708   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3709     return UnableToLegalize;
3710 
3711   unsigned NumDstParts = DstSize / NarrowSize;
3712   unsigned NumSrcParts = SrcSize / NarrowSize;
3713   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3714   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3715 
3716   SmallVector<Register, 2> Src1Parts, Src2Parts;
3717   SmallVector<Register, 2> DstTmpRegs(DstTmpParts);
3718   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3719   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3720   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3721 
3722   // Take only high half of registers if this is high mul.
3723   ArrayRef<Register> DstRegs(
3724       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3725   MIRBuilder.buildMerge(DstReg, DstRegs);
3726   MI.eraseFromParent();
3727   return Legalized;
3728 }
3729 
3730 LegalizerHelper::LegalizeResult
3731 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3732                                      LLT NarrowTy) {
3733   if (TypeIdx != 1)
3734     return UnableToLegalize;
3735 
3736   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3737 
3738   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3739   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3740   // NarrowSize.
3741   if (SizeOp1 % NarrowSize != 0)
3742     return UnableToLegalize;
3743   int NumParts = SizeOp1 / NarrowSize;
3744 
3745   SmallVector<Register, 2> SrcRegs, DstRegs;
3746   SmallVector<uint64_t, 2> Indexes;
3747   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3748 
3749   Register OpReg = MI.getOperand(0).getReg();
3750   uint64_t OpStart = MI.getOperand(2).getImm();
3751   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3752   for (int i = 0; i < NumParts; ++i) {
3753     unsigned SrcStart = i * NarrowSize;
3754 
3755     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3756       // No part of the extract uses this subregister, ignore it.
3757       continue;
3758     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3759       // The entire subregister is extracted, forward the value.
3760       DstRegs.push_back(SrcRegs[i]);
3761       continue;
3762     }
3763 
3764     // OpSegStart is where this destination segment would start in OpReg if it
3765     // extended infinitely in both directions.
3766     int64_t ExtractOffset;
3767     uint64_t SegSize;
3768     if (OpStart < SrcStart) {
3769       ExtractOffset = 0;
3770       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3771     } else {
3772       ExtractOffset = OpStart - SrcStart;
3773       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3774     }
3775 
3776     Register SegReg = SrcRegs[i];
3777     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3778       // A genuine extract is needed.
3779       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3780       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3781     }
3782 
3783     DstRegs.push_back(SegReg);
3784   }
3785 
3786   Register DstReg = MI.getOperand(0).getReg();
3787   if(MRI.getType(DstReg).isVector())
3788     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3789   else
3790     MIRBuilder.buildMerge(DstReg, DstRegs);
3791   MI.eraseFromParent();
3792   return Legalized;
3793 }
3794 
3795 LegalizerHelper::LegalizeResult
3796 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3797                                     LLT NarrowTy) {
3798   // FIXME: Don't know how to handle secondary types yet.
3799   if (TypeIdx != 0)
3800     return UnableToLegalize;
3801 
3802   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3803   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3804 
3805   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3806   // NarrowSize.
3807   if (SizeOp0 % NarrowSize != 0)
3808     return UnableToLegalize;
3809 
3810   int NumParts = SizeOp0 / NarrowSize;
3811 
3812   SmallVector<Register, 2> SrcRegs, DstRegs;
3813   SmallVector<uint64_t, 2> Indexes;
3814   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3815 
3816   Register OpReg = MI.getOperand(2).getReg();
3817   uint64_t OpStart = MI.getOperand(3).getImm();
3818   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3819   for (int i = 0; i < NumParts; ++i) {
3820     unsigned DstStart = i * NarrowSize;
3821 
3822     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3823       // No part of the insert affects this subregister, forward the original.
3824       DstRegs.push_back(SrcRegs[i]);
3825       continue;
3826     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3827       // The entire subregister is defined by this insert, forward the new
3828       // value.
3829       DstRegs.push_back(OpReg);
3830       continue;
3831     }
3832 
3833     // OpSegStart is where this destination segment would start in OpReg if it
3834     // extended infinitely in both directions.
3835     int64_t ExtractOffset, InsertOffset;
3836     uint64_t SegSize;
3837     if (OpStart < DstStart) {
3838       InsertOffset = 0;
3839       ExtractOffset = DstStart - OpStart;
3840       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3841     } else {
3842       InsertOffset = OpStart - DstStart;
3843       ExtractOffset = 0;
3844       SegSize =
3845         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3846     }
3847 
3848     Register SegReg = OpReg;
3849     if (ExtractOffset != 0 || SegSize != OpSize) {
3850       // A genuine extract is needed.
3851       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3852       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3853     }
3854 
3855     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3856     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3857     DstRegs.push_back(DstReg);
3858   }
3859 
3860   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3861   Register DstReg = MI.getOperand(0).getReg();
3862   if(MRI.getType(DstReg).isVector())
3863     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3864   else
3865     MIRBuilder.buildMerge(DstReg, DstRegs);
3866   MI.eraseFromParent();
3867   return Legalized;
3868 }
3869 
3870 LegalizerHelper::LegalizeResult
3871 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3872                                    LLT NarrowTy) {
3873   Register DstReg = MI.getOperand(0).getReg();
3874   LLT DstTy = MRI.getType(DstReg);
3875 
3876   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3877 
3878   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3879   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3880   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3881   LLT LeftoverTy;
3882   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3883                     Src0Regs, Src0LeftoverRegs))
3884     return UnableToLegalize;
3885 
3886   LLT Unused;
3887   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3888                     Src1Regs, Src1LeftoverRegs))
3889     llvm_unreachable("inconsistent extractParts result");
3890 
3891   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3892     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3893                                         {Src0Regs[I], Src1Regs[I]});
3894     DstRegs.push_back(Inst.getReg(0));
3895   }
3896 
3897   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3898     auto Inst = MIRBuilder.buildInstr(
3899       MI.getOpcode(),
3900       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3901     DstLeftoverRegs.push_back(Inst.getReg(0));
3902   }
3903 
3904   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3905               LeftoverTy, DstLeftoverRegs);
3906 
3907   MI.eraseFromParent();
3908   return Legalized;
3909 }
3910 
3911 LegalizerHelper::LegalizeResult
3912 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx,
3913                                  LLT NarrowTy) {
3914   if (TypeIdx != 0)
3915     return UnableToLegalize;
3916 
3917   Register DstReg = MI.getOperand(0).getReg();
3918   Register SrcReg = MI.getOperand(1).getReg();
3919 
3920   LLT DstTy = MRI.getType(DstReg);
3921   if (DstTy.isVector())
3922     return UnableToLegalize;
3923 
3924   SmallVector<Register, 8> Parts;
3925   LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
3926   LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode());
3927   buildWidenedRemergeToDst(DstReg, LCMTy, Parts);
3928 
3929   MI.eraseFromParent();
3930   return Legalized;
3931 }
3932 
3933 LegalizerHelper::LegalizeResult
3934 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3935                                     LLT NarrowTy) {
3936   if (TypeIdx != 0)
3937     return UnableToLegalize;
3938 
3939   Register CondReg = MI.getOperand(1).getReg();
3940   LLT CondTy = MRI.getType(CondReg);
3941   if (CondTy.isVector()) // TODO: Handle vselect
3942     return UnableToLegalize;
3943 
3944   Register DstReg = MI.getOperand(0).getReg();
3945   LLT DstTy = MRI.getType(DstReg);
3946 
3947   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3948   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3949   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3950   LLT LeftoverTy;
3951   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3952                     Src1Regs, Src1LeftoverRegs))
3953     return UnableToLegalize;
3954 
3955   LLT Unused;
3956   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3957                     Src2Regs, Src2LeftoverRegs))
3958     llvm_unreachable("inconsistent extractParts result");
3959 
3960   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3961     auto Select = MIRBuilder.buildSelect(NarrowTy,
3962                                          CondReg, Src1Regs[I], Src2Regs[I]);
3963     DstRegs.push_back(Select.getReg(0));
3964   }
3965 
3966   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3967     auto Select = MIRBuilder.buildSelect(
3968       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3969     DstLeftoverRegs.push_back(Select.getReg(0));
3970   }
3971 
3972   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3973               LeftoverTy, DstLeftoverRegs);
3974 
3975   MI.eraseFromParent();
3976   return Legalized;
3977 }
3978 
3979 LegalizerHelper::LegalizeResult
3980 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
3981                                   LLT NarrowTy) {
3982   if (TypeIdx != 1)
3983     return UnableToLegalize;
3984 
3985   Register DstReg = MI.getOperand(0).getReg();
3986   Register SrcReg = MI.getOperand(1).getReg();
3987   LLT DstTy = MRI.getType(DstReg);
3988   LLT SrcTy = MRI.getType(SrcReg);
3989   unsigned NarrowSize = NarrowTy.getSizeInBits();
3990 
3991   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
3992     const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF;
3993 
3994     MachineIRBuilder &B = MIRBuilder;
3995     auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
3996     // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)
3997     auto C_0 = B.buildConstant(NarrowTy, 0);
3998     auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3999                                 UnmergeSrc.getReg(1), C_0);
4000     auto LoCTLZ = IsUndef ?
4001       B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) :
4002       B.buildCTLZ(DstTy, UnmergeSrc.getReg(0));
4003     auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
4004     auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize);
4005     auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1));
4006     B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ);
4007 
4008     MI.eraseFromParent();
4009     return Legalized;
4010   }
4011 
4012   return UnableToLegalize;
4013 }
4014 
4015 LegalizerHelper::LegalizeResult
4016 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx,
4017                                   LLT NarrowTy) {
4018   if (TypeIdx != 1)
4019     return UnableToLegalize;
4020 
4021   Register DstReg = MI.getOperand(0).getReg();
4022   Register SrcReg = MI.getOperand(1).getReg();
4023   LLT DstTy = MRI.getType(DstReg);
4024   LLT SrcTy = MRI.getType(SrcReg);
4025   unsigned NarrowSize = NarrowTy.getSizeInBits();
4026 
4027   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4028     const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF;
4029 
4030     MachineIRBuilder &B = MIRBuilder;
4031     auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
4032     // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo)
4033     auto C_0 = B.buildConstant(NarrowTy, 0);
4034     auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
4035                                 UnmergeSrc.getReg(0), C_0);
4036     auto HiCTTZ = IsUndef ?
4037       B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) :
4038       B.buildCTTZ(DstTy, UnmergeSrc.getReg(1));
4039     auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
4040     auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize);
4041     auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0));
4042     B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ);
4043 
4044     MI.eraseFromParent();
4045     return Legalized;
4046   }
4047 
4048   return UnableToLegalize;
4049 }
4050 
4051 LegalizerHelper::LegalizeResult
4052 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx,
4053                                    LLT NarrowTy) {
4054   if (TypeIdx != 1)
4055     return UnableToLegalize;
4056 
4057   Register DstReg = MI.getOperand(0).getReg();
4058   LLT DstTy = MRI.getType(DstReg);
4059   LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
4060   unsigned NarrowSize = NarrowTy.getSizeInBits();
4061 
4062   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4063     auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
4064 
4065     auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0));
4066     auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1));
4067     MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP);
4068 
4069     MI.eraseFromParent();
4070     return Legalized;
4071   }
4072 
4073   return UnableToLegalize;
4074 }
4075 
4076 LegalizerHelper::LegalizeResult
4077 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4078   unsigned Opc = MI.getOpcode();
4079   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
4080   auto isSupported = [this](const LegalityQuery &Q) {
4081     auto QAction = LI.getAction(Q).Action;
4082     return QAction == Legal || QAction == Libcall || QAction == Custom;
4083   };
4084   switch (Opc) {
4085   default:
4086     return UnableToLegalize;
4087   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
4088     // This trivially expands to CTLZ.
4089     Observer.changingInstr(MI);
4090     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
4091     Observer.changedInstr(MI);
4092     return Legalized;
4093   }
4094   case TargetOpcode::G_CTLZ: {
4095     Register DstReg = MI.getOperand(0).getReg();
4096     Register SrcReg = MI.getOperand(1).getReg();
4097     LLT DstTy = MRI.getType(DstReg);
4098     LLT SrcTy = MRI.getType(SrcReg);
4099     unsigned Len = SrcTy.getSizeInBits();
4100 
4101     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
4102       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
4103       auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg);
4104       auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0);
4105       auto ICmp = MIRBuilder.buildICmp(
4106           CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc);
4107       auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
4108       MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU);
4109       MI.eraseFromParent();
4110       return Legalized;
4111     }
4112     // for now, we do this:
4113     // NewLen = NextPowerOf2(Len);
4114     // x = x | (x >> 1);
4115     // x = x | (x >> 2);
4116     // ...
4117     // x = x | (x >>16);
4118     // x = x | (x >>32); // for 64-bit input
4119     // Upto NewLen/2
4120     // return Len - popcount(x);
4121     //
4122     // Ref: "Hacker's Delight" by Henry Warren
4123     Register Op = SrcReg;
4124     unsigned NewLen = PowerOf2Ceil(Len);
4125     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
4126       auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i);
4127       auto MIBOp = MIRBuilder.buildOr(
4128           SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt));
4129       Op = MIBOp.getReg(0);
4130     }
4131     auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op);
4132     MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len),
4133                         MIBPop);
4134     MI.eraseFromParent();
4135     return Legalized;
4136   }
4137   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
4138     // This trivially expands to CTTZ.
4139     Observer.changingInstr(MI);
4140     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
4141     Observer.changedInstr(MI);
4142     return Legalized;
4143   }
4144   case TargetOpcode::G_CTTZ: {
4145     Register DstReg = MI.getOperand(0).getReg();
4146     Register SrcReg = MI.getOperand(1).getReg();
4147     LLT DstTy = MRI.getType(DstReg);
4148     LLT SrcTy = MRI.getType(SrcReg);
4149 
4150     unsigned Len = SrcTy.getSizeInBits();
4151     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
4152       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
4153       // zero.
4154       auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg);
4155       auto Zero = MIRBuilder.buildConstant(SrcTy, 0);
4156       auto ICmp = MIRBuilder.buildICmp(
4157           CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero);
4158       auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
4159       MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU);
4160       MI.eraseFromParent();
4161       return Legalized;
4162     }
4163     // for now, we use: { return popcount(~x & (x - 1)); }
4164     // unless the target has ctlz but not ctpop, in which case we use:
4165     // { return 32 - nlz(~x & (x-1)); }
4166     // Ref: "Hacker's Delight" by Henry Warren
4167     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
4168     auto MIBNot = MIRBuilder.buildXor(Ty, SrcReg, MIBCstNeg1);
4169     auto MIBTmp = MIRBuilder.buildAnd(
4170         Ty, MIBNot, MIRBuilder.buildAdd(Ty, SrcReg, MIBCstNeg1));
4171     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
4172         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
4173       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
4174       MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
4175                           MIRBuilder.buildCTLZ(Ty, MIBTmp));
4176       MI.eraseFromParent();
4177       return Legalized;
4178     }
4179     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
4180     MI.getOperand(1).setReg(MIBTmp.getReg(0));
4181     return Legalized;
4182   }
4183   case TargetOpcode::G_CTPOP: {
4184     unsigned Size = Ty.getSizeInBits();
4185     MachineIRBuilder &B = MIRBuilder;
4186 
4187     // Count set bits in blocks of 2 bits. Default approach would be
4188     // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 }
4189     // We use following formula instead:
4190     // B2Count = val - { (val >> 1) & 0x55555555 }
4191     // since it gives same result in blocks of 2 with one instruction less.
4192     auto C_1 = B.buildConstant(Ty, 1);
4193     auto B2Set1LoTo1Hi = B.buildLShr(Ty, MI.getOperand(1).getReg(), C_1);
4194     APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55));
4195     auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0);
4196     auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0);
4197     auto B2Count = B.buildSub(Ty, MI.getOperand(1).getReg(), B2Count1Hi);
4198 
4199     // In order to get count in blocks of 4 add values from adjacent block of 2.
4200     // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 }
4201     auto C_2 = B.buildConstant(Ty, 2);
4202     auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2);
4203     APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33));
4204     auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0);
4205     auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0);
4206     auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0);
4207     auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count);
4208 
4209     // For count in blocks of 8 bits we don't have to mask high 4 bits before
4210     // addition since count value sits in range {0,...,8} and 4 bits are enough
4211     // to hold such binary values. After addition high 4 bits still hold count
4212     // of set bits in high 4 bit block, set them to zero and get 8 bit result.
4213     // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F
4214     auto C_4 = B.buildConstant(Ty, 4);
4215     auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4);
4216     auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count);
4217     APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F));
4218     auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0);
4219     auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0);
4220 
4221     assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm");
4222     // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this
4223     // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks.
4224     auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01)));
4225     auto ResTmp = B.buildMul(Ty, B8Count, MulMask);
4226 
4227     // Shift count result from 8 high bits to low bits.
4228     auto C_SizeM8 = B.buildConstant(Ty, Size - 8);
4229     B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8);
4230 
4231     MI.eraseFromParent();
4232     return Legalized;
4233   }
4234   }
4235 }
4236 
4237 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
4238 // representation.
4239 LegalizerHelper::LegalizeResult
4240 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
4241   Register Dst = MI.getOperand(0).getReg();
4242   Register Src = MI.getOperand(1).getReg();
4243   const LLT S64 = LLT::scalar(64);
4244   const LLT S32 = LLT::scalar(32);
4245   const LLT S1 = LLT::scalar(1);
4246 
4247   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
4248 
4249   // unsigned cul2f(ulong u) {
4250   //   uint lz = clz(u);
4251   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
4252   //   u = (u << lz) & 0x7fffffffffffffffUL;
4253   //   ulong t = u & 0xffffffffffUL;
4254   //   uint v = (e << 23) | (uint)(u >> 40);
4255   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
4256   //   return as_float(v + r);
4257   // }
4258 
4259   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
4260   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
4261 
4262   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
4263 
4264   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
4265   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
4266 
4267   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
4268   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
4269 
4270   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
4271   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
4272 
4273   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
4274 
4275   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
4276   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
4277 
4278   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
4279   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
4280   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
4281 
4282   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
4283   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
4284   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
4285   auto One = MIRBuilder.buildConstant(S32, 1);
4286 
4287   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
4288   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
4289   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
4290   MIRBuilder.buildAdd(Dst, V, R);
4291 
4292   return Legalized;
4293 }
4294 
4295 LegalizerHelper::LegalizeResult
4296 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4297   Register Dst = MI.getOperand(0).getReg();
4298   Register Src = MI.getOperand(1).getReg();
4299   LLT DstTy = MRI.getType(Dst);
4300   LLT SrcTy = MRI.getType(Src);
4301 
4302   if (SrcTy == LLT::scalar(1)) {
4303     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
4304     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
4305     MIRBuilder.buildSelect(Dst, Src, True, False);
4306     MI.eraseFromParent();
4307     return Legalized;
4308   }
4309 
4310   if (SrcTy != LLT::scalar(64))
4311     return UnableToLegalize;
4312 
4313   if (DstTy == LLT::scalar(32)) {
4314     // TODO: SelectionDAG has several alternative expansions to port which may
4315     // be more reasonble depending on the available instructions. If a target
4316     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
4317     // intermediate type, this is probably worse.
4318     return lowerU64ToF32BitOps(MI);
4319   }
4320 
4321   return UnableToLegalize;
4322 }
4323 
4324 LegalizerHelper::LegalizeResult
4325 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4326   Register Dst = MI.getOperand(0).getReg();
4327   Register Src = MI.getOperand(1).getReg();
4328   LLT DstTy = MRI.getType(Dst);
4329   LLT SrcTy = MRI.getType(Src);
4330 
4331   const LLT S64 = LLT::scalar(64);
4332   const LLT S32 = LLT::scalar(32);
4333   const LLT S1 = LLT::scalar(1);
4334 
4335   if (SrcTy == S1) {
4336     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
4337     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
4338     MIRBuilder.buildSelect(Dst, Src, True, False);
4339     MI.eraseFromParent();
4340     return Legalized;
4341   }
4342 
4343   if (SrcTy != S64)
4344     return UnableToLegalize;
4345 
4346   if (DstTy == S32) {
4347     // signed cl2f(long l) {
4348     //   long s = l >> 63;
4349     //   float r = cul2f((l + s) ^ s);
4350     //   return s ? -r : r;
4351     // }
4352     Register L = Src;
4353     auto SignBit = MIRBuilder.buildConstant(S64, 63);
4354     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
4355 
4356     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
4357     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
4358     auto R = MIRBuilder.buildUITOFP(S32, Xor);
4359 
4360     auto RNeg = MIRBuilder.buildFNeg(S32, R);
4361     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
4362                                             MIRBuilder.buildConstant(S64, 0));
4363     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
4364     return Legalized;
4365   }
4366 
4367   return UnableToLegalize;
4368 }
4369 
4370 LegalizerHelper::LegalizeResult
4371 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4372   Register Dst = MI.getOperand(0).getReg();
4373   Register Src = MI.getOperand(1).getReg();
4374   LLT DstTy = MRI.getType(Dst);
4375   LLT SrcTy = MRI.getType(Src);
4376   const LLT S64 = LLT::scalar(64);
4377   const LLT S32 = LLT::scalar(32);
4378 
4379   if (SrcTy != S64 && SrcTy != S32)
4380     return UnableToLegalize;
4381   if (DstTy != S32 && DstTy != S64)
4382     return UnableToLegalize;
4383 
4384   // FPTOSI gives same result as FPTOUI for positive signed integers.
4385   // FPTOUI needs to deal with fp values that convert to unsigned integers
4386   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
4387 
4388   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
4389   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
4390                                                 : APFloat::IEEEdouble(),
4391                     APInt::getNullValue(SrcTy.getSizeInBits()));
4392   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
4393 
4394   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
4395 
4396   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
4397   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
4398   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
4399   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
4400   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
4401   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
4402   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
4403 
4404   const LLT S1 = LLT::scalar(1);
4405 
4406   MachineInstrBuilder FCMP =
4407       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
4408   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
4409 
4410   MI.eraseFromParent();
4411   return Legalized;
4412 }
4413 
4414 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {
4415   Register Dst = MI.getOperand(0).getReg();
4416   Register Src = MI.getOperand(1).getReg();
4417   LLT DstTy = MRI.getType(Dst);
4418   LLT SrcTy = MRI.getType(Src);
4419   const LLT S64 = LLT::scalar(64);
4420   const LLT S32 = LLT::scalar(32);
4421 
4422   // FIXME: Only f32 to i64 conversions are supported.
4423   if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)
4424     return UnableToLegalize;
4425 
4426   // Expand f32 -> i64 conversion
4427   // This algorithm comes from compiler-rt's implementation of fixsfdi:
4428   // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c
4429 
4430   unsigned SrcEltBits = SrcTy.getScalarSizeInBits();
4431 
4432   auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000);
4433   auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23);
4434 
4435   auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask);
4436   auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit);
4437 
4438   auto SignMask = MIRBuilder.buildConstant(SrcTy,
4439                                            APInt::getSignMask(SrcEltBits));
4440   auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask);
4441   auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1);
4442   auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit);
4443   Sign = MIRBuilder.buildSExt(DstTy, Sign);
4444 
4445   auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF);
4446   auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask);
4447   auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000);
4448 
4449   auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K);
4450   R = MIRBuilder.buildZExt(DstTy, R);
4451 
4452   auto Bias = MIRBuilder.buildConstant(SrcTy, 127);
4453   auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias);
4454   auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit);
4455   auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent);
4456 
4457   auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent);
4458   auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub);
4459 
4460   const LLT S1 = LLT::scalar(1);
4461   auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,
4462                                     S1, Exponent, ExponentLoBit);
4463 
4464   R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);
4465 
4466   auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign);
4467   auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign);
4468 
4469   auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0);
4470 
4471   auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT,
4472                                           S1, Exponent, ZeroSrcTy);
4473 
4474   auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0);
4475   MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret);
4476 
4477   MI.eraseFromParent();
4478   return Legalized;
4479 }
4480 
4481 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
4482 LegalizerHelper::LegalizeResult
4483 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
4484   Register Dst = MI.getOperand(0).getReg();
4485   Register Src = MI.getOperand(1).getReg();
4486 
4487   if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
4488     return UnableToLegalize;
4489 
4490   const unsigned ExpMask = 0x7ff;
4491   const unsigned ExpBiasf64 = 1023;
4492   const unsigned ExpBiasf16 = 15;
4493   const LLT S32 = LLT::scalar(32);
4494   const LLT S1 = LLT::scalar(1);
4495 
4496   auto Unmerge = MIRBuilder.buildUnmerge(S32, Src);
4497   Register U = Unmerge.getReg(0);
4498   Register UH = Unmerge.getReg(1);
4499 
4500   auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20));
4501 
4502   // Subtract the fp64 exponent bias (1023) to get the real exponent and
4503   // add the f16 bias (15) to get the biased exponent for the f16 format.
4504   E = MIRBuilder.buildAdd(
4505     S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16));
4506   E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));
4507 
4508   auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8));
4509   M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));
4510 
4511   auto MaskedSig = MIRBuilder.buildAnd(S32, UH,
4512                                        MIRBuilder.buildConstant(S32, 0x1ff));
4513   MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U);
4514 
4515   auto Zero = MIRBuilder.buildConstant(S32, 0);
4516   auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero);
4517   auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0);
4518   M = MIRBuilder.buildOr(S32, M, Lo40Set);
4519 
4520   // (M != 0 ? 0x0200 : 0) | 0x7c00;
4521   auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200);
4522   auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero);
4523   auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero);
4524 
4525   auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00);
4526   auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);
4527 
4528   // N = M | (E << 12);
4529   auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12));
4530   auto N = MIRBuilder.buildOr(S32, M, EShl12);
4531 
4532   // B = clamp(1-E, 0, 13);
4533   auto One = MIRBuilder.buildConstant(S32, 1);
4534   auto OneSubExp = MIRBuilder.buildSub(S32, One, E);
4535   auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero);
4536   B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13));
4537 
4538   auto SigSetHigh = MIRBuilder.buildOr(S32, M,
4539                                        MIRBuilder.buildConstant(S32, 0x1000));
4540 
4541   auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B);
4542   auto D0 = MIRBuilder.buildShl(S32, D, B);
4543 
4544   auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1,
4545                                              D0, SigSetHigh);
4546   auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh);
4547   D = MIRBuilder.buildOr(S32, D, D1);
4548 
4549   auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One);
4550   auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N);
4551 
4552   auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));
4553   V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2));
4554 
4555   auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3,
4556                                        MIRBuilder.buildConstant(S32, 3));
4557   auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3);
4558 
4559   auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3,
4560                                        MIRBuilder.buildConstant(S32, 5));
4561   auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5);
4562 
4563   V1 = MIRBuilder.buildOr(S32, V0, V1);
4564   V = MIRBuilder.buildAdd(S32, V, V1);
4565 
4566   auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,  S1,
4567                                        E, MIRBuilder.buildConstant(S32, 30));
4568   V = MIRBuilder.buildSelect(S32, CmpEGt30,
4569                              MIRBuilder.buildConstant(S32, 0x7c00), V);
4570 
4571   auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1,
4572                                          E, MIRBuilder.buildConstant(S32, 1039));
4573   V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V);
4574 
4575   // Extract the sign bit.
4576   auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16));
4577   Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));
4578 
4579   // Insert the sign bit
4580   V = MIRBuilder.buildOr(S32, Sign, V);
4581 
4582   MIRBuilder.buildTrunc(Dst, V);
4583   MI.eraseFromParent();
4584   return Legalized;
4585 }
4586 
4587 LegalizerHelper::LegalizeResult
4588 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4589   Register Dst = MI.getOperand(0).getReg();
4590   Register Src = MI.getOperand(1).getReg();
4591 
4592   LLT DstTy = MRI.getType(Dst);
4593   LLT SrcTy = MRI.getType(Src);
4594   const LLT S64 = LLT::scalar(64);
4595   const LLT S16 = LLT::scalar(16);
4596 
4597   if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64)
4598     return lowerFPTRUNC_F64_TO_F16(MI);
4599 
4600   return UnableToLegalize;
4601 }
4602 
4603 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4604   switch (Opc) {
4605   case TargetOpcode::G_SMIN:
4606     return CmpInst::ICMP_SLT;
4607   case TargetOpcode::G_SMAX:
4608     return CmpInst::ICMP_SGT;
4609   case TargetOpcode::G_UMIN:
4610     return CmpInst::ICMP_ULT;
4611   case TargetOpcode::G_UMAX:
4612     return CmpInst::ICMP_UGT;
4613   default:
4614     llvm_unreachable("not in integer min/max");
4615   }
4616 }
4617 
4618 LegalizerHelper::LegalizeResult
4619 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4620   Register Dst = MI.getOperand(0).getReg();
4621   Register Src0 = MI.getOperand(1).getReg();
4622   Register Src1 = MI.getOperand(2).getReg();
4623 
4624   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4625   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4626 
4627   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4628   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4629 
4630   MI.eraseFromParent();
4631   return Legalized;
4632 }
4633 
4634 LegalizerHelper::LegalizeResult
4635 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4636   Register Dst = MI.getOperand(0).getReg();
4637   Register Src0 = MI.getOperand(1).getReg();
4638   Register Src1 = MI.getOperand(2).getReg();
4639 
4640   const LLT Src0Ty = MRI.getType(Src0);
4641   const LLT Src1Ty = MRI.getType(Src1);
4642 
4643   const int Src0Size = Src0Ty.getScalarSizeInBits();
4644   const int Src1Size = Src1Ty.getScalarSizeInBits();
4645 
4646   auto SignBitMask = MIRBuilder.buildConstant(
4647     Src0Ty, APInt::getSignMask(Src0Size));
4648 
4649   auto NotSignBitMask = MIRBuilder.buildConstant(
4650     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4651 
4652   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4653   MachineInstr *Or;
4654 
4655   if (Src0Ty == Src1Ty) {
4656     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4657     Or = MIRBuilder.buildOr(Dst, And0, And1);
4658   } else if (Src0Size > Src1Size) {
4659     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4660     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4661     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4662     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4663     Or = MIRBuilder.buildOr(Dst, And0, And1);
4664   } else {
4665     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4666     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4667     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4668     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4669     Or = MIRBuilder.buildOr(Dst, And0, And1);
4670   }
4671 
4672   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4673   // constants are a nan and -0.0, but the final result should preserve
4674   // everything.
4675   if (unsigned Flags = MI.getFlags())
4676     Or->setFlags(Flags);
4677 
4678   MI.eraseFromParent();
4679   return Legalized;
4680 }
4681 
4682 LegalizerHelper::LegalizeResult
4683 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4684   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4685     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4686 
4687   Register Dst = MI.getOperand(0).getReg();
4688   Register Src0 = MI.getOperand(1).getReg();
4689   Register Src1 = MI.getOperand(2).getReg();
4690   LLT Ty = MRI.getType(Dst);
4691 
4692   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4693     // Insert canonicalizes if it's possible we need to quiet to get correct
4694     // sNaN behavior.
4695 
4696     // Note this must be done here, and not as an optimization combine in the
4697     // absence of a dedicate quiet-snan instruction as we're using an
4698     // omni-purpose G_FCANONICALIZE.
4699     if (!isKnownNeverSNaN(Src0, MRI))
4700       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4701 
4702     if (!isKnownNeverSNaN(Src1, MRI))
4703       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4704   }
4705 
4706   // If there are no nans, it's safe to simply replace this with the non-IEEE
4707   // version.
4708   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4709   MI.eraseFromParent();
4710   return Legalized;
4711 }
4712 
4713 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4714   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4715   Register DstReg = MI.getOperand(0).getReg();
4716   LLT Ty = MRI.getType(DstReg);
4717   unsigned Flags = MI.getFlags();
4718 
4719   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4720                                   Flags);
4721   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4722   MI.eraseFromParent();
4723   return Legalized;
4724 }
4725 
4726 LegalizerHelper::LegalizeResult
4727 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
4728   Register DstReg = MI.getOperand(0).getReg();
4729   Register SrcReg = MI.getOperand(1).getReg();
4730   unsigned Flags = MI.getFlags();
4731   LLT Ty = MRI.getType(DstReg);
4732   const LLT CondTy = Ty.changeElementSize(1);
4733 
4734   // result = trunc(src);
4735   // if (src < 0.0 && src != result)
4736   //   result += -1.0.
4737 
4738   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
4739   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
4740 
4741   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
4742                                   SrcReg, Zero, Flags);
4743   auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy,
4744                                       SrcReg, Trunc, Flags);
4745   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
4746   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
4747 
4748   MIRBuilder.buildFAdd(DstReg, Trunc, AddVal);
4749   MI.eraseFromParent();
4750   return Legalized;
4751 }
4752 
4753 LegalizerHelper::LegalizeResult
4754 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4755   const unsigned NumDst = MI.getNumOperands() - 1;
4756   const Register SrcReg = MI.getOperand(NumDst).getReg();
4757   LLT SrcTy = MRI.getType(SrcReg);
4758 
4759   Register Dst0Reg = MI.getOperand(0).getReg();
4760   LLT DstTy = MRI.getType(Dst0Reg);
4761 
4762 
4763   // Expand scalarizing unmerge as bitcast to integer and shift.
4764   if (!DstTy.isVector() && SrcTy.isVector() &&
4765       SrcTy.getElementType() == DstTy) {
4766     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4767     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4768 
4769     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4770 
4771     const unsigned DstSize = DstTy.getSizeInBits();
4772     unsigned Offset = DstSize;
4773     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4774       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4775       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4776       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4777     }
4778 
4779     MI.eraseFromParent();
4780     return Legalized;
4781   }
4782 
4783   return UnableToLegalize;
4784 }
4785 
4786 LegalizerHelper::LegalizeResult
4787 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4788   Register DstReg = MI.getOperand(0).getReg();
4789   Register Src0Reg = MI.getOperand(1).getReg();
4790   Register Src1Reg = MI.getOperand(2).getReg();
4791   LLT Src0Ty = MRI.getType(Src0Reg);
4792   LLT DstTy = MRI.getType(DstReg);
4793   LLT IdxTy = LLT::scalar(32);
4794 
4795   ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
4796 
4797   if (DstTy.isScalar()) {
4798     if (Src0Ty.isVector())
4799       return UnableToLegalize;
4800 
4801     // This is just a SELECT.
4802     assert(Mask.size() == 1 && "Expected a single mask element");
4803     Register Val;
4804     if (Mask[0] < 0 || Mask[0] > 1)
4805       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4806     else
4807       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4808     MIRBuilder.buildCopy(DstReg, Val);
4809     MI.eraseFromParent();
4810     return Legalized;
4811   }
4812 
4813   Register Undef;
4814   SmallVector<Register, 32> BuildVec;
4815   LLT EltTy = DstTy.getElementType();
4816 
4817   for (int Idx : Mask) {
4818     if (Idx < 0) {
4819       if (!Undef.isValid())
4820         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4821       BuildVec.push_back(Undef);
4822       continue;
4823     }
4824 
4825     if (Src0Ty.isScalar()) {
4826       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4827     } else {
4828       int NumElts = Src0Ty.getNumElements();
4829       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4830       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4831       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4832       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4833       BuildVec.push_back(Extract.getReg(0));
4834     }
4835   }
4836 
4837   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4838   MI.eraseFromParent();
4839   return Legalized;
4840 }
4841 
4842 LegalizerHelper::LegalizeResult
4843 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4844   Register Dst = MI.getOperand(0).getReg();
4845   Register AllocSize = MI.getOperand(1).getReg();
4846   unsigned Align = MI.getOperand(2).getImm();
4847 
4848   const auto &MF = *MI.getMF();
4849   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4850 
4851   LLT PtrTy = MRI.getType(Dst);
4852   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4853 
4854   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4855   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4856   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4857 
4858   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4859   // have to generate an extra instruction to negate the alloc and then use
4860   // G_PTR_ADD to add the negative offset.
4861   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4862   if (Align) {
4863     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4864     AlignMask.negate();
4865     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4866     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4867   }
4868 
4869   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4870   MIRBuilder.buildCopy(SPReg, SPTmp);
4871   MIRBuilder.buildCopy(Dst, SPTmp);
4872 
4873   MI.eraseFromParent();
4874   return Legalized;
4875 }
4876 
4877 LegalizerHelper::LegalizeResult
4878 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4879   Register Dst = MI.getOperand(0).getReg();
4880   Register Src = MI.getOperand(1).getReg();
4881   unsigned Offset = MI.getOperand(2).getImm();
4882 
4883   LLT DstTy = MRI.getType(Dst);
4884   LLT SrcTy = MRI.getType(Src);
4885 
4886   if (DstTy.isScalar() &&
4887       (SrcTy.isScalar() ||
4888        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4889     LLT SrcIntTy = SrcTy;
4890     if (!SrcTy.isScalar()) {
4891       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4892       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4893     }
4894 
4895     if (Offset == 0)
4896       MIRBuilder.buildTrunc(Dst, Src);
4897     else {
4898       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4899       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4900       MIRBuilder.buildTrunc(Dst, Shr);
4901     }
4902 
4903     MI.eraseFromParent();
4904     return Legalized;
4905   }
4906 
4907   return UnableToLegalize;
4908 }
4909 
4910 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4911   Register Dst = MI.getOperand(0).getReg();
4912   Register Src = MI.getOperand(1).getReg();
4913   Register InsertSrc = MI.getOperand(2).getReg();
4914   uint64_t Offset = MI.getOperand(3).getImm();
4915 
4916   LLT DstTy = MRI.getType(Src);
4917   LLT InsertTy = MRI.getType(InsertSrc);
4918 
4919   if (InsertTy.isScalar() &&
4920       (DstTy.isScalar() ||
4921        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4922     LLT IntDstTy = DstTy;
4923     if (!DstTy.isScalar()) {
4924       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4925       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4926     }
4927 
4928     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4929     if (Offset != 0) {
4930       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4931       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4932     }
4933 
4934     APInt MaskVal = APInt::getBitsSetWithWrap(DstTy.getSizeInBits(),
4935                                               Offset + InsertTy.getSizeInBits(),
4936                                               Offset);
4937 
4938     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4939     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4940     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4941 
4942     MIRBuilder.buildBitcast(Dst, Or);
4943     MI.eraseFromParent();
4944     return Legalized;
4945   }
4946 
4947   return UnableToLegalize;
4948 }
4949 
4950 LegalizerHelper::LegalizeResult
4951 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4952   Register Dst0 = MI.getOperand(0).getReg();
4953   Register Dst1 = MI.getOperand(1).getReg();
4954   Register LHS = MI.getOperand(2).getReg();
4955   Register RHS = MI.getOperand(3).getReg();
4956   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4957 
4958   LLT Ty = MRI.getType(Dst0);
4959   LLT BoolTy = MRI.getType(Dst1);
4960 
4961   if (IsAdd)
4962     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4963   else
4964     MIRBuilder.buildSub(Dst0, LHS, RHS);
4965 
4966   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4967 
4968   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4969 
4970   // For an addition, the result should be less than one of the operands (LHS)
4971   // if and only if the other operand (RHS) is negative, otherwise there will
4972   // be overflow.
4973   // For a subtraction, the result should be less than one of the operands
4974   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4975   // otherwise there will be overflow.
4976   auto ResultLowerThanLHS =
4977       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4978   auto ConditionRHS = MIRBuilder.buildICmp(
4979       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4980 
4981   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4982   MI.eraseFromParent();
4983   return Legalized;
4984 }
4985 
4986 LegalizerHelper::LegalizeResult
4987 LegalizerHelper::lowerBswap(MachineInstr &MI) {
4988   Register Dst = MI.getOperand(0).getReg();
4989   Register Src = MI.getOperand(1).getReg();
4990   const LLT Ty = MRI.getType(Src);
4991   unsigned SizeInBytes = Ty.getSizeInBytes();
4992   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
4993 
4994   // Swap most and least significant byte, set remaining bytes in Res to zero.
4995   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
4996   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
4997   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4998   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
4999 
5000   // Set i-th high/low byte in Res to i-th low/high byte from Src.
5001   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
5002     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
5003     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
5004     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
5005     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
5006     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
5007     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
5008     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
5009     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
5010     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
5011     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
5012     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
5013     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
5014   }
5015   Res.getInstr()->getOperand(0).setReg(Dst);
5016 
5017   MI.eraseFromParent();
5018   return Legalized;
5019 }
5020 
5021 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
5022 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
5023                                  MachineInstrBuilder Src, APInt Mask) {
5024   const LLT Ty = Dst.getLLTTy(*B.getMRI());
5025   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
5026   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
5027   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
5028   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
5029   return B.buildOr(Dst, LHS, RHS);
5030 }
5031 
5032 LegalizerHelper::LegalizeResult
5033 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
5034   Register Dst = MI.getOperand(0).getReg();
5035   Register Src = MI.getOperand(1).getReg();
5036   const LLT Ty = MRI.getType(Src);
5037   unsigned Size = Ty.getSizeInBits();
5038 
5039   MachineInstrBuilder BSWAP =
5040       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
5041 
5042   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
5043   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
5044   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
5045   MachineInstrBuilder Swap4 =
5046       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
5047 
5048   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
5049   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
5050   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
5051   MachineInstrBuilder Swap2 =
5052       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
5053 
5054   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
5055   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
5056   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
5057   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
5058 
5059   MI.eraseFromParent();
5060   return Legalized;
5061 }
5062 
5063 LegalizerHelper::LegalizeResult
5064 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
5065   MachineFunction &MF = MIRBuilder.getMF();
5066   const TargetSubtargetInfo &STI = MF.getSubtarget();
5067   const TargetLowering *TLI = STI.getTargetLowering();
5068 
5069   bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER;
5070   int NameOpIdx = IsRead ? 1 : 0;
5071   int ValRegIndex = IsRead ? 0 : 1;
5072 
5073   Register ValReg = MI.getOperand(ValRegIndex).getReg();
5074   const LLT Ty = MRI.getType(ValReg);
5075   const MDString *RegStr = cast<MDString>(
5076     cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));
5077 
5078   Register PhysReg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
5079   if (!PhysReg.isValid())
5080     return UnableToLegalize;
5081 
5082   if (IsRead)
5083     MIRBuilder.buildCopy(ValReg, PhysReg);
5084   else
5085     MIRBuilder.buildCopy(PhysReg, ValReg);
5086 
5087   MI.eraseFromParent();
5088   return Legalized;
5089 }
5090