1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 #define DEBUG_TYPE "legalizer" 30 31 using namespace llvm; 32 using namespace LegalizeActions; 33 using namespace MIPatternMatch; 34 35 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 36 /// 37 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 38 /// with any leftover piece as type \p LeftoverTy 39 /// 40 /// Returns -1 in the first element of the pair if the breakdown is not 41 /// satisfiable. 42 static std::pair<int, int> 43 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 44 assert(!LeftoverTy.isValid() && "this is an out argument"); 45 46 unsigned Size = OrigTy.getSizeInBits(); 47 unsigned NarrowSize = NarrowTy.getSizeInBits(); 48 unsigned NumParts = Size / NarrowSize; 49 unsigned LeftoverSize = Size - NumParts * NarrowSize; 50 assert(Size > NarrowSize); 51 52 if (LeftoverSize == 0) 53 return {NumParts, 0}; 54 55 if (NarrowTy.isVector()) { 56 unsigned EltSize = OrigTy.getScalarSizeInBits(); 57 if (LeftoverSize % EltSize != 0) 58 return {-1, -1}; 59 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 60 } else { 61 LeftoverTy = LLT::scalar(LeftoverSize); 62 } 63 64 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 65 return std::make_pair(NumParts, NumLeftover); 66 } 67 68 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 69 70 if (!Ty.isScalar()) 71 return nullptr; 72 73 switch (Ty.getSizeInBits()) { 74 case 16: 75 return Type::getHalfTy(Ctx); 76 case 32: 77 return Type::getFloatTy(Ctx); 78 case 64: 79 return Type::getDoubleTy(Ctx); 80 case 80: 81 return Type::getX86_FP80Ty(Ctx); 82 case 128: 83 return Type::getFP128Ty(Ctx); 84 default: 85 return nullptr; 86 } 87 } 88 89 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 90 GISelChangeObserver &Observer, 91 MachineIRBuilder &Builder) 92 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 93 LI(*MF.getSubtarget().getLegalizerInfo()), 94 TLI(*MF.getSubtarget().getTargetLowering()) { } 95 96 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 97 GISelChangeObserver &Observer, 98 MachineIRBuilder &B) 99 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 100 TLI(*MF.getSubtarget().getTargetLowering()) { } 101 102 LegalizerHelper::LegalizeResult 103 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { 104 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 105 106 MIRBuilder.setInstrAndDebugLoc(MI); 107 108 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 109 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 110 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 111 auto Step = LI.getAction(MI, MRI); 112 switch (Step.Action) { 113 case Legal: 114 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 115 return AlreadyLegal; 116 case Libcall: 117 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 118 return libcall(MI); 119 case NarrowScalar: 120 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 121 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 122 case WidenScalar: 123 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 124 return widenScalar(MI, Step.TypeIdx, Step.NewType); 125 case Bitcast: 126 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 127 return bitcast(MI, Step.TypeIdx, Step.NewType); 128 case Lower: 129 LLVM_DEBUG(dbgs() << ".. Lower\n"); 130 return lower(MI, Step.TypeIdx, Step.NewType); 131 case FewerElements: 132 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 133 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 134 case MoreElements: 135 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 136 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 137 case Custom: 138 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 139 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 140 default: 141 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 142 return UnableToLegalize; 143 } 144 } 145 146 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 147 SmallVectorImpl<Register> &VRegs) { 148 for (int i = 0; i < NumParts; ++i) 149 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 150 MIRBuilder.buildUnmerge(VRegs, Reg); 151 } 152 153 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 154 LLT MainTy, LLT &LeftoverTy, 155 SmallVectorImpl<Register> &VRegs, 156 SmallVectorImpl<Register> &LeftoverRegs) { 157 assert(!LeftoverTy.isValid() && "this is an out argument"); 158 159 unsigned RegSize = RegTy.getSizeInBits(); 160 unsigned MainSize = MainTy.getSizeInBits(); 161 unsigned NumParts = RegSize / MainSize; 162 unsigned LeftoverSize = RegSize - NumParts * MainSize; 163 164 // Use an unmerge when possible. 165 if (LeftoverSize == 0) { 166 for (unsigned I = 0; I < NumParts; ++I) 167 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 168 MIRBuilder.buildUnmerge(VRegs, Reg); 169 return true; 170 } 171 172 if (MainTy.isVector()) { 173 unsigned EltSize = MainTy.getScalarSizeInBits(); 174 if (LeftoverSize % EltSize != 0) 175 return false; 176 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 177 } else { 178 LeftoverTy = LLT::scalar(LeftoverSize); 179 } 180 181 // For irregular sizes, extract the individual parts. 182 for (unsigned I = 0; I != NumParts; ++I) { 183 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 184 VRegs.push_back(NewReg); 185 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 186 } 187 188 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 189 Offset += LeftoverSize) { 190 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 191 LeftoverRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, Offset); 193 } 194 195 return true; 196 } 197 198 void LegalizerHelper::insertParts(Register DstReg, 199 LLT ResultTy, LLT PartTy, 200 ArrayRef<Register> PartRegs, 201 LLT LeftoverTy, 202 ArrayRef<Register> LeftoverRegs) { 203 if (!LeftoverTy.isValid()) { 204 assert(LeftoverRegs.empty()); 205 206 if (!ResultTy.isVector()) { 207 MIRBuilder.buildMerge(DstReg, PartRegs); 208 return; 209 } 210 211 if (PartTy.isVector()) 212 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 213 else 214 MIRBuilder.buildBuildVector(DstReg, PartRegs); 215 return; 216 } 217 218 unsigned PartSize = PartTy.getSizeInBits(); 219 unsigned LeftoverPartSize = LeftoverTy.getSizeInBits(); 220 221 Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy); 222 MIRBuilder.buildUndef(CurResultReg); 223 224 unsigned Offset = 0; 225 for (Register PartReg : PartRegs) { 226 Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy); 227 MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset); 228 CurResultReg = NewResultReg; 229 Offset += PartSize; 230 } 231 232 for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) { 233 // Use the original output register for the final insert to avoid a copy. 234 Register NewResultReg = (I + 1 == E) ? 235 DstReg : MRI.createGenericVirtualRegister(ResultTy); 236 237 MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset); 238 CurResultReg = NewResultReg; 239 Offset += LeftoverPartSize; 240 } 241 } 242 243 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 244 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 245 const MachineInstr &MI) { 246 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 247 248 const int StartIdx = Regs.size(); 249 const int NumResults = MI.getNumOperands() - 1; 250 Regs.resize(Regs.size() + NumResults); 251 for (int I = 0; I != NumResults; ++I) 252 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 253 } 254 255 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 256 LLT GCDTy, Register SrcReg) { 257 LLT SrcTy = MRI.getType(SrcReg); 258 if (SrcTy == GCDTy) { 259 // If the source already evenly divides the result type, we don't need to do 260 // anything. 261 Parts.push_back(SrcReg); 262 } else { 263 // Need to split into common type sized pieces. 264 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 265 getUnmergeResults(Parts, *Unmerge); 266 } 267 } 268 269 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 270 LLT NarrowTy, Register SrcReg) { 271 LLT SrcTy = MRI.getType(SrcReg); 272 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 273 extractGCDType(Parts, GCDTy, SrcReg); 274 return GCDTy; 275 } 276 277 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 278 SmallVectorImpl<Register> &VRegs, 279 unsigned PadStrategy) { 280 LLT LCMTy = getLCMType(DstTy, NarrowTy); 281 282 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 283 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 284 int NumOrigSrc = VRegs.size(); 285 286 Register PadReg; 287 288 // Get a value we can use to pad the source value if the sources won't evenly 289 // cover the result type. 290 if (NumOrigSrc < NumParts * NumSubParts) { 291 if (PadStrategy == TargetOpcode::G_ZEXT) 292 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 293 else if (PadStrategy == TargetOpcode::G_ANYEXT) 294 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 295 else { 296 assert(PadStrategy == TargetOpcode::G_SEXT); 297 298 // Shift the sign bit of the low register through the high register. 299 auto ShiftAmt = 300 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 301 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 302 } 303 } 304 305 // Registers for the final merge to be produced. 306 SmallVector<Register, 4> Remerge(NumParts); 307 308 // Registers needed for intermediate merges, which will be merged into a 309 // source for Remerge. 310 SmallVector<Register, 4> SubMerge(NumSubParts); 311 312 // Once we've fully read off the end of the original source bits, we can reuse 313 // the same high bits for remaining padding elements. 314 Register AllPadReg; 315 316 // Build merges to the LCM type to cover the original result type. 317 for (int I = 0; I != NumParts; ++I) { 318 bool AllMergePartsArePadding = true; 319 320 // Build the requested merges to the requested type. 321 for (int J = 0; J != NumSubParts; ++J) { 322 int Idx = I * NumSubParts + J; 323 if (Idx >= NumOrigSrc) { 324 SubMerge[J] = PadReg; 325 continue; 326 } 327 328 SubMerge[J] = VRegs[Idx]; 329 330 // There are meaningful bits here we can't reuse later. 331 AllMergePartsArePadding = false; 332 } 333 334 // If we've filled up a complete piece with padding bits, we can directly 335 // emit the natural sized constant if applicable, rather than a merge of 336 // smaller constants. 337 if (AllMergePartsArePadding && !AllPadReg) { 338 if (PadStrategy == TargetOpcode::G_ANYEXT) 339 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 340 else if (PadStrategy == TargetOpcode::G_ZEXT) 341 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 342 343 // If this is a sign extension, we can't materialize a trivial constant 344 // with the right type and have to produce a merge. 345 } 346 347 if (AllPadReg) { 348 // Avoid creating additional instructions if we're just adding additional 349 // copies of padding bits. 350 Remerge[I] = AllPadReg; 351 continue; 352 } 353 354 if (NumSubParts == 1) 355 Remerge[I] = SubMerge[0]; 356 else 357 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 358 359 // In the sign extend padding case, re-use the first all-signbit merge. 360 if (AllMergePartsArePadding && !AllPadReg) 361 AllPadReg = Remerge[I]; 362 } 363 364 VRegs = std::move(Remerge); 365 return LCMTy; 366 } 367 368 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 369 ArrayRef<Register> RemergeRegs) { 370 LLT DstTy = MRI.getType(DstReg); 371 372 // Create the merge to the widened source, and extract the relevant bits into 373 // the result. 374 375 if (DstTy == LCMTy) { 376 MIRBuilder.buildMerge(DstReg, RemergeRegs); 377 return; 378 } 379 380 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 381 if (DstTy.isScalar() && LCMTy.isScalar()) { 382 MIRBuilder.buildTrunc(DstReg, Remerge); 383 return; 384 } 385 386 if (LCMTy.isVector()) { 387 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 388 SmallVector<Register, 8> UnmergeDefs(NumDefs); 389 UnmergeDefs[0] = DstReg; 390 for (unsigned I = 1; I != NumDefs; ++I) 391 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 392 393 MIRBuilder.buildUnmerge(UnmergeDefs, 394 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 395 return; 396 } 397 398 llvm_unreachable("unhandled case"); 399 } 400 401 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 402 #define RTLIBCASE_INT(LibcallPrefix) \ 403 do { \ 404 switch (Size) { \ 405 case 32: \ 406 return RTLIB::LibcallPrefix##32; \ 407 case 64: \ 408 return RTLIB::LibcallPrefix##64; \ 409 case 128: \ 410 return RTLIB::LibcallPrefix##128; \ 411 default: \ 412 llvm_unreachable("unexpected size"); \ 413 } \ 414 } while (0) 415 416 #define RTLIBCASE(LibcallPrefix) \ 417 do { \ 418 switch (Size) { \ 419 case 32: \ 420 return RTLIB::LibcallPrefix##32; \ 421 case 64: \ 422 return RTLIB::LibcallPrefix##64; \ 423 case 80: \ 424 return RTLIB::LibcallPrefix##80; \ 425 case 128: \ 426 return RTLIB::LibcallPrefix##128; \ 427 default: \ 428 llvm_unreachable("unexpected size"); \ 429 } \ 430 } while (0) 431 432 switch (Opcode) { 433 case TargetOpcode::G_SDIV: 434 RTLIBCASE_INT(SDIV_I); 435 case TargetOpcode::G_UDIV: 436 RTLIBCASE_INT(UDIV_I); 437 case TargetOpcode::G_SREM: 438 RTLIBCASE_INT(SREM_I); 439 case TargetOpcode::G_UREM: 440 RTLIBCASE_INT(UREM_I); 441 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 442 RTLIBCASE_INT(CTLZ_I); 443 case TargetOpcode::G_FADD: 444 RTLIBCASE(ADD_F); 445 case TargetOpcode::G_FSUB: 446 RTLIBCASE(SUB_F); 447 case TargetOpcode::G_FMUL: 448 RTLIBCASE(MUL_F); 449 case TargetOpcode::G_FDIV: 450 RTLIBCASE(DIV_F); 451 case TargetOpcode::G_FEXP: 452 RTLIBCASE(EXP_F); 453 case TargetOpcode::G_FEXP2: 454 RTLIBCASE(EXP2_F); 455 case TargetOpcode::G_FREM: 456 RTLIBCASE(REM_F); 457 case TargetOpcode::G_FPOW: 458 RTLIBCASE(POW_F); 459 case TargetOpcode::G_FMA: 460 RTLIBCASE(FMA_F); 461 case TargetOpcode::G_FSIN: 462 RTLIBCASE(SIN_F); 463 case TargetOpcode::G_FCOS: 464 RTLIBCASE(COS_F); 465 case TargetOpcode::G_FLOG10: 466 RTLIBCASE(LOG10_F); 467 case TargetOpcode::G_FLOG: 468 RTLIBCASE(LOG_F); 469 case TargetOpcode::G_FLOG2: 470 RTLIBCASE(LOG2_F); 471 case TargetOpcode::G_FCEIL: 472 RTLIBCASE(CEIL_F); 473 case TargetOpcode::G_FFLOOR: 474 RTLIBCASE(FLOOR_F); 475 case TargetOpcode::G_FMINNUM: 476 RTLIBCASE(FMIN_F); 477 case TargetOpcode::G_FMAXNUM: 478 RTLIBCASE(FMAX_F); 479 case TargetOpcode::G_FSQRT: 480 RTLIBCASE(SQRT_F); 481 case TargetOpcode::G_FRINT: 482 RTLIBCASE(RINT_F); 483 case TargetOpcode::G_FNEARBYINT: 484 RTLIBCASE(NEARBYINT_F); 485 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 486 RTLIBCASE(ROUNDEVEN_F); 487 } 488 llvm_unreachable("Unknown libcall function"); 489 } 490 491 /// True if an instruction is in tail position in its caller. Intended for 492 /// legalizing libcalls as tail calls when possible. 493 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 494 MachineInstr &MI) { 495 MachineBasicBlock &MBB = *MI.getParent(); 496 const Function &F = MBB.getParent()->getFunction(); 497 498 // Conservatively require the attributes of the call to match those of 499 // the return. Ignore NoAlias and NonNull because they don't affect the 500 // call sequence. 501 AttributeList CallerAttrs = F.getAttributes(); 502 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 503 .removeAttribute(Attribute::NoAlias) 504 .removeAttribute(Attribute::NonNull) 505 .hasAttributes()) 506 return false; 507 508 // It's not safe to eliminate the sign / zero extension of the return value. 509 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 510 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 511 return false; 512 513 // Only tail call if the following instruction is a standard return. 514 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 515 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 516 return false; 517 518 return true; 519 } 520 521 LegalizerHelper::LegalizeResult 522 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 523 const CallLowering::ArgInfo &Result, 524 ArrayRef<CallLowering::ArgInfo> Args, 525 const CallingConv::ID CC) { 526 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 527 528 CallLowering::CallLoweringInfo Info; 529 Info.CallConv = CC; 530 Info.Callee = MachineOperand::CreateES(Name); 531 Info.OrigRet = Result; 532 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 533 if (!CLI.lowerCall(MIRBuilder, Info)) 534 return LegalizerHelper::UnableToLegalize; 535 536 return LegalizerHelper::Legalized; 537 } 538 539 LegalizerHelper::LegalizeResult 540 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 541 const CallLowering::ArgInfo &Result, 542 ArrayRef<CallLowering::ArgInfo> Args) { 543 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 544 const char *Name = TLI.getLibcallName(Libcall); 545 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 546 return createLibcall(MIRBuilder, Name, Result, Args, CC); 547 } 548 549 // Useful for libcalls where all operands have the same type. 550 static LegalizerHelper::LegalizeResult 551 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 552 Type *OpType) { 553 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 554 555 SmallVector<CallLowering::ArgInfo, 3> Args; 556 for (unsigned i = 1; i < MI.getNumOperands(); i++) 557 Args.push_back({MI.getOperand(i).getReg(), OpType}); 558 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, 559 Args); 560 } 561 562 LegalizerHelper::LegalizeResult 563 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 564 MachineInstr &MI) { 565 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 566 567 SmallVector<CallLowering::ArgInfo, 3> Args; 568 // Add all the args, except for the last which is an imm denoting 'tail'. 569 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 570 Register Reg = MI.getOperand(i).getReg(); 571 572 // Need derive an IR type for call lowering. 573 LLT OpLLT = MRI.getType(Reg); 574 Type *OpTy = nullptr; 575 if (OpLLT.isPointer()) 576 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 577 else 578 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 579 Args.push_back({Reg, OpTy}); 580 } 581 582 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 583 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 584 RTLIB::Libcall RTLibcall; 585 switch (MI.getOpcode()) { 586 case TargetOpcode::G_MEMCPY: 587 RTLibcall = RTLIB::MEMCPY; 588 break; 589 case TargetOpcode::G_MEMMOVE: 590 RTLibcall = RTLIB::MEMMOVE; 591 break; 592 case TargetOpcode::G_MEMSET: 593 RTLibcall = RTLIB::MEMSET; 594 break; 595 default: 596 return LegalizerHelper::UnableToLegalize; 597 } 598 const char *Name = TLI.getLibcallName(RTLibcall); 599 600 CallLowering::CallLoweringInfo Info; 601 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 602 Info.Callee = MachineOperand::CreateES(Name); 603 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); 604 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 605 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 606 607 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 608 if (!CLI.lowerCall(MIRBuilder, Info)) 609 return LegalizerHelper::UnableToLegalize; 610 611 if (Info.LoweredTailCall) { 612 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 613 // We must have a return following the call (or debug insts) to get past 614 // isLibCallInTailPosition. 615 do { 616 MachineInstr *Next = MI.getNextNode(); 617 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 618 "Expected instr following MI to be return or debug inst?"); 619 // We lowered a tail call, so the call is now the return from the block. 620 // Delete the old return. 621 Next->eraseFromParent(); 622 } while (MI.getNextNode()); 623 } 624 625 return LegalizerHelper::Legalized; 626 } 627 628 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 629 Type *FromType) { 630 auto ToMVT = MVT::getVT(ToType); 631 auto FromMVT = MVT::getVT(FromType); 632 633 switch (Opcode) { 634 case TargetOpcode::G_FPEXT: 635 return RTLIB::getFPEXT(FromMVT, ToMVT); 636 case TargetOpcode::G_FPTRUNC: 637 return RTLIB::getFPROUND(FromMVT, ToMVT); 638 case TargetOpcode::G_FPTOSI: 639 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 640 case TargetOpcode::G_FPTOUI: 641 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 642 case TargetOpcode::G_SITOFP: 643 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 644 case TargetOpcode::G_UITOFP: 645 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 646 } 647 llvm_unreachable("Unsupported libcall function"); 648 } 649 650 static LegalizerHelper::LegalizeResult 651 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 652 Type *FromType) { 653 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 654 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, 655 {{MI.getOperand(1).getReg(), FromType}}); 656 } 657 658 LegalizerHelper::LegalizeResult 659 LegalizerHelper::libcall(MachineInstr &MI) { 660 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 661 unsigned Size = LLTy.getSizeInBits(); 662 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 663 664 switch (MI.getOpcode()) { 665 default: 666 return UnableToLegalize; 667 case TargetOpcode::G_SDIV: 668 case TargetOpcode::G_UDIV: 669 case TargetOpcode::G_SREM: 670 case TargetOpcode::G_UREM: 671 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 672 Type *HLTy = IntegerType::get(Ctx, Size); 673 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 674 if (Status != Legalized) 675 return Status; 676 break; 677 } 678 case TargetOpcode::G_FADD: 679 case TargetOpcode::G_FSUB: 680 case TargetOpcode::G_FMUL: 681 case TargetOpcode::G_FDIV: 682 case TargetOpcode::G_FMA: 683 case TargetOpcode::G_FPOW: 684 case TargetOpcode::G_FREM: 685 case TargetOpcode::G_FCOS: 686 case TargetOpcode::G_FSIN: 687 case TargetOpcode::G_FLOG10: 688 case TargetOpcode::G_FLOG: 689 case TargetOpcode::G_FLOG2: 690 case TargetOpcode::G_FEXP: 691 case TargetOpcode::G_FEXP2: 692 case TargetOpcode::G_FCEIL: 693 case TargetOpcode::G_FFLOOR: 694 case TargetOpcode::G_FMINNUM: 695 case TargetOpcode::G_FMAXNUM: 696 case TargetOpcode::G_FSQRT: 697 case TargetOpcode::G_FRINT: 698 case TargetOpcode::G_FNEARBYINT: 699 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 700 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 701 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 702 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 703 return UnableToLegalize; 704 } 705 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 706 if (Status != Legalized) 707 return Status; 708 break; 709 } 710 case TargetOpcode::G_FPEXT: 711 case TargetOpcode::G_FPTRUNC: { 712 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 713 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 714 if (!FromTy || !ToTy) 715 return UnableToLegalize; 716 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPTOSI: 722 case TargetOpcode::G_FPTOUI: { 723 // FIXME: Support other types 724 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 725 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 726 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 727 return UnableToLegalize; 728 LegalizeResult Status = conversionLibcall( 729 MI, MIRBuilder, 730 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 731 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 732 if (Status != Legalized) 733 return Status; 734 break; 735 } 736 case TargetOpcode::G_SITOFP: 737 case TargetOpcode::G_UITOFP: { 738 // FIXME: Support other types 739 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 740 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 741 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 742 return UnableToLegalize; 743 LegalizeResult Status = conversionLibcall( 744 MI, MIRBuilder, 745 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 746 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 747 if (Status != Legalized) 748 return Status; 749 break; 750 } 751 case TargetOpcode::G_MEMCPY: 752 case TargetOpcode::G_MEMMOVE: 753 case TargetOpcode::G_MEMSET: { 754 LegalizeResult Result = createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI); 755 MI.eraseFromParent(); 756 return Result; 757 } 758 } 759 760 MI.eraseFromParent(); 761 return Legalized; 762 } 763 764 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 765 unsigned TypeIdx, 766 LLT NarrowTy) { 767 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 768 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 769 770 switch (MI.getOpcode()) { 771 default: 772 return UnableToLegalize; 773 case TargetOpcode::G_IMPLICIT_DEF: { 774 Register DstReg = MI.getOperand(0).getReg(); 775 LLT DstTy = MRI.getType(DstReg); 776 777 // If SizeOp0 is not an exact multiple of NarrowSize, emit 778 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 779 // FIXME: Although this would also be legal for the general case, it causes 780 // a lot of regressions in the emitted code (superfluous COPYs, artifact 781 // combines not being hit). This seems to be a problem related to the 782 // artifact combiner. 783 if (SizeOp0 % NarrowSize != 0) { 784 LLT ImplicitTy = NarrowTy; 785 if (DstTy.isVector()) 786 ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy); 787 788 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 789 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 790 791 MI.eraseFromParent(); 792 return Legalized; 793 } 794 795 int NumParts = SizeOp0 / NarrowSize; 796 797 SmallVector<Register, 2> DstRegs; 798 for (int i = 0; i < NumParts; ++i) 799 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 800 801 if (DstTy.isVector()) 802 MIRBuilder.buildBuildVector(DstReg, DstRegs); 803 else 804 MIRBuilder.buildMerge(DstReg, DstRegs); 805 MI.eraseFromParent(); 806 return Legalized; 807 } 808 case TargetOpcode::G_CONSTANT: { 809 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 810 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 811 unsigned TotalSize = Ty.getSizeInBits(); 812 unsigned NarrowSize = NarrowTy.getSizeInBits(); 813 int NumParts = TotalSize / NarrowSize; 814 815 SmallVector<Register, 4> PartRegs; 816 for (int I = 0; I != NumParts; ++I) { 817 unsigned Offset = I * NarrowSize; 818 auto K = MIRBuilder.buildConstant(NarrowTy, 819 Val.lshr(Offset).trunc(NarrowSize)); 820 PartRegs.push_back(K.getReg(0)); 821 } 822 823 LLT LeftoverTy; 824 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 825 SmallVector<Register, 1> LeftoverRegs; 826 if (LeftoverBits != 0) { 827 LeftoverTy = LLT::scalar(LeftoverBits); 828 auto K = MIRBuilder.buildConstant( 829 LeftoverTy, 830 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 831 LeftoverRegs.push_back(K.getReg(0)); 832 } 833 834 insertParts(MI.getOperand(0).getReg(), 835 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 836 837 MI.eraseFromParent(); 838 return Legalized; 839 } 840 case TargetOpcode::G_SEXT: 841 case TargetOpcode::G_ZEXT: 842 case TargetOpcode::G_ANYEXT: 843 return narrowScalarExt(MI, TypeIdx, NarrowTy); 844 case TargetOpcode::G_TRUNC: { 845 if (TypeIdx != 1) 846 return UnableToLegalize; 847 848 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 849 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 850 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 851 return UnableToLegalize; 852 } 853 854 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 855 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 856 MI.eraseFromParent(); 857 return Legalized; 858 } 859 860 case TargetOpcode::G_FREEZE: 861 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 862 863 case TargetOpcode::G_ADD: { 864 // FIXME: add support for when SizeOp0 isn't an exact multiple of 865 // NarrowSize. 866 if (SizeOp0 % NarrowSize != 0) 867 return UnableToLegalize; 868 // Expand in terms of carry-setting/consuming G_ADDE instructions. 869 int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); 870 871 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 872 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); 873 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); 874 875 Register CarryIn; 876 for (int i = 0; i < NumParts; ++i) { 877 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 878 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 879 880 if (i == 0) 881 MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]); 882 else { 883 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i], 884 Src2Regs[i], CarryIn); 885 } 886 887 DstRegs.push_back(DstReg); 888 CarryIn = CarryOut; 889 } 890 Register DstReg = MI.getOperand(0).getReg(); 891 if(MRI.getType(DstReg).isVector()) 892 MIRBuilder.buildBuildVector(DstReg, DstRegs); 893 else 894 MIRBuilder.buildMerge(DstReg, DstRegs); 895 MI.eraseFromParent(); 896 return Legalized; 897 } 898 case TargetOpcode::G_SUB: { 899 // FIXME: add support for when SizeOp0 isn't an exact multiple of 900 // NarrowSize. 901 if (SizeOp0 % NarrowSize != 0) 902 return UnableToLegalize; 903 904 int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); 905 906 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 907 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); 908 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); 909 910 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 911 Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 912 MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut}, 913 {Src1Regs[0], Src2Regs[0]}); 914 DstRegs.push_back(DstReg); 915 Register BorrowIn = BorrowOut; 916 for (int i = 1; i < NumParts; ++i) { 917 DstReg = MRI.createGenericVirtualRegister(NarrowTy); 918 BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 919 920 MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut}, 921 {Src1Regs[i], Src2Regs[i], BorrowIn}); 922 923 DstRegs.push_back(DstReg); 924 BorrowIn = BorrowOut; 925 } 926 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 927 MI.eraseFromParent(); 928 return Legalized; 929 } 930 case TargetOpcode::G_MUL: 931 case TargetOpcode::G_UMULH: 932 return narrowScalarMul(MI, NarrowTy); 933 case TargetOpcode::G_EXTRACT: 934 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 935 case TargetOpcode::G_INSERT: 936 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 937 case TargetOpcode::G_LOAD: { 938 auto &MMO = **MI.memoperands_begin(); 939 Register DstReg = MI.getOperand(0).getReg(); 940 LLT DstTy = MRI.getType(DstReg); 941 if (DstTy.isVector()) 942 return UnableToLegalize; 943 944 if (8 * MMO.getSize() != DstTy.getSizeInBits()) { 945 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 946 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); 947 MIRBuilder.buildAnyExt(DstReg, TmpReg); 948 MI.eraseFromParent(); 949 return Legalized; 950 } 951 952 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 953 } 954 case TargetOpcode::G_ZEXTLOAD: 955 case TargetOpcode::G_SEXTLOAD: { 956 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 957 Register DstReg = MI.getOperand(0).getReg(); 958 Register PtrReg = MI.getOperand(1).getReg(); 959 960 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 961 auto &MMO = **MI.memoperands_begin(); 962 unsigned MemSize = MMO.getSizeInBits(); 963 964 if (MemSize == NarrowSize) { 965 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 966 } else if (MemSize < NarrowSize) { 967 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); 968 } else if (MemSize > NarrowSize) { 969 // FIXME: Need to split the load. 970 return UnableToLegalize; 971 } 972 973 if (ZExt) 974 MIRBuilder.buildZExt(DstReg, TmpReg); 975 else 976 MIRBuilder.buildSExt(DstReg, TmpReg); 977 978 MI.eraseFromParent(); 979 return Legalized; 980 } 981 case TargetOpcode::G_STORE: { 982 const auto &MMO = **MI.memoperands_begin(); 983 984 Register SrcReg = MI.getOperand(0).getReg(); 985 LLT SrcTy = MRI.getType(SrcReg); 986 if (SrcTy.isVector()) 987 return UnableToLegalize; 988 989 int NumParts = SizeOp0 / NarrowSize; 990 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 991 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 992 if (SrcTy.isVector() && LeftoverBits != 0) 993 return UnableToLegalize; 994 995 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) { 996 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 997 auto &MMO = **MI.memoperands_begin(); 998 MIRBuilder.buildTrunc(TmpReg, SrcReg); 999 MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO); 1000 MI.eraseFromParent(); 1001 return Legalized; 1002 } 1003 1004 return reduceLoadStoreWidth(MI, 0, NarrowTy); 1005 } 1006 case TargetOpcode::G_SELECT: 1007 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 1008 case TargetOpcode::G_AND: 1009 case TargetOpcode::G_OR: 1010 case TargetOpcode::G_XOR: { 1011 // Legalize bitwise operation: 1012 // A = BinOp<Ty> B, C 1013 // into: 1014 // B1, ..., BN = G_UNMERGE_VALUES B 1015 // C1, ..., CN = G_UNMERGE_VALUES C 1016 // A1 = BinOp<Ty/N> B1, C2 1017 // ... 1018 // AN = BinOp<Ty/N> BN, CN 1019 // A = G_MERGE_VALUES A1, ..., AN 1020 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 1021 } 1022 case TargetOpcode::G_SHL: 1023 case TargetOpcode::G_LSHR: 1024 case TargetOpcode::G_ASHR: 1025 return narrowScalarShift(MI, TypeIdx, NarrowTy); 1026 case TargetOpcode::G_CTLZ: 1027 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1028 case TargetOpcode::G_CTTZ: 1029 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1030 case TargetOpcode::G_CTPOP: 1031 if (TypeIdx == 1) 1032 switch (MI.getOpcode()) { 1033 case TargetOpcode::G_CTLZ: 1034 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1035 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 1036 case TargetOpcode::G_CTTZ: 1037 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1038 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 1039 case TargetOpcode::G_CTPOP: 1040 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 1041 default: 1042 return UnableToLegalize; 1043 } 1044 1045 Observer.changingInstr(MI); 1046 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1047 Observer.changedInstr(MI); 1048 return Legalized; 1049 case TargetOpcode::G_INTTOPTR: 1050 if (TypeIdx != 1) 1051 return UnableToLegalize; 1052 1053 Observer.changingInstr(MI); 1054 narrowScalarSrc(MI, NarrowTy, 1); 1055 Observer.changedInstr(MI); 1056 return Legalized; 1057 case TargetOpcode::G_PTRTOINT: 1058 if (TypeIdx != 0) 1059 return UnableToLegalize; 1060 1061 Observer.changingInstr(MI); 1062 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1063 Observer.changedInstr(MI); 1064 return Legalized; 1065 case TargetOpcode::G_PHI: { 1066 unsigned NumParts = SizeOp0 / NarrowSize; 1067 SmallVector<Register, 2> DstRegs(NumParts); 1068 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1069 Observer.changingInstr(MI); 1070 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1071 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1072 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1073 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1074 SrcRegs[i / 2]); 1075 } 1076 MachineBasicBlock &MBB = *MI.getParent(); 1077 MIRBuilder.setInsertPt(MBB, MI); 1078 for (unsigned i = 0; i < NumParts; ++i) { 1079 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1080 MachineInstrBuilder MIB = 1081 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1082 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1083 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1084 } 1085 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1086 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1087 Observer.changedInstr(MI); 1088 MI.eraseFromParent(); 1089 return Legalized; 1090 } 1091 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1092 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1093 if (TypeIdx != 2) 1094 return UnableToLegalize; 1095 1096 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1097 Observer.changingInstr(MI); 1098 narrowScalarSrc(MI, NarrowTy, OpIdx); 1099 Observer.changedInstr(MI); 1100 return Legalized; 1101 } 1102 case TargetOpcode::G_ICMP: { 1103 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 1104 if (NarrowSize * 2 != SrcSize) 1105 return UnableToLegalize; 1106 1107 Observer.changingInstr(MI); 1108 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); 1109 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); 1110 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2)); 1111 1112 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); 1113 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); 1114 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3)); 1115 1116 CmpInst::Predicate Pred = 1117 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1118 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 1119 1120 if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) { 1121 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL); 1122 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); 1123 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); 1124 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1125 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero); 1126 } else { 1127 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1128 MachineInstrBuilder CmpHEQ = 1129 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1130 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1131 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1132 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); 1133 } 1134 Observer.changedInstr(MI); 1135 MI.eraseFromParent(); 1136 return Legalized; 1137 } 1138 case TargetOpcode::G_SEXT_INREG: { 1139 if (TypeIdx != 0) 1140 return UnableToLegalize; 1141 1142 int64_t SizeInBits = MI.getOperand(2).getImm(); 1143 1144 // So long as the new type has more bits than the bits we're extending we 1145 // don't need to break it apart. 1146 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1147 Observer.changingInstr(MI); 1148 // We don't lose any non-extension bits by truncating the src and 1149 // sign-extending the dst. 1150 MachineOperand &MO1 = MI.getOperand(1); 1151 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1152 MO1.setReg(TruncMIB.getReg(0)); 1153 1154 MachineOperand &MO2 = MI.getOperand(0); 1155 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1156 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1157 MIRBuilder.buildSExt(MO2, DstExt); 1158 MO2.setReg(DstExt); 1159 Observer.changedInstr(MI); 1160 return Legalized; 1161 } 1162 1163 // Break it apart. Components below the extension point are unmodified. The 1164 // component containing the extension point becomes a narrower SEXT_INREG. 1165 // Components above it are ashr'd from the component containing the 1166 // extension point. 1167 if (SizeOp0 % NarrowSize != 0) 1168 return UnableToLegalize; 1169 int NumParts = SizeOp0 / NarrowSize; 1170 1171 // List the registers where the destination will be scattered. 1172 SmallVector<Register, 2> DstRegs; 1173 // List the registers where the source will be split. 1174 SmallVector<Register, 2> SrcRegs; 1175 1176 // Create all the temporary registers. 1177 for (int i = 0; i < NumParts; ++i) { 1178 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1179 1180 SrcRegs.push_back(SrcReg); 1181 } 1182 1183 // Explode the big arguments into smaller chunks. 1184 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1185 1186 Register AshrCstReg = 1187 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1188 .getReg(0); 1189 Register FullExtensionReg = 0; 1190 Register PartialExtensionReg = 0; 1191 1192 // Do the operation on each small part. 1193 for (int i = 0; i < NumParts; ++i) { 1194 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1195 DstRegs.push_back(SrcRegs[i]); 1196 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1197 assert(PartialExtensionReg && 1198 "Expected to visit partial extension before full"); 1199 if (FullExtensionReg) { 1200 DstRegs.push_back(FullExtensionReg); 1201 continue; 1202 } 1203 DstRegs.push_back( 1204 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1205 .getReg(0)); 1206 FullExtensionReg = DstRegs.back(); 1207 } else { 1208 DstRegs.push_back( 1209 MIRBuilder 1210 .buildInstr( 1211 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1212 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1213 .getReg(0)); 1214 PartialExtensionReg = DstRegs.back(); 1215 } 1216 } 1217 1218 // Gather the destination registers into the final destination. 1219 Register DstReg = MI.getOperand(0).getReg(); 1220 MIRBuilder.buildMerge(DstReg, DstRegs); 1221 MI.eraseFromParent(); 1222 return Legalized; 1223 } 1224 case TargetOpcode::G_BSWAP: 1225 case TargetOpcode::G_BITREVERSE: { 1226 if (SizeOp0 % NarrowSize != 0) 1227 return UnableToLegalize; 1228 1229 Observer.changingInstr(MI); 1230 SmallVector<Register, 2> SrcRegs, DstRegs; 1231 unsigned NumParts = SizeOp0 / NarrowSize; 1232 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1233 1234 for (unsigned i = 0; i < NumParts; ++i) { 1235 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1236 {SrcRegs[NumParts - 1 - i]}); 1237 DstRegs.push_back(DstPart.getReg(0)); 1238 } 1239 1240 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1241 1242 Observer.changedInstr(MI); 1243 MI.eraseFromParent(); 1244 return Legalized; 1245 } 1246 case TargetOpcode::G_PTR_ADD: 1247 case TargetOpcode::G_PTRMASK: { 1248 if (TypeIdx != 1) 1249 return UnableToLegalize; 1250 Observer.changingInstr(MI); 1251 narrowScalarSrc(MI, NarrowTy, 2); 1252 Observer.changedInstr(MI); 1253 return Legalized; 1254 } 1255 case TargetOpcode::G_FPTOUI: { 1256 if (TypeIdx != 0) 1257 return UnableToLegalize; 1258 Observer.changingInstr(MI); 1259 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1260 Observer.changedInstr(MI); 1261 return Legalized; 1262 } 1263 case TargetOpcode::G_FPTOSI: { 1264 if (TypeIdx != 0) 1265 return UnableToLegalize; 1266 Observer.changingInstr(MI); 1267 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_SEXT); 1268 Observer.changedInstr(MI); 1269 return Legalized; 1270 } 1271 case TargetOpcode::G_FPEXT: 1272 if (TypeIdx != 0) 1273 return UnableToLegalize; 1274 Observer.changingInstr(MI); 1275 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1276 Observer.changedInstr(MI); 1277 return Legalized; 1278 } 1279 } 1280 1281 Register LegalizerHelper::coerceToScalar(Register Val) { 1282 LLT Ty = MRI.getType(Val); 1283 if (Ty.isScalar()) 1284 return Val; 1285 1286 const DataLayout &DL = MIRBuilder.getDataLayout(); 1287 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1288 if (Ty.isPointer()) { 1289 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1290 return Register(); 1291 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1292 } 1293 1294 Register NewVal = Val; 1295 1296 assert(Ty.isVector()); 1297 LLT EltTy = Ty.getElementType(); 1298 if (EltTy.isPointer()) 1299 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1300 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1301 } 1302 1303 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1304 unsigned OpIdx, unsigned ExtOpcode) { 1305 MachineOperand &MO = MI.getOperand(OpIdx); 1306 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1307 MO.setReg(ExtB.getReg(0)); 1308 } 1309 1310 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1311 unsigned OpIdx) { 1312 MachineOperand &MO = MI.getOperand(OpIdx); 1313 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1314 MO.setReg(ExtB.getReg(0)); 1315 } 1316 1317 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1318 unsigned OpIdx, unsigned TruncOpcode) { 1319 MachineOperand &MO = MI.getOperand(OpIdx); 1320 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1321 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1322 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1323 MO.setReg(DstExt); 1324 } 1325 1326 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1327 unsigned OpIdx, unsigned ExtOpcode) { 1328 MachineOperand &MO = MI.getOperand(OpIdx); 1329 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1330 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1331 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1332 MO.setReg(DstTrunc); 1333 } 1334 1335 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1336 unsigned OpIdx) { 1337 MachineOperand &MO = MI.getOperand(OpIdx); 1338 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1339 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1340 } 1341 1342 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1343 unsigned OpIdx) { 1344 MachineOperand &MO = MI.getOperand(OpIdx); 1345 1346 LLT OldTy = MRI.getType(MO.getReg()); 1347 unsigned OldElts = OldTy.getNumElements(); 1348 unsigned NewElts = MoreTy.getNumElements(); 1349 1350 unsigned NumParts = NewElts / OldElts; 1351 1352 // Use concat_vectors if the result is a multiple of the number of elements. 1353 if (NumParts * OldElts == NewElts) { 1354 SmallVector<Register, 8> Parts; 1355 Parts.push_back(MO.getReg()); 1356 1357 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1358 for (unsigned I = 1; I != NumParts; ++I) 1359 Parts.push_back(ImpDef); 1360 1361 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1362 MO.setReg(Concat.getReg(0)); 1363 return; 1364 } 1365 1366 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1367 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1368 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1369 MO.setReg(MoreReg); 1370 } 1371 1372 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1373 MachineOperand &Op = MI.getOperand(OpIdx); 1374 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1375 } 1376 1377 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1378 MachineOperand &MO = MI.getOperand(OpIdx); 1379 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1380 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1381 MIRBuilder.buildBitcast(MO, CastDst); 1382 MO.setReg(CastDst); 1383 } 1384 1385 LegalizerHelper::LegalizeResult 1386 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1387 LLT WideTy) { 1388 if (TypeIdx != 1) 1389 return UnableToLegalize; 1390 1391 Register DstReg = MI.getOperand(0).getReg(); 1392 LLT DstTy = MRI.getType(DstReg); 1393 if (DstTy.isVector()) 1394 return UnableToLegalize; 1395 1396 Register Src1 = MI.getOperand(1).getReg(); 1397 LLT SrcTy = MRI.getType(Src1); 1398 const int DstSize = DstTy.getSizeInBits(); 1399 const int SrcSize = SrcTy.getSizeInBits(); 1400 const int WideSize = WideTy.getSizeInBits(); 1401 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1402 1403 unsigned NumOps = MI.getNumOperands(); 1404 unsigned NumSrc = MI.getNumOperands() - 1; 1405 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1406 1407 if (WideSize >= DstSize) { 1408 // Directly pack the bits in the target type. 1409 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1410 1411 for (unsigned I = 2; I != NumOps; ++I) { 1412 const unsigned Offset = (I - 1) * PartSize; 1413 1414 Register SrcReg = MI.getOperand(I).getReg(); 1415 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1416 1417 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1418 1419 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1420 MRI.createGenericVirtualRegister(WideTy); 1421 1422 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1423 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1424 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1425 ResultReg = NextResult; 1426 } 1427 1428 if (WideSize > DstSize) 1429 MIRBuilder.buildTrunc(DstReg, ResultReg); 1430 else if (DstTy.isPointer()) 1431 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1432 1433 MI.eraseFromParent(); 1434 return Legalized; 1435 } 1436 1437 // Unmerge the original values to the GCD type, and recombine to the next 1438 // multiple greater than the original type. 1439 // 1440 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1441 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1442 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1443 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1444 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1445 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1446 // %12:_(s12) = G_MERGE_VALUES %10, %11 1447 // 1448 // Padding with undef if necessary: 1449 // 1450 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1451 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1452 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1453 // %7:_(s2) = G_IMPLICIT_DEF 1454 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1455 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1456 // %10:_(s12) = G_MERGE_VALUES %8, %9 1457 1458 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1459 LLT GCDTy = LLT::scalar(GCD); 1460 1461 SmallVector<Register, 8> Parts; 1462 SmallVector<Register, 8> NewMergeRegs; 1463 SmallVector<Register, 8> Unmerges; 1464 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1465 1466 // Decompose the original operands if they don't evenly divide. 1467 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1468 Register SrcReg = MI.getOperand(I).getReg(); 1469 if (GCD == SrcSize) { 1470 Unmerges.push_back(SrcReg); 1471 } else { 1472 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1473 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1474 Unmerges.push_back(Unmerge.getReg(J)); 1475 } 1476 } 1477 1478 // Pad with undef to the next size that is a multiple of the requested size. 1479 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1480 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1481 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1482 Unmerges.push_back(UndefReg); 1483 } 1484 1485 const int PartsPerGCD = WideSize / GCD; 1486 1487 // Build merges of each piece. 1488 ArrayRef<Register> Slicer(Unmerges); 1489 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1490 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1491 NewMergeRegs.push_back(Merge.getReg(0)); 1492 } 1493 1494 // A truncate may be necessary if the requested type doesn't evenly divide the 1495 // original result type. 1496 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1497 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1498 } else { 1499 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1500 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1501 } 1502 1503 MI.eraseFromParent(); 1504 return Legalized; 1505 } 1506 1507 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1508 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1509 LLT OrigTy = MRI.getType(OrigReg); 1510 LLT LCMTy = getLCMType(WideTy, OrigTy); 1511 1512 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1513 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1514 1515 Register UnmergeSrc = WideReg; 1516 1517 // Create a merge to the LCM type, padding with undef 1518 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1519 // => 1520 // %1:_(<4 x s32>) = G_FOO 1521 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1522 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1523 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1524 if (NumMergeParts > 1) { 1525 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1526 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1527 MergeParts[0] = WideReg; 1528 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1529 } 1530 1531 // Unmerge to the original register and pad with dead defs. 1532 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1533 UnmergeResults[0] = OrigReg; 1534 for (int I = 1; I != NumUnmergeParts; ++I) 1535 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1536 1537 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1538 return WideReg; 1539 } 1540 1541 LegalizerHelper::LegalizeResult 1542 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1543 LLT WideTy) { 1544 if (TypeIdx != 0) 1545 return UnableToLegalize; 1546 1547 int NumDst = MI.getNumOperands() - 1; 1548 Register SrcReg = MI.getOperand(NumDst).getReg(); 1549 LLT SrcTy = MRI.getType(SrcReg); 1550 if (SrcTy.isVector()) 1551 return UnableToLegalize; 1552 1553 Register Dst0Reg = MI.getOperand(0).getReg(); 1554 LLT DstTy = MRI.getType(Dst0Reg); 1555 if (!DstTy.isScalar()) 1556 return UnableToLegalize; 1557 1558 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1559 if (SrcTy.isPointer()) { 1560 const DataLayout &DL = MIRBuilder.getDataLayout(); 1561 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1562 LLVM_DEBUG( 1563 dbgs() << "Not casting non-integral address space integer\n"); 1564 return UnableToLegalize; 1565 } 1566 1567 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1568 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1569 } 1570 1571 // Widen SrcTy to WideTy. This does not affect the result, but since the 1572 // user requested this size, it is probably better handled than SrcTy and 1573 // should reduce the total number of legalization artifacts 1574 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1575 SrcTy = WideTy; 1576 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1577 } 1578 1579 // Theres no unmerge type to target. Directly extract the bits from the 1580 // source type 1581 unsigned DstSize = DstTy.getSizeInBits(); 1582 1583 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1584 for (int I = 1; I != NumDst; ++I) { 1585 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1586 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1587 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1588 } 1589 1590 MI.eraseFromParent(); 1591 return Legalized; 1592 } 1593 1594 // Extend the source to a wider type. 1595 LLT LCMTy = getLCMType(SrcTy, WideTy); 1596 1597 Register WideSrc = SrcReg; 1598 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1599 // TODO: If this is an integral address space, cast to integer and anyext. 1600 if (SrcTy.isPointer()) { 1601 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1602 return UnableToLegalize; 1603 } 1604 1605 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1606 } 1607 1608 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1609 1610 // Create a sequence of unmerges and merges to the original results. Since we 1611 // may have widened the source, we will need to pad the results with dead defs 1612 // to cover the source register. 1613 // e.g. widen s48 to s64: 1614 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1615 // 1616 // => 1617 // %4:_(s192) = G_ANYEXT %0:_(s96) 1618 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1619 // ; unpack to GCD type, with extra dead defs 1620 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1621 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1622 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1623 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1624 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1625 const LLT GCDTy = getGCDType(WideTy, DstTy); 1626 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1627 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1628 1629 // Directly unmerge to the destination without going through a GCD type 1630 // if possible 1631 if (PartsPerRemerge == 1) { 1632 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1633 1634 for (int I = 0; I != NumUnmerge; ++I) { 1635 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1636 1637 for (int J = 0; J != PartsPerUnmerge; ++J) { 1638 int Idx = I * PartsPerUnmerge + J; 1639 if (Idx < NumDst) 1640 MIB.addDef(MI.getOperand(Idx).getReg()); 1641 else { 1642 // Create dead def for excess components. 1643 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1644 } 1645 } 1646 1647 MIB.addUse(Unmerge.getReg(I)); 1648 } 1649 } else { 1650 SmallVector<Register, 16> Parts; 1651 for (int J = 0; J != NumUnmerge; ++J) 1652 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1653 1654 SmallVector<Register, 8> RemergeParts; 1655 for (int I = 0; I != NumDst; ++I) { 1656 for (int J = 0; J < PartsPerRemerge; ++J) { 1657 const int Idx = I * PartsPerRemerge + J; 1658 RemergeParts.emplace_back(Parts[Idx]); 1659 } 1660 1661 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1662 RemergeParts.clear(); 1663 } 1664 } 1665 1666 MI.eraseFromParent(); 1667 return Legalized; 1668 } 1669 1670 LegalizerHelper::LegalizeResult 1671 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1672 LLT WideTy) { 1673 Register DstReg = MI.getOperand(0).getReg(); 1674 Register SrcReg = MI.getOperand(1).getReg(); 1675 LLT SrcTy = MRI.getType(SrcReg); 1676 1677 LLT DstTy = MRI.getType(DstReg); 1678 unsigned Offset = MI.getOperand(2).getImm(); 1679 1680 if (TypeIdx == 0) { 1681 if (SrcTy.isVector() || DstTy.isVector()) 1682 return UnableToLegalize; 1683 1684 SrcOp Src(SrcReg); 1685 if (SrcTy.isPointer()) { 1686 // Extracts from pointers can be handled only if they are really just 1687 // simple integers. 1688 const DataLayout &DL = MIRBuilder.getDataLayout(); 1689 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1690 return UnableToLegalize; 1691 1692 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1693 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1694 SrcTy = SrcAsIntTy; 1695 } 1696 1697 if (DstTy.isPointer()) 1698 return UnableToLegalize; 1699 1700 if (Offset == 0) { 1701 // Avoid a shift in the degenerate case. 1702 MIRBuilder.buildTrunc(DstReg, 1703 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1704 MI.eraseFromParent(); 1705 return Legalized; 1706 } 1707 1708 // Do a shift in the source type. 1709 LLT ShiftTy = SrcTy; 1710 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1711 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1712 ShiftTy = WideTy; 1713 } 1714 1715 auto LShr = MIRBuilder.buildLShr( 1716 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1717 MIRBuilder.buildTrunc(DstReg, LShr); 1718 MI.eraseFromParent(); 1719 return Legalized; 1720 } 1721 1722 if (SrcTy.isScalar()) { 1723 Observer.changingInstr(MI); 1724 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1725 Observer.changedInstr(MI); 1726 return Legalized; 1727 } 1728 1729 if (!SrcTy.isVector()) 1730 return UnableToLegalize; 1731 1732 if (DstTy != SrcTy.getElementType()) 1733 return UnableToLegalize; 1734 1735 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1736 return UnableToLegalize; 1737 1738 Observer.changingInstr(MI); 1739 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1740 1741 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1742 Offset); 1743 widenScalarDst(MI, WideTy.getScalarType(), 0); 1744 Observer.changedInstr(MI); 1745 return Legalized; 1746 } 1747 1748 LegalizerHelper::LegalizeResult 1749 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1750 LLT WideTy) { 1751 if (TypeIdx != 0 || WideTy.isVector()) 1752 return UnableToLegalize; 1753 Observer.changingInstr(MI); 1754 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1755 widenScalarDst(MI, WideTy); 1756 Observer.changedInstr(MI); 1757 return Legalized; 1758 } 1759 1760 LegalizerHelper::LegalizeResult 1761 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1762 LLT WideTy) { 1763 if (TypeIdx == 1) 1764 return UnableToLegalize; // TODO 1765 1766 unsigned Opcode; 1767 unsigned ExtOpcode; 1768 Optional<Register> CarryIn = None; 1769 switch (MI.getOpcode()) { 1770 default: 1771 llvm_unreachable("Unexpected opcode!"); 1772 case TargetOpcode::G_SADDO: 1773 Opcode = TargetOpcode::G_ADD; 1774 ExtOpcode = TargetOpcode::G_SEXT; 1775 break; 1776 case TargetOpcode::G_SSUBO: 1777 Opcode = TargetOpcode::G_SUB; 1778 ExtOpcode = TargetOpcode::G_SEXT; 1779 break; 1780 case TargetOpcode::G_UADDO: 1781 Opcode = TargetOpcode::G_ADD; 1782 ExtOpcode = TargetOpcode::G_ZEXT; 1783 break; 1784 case TargetOpcode::G_USUBO: 1785 Opcode = TargetOpcode::G_SUB; 1786 ExtOpcode = TargetOpcode::G_ZEXT; 1787 break; 1788 case TargetOpcode::G_SADDE: 1789 Opcode = TargetOpcode::G_UADDE; 1790 ExtOpcode = TargetOpcode::G_SEXT; 1791 CarryIn = MI.getOperand(4).getReg(); 1792 break; 1793 case TargetOpcode::G_SSUBE: 1794 Opcode = TargetOpcode::G_USUBE; 1795 ExtOpcode = TargetOpcode::G_SEXT; 1796 CarryIn = MI.getOperand(4).getReg(); 1797 break; 1798 case TargetOpcode::G_UADDE: 1799 Opcode = TargetOpcode::G_UADDE; 1800 ExtOpcode = TargetOpcode::G_ZEXT; 1801 CarryIn = MI.getOperand(4).getReg(); 1802 break; 1803 case TargetOpcode::G_USUBE: 1804 Opcode = TargetOpcode::G_USUBE; 1805 ExtOpcode = TargetOpcode::G_ZEXT; 1806 CarryIn = MI.getOperand(4).getReg(); 1807 break; 1808 } 1809 1810 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1811 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1812 // Do the arithmetic in the larger type. 1813 Register NewOp; 1814 if (CarryIn) { 1815 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1816 NewOp = MIRBuilder 1817 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1818 {LHSExt, RHSExt, *CarryIn}) 1819 .getReg(0); 1820 } else { 1821 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1822 } 1823 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1824 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1825 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1826 // There is no overflow if the ExtOp is the same as NewOp. 1827 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1828 // Now trunc the NewOp to the original result. 1829 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1830 MI.eraseFromParent(); 1831 return Legalized; 1832 } 1833 1834 LegalizerHelper::LegalizeResult 1835 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1836 LLT WideTy) { 1837 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1838 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1839 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1840 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1841 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1842 // We can convert this to: 1843 // 1. Any extend iN to iM 1844 // 2. SHL by M-N 1845 // 3. [US][ADD|SUB|SHL]SAT 1846 // 4. L/ASHR by M-N 1847 // 1848 // It may be more efficient to lower this to a min and a max operation in 1849 // the higher precision arithmetic if the promoted operation isn't legal, 1850 // but this decision is up to the target's lowering request. 1851 Register DstReg = MI.getOperand(0).getReg(); 1852 1853 unsigned NewBits = WideTy.getScalarSizeInBits(); 1854 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1855 1856 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1857 // must not left shift the RHS to preserve the shift amount. 1858 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1859 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1860 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1861 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1862 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1863 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1864 1865 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1866 {ShiftL, ShiftR}, MI.getFlags()); 1867 1868 // Use a shift that will preserve the number of sign bits when the trunc is 1869 // folded away. 1870 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1871 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1872 1873 MIRBuilder.buildTrunc(DstReg, Result); 1874 MI.eraseFromParent(); 1875 return Legalized; 1876 } 1877 1878 LegalizerHelper::LegalizeResult 1879 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1880 switch (MI.getOpcode()) { 1881 default: 1882 return UnableToLegalize; 1883 case TargetOpcode::G_EXTRACT: 1884 return widenScalarExtract(MI, TypeIdx, WideTy); 1885 case TargetOpcode::G_INSERT: 1886 return widenScalarInsert(MI, TypeIdx, WideTy); 1887 case TargetOpcode::G_MERGE_VALUES: 1888 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1889 case TargetOpcode::G_UNMERGE_VALUES: 1890 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1891 case TargetOpcode::G_SADDO: 1892 case TargetOpcode::G_SSUBO: 1893 case TargetOpcode::G_UADDO: 1894 case TargetOpcode::G_USUBO: 1895 case TargetOpcode::G_SADDE: 1896 case TargetOpcode::G_SSUBE: 1897 case TargetOpcode::G_UADDE: 1898 case TargetOpcode::G_USUBE: 1899 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1900 case TargetOpcode::G_SADDSAT: 1901 case TargetOpcode::G_SSUBSAT: 1902 case TargetOpcode::G_SSHLSAT: 1903 case TargetOpcode::G_UADDSAT: 1904 case TargetOpcode::G_USUBSAT: 1905 case TargetOpcode::G_USHLSAT: 1906 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1907 case TargetOpcode::G_CTTZ: 1908 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1909 case TargetOpcode::G_CTLZ: 1910 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1911 case TargetOpcode::G_CTPOP: { 1912 if (TypeIdx == 0) { 1913 Observer.changingInstr(MI); 1914 widenScalarDst(MI, WideTy, 0); 1915 Observer.changedInstr(MI); 1916 return Legalized; 1917 } 1918 1919 Register SrcReg = MI.getOperand(1).getReg(); 1920 1921 // First ZEXT the input. 1922 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1923 LLT CurTy = MRI.getType(SrcReg); 1924 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1925 // The count is the same in the larger type except if the original 1926 // value was zero. This can be handled by setting the bit just off 1927 // the top of the original type. 1928 auto TopBit = 1929 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1930 MIBSrc = MIRBuilder.buildOr( 1931 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1932 } 1933 1934 // Perform the operation at the larger size. 1935 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1936 // This is already the correct result for CTPOP and CTTZs 1937 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1938 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1939 // The correct result is NewOp - (Difference in widety and current ty). 1940 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1941 MIBNewOp = MIRBuilder.buildSub( 1942 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1943 } 1944 1945 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1946 MI.eraseFromParent(); 1947 return Legalized; 1948 } 1949 case TargetOpcode::G_BSWAP: { 1950 Observer.changingInstr(MI); 1951 Register DstReg = MI.getOperand(0).getReg(); 1952 1953 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 1954 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1955 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 1956 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1957 1958 MI.getOperand(0).setReg(DstExt); 1959 1960 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1961 1962 LLT Ty = MRI.getType(DstReg); 1963 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1964 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 1965 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 1966 1967 MIRBuilder.buildTrunc(DstReg, ShrReg); 1968 Observer.changedInstr(MI); 1969 return Legalized; 1970 } 1971 case TargetOpcode::G_BITREVERSE: { 1972 Observer.changingInstr(MI); 1973 1974 Register DstReg = MI.getOperand(0).getReg(); 1975 LLT Ty = MRI.getType(DstReg); 1976 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1977 1978 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1979 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1980 MI.getOperand(0).setReg(DstExt); 1981 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1982 1983 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 1984 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 1985 MIRBuilder.buildTrunc(DstReg, Shift); 1986 Observer.changedInstr(MI); 1987 return Legalized; 1988 } 1989 case TargetOpcode::G_FREEZE: 1990 Observer.changingInstr(MI); 1991 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1992 widenScalarDst(MI, WideTy); 1993 Observer.changedInstr(MI); 1994 return Legalized; 1995 1996 case TargetOpcode::G_ADD: 1997 case TargetOpcode::G_AND: 1998 case TargetOpcode::G_MUL: 1999 case TargetOpcode::G_OR: 2000 case TargetOpcode::G_XOR: 2001 case TargetOpcode::G_SUB: 2002 // Perform operation at larger width (any extension is fines here, high bits 2003 // don't affect the result) and then truncate the result back to the 2004 // original type. 2005 Observer.changingInstr(MI); 2006 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2007 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2008 widenScalarDst(MI, WideTy); 2009 Observer.changedInstr(MI); 2010 return Legalized; 2011 2012 case TargetOpcode::G_SHL: 2013 Observer.changingInstr(MI); 2014 2015 if (TypeIdx == 0) { 2016 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2017 widenScalarDst(MI, WideTy); 2018 } else { 2019 assert(TypeIdx == 1); 2020 // The "number of bits to shift" operand must preserve its value as an 2021 // unsigned integer: 2022 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2023 } 2024 2025 Observer.changedInstr(MI); 2026 return Legalized; 2027 2028 case TargetOpcode::G_SDIV: 2029 case TargetOpcode::G_SREM: 2030 case TargetOpcode::G_SMIN: 2031 case TargetOpcode::G_SMAX: 2032 Observer.changingInstr(MI); 2033 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2034 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2035 widenScalarDst(MI, WideTy); 2036 Observer.changedInstr(MI); 2037 return Legalized; 2038 2039 case TargetOpcode::G_ASHR: 2040 case TargetOpcode::G_LSHR: 2041 Observer.changingInstr(MI); 2042 2043 if (TypeIdx == 0) { 2044 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2045 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2046 2047 widenScalarSrc(MI, WideTy, 1, CvtOp); 2048 widenScalarDst(MI, WideTy); 2049 } else { 2050 assert(TypeIdx == 1); 2051 // The "number of bits to shift" operand must preserve its value as an 2052 // unsigned integer: 2053 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2054 } 2055 2056 Observer.changedInstr(MI); 2057 return Legalized; 2058 case TargetOpcode::G_UDIV: 2059 case TargetOpcode::G_UREM: 2060 case TargetOpcode::G_UMIN: 2061 case TargetOpcode::G_UMAX: 2062 Observer.changingInstr(MI); 2063 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2064 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2065 widenScalarDst(MI, WideTy); 2066 Observer.changedInstr(MI); 2067 return Legalized; 2068 2069 case TargetOpcode::G_SELECT: 2070 Observer.changingInstr(MI); 2071 if (TypeIdx == 0) { 2072 // Perform operation at larger width (any extension is fine here, high 2073 // bits don't affect the result) and then truncate the result back to the 2074 // original type. 2075 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2076 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2077 widenScalarDst(MI, WideTy); 2078 } else { 2079 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2080 // Explicit extension is required here since high bits affect the result. 2081 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2082 } 2083 Observer.changedInstr(MI); 2084 return Legalized; 2085 2086 case TargetOpcode::G_FPTOSI: 2087 case TargetOpcode::G_FPTOUI: 2088 Observer.changingInstr(MI); 2089 2090 if (TypeIdx == 0) 2091 widenScalarDst(MI, WideTy); 2092 else 2093 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2094 2095 Observer.changedInstr(MI); 2096 return Legalized; 2097 case TargetOpcode::G_SITOFP: 2098 Observer.changingInstr(MI); 2099 2100 if (TypeIdx == 0) 2101 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2102 else 2103 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2104 2105 Observer.changedInstr(MI); 2106 return Legalized; 2107 case TargetOpcode::G_UITOFP: 2108 Observer.changingInstr(MI); 2109 2110 if (TypeIdx == 0) 2111 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2112 else 2113 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2114 2115 Observer.changedInstr(MI); 2116 return Legalized; 2117 case TargetOpcode::G_LOAD: 2118 case TargetOpcode::G_SEXTLOAD: 2119 case TargetOpcode::G_ZEXTLOAD: 2120 Observer.changingInstr(MI); 2121 widenScalarDst(MI, WideTy); 2122 Observer.changedInstr(MI); 2123 return Legalized; 2124 2125 case TargetOpcode::G_STORE: { 2126 if (TypeIdx != 0) 2127 return UnableToLegalize; 2128 2129 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2130 if (!Ty.isScalar()) 2131 return UnableToLegalize; 2132 2133 Observer.changingInstr(MI); 2134 2135 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2136 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2137 widenScalarSrc(MI, WideTy, 0, ExtType); 2138 2139 Observer.changedInstr(MI); 2140 return Legalized; 2141 } 2142 case TargetOpcode::G_CONSTANT: { 2143 MachineOperand &SrcMO = MI.getOperand(1); 2144 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2145 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2146 MRI.getType(MI.getOperand(0).getReg())); 2147 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2148 ExtOpc == TargetOpcode::G_ANYEXT) && 2149 "Illegal Extend"); 2150 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2151 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2152 ? SrcVal.sext(WideTy.getSizeInBits()) 2153 : SrcVal.zext(WideTy.getSizeInBits()); 2154 Observer.changingInstr(MI); 2155 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2156 2157 widenScalarDst(MI, WideTy); 2158 Observer.changedInstr(MI); 2159 return Legalized; 2160 } 2161 case TargetOpcode::G_FCONSTANT: { 2162 MachineOperand &SrcMO = MI.getOperand(1); 2163 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2164 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2165 bool LosesInfo; 2166 switch (WideTy.getSizeInBits()) { 2167 case 32: 2168 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2169 &LosesInfo); 2170 break; 2171 case 64: 2172 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2173 &LosesInfo); 2174 break; 2175 default: 2176 return UnableToLegalize; 2177 } 2178 2179 assert(!LosesInfo && "extend should always be lossless"); 2180 2181 Observer.changingInstr(MI); 2182 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2183 2184 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2185 Observer.changedInstr(MI); 2186 return Legalized; 2187 } 2188 case TargetOpcode::G_IMPLICIT_DEF: { 2189 Observer.changingInstr(MI); 2190 widenScalarDst(MI, WideTy); 2191 Observer.changedInstr(MI); 2192 return Legalized; 2193 } 2194 case TargetOpcode::G_BRCOND: 2195 Observer.changingInstr(MI); 2196 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2197 Observer.changedInstr(MI); 2198 return Legalized; 2199 2200 case TargetOpcode::G_FCMP: 2201 Observer.changingInstr(MI); 2202 if (TypeIdx == 0) 2203 widenScalarDst(MI, WideTy); 2204 else { 2205 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2206 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2207 } 2208 Observer.changedInstr(MI); 2209 return Legalized; 2210 2211 case TargetOpcode::G_ICMP: 2212 Observer.changingInstr(MI); 2213 if (TypeIdx == 0) 2214 widenScalarDst(MI, WideTy); 2215 else { 2216 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2217 MI.getOperand(1).getPredicate())) 2218 ? TargetOpcode::G_SEXT 2219 : TargetOpcode::G_ZEXT; 2220 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2221 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2222 } 2223 Observer.changedInstr(MI); 2224 return Legalized; 2225 2226 case TargetOpcode::G_PTR_ADD: 2227 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2228 Observer.changingInstr(MI); 2229 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2230 Observer.changedInstr(MI); 2231 return Legalized; 2232 2233 case TargetOpcode::G_PHI: { 2234 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2235 2236 Observer.changingInstr(MI); 2237 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2238 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2239 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2240 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2241 } 2242 2243 MachineBasicBlock &MBB = *MI.getParent(); 2244 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2245 widenScalarDst(MI, WideTy); 2246 Observer.changedInstr(MI); 2247 return Legalized; 2248 } 2249 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2250 if (TypeIdx == 0) { 2251 Register VecReg = MI.getOperand(1).getReg(); 2252 LLT VecTy = MRI.getType(VecReg); 2253 Observer.changingInstr(MI); 2254 2255 widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(), 2256 WideTy.getSizeInBits()), 2257 1, TargetOpcode::G_SEXT); 2258 2259 widenScalarDst(MI, WideTy, 0); 2260 Observer.changedInstr(MI); 2261 return Legalized; 2262 } 2263 2264 if (TypeIdx != 2) 2265 return UnableToLegalize; 2266 Observer.changingInstr(MI); 2267 // TODO: Probably should be zext 2268 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2269 Observer.changedInstr(MI); 2270 return Legalized; 2271 } 2272 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2273 if (TypeIdx == 1) { 2274 Observer.changingInstr(MI); 2275 2276 Register VecReg = MI.getOperand(1).getReg(); 2277 LLT VecTy = MRI.getType(VecReg); 2278 LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy); 2279 2280 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2281 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2282 widenScalarDst(MI, WideVecTy, 0); 2283 Observer.changedInstr(MI); 2284 return Legalized; 2285 } 2286 2287 if (TypeIdx == 2) { 2288 Observer.changingInstr(MI); 2289 // TODO: Probably should be zext 2290 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2291 Observer.changedInstr(MI); 2292 return Legalized; 2293 } 2294 2295 return UnableToLegalize; 2296 } 2297 case TargetOpcode::G_FADD: 2298 case TargetOpcode::G_FMUL: 2299 case TargetOpcode::G_FSUB: 2300 case TargetOpcode::G_FMA: 2301 case TargetOpcode::G_FMAD: 2302 case TargetOpcode::G_FNEG: 2303 case TargetOpcode::G_FABS: 2304 case TargetOpcode::G_FCANONICALIZE: 2305 case TargetOpcode::G_FMINNUM: 2306 case TargetOpcode::G_FMAXNUM: 2307 case TargetOpcode::G_FMINNUM_IEEE: 2308 case TargetOpcode::G_FMAXNUM_IEEE: 2309 case TargetOpcode::G_FMINIMUM: 2310 case TargetOpcode::G_FMAXIMUM: 2311 case TargetOpcode::G_FDIV: 2312 case TargetOpcode::G_FREM: 2313 case TargetOpcode::G_FCEIL: 2314 case TargetOpcode::G_FFLOOR: 2315 case TargetOpcode::G_FCOS: 2316 case TargetOpcode::G_FSIN: 2317 case TargetOpcode::G_FLOG10: 2318 case TargetOpcode::G_FLOG: 2319 case TargetOpcode::G_FLOG2: 2320 case TargetOpcode::G_FRINT: 2321 case TargetOpcode::G_FNEARBYINT: 2322 case TargetOpcode::G_FSQRT: 2323 case TargetOpcode::G_FEXP: 2324 case TargetOpcode::G_FEXP2: 2325 case TargetOpcode::G_FPOW: 2326 case TargetOpcode::G_INTRINSIC_TRUNC: 2327 case TargetOpcode::G_INTRINSIC_ROUND: 2328 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2329 assert(TypeIdx == 0); 2330 Observer.changingInstr(MI); 2331 2332 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2333 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2334 2335 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2336 Observer.changedInstr(MI); 2337 return Legalized; 2338 case TargetOpcode::G_FPOWI: { 2339 if (TypeIdx != 0) 2340 return UnableToLegalize; 2341 Observer.changingInstr(MI); 2342 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2343 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2344 Observer.changedInstr(MI); 2345 return Legalized; 2346 } 2347 case TargetOpcode::G_INTTOPTR: 2348 if (TypeIdx != 1) 2349 return UnableToLegalize; 2350 2351 Observer.changingInstr(MI); 2352 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2353 Observer.changedInstr(MI); 2354 return Legalized; 2355 case TargetOpcode::G_PTRTOINT: 2356 if (TypeIdx != 0) 2357 return UnableToLegalize; 2358 2359 Observer.changingInstr(MI); 2360 widenScalarDst(MI, WideTy, 0); 2361 Observer.changedInstr(MI); 2362 return Legalized; 2363 case TargetOpcode::G_BUILD_VECTOR: { 2364 Observer.changingInstr(MI); 2365 2366 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2367 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2368 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2369 2370 // Avoid changing the result vector type if the source element type was 2371 // requested. 2372 if (TypeIdx == 1) { 2373 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2374 } else { 2375 widenScalarDst(MI, WideTy, 0); 2376 } 2377 2378 Observer.changedInstr(MI); 2379 return Legalized; 2380 } 2381 case TargetOpcode::G_SEXT_INREG: 2382 if (TypeIdx != 0) 2383 return UnableToLegalize; 2384 2385 Observer.changingInstr(MI); 2386 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2387 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2388 Observer.changedInstr(MI); 2389 return Legalized; 2390 case TargetOpcode::G_PTRMASK: { 2391 if (TypeIdx != 1) 2392 return UnableToLegalize; 2393 Observer.changingInstr(MI); 2394 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2395 Observer.changedInstr(MI); 2396 return Legalized; 2397 } 2398 } 2399 } 2400 2401 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2402 MachineIRBuilder &B, Register Src, LLT Ty) { 2403 auto Unmerge = B.buildUnmerge(Ty, Src); 2404 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2405 Pieces.push_back(Unmerge.getReg(I)); 2406 } 2407 2408 LegalizerHelper::LegalizeResult 2409 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2410 Register Dst = MI.getOperand(0).getReg(); 2411 Register Src = MI.getOperand(1).getReg(); 2412 LLT DstTy = MRI.getType(Dst); 2413 LLT SrcTy = MRI.getType(Src); 2414 2415 if (SrcTy.isVector()) { 2416 LLT SrcEltTy = SrcTy.getElementType(); 2417 SmallVector<Register, 8> SrcRegs; 2418 2419 if (DstTy.isVector()) { 2420 int NumDstElt = DstTy.getNumElements(); 2421 int NumSrcElt = SrcTy.getNumElements(); 2422 2423 LLT DstEltTy = DstTy.getElementType(); 2424 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2425 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2426 2427 // If there's an element size mismatch, insert intermediate casts to match 2428 // the result element type. 2429 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2430 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2431 // 2432 // => 2433 // 2434 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2435 // %3:_(<2 x s8>) = G_BITCAST %2 2436 // %4:_(<2 x s8>) = G_BITCAST %3 2437 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2438 DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy); 2439 SrcPartTy = SrcEltTy; 2440 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2441 // 2442 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2443 // 2444 // => 2445 // 2446 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2447 // %3:_(s16) = G_BITCAST %2 2448 // %4:_(s16) = G_BITCAST %3 2449 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2450 SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy); 2451 DstCastTy = DstEltTy; 2452 } 2453 2454 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2455 for (Register &SrcReg : SrcRegs) 2456 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2457 } else 2458 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2459 2460 MIRBuilder.buildMerge(Dst, SrcRegs); 2461 MI.eraseFromParent(); 2462 return Legalized; 2463 } 2464 2465 if (DstTy.isVector()) { 2466 SmallVector<Register, 8> SrcRegs; 2467 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2468 MIRBuilder.buildMerge(Dst, SrcRegs); 2469 MI.eraseFromParent(); 2470 return Legalized; 2471 } 2472 2473 return UnableToLegalize; 2474 } 2475 2476 /// Figure out the bit offset into a register when coercing a vector index for 2477 /// the wide element type. This is only for the case when promoting vector to 2478 /// one with larger elements. 2479 // 2480 /// 2481 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2482 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2483 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2484 Register Idx, 2485 unsigned NewEltSize, 2486 unsigned OldEltSize) { 2487 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2488 LLT IdxTy = B.getMRI()->getType(Idx); 2489 2490 // Now figure out the amount we need to shift to get the target bits. 2491 auto OffsetMask = B.buildConstant( 2492 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2493 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2494 return B.buildShl(IdxTy, OffsetIdx, 2495 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2496 } 2497 2498 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2499 /// is casting to a vector with a smaller element size, perform multiple element 2500 /// extracts and merge the results. If this is coercing to a vector with larger 2501 /// elements, index the bitcasted vector and extract the target element with bit 2502 /// operations. This is intended to force the indexing in the native register 2503 /// size for architectures that can dynamically index the register file. 2504 LegalizerHelper::LegalizeResult 2505 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2506 LLT CastTy) { 2507 if (TypeIdx != 1) 2508 return UnableToLegalize; 2509 2510 Register Dst = MI.getOperand(0).getReg(); 2511 Register SrcVec = MI.getOperand(1).getReg(); 2512 Register Idx = MI.getOperand(2).getReg(); 2513 LLT SrcVecTy = MRI.getType(SrcVec); 2514 LLT IdxTy = MRI.getType(Idx); 2515 2516 LLT SrcEltTy = SrcVecTy.getElementType(); 2517 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2518 unsigned OldNumElts = SrcVecTy.getNumElements(); 2519 2520 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2521 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2522 2523 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2524 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2525 if (NewNumElts > OldNumElts) { 2526 // Decreasing the vector element size 2527 // 2528 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2529 // => 2530 // v4i32:castx = bitcast x:v2i64 2531 // 2532 // i64 = bitcast 2533 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2534 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2535 // 2536 if (NewNumElts % OldNumElts != 0) 2537 return UnableToLegalize; 2538 2539 // Type of the intermediate result vector. 2540 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2541 LLT MidTy = LLT::scalarOrVector(NewEltsPerOldElt, NewEltTy); 2542 2543 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2544 2545 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2546 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2547 2548 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2549 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2550 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2551 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2552 NewOps[I] = Elt.getReg(0); 2553 } 2554 2555 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2556 MIRBuilder.buildBitcast(Dst, NewVec); 2557 MI.eraseFromParent(); 2558 return Legalized; 2559 } 2560 2561 if (NewNumElts < OldNumElts) { 2562 if (NewEltSize % OldEltSize != 0) 2563 return UnableToLegalize; 2564 2565 // This only depends on powers of 2 because we use bit tricks to figure out 2566 // the bit offset we need to shift to get the target element. A general 2567 // expansion could emit division/multiply. 2568 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2569 return UnableToLegalize; 2570 2571 // Increasing the vector element size. 2572 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2573 // 2574 // => 2575 // 2576 // %cast = G_BITCAST %vec 2577 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2578 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2579 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2580 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2581 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2582 // %elt = G_TRUNC %elt_bits 2583 2584 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2585 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2586 2587 // Divide to get the index in the wider element type. 2588 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2589 2590 Register WideElt = CastVec; 2591 if (CastTy.isVector()) { 2592 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2593 ScaledIdx).getReg(0); 2594 } 2595 2596 // Compute the bit offset into the register of the target element. 2597 Register OffsetBits = getBitcastWiderVectorElementOffset( 2598 MIRBuilder, Idx, NewEltSize, OldEltSize); 2599 2600 // Shift the wide element to get the target element. 2601 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2602 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2603 MI.eraseFromParent(); 2604 return Legalized; 2605 } 2606 2607 return UnableToLegalize; 2608 } 2609 2610 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2611 /// TargetReg, while preserving other bits in \p TargetReg. 2612 /// 2613 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2614 static Register buildBitFieldInsert(MachineIRBuilder &B, 2615 Register TargetReg, Register InsertReg, 2616 Register OffsetBits) { 2617 LLT TargetTy = B.getMRI()->getType(TargetReg); 2618 LLT InsertTy = B.getMRI()->getType(InsertReg); 2619 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2620 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2621 2622 // Produce a bitmask of the value to insert 2623 auto EltMask = B.buildConstant( 2624 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2625 InsertTy.getSizeInBits())); 2626 // Shift it into position 2627 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2628 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2629 2630 // Clear out the bits in the wide element 2631 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2632 2633 // The value to insert has all zeros already, so stick it into the masked 2634 // wide element. 2635 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2636 } 2637 2638 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2639 /// is increasing the element size, perform the indexing in the target element 2640 /// type, and use bit operations to insert at the element position. This is 2641 /// intended for architectures that can dynamically index the register file and 2642 /// want to force indexing in the native register size. 2643 LegalizerHelper::LegalizeResult 2644 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2645 LLT CastTy) { 2646 if (TypeIdx != 0) 2647 return UnableToLegalize; 2648 2649 Register Dst = MI.getOperand(0).getReg(); 2650 Register SrcVec = MI.getOperand(1).getReg(); 2651 Register Val = MI.getOperand(2).getReg(); 2652 Register Idx = MI.getOperand(3).getReg(); 2653 2654 LLT VecTy = MRI.getType(Dst); 2655 LLT IdxTy = MRI.getType(Idx); 2656 2657 LLT VecEltTy = VecTy.getElementType(); 2658 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2659 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2660 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2661 2662 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2663 unsigned OldNumElts = VecTy.getNumElements(); 2664 2665 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2666 if (NewNumElts < OldNumElts) { 2667 if (NewEltSize % OldEltSize != 0) 2668 return UnableToLegalize; 2669 2670 // This only depends on powers of 2 because we use bit tricks to figure out 2671 // the bit offset we need to shift to get the target element. A general 2672 // expansion could emit division/multiply. 2673 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2674 return UnableToLegalize; 2675 2676 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2677 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2678 2679 // Divide to get the index in the wider element type. 2680 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2681 2682 Register ExtractedElt = CastVec; 2683 if (CastTy.isVector()) { 2684 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2685 ScaledIdx).getReg(0); 2686 } 2687 2688 // Compute the bit offset into the register of the target element. 2689 Register OffsetBits = getBitcastWiderVectorElementOffset( 2690 MIRBuilder, Idx, NewEltSize, OldEltSize); 2691 2692 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2693 Val, OffsetBits); 2694 if (CastTy.isVector()) { 2695 InsertedElt = MIRBuilder.buildInsertVectorElement( 2696 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2697 } 2698 2699 MIRBuilder.buildBitcast(Dst, InsertedElt); 2700 MI.eraseFromParent(); 2701 return Legalized; 2702 } 2703 2704 return UnableToLegalize; 2705 } 2706 2707 LegalizerHelper::LegalizeResult 2708 LegalizerHelper::lowerLoad(MachineInstr &MI) { 2709 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2710 Register DstReg = MI.getOperand(0).getReg(); 2711 Register PtrReg = MI.getOperand(1).getReg(); 2712 LLT DstTy = MRI.getType(DstReg); 2713 auto &MMO = **MI.memoperands_begin(); 2714 2715 if (DstTy.getSizeInBits() == MMO.getSizeInBits()) { 2716 if (MI.getOpcode() == TargetOpcode::G_LOAD) { 2717 // This load needs splitting into power of 2 sized loads. 2718 if (DstTy.isVector()) 2719 return UnableToLegalize; 2720 if (isPowerOf2_32(DstTy.getSizeInBits())) 2721 return UnableToLegalize; // Don't know what we're being asked to do. 2722 2723 // Our strategy here is to generate anyextending loads for the smaller 2724 // types up to next power-2 result type, and then combine the two larger 2725 // result values together, before truncating back down to the non-pow-2 2726 // type. 2727 // E.g. v1 = i24 load => 2728 // v2 = i32 zextload (2 byte) 2729 // v3 = i32 load (1 byte) 2730 // v4 = i32 shl v3, 16 2731 // v5 = i32 or v4, v2 2732 // v1 = i24 trunc v5 2733 // By doing this we generate the correct truncate which should get 2734 // combined away as an artifact with a matching extend. 2735 uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits()); 2736 uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize; 2737 2738 MachineFunction &MF = MIRBuilder.getMF(); 2739 MachineMemOperand *LargeMMO = 2740 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2741 MachineMemOperand *SmallMMO = MF.getMachineMemOperand( 2742 &MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2743 2744 LLT PtrTy = MRI.getType(PtrReg); 2745 unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits()); 2746 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2747 Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2748 Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2749 auto LargeLoad = MIRBuilder.buildLoadInstr( 2750 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO); 2751 2752 auto OffsetCst = MIRBuilder.buildConstant( 2753 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2754 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2755 auto SmallPtr = 2756 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2757 auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0), 2758 *SmallMMO); 2759 2760 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2761 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2762 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2763 MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)}); 2764 MI.eraseFromParent(); 2765 return Legalized; 2766 } 2767 2768 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); 2769 MI.eraseFromParent(); 2770 return Legalized; 2771 } 2772 2773 if (DstTy.isScalar()) { 2774 Register TmpReg = 2775 MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits())); 2776 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 2777 switch (MI.getOpcode()) { 2778 default: 2779 llvm_unreachable("Unexpected opcode"); 2780 case TargetOpcode::G_LOAD: 2781 MIRBuilder.buildAnyExtOrTrunc(DstReg, TmpReg); 2782 break; 2783 case TargetOpcode::G_SEXTLOAD: 2784 MIRBuilder.buildSExt(DstReg, TmpReg); 2785 break; 2786 case TargetOpcode::G_ZEXTLOAD: 2787 MIRBuilder.buildZExt(DstReg, TmpReg); 2788 break; 2789 } 2790 2791 MI.eraseFromParent(); 2792 return Legalized; 2793 } 2794 2795 return UnableToLegalize; 2796 } 2797 2798 LegalizerHelper::LegalizeResult 2799 LegalizerHelper::lowerStore(MachineInstr &MI) { 2800 // Lower a non-power of 2 store into multiple pow-2 stores. 2801 // E.g. split an i24 store into an i16 store + i8 store. 2802 // We do this by first extending the stored value to the next largest power 2803 // of 2 type, and then using truncating stores to store the components. 2804 // By doing this, likewise with G_LOAD, generate an extend that can be 2805 // artifact-combined away instead of leaving behind extracts. 2806 Register SrcReg = MI.getOperand(0).getReg(); 2807 Register PtrReg = MI.getOperand(1).getReg(); 2808 LLT SrcTy = MRI.getType(SrcReg); 2809 MachineMemOperand &MMO = **MI.memoperands_begin(); 2810 if (SrcTy.getSizeInBits() != MMO.getSizeInBits()) 2811 return UnableToLegalize; 2812 if (SrcTy.isVector()) 2813 return UnableToLegalize; 2814 if (isPowerOf2_32(SrcTy.getSizeInBits())) 2815 return UnableToLegalize; // Don't know what we're being asked to do. 2816 2817 // Extend to the next pow-2. 2818 const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits())); 2819 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2820 2821 // Obtain the smaller value by shifting away the larger value. 2822 uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits()); 2823 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2824 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2825 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2826 2827 // Generate the PtrAdd and truncating stores. 2828 LLT PtrTy = MRI.getType(PtrReg); 2829 auto OffsetCst = MIRBuilder.buildConstant( 2830 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2831 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2832 auto SmallPtr = 2833 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2834 2835 MachineFunction &MF = MIRBuilder.getMF(); 2836 MachineMemOperand *LargeMMO = 2837 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2838 MachineMemOperand *SmallMMO = 2839 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2840 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO); 2841 MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO); 2842 MI.eraseFromParent(); 2843 return Legalized; 2844 } 2845 2846 LegalizerHelper::LegalizeResult 2847 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2848 switch (MI.getOpcode()) { 2849 case TargetOpcode::G_LOAD: { 2850 if (TypeIdx != 0) 2851 return UnableToLegalize; 2852 2853 Observer.changingInstr(MI); 2854 bitcastDst(MI, CastTy, 0); 2855 Observer.changedInstr(MI); 2856 return Legalized; 2857 } 2858 case TargetOpcode::G_STORE: { 2859 if (TypeIdx != 0) 2860 return UnableToLegalize; 2861 2862 Observer.changingInstr(MI); 2863 bitcastSrc(MI, CastTy, 0); 2864 Observer.changedInstr(MI); 2865 return Legalized; 2866 } 2867 case TargetOpcode::G_SELECT: { 2868 if (TypeIdx != 0) 2869 return UnableToLegalize; 2870 2871 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 2872 LLVM_DEBUG( 2873 dbgs() << "bitcast action not implemented for vector select\n"); 2874 return UnableToLegalize; 2875 } 2876 2877 Observer.changingInstr(MI); 2878 bitcastSrc(MI, CastTy, 2); 2879 bitcastSrc(MI, CastTy, 3); 2880 bitcastDst(MI, CastTy, 0); 2881 Observer.changedInstr(MI); 2882 return Legalized; 2883 } 2884 case TargetOpcode::G_AND: 2885 case TargetOpcode::G_OR: 2886 case TargetOpcode::G_XOR: { 2887 Observer.changingInstr(MI); 2888 bitcastSrc(MI, CastTy, 1); 2889 bitcastSrc(MI, CastTy, 2); 2890 bitcastDst(MI, CastTy, 0); 2891 Observer.changedInstr(MI); 2892 return Legalized; 2893 } 2894 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 2895 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 2896 case TargetOpcode::G_INSERT_VECTOR_ELT: 2897 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 2898 default: 2899 return UnableToLegalize; 2900 } 2901 } 2902 2903 // Legalize an instruction by changing the opcode in place. 2904 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 2905 Observer.changingInstr(MI); 2906 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 2907 Observer.changedInstr(MI); 2908 } 2909 2910 LegalizerHelper::LegalizeResult 2911 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 2912 using namespace TargetOpcode; 2913 2914 switch(MI.getOpcode()) { 2915 default: 2916 return UnableToLegalize; 2917 case TargetOpcode::G_BITCAST: 2918 return lowerBitcast(MI); 2919 case TargetOpcode::G_SREM: 2920 case TargetOpcode::G_UREM: { 2921 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2922 auto Quot = 2923 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 2924 {MI.getOperand(1), MI.getOperand(2)}); 2925 2926 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 2927 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 2928 MI.eraseFromParent(); 2929 return Legalized; 2930 } 2931 case TargetOpcode::G_SADDO: 2932 case TargetOpcode::G_SSUBO: 2933 return lowerSADDO_SSUBO(MI); 2934 case TargetOpcode::G_UMULH: 2935 case TargetOpcode::G_SMULH: 2936 return lowerSMULH_UMULH(MI); 2937 case TargetOpcode::G_SMULO: 2938 case TargetOpcode::G_UMULO: { 2939 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 2940 // result. 2941 Register Res = MI.getOperand(0).getReg(); 2942 Register Overflow = MI.getOperand(1).getReg(); 2943 Register LHS = MI.getOperand(2).getReg(); 2944 Register RHS = MI.getOperand(3).getReg(); 2945 LLT Ty = MRI.getType(Res); 2946 2947 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 2948 ? TargetOpcode::G_SMULH 2949 : TargetOpcode::G_UMULH; 2950 2951 Observer.changingInstr(MI); 2952 const auto &TII = MIRBuilder.getTII(); 2953 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 2954 MI.RemoveOperand(1); 2955 Observer.changedInstr(MI); 2956 2957 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 2958 auto Zero = MIRBuilder.buildConstant(Ty, 0); 2959 2960 // Move insert point forward so we can use the Res register if needed. 2961 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2962 2963 // For *signed* multiply, overflow is detected by checking: 2964 // (hi != (lo >> bitwidth-1)) 2965 if (Opcode == TargetOpcode::G_SMULH) { 2966 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 2967 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 2968 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 2969 } else { 2970 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 2971 } 2972 return Legalized; 2973 } 2974 case TargetOpcode::G_FNEG: { 2975 Register Res = MI.getOperand(0).getReg(); 2976 LLT Ty = MRI.getType(Res); 2977 2978 // TODO: Handle vector types once we are able to 2979 // represent them. 2980 if (Ty.isVector()) 2981 return UnableToLegalize; 2982 auto SignMask = 2983 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 2984 Register SubByReg = MI.getOperand(1).getReg(); 2985 MIRBuilder.buildXor(Res, SubByReg, SignMask); 2986 MI.eraseFromParent(); 2987 return Legalized; 2988 } 2989 case TargetOpcode::G_FSUB: { 2990 Register Res = MI.getOperand(0).getReg(); 2991 LLT Ty = MRI.getType(Res); 2992 2993 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 2994 // First, check if G_FNEG is marked as Lower. If so, we may 2995 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 2996 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 2997 return UnableToLegalize; 2998 Register LHS = MI.getOperand(1).getReg(); 2999 Register RHS = MI.getOperand(2).getReg(); 3000 Register Neg = MRI.createGenericVirtualRegister(Ty); 3001 MIRBuilder.buildFNeg(Neg, RHS); 3002 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3003 MI.eraseFromParent(); 3004 return Legalized; 3005 } 3006 case TargetOpcode::G_FMAD: 3007 return lowerFMad(MI); 3008 case TargetOpcode::G_FFLOOR: 3009 return lowerFFloor(MI); 3010 case TargetOpcode::G_INTRINSIC_ROUND: 3011 return lowerIntrinsicRound(MI); 3012 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3013 // Since round even is the assumed rounding mode for unconstrained FP 3014 // operations, rint and roundeven are the same operation. 3015 changeOpcode(MI, TargetOpcode::G_FRINT); 3016 return Legalized; 3017 } 3018 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3019 Register OldValRes = MI.getOperand(0).getReg(); 3020 Register SuccessRes = MI.getOperand(1).getReg(); 3021 Register Addr = MI.getOperand(2).getReg(); 3022 Register CmpVal = MI.getOperand(3).getReg(); 3023 Register NewVal = MI.getOperand(4).getReg(); 3024 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3025 **MI.memoperands_begin()); 3026 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3027 MI.eraseFromParent(); 3028 return Legalized; 3029 } 3030 case TargetOpcode::G_LOAD: 3031 case TargetOpcode::G_SEXTLOAD: 3032 case TargetOpcode::G_ZEXTLOAD: 3033 return lowerLoad(MI); 3034 case TargetOpcode::G_STORE: 3035 return lowerStore(MI); 3036 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3037 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3038 case TargetOpcode::G_CTLZ: 3039 case TargetOpcode::G_CTTZ: 3040 case TargetOpcode::G_CTPOP: 3041 return lowerBitCount(MI); 3042 case G_UADDO: { 3043 Register Res = MI.getOperand(0).getReg(); 3044 Register CarryOut = MI.getOperand(1).getReg(); 3045 Register LHS = MI.getOperand(2).getReg(); 3046 Register RHS = MI.getOperand(3).getReg(); 3047 3048 MIRBuilder.buildAdd(Res, LHS, RHS); 3049 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3050 3051 MI.eraseFromParent(); 3052 return Legalized; 3053 } 3054 case G_UADDE: { 3055 Register Res = MI.getOperand(0).getReg(); 3056 Register CarryOut = MI.getOperand(1).getReg(); 3057 Register LHS = MI.getOperand(2).getReg(); 3058 Register RHS = MI.getOperand(3).getReg(); 3059 Register CarryIn = MI.getOperand(4).getReg(); 3060 LLT Ty = MRI.getType(Res); 3061 3062 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3063 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3064 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3065 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3066 3067 MI.eraseFromParent(); 3068 return Legalized; 3069 } 3070 case G_USUBO: { 3071 Register Res = MI.getOperand(0).getReg(); 3072 Register BorrowOut = MI.getOperand(1).getReg(); 3073 Register LHS = MI.getOperand(2).getReg(); 3074 Register RHS = MI.getOperand(3).getReg(); 3075 3076 MIRBuilder.buildSub(Res, LHS, RHS); 3077 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3078 3079 MI.eraseFromParent(); 3080 return Legalized; 3081 } 3082 case G_USUBE: { 3083 Register Res = MI.getOperand(0).getReg(); 3084 Register BorrowOut = MI.getOperand(1).getReg(); 3085 Register LHS = MI.getOperand(2).getReg(); 3086 Register RHS = MI.getOperand(3).getReg(); 3087 Register BorrowIn = MI.getOperand(4).getReg(); 3088 const LLT CondTy = MRI.getType(BorrowOut); 3089 const LLT Ty = MRI.getType(Res); 3090 3091 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3092 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3093 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3094 3095 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3096 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3097 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3098 3099 MI.eraseFromParent(); 3100 return Legalized; 3101 } 3102 case G_UITOFP: 3103 return lowerUITOFP(MI); 3104 case G_SITOFP: 3105 return lowerSITOFP(MI); 3106 case G_FPTOUI: 3107 return lowerFPTOUI(MI); 3108 case G_FPTOSI: 3109 return lowerFPTOSI(MI); 3110 case G_FPTRUNC: 3111 return lowerFPTRUNC(MI); 3112 case G_FPOWI: 3113 return lowerFPOWI(MI); 3114 case G_SMIN: 3115 case G_SMAX: 3116 case G_UMIN: 3117 case G_UMAX: 3118 return lowerMinMax(MI); 3119 case G_FCOPYSIGN: 3120 return lowerFCopySign(MI); 3121 case G_FMINNUM: 3122 case G_FMAXNUM: 3123 return lowerFMinNumMaxNum(MI); 3124 case G_MERGE_VALUES: 3125 return lowerMergeValues(MI); 3126 case G_UNMERGE_VALUES: 3127 return lowerUnmergeValues(MI); 3128 case TargetOpcode::G_SEXT_INREG: { 3129 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3130 int64_t SizeInBits = MI.getOperand(2).getImm(); 3131 3132 Register DstReg = MI.getOperand(0).getReg(); 3133 Register SrcReg = MI.getOperand(1).getReg(); 3134 LLT DstTy = MRI.getType(DstReg); 3135 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3136 3137 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3138 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3139 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3140 MI.eraseFromParent(); 3141 return Legalized; 3142 } 3143 case G_EXTRACT_VECTOR_ELT: 3144 case G_INSERT_VECTOR_ELT: 3145 return lowerExtractInsertVectorElt(MI); 3146 case G_SHUFFLE_VECTOR: 3147 return lowerShuffleVector(MI); 3148 case G_DYN_STACKALLOC: 3149 return lowerDynStackAlloc(MI); 3150 case G_EXTRACT: 3151 return lowerExtract(MI); 3152 case G_INSERT: 3153 return lowerInsert(MI); 3154 case G_BSWAP: 3155 return lowerBswap(MI); 3156 case G_BITREVERSE: 3157 return lowerBitreverse(MI); 3158 case G_READ_REGISTER: 3159 case G_WRITE_REGISTER: 3160 return lowerReadWriteRegister(MI); 3161 case G_UADDSAT: 3162 case G_USUBSAT: { 3163 // Try to make a reasonable guess about which lowering strategy to use. The 3164 // target can override this with custom lowering and calling the 3165 // implementation functions. 3166 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3167 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3168 return lowerAddSubSatToMinMax(MI); 3169 return lowerAddSubSatToAddoSubo(MI); 3170 } 3171 case G_SADDSAT: 3172 case G_SSUBSAT: { 3173 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3174 3175 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3176 // since it's a shorter expansion. However, we would need to figure out the 3177 // preferred boolean type for the carry out for the query. 3178 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3179 return lowerAddSubSatToMinMax(MI); 3180 return lowerAddSubSatToAddoSubo(MI); 3181 } 3182 case G_SSHLSAT: 3183 case G_USHLSAT: 3184 return lowerShlSat(MI); 3185 case G_ABS: { 3186 // Expand %res = G_ABS %a into: 3187 // %v1 = G_ASHR %a, scalar_size-1 3188 // %v2 = G_ADD %a, %v1 3189 // %res = G_XOR %v2, %v1 3190 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3191 Register OpReg = MI.getOperand(1).getReg(); 3192 auto ShiftAmt = 3193 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 3194 auto Shift = 3195 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 3196 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 3197 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 3198 MI.eraseFromParent(); 3199 return Legalized; 3200 } 3201 case G_SELECT: 3202 return lowerSelect(MI); 3203 } 3204 } 3205 3206 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3207 Align MinAlign) const { 3208 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3209 // datalayout for the preferred alignment. Also there should be a target hook 3210 // for this to allow targets to reduce the alignment and ignore the 3211 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3212 // the type. 3213 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3214 } 3215 3216 MachineInstrBuilder 3217 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3218 MachinePointerInfo &PtrInfo) { 3219 MachineFunction &MF = MIRBuilder.getMF(); 3220 const DataLayout &DL = MIRBuilder.getDataLayout(); 3221 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3222 3223 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3224 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3225 3226 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3227 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3228 } 3229 3230 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3231 LLT VecTy) { 3232 int64_t IdxVal; 3233 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3234 return IdxReg; 3235 3236 LLT IdxTy = B.getMRI()->getType(IdxReg); 3237 unsigned NElts = VecTy.getNumElements(); 3238 if (isPowerOf2_32(NElts)) { 3239 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3240 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3241 } 3242 3243 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3244 .getReg(0); 3245 } 3246 3247 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3248 Register Index) { 3249 LLT EltTy = VecTy.getElementType(); 3250 3251 // Calculate the element offset and add it to the pointer. 3252 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3253 assert(EltSize * 8 == EltTy.getSizeInBits() && 3254 "Converting bits to bytes lost precision"); 3255 3256 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3257 3258 LLT IdxTy = MRI.getType(Index); 3259 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3260 MIRBuilder.buildConstant(IdxTy, EltSize)); 3261 3262 LLT PtrTy = MRI.getType(VecPtr); 3263 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3264 } 3265 3266 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3267 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3268 Register DstReg = MI.getOperand(0).getReg(); 3269 LLT DstTy = MRI.getType(DstReg); 3270 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3271 3272 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3273 3274 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3275 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3276 3277 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3278 MI.eraseFromParent(); 3279 return Legalized; 3280 } 3281 3282 // Handle splitting vector operations which need to have the same number of 3283 // elements in each type index, but each type index may have a different element 3284 // type. 3285 // 3286 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3287 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3288 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3289 // 3290 // Also handles some irregular breakdown cases, e.g. 3291 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3292 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3293 // s64 = G_SHL s64, s32 3294 LegalizerHelper::LegalizeResult 3295 LegalizerHelper::fewerElementsVectorMultiEltType( 3296 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3297 if (TypeIdx != 0) 3298 return UnableToLegalize; 3299 3300 const LLT NarrowTy0 = NarrowTyArg; 3301 const unsigned NewNumElts = 3302 NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1; 3303 3304 const Register DstReg = MI.getOperand(0).getReg(); 3305 LLT DstTy = MRI.getType(DstReg); 3306 LLT LeftoverTy0; 3307 3308 // All of the operands need to have the same number of elements, so if we can 3309 // determine a type breakdown for the result type, we can for all of the 3310 // source types. 3311 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3312 if (NumParts < 0) 3313 return UnableToLegalize; 3314 3315 SmallVector<MachineInstrBuilder, 4> NewInsts; 3316 3317 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3318 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3319 3320 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3321 Register SrcReg = MI.getOperand(I).getReg(); 3322 LLT SrcTyI = MRI.getType(SrcReg); 3323 LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType()); 3324 LLT LeftoverTyI; 3325 3326 // Split this operand into the requested typed registers, and any leftover 3327 // required to reproduce the original type. 3328 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3329 LeftoverRegs)) 3330 return UnableToLegalize; 3331 3332 if (I == 1) { 3333 // For the first operand, create an instruction for each part and setup 3334 // the result. 3335 for (Register PartReg : PartRegs) { 3336 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3337 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3338 .addDef(PartDstReg) 3339 .addUse(PartReg)); 3340 DstRegs.push_back(PartDstReg); 3341 } 3342 3343 for (Register LeftoverReg : LeftoverRegs) { 3344 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3345 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3346 .addDef(PartDstReg) 3347 .addUse(LeftoverReg)); 3348 LeftoverDstRegs.push_back(PartDstReg); 3349 } 3350 } else { 3351 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3352 3353 // Add the newly created operand splits to the existing instructions. The 3354 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3355 // pieces. 3356 unsigned InstCount = 0; 3357 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3358 NewInsts[InstCount++].addUse(PartRegs[J]); 3359 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3360 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3361 } 3362 3363 PartRegs.clear(); 3364 LeftoverRegs.clear(); 3365 } 3366 3367 // Insert the newly built operations and rebuild the result register. 3368 for (auto &MIB : NewInsts) 3369 MIRBuilder.insertInstr(MIB); 3370 3371 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3372 3373 MI.eraseFromParent(); 3374 return Legalized; 3375 } 3376 3377 LegalizerHelper::LegalizeResult 3378 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3379 LLT NarrowTy) { 3380 if (TypeIdx != 0) 3381 return UnableToLegalize; 3382 3383 Register DstReg = MI.getOperand(0).getReg(); 3384 Register SrcReg = MI.getOperand(1).getReg(); 3385 LLT DstTy = MRI.getType(DstReg); 3386 LLT SrcTy = MRI.getType(SrcReg); 3387 3388 LLT NarrowTy0 = NarrowTy; 3389 LLT NarrowTy1; 3390 unsigned NumParts; 3391 3392 if (NarrowTy.isVector()) { 3393 // Uneven breakdown not handled. 3394 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3395 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3396 return UnableToLegalize; 3397 3398 NarrowTy1 = LLT::vector(NarrowTy.getNumElements(), SrcTy.getElementType()); 3399 } else { 3400 NumParts = DstTy.getNumElements(); 3401 NarrowTy1 = SrcTy.getElementType(); 3402 } 3403 3404 SmallVector<Register, 4> SrcRegs, DstRegs; 3405 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3406 3407 for (unsigned I = 0; I < NumParts; ++I) { 3408 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3409 MachineInstr *NewInst = 3410 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3411 3412 NewInst->setFlags(MI.getFlags()); 3413 DstRegs.push_back(DstReg); 3414 } 3415 3416 if (NarrowTy.isVector()) 3417 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3418 else 3419 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3420 3421 MI.eraseFromParent(); 3422 return Legalized; 3423 } 3424 3425 LegalizerHelper::LegalizeResult 3426 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3427 LLT NarrowTy) { 3428 Register DstReg = MI.getOperand(0).getReg(); 3429 Register Src0Reg = MI.getOperand(2).getReg(); 3430 LLT DstTy = MRI.getType(DstReg); 3431 LLT SrcTy = MRI.getType(Src0Reg); 3432 3433 unsigned NumParts; 3434 LLT NarrowTy0, NarrowTy1; 3435 3436 if (TypeIdx == 0) { 3437 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3438 unsigned OldElts = DstTy.getNumElements(); 3439 3440 NarrowTy0 = NarrowTy; 3441 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3442 NarrowTy1 = NarrowTy.isVector() ? 3443 LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) : 3444 SrcTy.getElementType(); 3445 3446 } else { 3447 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3448 unsigned OldElts = SrcTy.getNumElements(); 3449 3450 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3451 NarrowTy.getNumElements(); 3452 NarrowTy0 = LLT::vector(NarrowTy.getNumElements(), 3453 DstTy.getScalarSizeInBits()); 3454 NarrowTy1 = NarrowTy; 3455 } 3456 3457 // FIXME: Don't know how to handle the situation where the small vectors 3458 // aren't all the same size yet. 3459 if (NarrowTy1.isVector() && 3460 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3461 return UnableToLegalize; 3462 3463 CmpInst::Predicate Pred 3464 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3465 3466 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3467 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3468 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3469 3470 for (unsigned I = 0; I < NumParts; ++I) { 3471 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3472 DstRegs.push_back(DstReg); 3473 3474 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3475 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3476 else { 3477 MachineInstr *NewCmp 3478 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3479 NewCmp->setFlags(MI.getFlags()); 3480 } 3481 } 3482 3483 if (NarrowTy1.isVector()) 3484 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3485 else 3486 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3487 3488 MI.eraseFromParent(); 3489 return Legalized; 3490 } 3491 3492 LegalizerHelper::LegalizeResult 3493 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3494 LLT NarrowTy) { 3495 Register DstReg = MI.getOperand(0).getReg(); 3496 Register CondReg = MI.getOperand(1).getReg(); 3497 3498 unsigned NumParts = 0; 3499 LLT NarrowTy0, NarrowTy1; 3500 3501 LLT DstTy = MRI.getType(DstReg); 3502 LLT CondTy = MRI.getType(CondReg); 3503 unsigned Size = DstTy.getSizeInBits(); 3504 3505 assert(TypeIdx == 0 || CondTy.isVector()); 3506 3507 if (TypeIdx == 0) { 3508 NarrowTy0 = NarrowTy; 3509 NarrowTy1 = CondTy; 3510 3511 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3512 // FIXME: Don't know how to handle the situation where the small vectors 3513 // aren't all the same size yet. 3514 if (Size % NarrowSize != 0) 3515 return UnableToLegalize; 3516 3517 NumParts = Size / NarrowSize; 3518 3519 // Need to break down the condition type 3520 if (CondTy.isVector()) { 3521 if (CondTy.getNumElements() == NumParts) 3522 NarrowTy1 = CondTy.getElementType(); 3523 else 3524 NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts, 3525 CondTy.getScalarSizeInBits()); 3526 } 3527 } else { 3528 NumParts = CondTy.getNumElements(); 3529 if (NarrowTy.isVector()) { 3530 // TODO: Handle uneven breakdown. 3531 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3532 return UnableToLegalize; 3533 3534 return UnableToLegalize; 3535 } else { 3536 NarrowTy0 = DstTy.getElementType(); 3537 NarrowTy1 = NarrowTy; 3538 } 3539 } 3540 3541 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3542 if (CondTy.isVector()) 3543 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3544 3545 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3546 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3547 3548 for (unsigned i = 0; i < NumParts; ++i) { 3549 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3550 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3551 Src1Regs[i], Src2Regs[i]); 3552 DstRegs.push_back(DstReg); 3553 } 3554 3555 if (NarrowTy0.isVector()) 3556 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3557 else 3558 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3559 3560 MI.eraseFromParent(); 3561 return Legalized; 3562 } 3563 3564 LegalizerHelper::LegalizeResult 3565 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3566 LLT NarrowTy) { 3567 const Register DstReg = MI.getOperand(0).getReg(); 3568 LLT PhiTy = MRI.getType(DstReg); 3569 LLT LeftoverTy; 3570 3571 // All of the operands need to have the same number of elements, so if we can 3572 // determine a type breakdown for the result type, we can for all of the 3573 // source types. 3574 int NumParts, NumLeftover; 3575 std::tie(NumParts, NumLeftover) 3576 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3577 if (NumParts < 0) 3578 return UnableToLegalize; 3579 3580 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3581 SmallVector<MachineInstrBuilder, 4> NewInsts; 3582 3583 const int TotalNumParts = NumParts + NumLeftover; 3584 3585 // Insert the new phis in the result block first. 3586 for (int I = 0; I != TotalNumParts; ++I) { 3587 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3588 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3589 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3590 .addDef(PartDstReg)); 3591 if (I < NumParts) 3592 DstRegs.push_back(PartDstReg); 3593 else 3594 LeftoverDstRegs.push_back(PartDstReg); 3595 } 3596 3597 MachineBasicBlock *MBB = MI.getParent(); 3598 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3599 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3600 3601 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3602 3603 // Insert code to extract the incoming values in each predecessor block. 3604 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3605 PartRegs.clear(); 3606 LeftoverRegs.clear(); 3607 3608 Register SrcReg = MI.getOperand(I).getReg(); 3609 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3610 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3611 3612 LLT Unused; 3613 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3614 LeftoverRegs)) 3615 return UnableToLegalize; 3616 3617 // Add the newly created operand splits to the existing instructions. The 3618 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3619 // pieces. 3620 for (int J = 0; J != TotalNumParts; ++J) { 3621 MachineInstrBuilder MIB = NewInsts[J]; 3622 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3623 MIB.addMBB(&OpMBB); 3624 } 3625 } 3626 3627 MI.eraseFromParent(); 3628 return Legalized; 3629 } 3630 3631 LegalizerHelper::LegalizeResult 3632 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3633 unsigned TypeIdx, 3634 LLT NarrowTy) { 3635 if (TypeIdx != 1) 3636 return UnableToLegalize; 3637 3638 const int NumDst = MI.getNumOperands() - 1; 3639 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3640 LLT SrcTy = MRI.getType(SrcReg); 3641 3642 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3643 3644 // TODO: Create sequence of extracts. 3645 if (DstTy == NarrowTy) 3646 return UnableToLegalize; 3647 3648 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3649 if (DstTy == GCDTy) { 3650 // This would just be a copy of the same unmerge. 3651 // TODO: Create extracts, pad with undef and create intermediate merges. 3652 return UnableToLegalize; 3653 } 3654 3655 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3656 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3657 const int PartsPerUnmerge = NumDst / NumUnmerge; 3658 3659 for (int I = 0; I != NumUnmerge; ++I) { 3660 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3661 3662 for (int J = 0; J != PartsPerUnmerge; ++J) 3663 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3664 MIB.addUse(Unmerge.getReg(I)); 3665 } 3666 3667 MI.eraseFromParent(); 3668 return Legalized; 3669 } 3670 3671 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3672 // a vector 3673 // 3674 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3675 // undef as necessary. 3676 // 3677 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3678 // -> <2 x s16> 3679 // 3680 // %4:_(s16) = G_IMPLICIT_DEF 3681 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3682 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3683 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3684 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3685 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3686 LegalizerHelper::LegalizeResult 3687 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3688 LLT NarrowTy) { 3689 Register DstReg = MI.getOperand(0).getReg(); 3690 LLT DstTy = MRI.getType(DstReg); 3691 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3692 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3693 3694 // Break into a common type 3695 SmallVector<Register, 16> Parts; 3696 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3697 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3698 3699 // Build the requested new merge, padding with undef. 3700 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3701 TargetOpcode::G_ANYEXT); 3702 3703 // Pack into the original result register. 3704 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3705 3706 MI.eraseFromParent(); 3707 return Legalized; 3708 } 3709 3710 LegalizerHelper::LegalizeResult 3711 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3712 unsigned TypeIdx, 3713 LLT NarrowVecTy) { 3714 Register DstReg = MI.getOperand(0).getReg(); 3715 Register SrcVec = MI.getOperand(1).getReg(); 3716 Register InsertVal; 3717 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3718 3719 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3720 if (IsInsert) 3721 InsertVal = MI.getOperand(2).getReg(); 3722 3723 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3724 3725 // TODO: Handle total scalarization case. 3726 if (!NarrowVecTy.isVector()) 3727 return UnableToLegalize; 3728 3729 LLT VecTy = MRI.getType(SrcVec); 3730 3731 // If the index is a constant, we can really break this down as you would 3732 // expect, and index into the target size pieces. 3733 int64_t IdxVal; 3734 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 3735 // Avoid out of bounds indexing the pieces. 3736 if (IdxVal >= VecTy.getNumElements()) { 3737 MIRBuilder.buildUndef(DstReg); 3738 MI.eraseFromParent(); 3739 return Legalized; 3740 } 3741 3742 SmallVector<Register, 8> VecParts; 3743 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3744 3745 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3746 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3747 TargetOpcode::G_ANYEXT); 3748 3749 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3750 3751 LLT IdxTy = MRI.getType(Idx); 3752 int64_t PartIdx = IdxVal / NewNumElts; 3753 auto NewIdx = 3754 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3755 3756 if (IsInsert) { 3757 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3758 3759 // Use the adjusted index to insert into one of the subvectors. 3760 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3761 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3762 VecParts[PartIdx] = InsertPart.getReg(0); 3763 3764 // Recombine the inserted subvector with the others to reform the result 3765 // vector. 3766 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3767 } else { 3768 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3769 } 3770 3771 MI.eraseFromParent(); 3772 return Legalized; 3773 } 3774 3775 // With a variable index, we can't perform the operation in a smaller type, so 3776 // we're forced to expand this. 3777 // 3778 // TODO: We could emit a chain of compare/select to figure out which piece to 3779 // index. 3780 return lowerExtractInsertVectorElt(MI); 3781 } 3782 3783 LegalizerHelper::LegalizeResult 3784 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, 3785 LLT NarrowTy) { 3786 // FIXME: Don't know how to handle secondary types yet. 3787 if (TypeIdx != 0) 3788 return UnableToLegalize; 3789 3790 MachineMemOperand *MMO = *MI.memoperands_begin(); 3791 3792 // This implementation doesn't work for atomics. Give up instead of doing 3793 // something invalid. 3794 if (MMO->getOrdering() != AtomicOrdering::NotAtomic || 3795 MMO->getFailureOrdering() != AtomicOrdering::NotAtomic) 3796 return UnableToLegalize; 3797 3798 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; 3799 Register ValReg = MI.getOperand(0).getReg(); 3800 Register AddrReg = MI.getOperand(1).getReg(); 3801 LLT ValTy = MRI.getType(ValReg); 3802 3803 // FIXME: Do we need a distinct NarrowMemory legalize action? 3804 if (ValTy.getSizeInBits() != 8 * MMO->getSize()) { 3805 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3806 return UnableToLegalize; 3807 } 3808 3809 int NumParts = -1; 3810 int NumLeftover = -1; 3811 LLT LeftoverTy; 3812 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3813 if (IsLoad) { 3814 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3815 } else { 3816 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3817 NarrowLeftoverRegs)) { 3818 NumParts = NarrowRegs.size(); 3819 NumLeftover = NarrowLeftoverRegs.size(); 3820 } 3821 } 3822 3823 if (NumParts == -1) 3824 return UnableToLegalize; 3825 3826 LLT PtrTy = MRI.getType(AddrReg); 3827 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 3828 3829 unsigned TotalSize = ValTy.getSizeInBits(); 3830 3831 // Split the load/store into PartTy sized pieces starting at Offset. If this 3832 // is a load, return the new registers in ValRegs. For a store, each elements 3833 // of ValRegs should be PartTy. Returns the next offset that needs to be 3834 // handled. 3835 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3836 unsigned Offset) -> unsigned { 3837 MachineFunction &MF = MIRBuilder.getMF(); 3838 unsigned PartSize = PartTy.getSizeInBits(); 3839 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 3840 Offset += PartSize, ++Idx) { 3841 unsigned ByteSize = PartSize / 8; 3842 unsigned ByteOffset = Offset / 8; 3843 Register NewAddrReg; 3844 3845 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 3846 3847 MachineMemOperand *NewMMO = 3848 MF.getMachineMemOperand(MMO, ByteOffset, ByteSize); 3849 3850 if (IsLoad) { 3851 Register Dst = MRI.createGenericVirtualRegister(PartTy); 3852 ValRegs.push_back(Dst); 3853 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 3854 } else { 3855 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 3856 } 3857 } 3858 3859 return Offset; 3860 }; 3861 3862 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 3863 3864 // Handle the rest of the register if this isn't an even type breakdown. 3865 if (LeftoverTy.isValid()) 3866 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 3867 3868 if (IsLoad) { 3869 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 3870 LeftoverTy, NarrowLeftoverRegs); 3871 } 3872 3873 MI.eraseFromParent(); 3874 return Legalized; 3875 } 3876 3877 LegalizerHelper::LegalizeResult 3878 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 3879 LLT NarrowTy) { 3880 assert(TypeIdx == 0 && "only one type index expected"); 3881 3882 const unsigned Opc = MI.getOpcode(); 3883 const int NumOps = MI.getNumOperands() - 1; 3884 const Register DstReg = MI.getOperand(0).getReg(); 3885 const unsigned Flags = MI.getFlags(); 3886 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 3887 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 3888 3889 assert(NumOps <= 3 && "expected instruction with 1 result and 1-3 sources"); 3890 3891 // First of all check whether we are narrowing (changing the element type) 3892 // or reducing the vector elements 3893 const LLT DstTy = MRI.getType(DstReg); 3894 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 3895 3896 SmallVector<Register, 8> ExtractedRegs[3]; 3897 SmallVector<Register, 8> Parts; 3898 3899 unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3900 3901 // Break down all the sources into NarrowTy pieces we can operate on. This may 3902 // involve creating merges to a wider type, padded with undef. 3903 for (int I = 0; I != NumOps; ++I) { 3904 Register SrcReg = MI.getOperand(I + 1).getReg(); 3905 LLT SrcTy = MRI.getType(SrcReg); 3906 3907 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 3908 // For fewerElements, this is a smaller vector with the same element type. 3909 LLT OpNarrowTy; 3910 if (IsNarrow) { 3911 OpNarrowTy = NarrowScalarTy; 3912 3913 // In case of narrowing, we need to cast vectors to scalars for this to 3914 // work properly 3915 // FIXME: Can we do without the bitcast here if we're narrowing? 3916 if (SrcTy.isVector()) { 3917 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 3918 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 3919 } 3920 } else { 3921 OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType()); 3922 } 3923 3924 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 3925 3926 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 3927 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 3928 TargetOpcode::G_ANYEXT); 3929 } 3930 3931 SmallVector<Register, 8> ResultRegs; 3932 3933 // Input operands for each sub-instruction. 3934 SmallVector<SrcOp, 4> InputRegs(NumOps, Register()); 3935 3936 int NumParts = ExtractedRegs[0].size(); 3937 const unsigned DstSize = DstTy.getSizeInBits(); 3938 const LLT DstScalarTy = LLT::scalar(DstSize); 3939 3940 // Narrowing needs to use scalar types 3941 LLT DstLCMTy, NarrowDstTy; 3942 if (IsNarrow) { 3943 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 3944 NarrowDstTy = NarrowScalarTy; 3945 } else { 3946 DstLCMTy = getLCMType(DstTy, NarrowTy); 3947 NarrowDstTy = NarrowTy; 3948 } 3949 3950 // We widened the source registers to satisfy merge/unmerge size 3951 // constraints. We'll have some extra fully undef parts. 3952 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 3953 3954 for (int I = 0; I != NumRealParts; ++I) { 3955 // Emit this instruction on each of the split pieces. 3956 for (int J = 0; J != NumOps; ++J) 3957 InputRegs[J] = ExtractedRegs[J][I]; 3958 3959 auto Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 3960 ResultRegs.push_back(Inst.getReg(0)); 3961 } 3962 3963 // Fill out the widened result with undef instead of creating instructions 3964 // with undef inputs. 3965 int NumUndefParts = NumParts - NumRealParts; 3966 if (NumUndefParts != 0) 3967 ResultRegs.append(NumUndefParts, 3968 MIRBuilder.buildUndef(NarrowDstTy).getReg(0)); 3969 3970 // Extract the possibly padded result. Use a scratch register if we need to do 3971 // a final bitcast, otherwise use the original result register. 3972 Register MergeDstReg; 3973 if (IsNarrow && DstTy.isVector()) 3974 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 3975 else 3976 MergeDstReg = DstReg; 3977 3978 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs); 3979 3980 // Recast to vector if we narrowed a vector 3981 if (IsNarrow && DstTy.isVector()) 3982 MIRBuilder.buildBitcast(DstReg, MergeDstReg); 3983 3984 MI.eraseFromParent(); 3985 return Legalized; 3986 } 3987 3988 LegalizerHelper::LegalizeResult 3989 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 3990 LLT NarrowTy) { 3991 Register DstReg = MI.getOperand(0).getReg(); 3992 Register SrcReg = MI.getOperand(1).getReg(); 3993 int64_t Imm = MI.getOperand(2).getImm(); 3994 3995 LLT DstTy = MRI.getType(DstReg); 3996 3997 SmallVector<Register, 8> Parts; 3998 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 3999 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4000 4001 for (Register &R : Parts) 4002 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4003 4004 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4005 4006 MI.eraseFromParent(); 4007 return Legalized; 4008 } 4009 4010 LegalizerHelper::LegalizeResult 4011 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4012 LLT NarrowTy) { 4013 using namespace TargetOpcode; 4014 4015 switch (MI.getOpcode()) { 4016 case G_IMPLICIT_DEF: 4017 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4018 case G_TRUNC: 4019 case G_AND: 4020 case G_OR: 4021 case G_XOR: 4022 case G_ADD: 4023 case G_SUB: 4024 case G_MUL: 4025 case G_PTR_ADD: 4026 case G_SMULH: 4027 case G_UMULH: 4028 case G_FADD: 4029 case G_FMUL: 4030 case G_FSUB: 4031 case G_FNEG: 4032 case G_FABS: 4033 case G_FCANONICALIZE: 4034 case G_FDIV: 4035 case G_FREM: 4036 case G_FMA: 4037 case G_FMAD: 4038 case G_FPOW: 4039 case G_FEXP: 4040 case G_FEXP2: 4041 case G_FLOG: 4042 case G_FLOG2: 4043 case G_FLOG10: 4044 case G_FNEARBYINT: 4045 case G_FCEIL: 4046 case G_FFLOOR: 4047 case G_FRINT: 4048 case G_INTRINSIC_ROUND: 4049 case G_INTRINSIC_ROUNDEVEN: 4050 case G_INTRINSIC_TRUNC: 4051 case G_FCOS: 4052 case G_FSIN: 4053 case G_FSQRT: 4054 case G_BSWAP: 4055 case G_BITREVERSE: 4056 case G_SDIV: 4057 case G_UDIV: 4058 case G_SREM: 4059 case G_UREM: 4060 case G_SMIN: 4061 case G_SMAX: 4062 case G_UMIN: 4063 case G_UMAX: 4064 case G_FMINNUM: 4065 case G_FMAXNUM: 4066 case G_FMINNUM_IEEE: 4067 case G_FMAXNUM_IEEE: 4068 case G_FMINIMUM: 4069 case G_FMAXIMUM: 4070 case G_FSHL: 4071 case G_FSHR: 4072 case G_FREEZE: 4073 case G_SADDSAT: 4074 case G_SSUBSAT: 4075 case G_UADDSAT: 4076 case G_USUBSAT: 4077 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4078 case G_SHL: 4079 case G_LSHR: 4080 case G_ASHR: 4081 case G_SSHLSAT: 4082 case G_USHLSAT: 4083 case G_CTLZ: 4084 case G_CTLZ_ZERO_UNDEF: 4085 case G_CTTZ: 4086 case G_CTTZ_ZERO_UNDEF: 4087 case G_CTPOP: 4088 case G_FCOPYSIGN: 4089 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4090 case G_ZEXT: 4091 case G_SEXT: 4092 case G_ANYEXT: 4093 case G_FPEXT: 4094 case G_FPTRUNC: 4095 case G_SITOFP: 4096 case G_UITOFP: 4097 case G_FPTOSI: 4098 case G_FPTOUI: 4099 case G_INTTOPTR: 4100 case G_PTRTOINT: 4101 case G_ADDRSPACE_CAST: 4102 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4103 case G_ICMP: 4104 case G_FCMP: 4105 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4106 case G_SELECT: 4107 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4108 case G_PHI: 4109 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4110 case G_UNMERGE_VALUES: 4111 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4112 case G_BUILD_VECTOR: 4113 assert(TypeIdx == 0 && "not a vector type index"); 4114 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4115 case G_CONCAT_VECTORS: 4116 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4117 return UnableToLegalize; 4118 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4119 case G_EXTRACT_VECTOR_ELT: 4120 case G_INSERT_VECTOR_ELT: 4121 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4122 case G_LOAD: 4123 case G_STORE: 4124 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 4125 case G_SEXT_INREG: 4126 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4127 default: 4128 return UnableToLegalize; 4129 } 4130 } 4131 4132 LegalizerHelper::LegalizeResult 4133 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4134 const LLT HalfTy, const LLT AmtTy) { 4135 4136 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4137 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4138 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4139 4140 if (Amt.isNullValue()) { 4141 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4142 MI.eraseFromParent(); 4143 return Legalized; 4144 } 4145 4146 LLT NVT = HalfTy; 4147 unsigned NVTBits = HalfTy.getSizeInBits(); 4148 unsigned VTBits = 2 * NVTBits; 4149 4150 SrcOp Lo(Register(0)), Hi(Register(0)); 4151 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4152 if (Amt.ugt(VTBits)) { 4153 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4154 } else if (Amt.ugt(NVTBits)) { 4155 Lo = MIRBuilder.buildConstant(NVT, 0); 4156 Hi = MIRBuilder.buildShl(NVT, InL, 4157 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4158 } else if (Amt == NVTBits) { 4159 Lo = MIRBuilder.buildConstant(NVT, 0); 4160 Hi = InL; 4161 } else { 4162 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4163 auto OrLHS = 4164 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4165 auto OrRHS = MIRBuilder.buildLShr( 4166 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4167 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4168 } 4169 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4170 if (Amt.ugt(VTBits)) { 4171 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4172 } else if (Amt.ugt(NVTBits)) { 4173 Lo = MIRBuilder.buildLShr(NVT, InH, 4174 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4175 Hi = MIRBuilder.buildConstant(NVT, 0); 4176 } else if (Amt == NVTBits) { 4177 Lo = InH; 4178 Hi = MIRBuilder.buildConstant(NVT, 0); 4179 } else { 4180 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4181 4182 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4183 auto OrRHS = MIRBuilder.buildShl( 4184 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4185 4186 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4187 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4188 } 4189 } else { 4190 if (Amt.ugt(VTBits)) { 4191 Hi = Lo = MIRBuilder.buildAShr( 4192 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4193 } else if (Amt.ugt(NVTBits)) { 4194 Lo = MIRBuilder.buildAShr(NVT, InH, 4195 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4196 Hi = MIRBuilder.buildAShr(NVT, InH, 4197 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4198 } else if (Amt == NVTBits) { 4199 Lo = InH; 4200 Hi = MIRBuilder.buildAShr(NVT, InH, 4201 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4202 } else { 4203 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4204 4205 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4206 auto OrRHS = MIRBuilder.buildShl( 4207 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4208 4209 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4210 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4211 } 4212 } 4213 4214 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4215 MI.eraseFromParent(); 4216 4217 return Legalized; 4218 } 4219 4220 // TODO: Optimize if constant shift amount. 4221 LegalizerHelper::LegalizeResult 4222 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4223 LLT RequestedTy) { 4224 if (TypeIdx == 1) { 4225 Observer.changingInstr(MI); 4226 narrowScalarSrc(MI, RequestedTy, 2); 4227 Observer.changedInstr(MI); 4228 return Legalized; 4229 } 4230 4231 Register DstReg = MI.getOperand(0).getReg(); 4232 LLT DstTy = MRI.getType(DstReg); 4233 if (DstTy.isVector()) 4234 return UnableToLegalize; 4235 4236 Register Amt = MI.getOperand(2).getReg(); 4237 LLT ShiftAmtTy = MRI.getType(Amt); 4238 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4239 if (DstEltSize % 2 != 0) 4240 return UnableToLegalize; 4241 4242 // Ignore the input type. We can only go to exactly half the size of the 4243 // input. If that isn't small enough, the resulting pieces will be further 4244 // legalized. 4245 const unsigned NewBitSize = DstEltSize / 2; 4246 const LLT HalfTy = LLT::scalar(NewBitSize); 4247 const LLT CondTy = LLT::scalar(1); 4248 4249 if (const MachineInstr *KShiftAmt = 4250 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4251 return narrowScalarShiftByConstant( 4252 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4253 } 4254 4255 // TODO: Expand with known bits. 4256 4257 // Handle the fully general expansion by an unknown amount. 4258 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4259 4260 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4261 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4262 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4263 4264 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4265 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4266 4267 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4268 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4269 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4270 4271 Register ResultRegs[2]; 4272 switch (MI.getOpcode()) { 4273 case TargetOpcode::G_SHL: { 4274 // Short: ShAmt < NewBitSize 4275 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4276 4277 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4278 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4279 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4280 4281 // Long: ShAmt >= NewBitSize 4282 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4283 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4284 4285 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4286 auto Hi = MIRBuilder.buildSelect( 4287 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4288 4289 ResultRegs[0] = Lo.getReg(0); 4290 ResultRegs[1] = Hi.getReg(0); 4291 break; 4292 } 4293 case TargetOpcode::G_LSHR: 4294 case TargetOpcode::G_ASHR: { 4295 // Short: ShAmt < NewBitSize 4296 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4297 4298 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4299 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4300 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4301 4302 // Long: ShAmt >= NewBitSize 4303 MachineInstrBuilder HiL; 4304 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4305 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4306 } else { 4307 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4308 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4309 } 4310 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4311 {InH, AmtExcess}); // Lo from Hi part. 4312 4313 auto Lo = MIRBuilder.buildSelect( 4314 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4315 4316 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4317 4318 ResultRegs[0] = Lo.getReg(0); 4319 ResultRegs[1] = Hi.getReg(0); 4320 break; 4321 } 4322 default: 4323 llvm_unreachable("not a shift"); 4324 } 4325 4326 MIRBuilder.buildMerge(DstReg, ResultRegs); 4327 MI.eraseFromParent(); 4328 return Legalized; 4329 } 4330 4331 LegalizerHelper::LegalizeResult 4332 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4333 LLT MoreTy) { 4334 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4335 4336 Observer.changingInstr(MI); 4337 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4338 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4339 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4340 moreElementsVectorSrc(MI, MoreTy, I); 4341 } 4342 4343 MachineBasicBlock &MBB = *MI.getParent(); 4344 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4345 moreElementsVectorDst(MI, MoreTy, 0); 4346 Observer.changedInstr(MI); 4347 return Legalized; 4348 } 4349 4350 LegalizerHelper::LegalizeResult 4351 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4352 LLT MoreTy) { 4353 unsigned Opc = MI.getOpcode(); 4354 switch (Opc) { 4355 case TargetOpcode::G_IMPLICIT_DEF: 4356 case TargetOpcode::G_LOAD: { 4357 if (TypeIdx != 0) 4358 return UnableToLegalize; 4359 Observer.changingInstr(MI); 4360 moreElementsVectorDst(MI, MoreTy, 0); 4361 Observer.changedInstr(MI); 4362 return Legalized; 4363 } 4364 case TargetOpcode::G_STORE: 4365 if (TypeIdx != 0) 4366 return UnableToLegalize; 4367 Observer.changingInstr(MI); 4368 moreElementsVectorSrc(MI, MoreTy, 0); 4369 Observer.changedInstr(MI); 4370 return Legalized; 4371 case TargetOpcode::G_AND: 4372 case TargetOpcode::G_OR: 4373 case TargetOpcode::G_XOR: 4374 case TargetOpcode::G_SMIN: 4375 case TargetOpcode::G_SMAX: 4376 case TargetOpcode::G_UMIN: 4377 case TargetOpcode::G_UMAX: 4378 case TargetOpcode::G_FMINNUM: 4379 case TargetOpcode::G_FMAXNUM: 4380 case TargetOpcode::G_FMINNUM_IEEE: 4381 case TargetOpcode::G_FMAXNUM_IEEE: 4382 case TargetOpcode::G_FMINIMUM: 4383 case TargetOpcode::G_FMAXIMUM: { 4384 Observer.changingInstr(MI); 4385 moreElementsVectorSrc(MI, MoreTy, 1); 4386 moreElementsVectorSrc(MI, MoreTy, 2); 4387 moreElementsVectorDst(MI, MoreTy, 0); 4388 Observer.changedInstr(MI); 4389 return Legalized; 4390 } 4391 case TargetOpcode::G_EXTRACT: 4392 if (TypeIdx != 1) 4393 return UnableToLegalize; 4394 Observer.changingInstr(MI); 4395 moreElementsVectorSrc(MI, MoreTy, 1); 4396 Observer.changedInstr(MI); 4397 return Legalized; 4398 case TargetOpcode::G_INSERT: 4399 case TargetOpcode::G_FREEZE: 4400 if (TypeIdx != 0) 4401 return UnableToLegalize; 4402 Observer.changingInstr(MI); 4403 moreElementsVectorSrc(MI, MoreTy, 1); 4404 moreElementsVectorDst(MI, MoreTy, 0); 4405 Observer.changedInstr(MI); 4406 return Legalized; 4407 case TargetOpcode::G_SELECT: 4408 if (TypeIdx != 0) 4409 return UnableToLegalize; 4410 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4411 return UnableToLegalize; 4412 4413 Observer.changingInstr(MI); 4414 moreElementsVectorSrc(MI, MoreTy, 2); 4415 moreElementsVectorSrc(MI, MoreTy, 3); 4416 moreElementsVectorDst(MI, MoreTy, 0); 4417 Observer.changedInstr(MI); 4418 return Legalized; 4419 case TargetOpcode::G_UNMERGE_VALUES: { 4420 if (TypeIdx != 1) 4421 return UnableToLegalize; 4422 4423 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4424 int NumDst = MI.getNumOperands() - 1; 4425 moreElementsVectorSrc(MI, MoreTy, NumDst); 4426 4427 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4428 for (int I = 0; I != NumDst; ++I) 4429 MIB.addDef(MI.getOperand(I).getReg()); 4430 4431 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4432 for (int I = NumDst; I != NewNumDst; ++I) 4433 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4434 4435 MIB.addUse(MI.getOperand(NumDst).getReg()); 4436 MI.eraseFromParent(); 4437 return Legalized; 4438 } 4439 case TargetOpcode::G_PHI: 4440 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4441 default: 4442 return UnableToLegalize; 4443 } 4444 } 4445 4446 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4447 ArrayRef<Register> Src1Regs, 4448 ArrayRef<Register> Src2Regs, 4449 LLT NarrowTy) { 4450 MachineIRBuilder &B = MIRBuilder; 4451 unsigned SrcParts = Src1Regs.size(); 4452 unsigned DstParts = DstRegs.size(); 4453 4454 unsigned DstIdx = 0; // Low bits of the result. 4455 Register FactorSum = 4456 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4457 DstRegs[DstIdx] = FactorSum; 4458 4459 unsigned CarrySumPrevDstIdx; 4460 SmallVector<Register, 4> Factors; 4461 4462 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4463 // Collect low parts of muls for DstIdx. 4464 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4465 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4466 MachineInstrBuilder Mul = 4467 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4468 Factors.push_back(Mul.getReg(0)); 4469 } 4470 // Collect high parts of muls from previous DstIdx. 4471 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4472 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4473 MachineInstrBuilder Umulh = 4474 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4475 Factors.push_back(Umulh.getReg(0)); 4476 } 4477 // Add CarrySum from additions calculated for previous DstIdx. 4478 if (DstIdx != 1) { 4479 Factors.push_back(CarrySumPrevDstIdx); 4480 } 4481 4482 Register CarrySum; 4483 // Add all factors and accumulate all carries into CarrySum. 4484 if (DstIdx != DstParts - 1) { 4485 MachineInstrBuilder Uaddo = 4486 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 4487 FactorSum = Uaddo.getReg(0); 4488 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 4489 for (unsigned i = 2; i < Factors.size(); ++i) { 4490 MachineInstrBuilder Uaddo = 4491 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 4492 FactorSum = Uaddo.getReg(0); 4493 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 4494 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 4495 } 4496 } else { 4497 // Since value for the next index is not calculated, neither is CarrySum. 4498 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 4499 for (unsigned i = 2; i < Factors.size(); ++i) 4500 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 4501 } 4502 4503 CarrySumPrevDstIdx = CarrySum; 4504 DstRegs[DstIdx] = FactorSum; 4505 Factors.clear(); 4506 } 4507 } 4508 4509 LegalizerHelper::LegalizeResult 4510 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 4511 Register DstReg = MI.getOperand(0).getReg(); 4512 Register Src1 = MI.getOperand(1).getReg(); 4513 Register Src2 = MI.getOperand(2).getReg(); 4514 4515 LLT Ty = MRI.getType(DstReg); 4516 if (Ty.isVector()) 4517 return UnableToLegalize; 4518 4519 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 4520 unsigned DstSize = Ty.getSizeInBits(); 4521 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4522 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 4523 return UnableToLegalize; 4524 4525 unsigned NumDstParts = DstSize / NarrowSize; 4526 unsigned NumSrcParts = SrcSize / NarrowSize; 4527 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 4528 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 4529 4530 SmallVector<Register, 2> Src1Parts, Src2Parts; 4531 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 4532 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 4533 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 4534 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 4535 4536 // Take only high half of registers if this is high mul. 4537 ArrayRef<Register> DstRegs( 4538 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 4539 MIRBuilder.buildMerge(DstReg, DstRegs); 4540 MI.eraseFromParent(); 4541 return Legalized; 4542 } 4543 4544 LegalizerHelper::LegalizeResult 4545 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 4546 LLT NarrowTy) { 4547 if (TypeIdx != 1) 4548 return UnableToLegalize; 4549 4550 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4551 4552 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 4553 // FIXME: add support for when SizeOp1 isn't an exact multiple of 4554 // NarrowSize. 4555 if (SizeOp1 % NarrowSize != 0) 4556 return UnableToLegalize; 4557 int NumParts = SizeOp1 / NarrowSize; 4558 4559 SmallVector<Register, 2> SrcRegs, DstRegs; 4560 SmallVector<uint64_t, 2> Indexes; 4561 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4562 4563 Register OpReg = MI.getOperand(0).getReg(); 4564 uint64_t OpStart = MI.getOperand(2).getImm(); 4565 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4566 for (int i = 0; i < NumParts; ++i) { 4567 unsigned SrcStart = i * NarrowSize; 4568 4569 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 4570 // No part of the extract uses this subregister, ignore it. 4571 continue; 4572 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4573 // The entire subregister is extracted, forward the value. 4574 DstRegs.push_back(SrcRegs[i]); 4575 continue; 4576 } 4577 4578 // OpSegStart is where this destination segment would start in OpReg if it 4579 // extended infinitely in both directions. 4580 int64_t ExtractOffset; 4581 uint64_t SegSize; 4582 if (OpStart < SrcStart) { 4583 ExtractOffset = 0; 4584 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 4585 } else { 4586 ExtractOffset = OpStart - SrcStart; 4587 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 4588 } 4589 4590 Register SegReg = SrcRegs[i]; 4591 if (ExtractOffset != 0 || SegSize != NarrowSize) { 4592 // A genuine extract is needed. 4593 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4594 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 4595 } 4596 4597 DstRegs.push_back(SegReg); 4598 } 4599 4600 Register DstReg = MI.getOperand(0).getReg(); 4601 if (MRI.getType(DstReg).isVector()) 4602 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4603 else if (DstRegs.size() > 1) 4604 MIRBuilder.buildMerge(DstReg, DstRegs); 4605 else 4606 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 4607 MI.eraseFromParent(); 4608 return Legalized; 4609 } 4610 4611 LegalizerHelper::LegalizeResult 4612 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 4613 LLT NarrowTy) { 4614 // FIXME: Don't know how to handle secondary types yet. 4615 if (TypeIdx != 0) 4616 return UnableToLegalize; 4617 4618 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 4619 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4620 4621 // FIXME: add support for when SizeOp0 isn't an exact multiple of 4622 // NarrowSize. 4623 if (SizeOp0 % NarrowSize != 0) 4624 return UnableToLegalize; 4625 4626 int NumParts = SizeOp0 / NarrowSize; 4627 4628 SmallVector<Register, 2> SrcRegs, DstRegs; 4629 SmallVector<uint64_t, 2> Indexes; 4630 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4631 4632 Register OpReg = MI.getOperand(2).getReg(); 4633 uint64_t OpStart = MI.getOperand(3).getImm(); 4634 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4635 for (int i = 0; i < NumParts; ++i) { 4636 unsigned DstStart = i * NarrowSize; 4637 4638 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 4639 // No part of the insert affects this subregister, forward the original. 4640 DstRegs.push_back(SrcRegs[i]); 4641 continue; 4642 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4643 // The entire subregister is defined by this insert, forward the new 4644 // value. 4645 DstRegs.push_back(OpReg); 4646 continue; 4647 } 4648 4649 // OpSegStart is where this destination segment would start in OpReg if it 4650 // extended infinitely in both directions. 4651 int64_t ExtractOffset, InsertOffset; 4652 uint64_t SegSize; 4653 if (OpStart < DstStart) { 4654 InsertOffset = 0; 4655 ExtractOffset = DstStart - OpStart; 4656 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 4657 } else { 4658 InsertOffset = OpStart - DstStart; 4659 ExtractOffset = 0; 4660 SegSize = 4661 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 4662 } 4663 4664 Register SegReg = OpReg; 4665 if (ExtractOffset != 0 || SegSize != OpSize) { 4666 // A genuine extract is needed. 4667 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4668 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 4669 } 4670 4671 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 4672 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset); 4673 DstRegs.push_back(DstReg); 4674 } 4675 4676 assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered"); 4677 Register DstReg = MI.getOperand(0).getReg(); 4678 if(MRI.getType(DstReg).isVector()) 4679 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4680 else 4681 MIRBuilder.buildMerge(DstReg, DstRegs); 4682 MI.eraseFromParent(); 4683 return Legalized; 4684 } 4685 4686 LegalizerHelper::LegalizeResult 4687 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 4688 LLT NarrowTy) { 4689 Register DstReg = MI.getOperand(0).getReg(); 4690 LLT DstTy = MRI.getType(DstReg); 4691 4692 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 4693 4694 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4695 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 4696 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4697 LLT LeftoverTy; 4698 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 4699 Src0Regs, Src0LeftoverRegs)) 4700 return UnableToLegalize; 4701 4702 LLT Unused; 4703 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 4704 Src1Regs, Src1LeftoverRegs)) 4705 llvm_unreachable("inconsistent extractParts result"); 4706 4707 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4708 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 4709 {Src0Regs[I], Src1Regs[I]}); 4710 DstRegs.push_back(Inst.getReg(0)); 4711 } 4712 4713 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4714 auto Inst = MIRBuilder.buildInstr( 4715 MI.getOpcode(), 4716 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 4717 DstLeftoverRegs.push_back(Inst.getReg(0)); 4718 } 4719 4720 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4721 LeftoverTy, DstLeftoverRegs); 4722 4723 MI.eraseFromParent(); 4724 return Legalized; 4725 } 4726 4727 LegalizerHelper::LegalizeResult 4728 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 4729 LLT NarrowTy) { 4730 if (TypeIdx != 0) 4731 return UnableToLegalize; 4732 4733 Register DstReg = MI.getOperand(0).getReg(); 4734 Register SrcReg = MI.getOperand(1).getReg(); 4735 4736 LLT DstTy = MRI.getType(DstReg); 4737 if (DstTy.isVector()) 4738 return UnableToLegalize; 4739 4740 SmallVector<Register, 8> Parts; 4741 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4742 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 4743 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4744 4745 MI.eraseFromParent(); 4746 return Legalized; 4747 } 4748 4749 LegalizerHelper::LegalizeResult 4750 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 4751 LLT NarrowTy) { 4752 if (TypeIdx != 0) 4753 return UnableToLegalize; 4754 4755 Register CondReg = MI.getOperand(1).getReg(); 4756 LLT CondTy = MRI.getType(CondReg); 4757 if (CondTy.isVector()) // TODO: Handle vselect 4758 return UnableToLegalize; 4759 4760 Register DstReg = MI.getOperand(0).getReg(); 4761 LLT DstTy = MRI.getType(DstReg); 4762 4763 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4764 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4765 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 4766 LLT LeftoverTy; 4767 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 4768 Src1Regs, Src1LeftoverRegs)) 4769 return UnableToLegalize; 4770 4771 LLT Unused; 4772 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 4773 Src2Regs, Src2LeftoverRegs)) 4774 llvm_unreachable("inconsistent extractParts result"); 4775 4776 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4777 auto Select = MIRBuilder.buildSelect(NarrowTy, 4778 CondReg, Src1Regs[I], Src2Regs[I]); 4779 DstRegs.push_back(Select.getReg(0)); 4780 } 4781 4782 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4783 auto Select = MIRBuilder.buildSelect( 4784 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 4785 DstLeftoverRegs.push_back(Select.getReg(0)); 4786 } 4787 4788 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4789 LeftoverTy, DstLeftoverRegs); 4790 4791 MI.eraseFromParent(); 4792 return Legalized; 4793 } 4794 4795 LegalizerHelper::LegalizeResult 4796 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 4797 LLT NarrowTy) { 4798 if (TypeIdx != 1) 4799 return UnableToLegalize; 4800 4801 Register DstReg = MI.getOperand(0).getReg(); 4802 Register SrcReg = MI.getOperand(1).getReg(); 4803 LLT DstTy = MRI.getType(DstReg); 4804 LLT SrcTy = MRI.getType(SrcReg); 4805 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4806 4807 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4808 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 4809 4810 MachineIRBuilder &B = MIRBuilder; 4811 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 4812 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 4813 auto C_0 = B.buildConstant(NarrowTy, 0); 4814 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 4815 UnmergeSrc.getReg(1), C_0); 4816 auto LoCTLZ = IsUndef ? 4817 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 4818 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 4819 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 4820 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 4821 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 4822 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 4823 4824 MI.eraseFromParent(); 4825 return Legalized; 4826 } 4827 4828 return UnableToLegalize; 4829 } 4830 4831 LegalizerHelper::LegalizeResult 4832 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 4833 LLT NarrowTy) { 4834 if (TypeIdx != 1) 4835 return UnableToLegalize; 4836 4837 Register DstReg = MI.getOperand(0).getReg(); 4838 Register SrcReg = MI.getOperand(1).getReg(); 4839 LLT DstTy = MRI.getType(DstReg); 4840 LLT SrcTy = MRI.getType(SrcReg); 4841 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4842 4843 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4844 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 4845 4846 MachineIRBuilder &B = MIRBuilder; 4847 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 4848 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 4849 auto C_0 = B.buildConstant(NarrowTy, 0); 4850 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 4851 UnmergeSrc.getReg(0), C_0); 4852 auto HiCTTZ = IsUndef ? 4853 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 4854 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 4855 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 4856 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 4857 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 4858 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 4859 4860 MI.eraseFromParent(); 4861 return Legalized; 4862 } 4863 4864 return UnableToLegalize; 4865 } 4866 4867 LegalizerHelper::LegalizeResult 4868 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 4869 LLT NarrowTy) { 4870 if (TypeIdx != 1) 4871 return UnableToLegalize; 4872 4873 Register DstReg = MI.getOperand(0).getReg(); 4874 LLT DstTy = MRI.getType(DstReg); 4875 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 4876 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4877 4878 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4879 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 4880 4881 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 4882 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 4883 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 4884 4885 MI.eraseFromParent(); 4886 return Legalized; 4887 } 4888 4889 return UnableToLegalize; 4890 } 4891 4892 LegalizerHelper::LegalizeResult 4893 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 4894 unsigned Opc = MI.getOpcode(); 4895 const auto &TII = MIRBuilder.getTII(); 4896 auto isSupported = [this](const LegalityQuery &Q) { 4897 auto QAction = LI.getAction(Q).Action; 4898 return QAction == Legal || QAction == Libcall || QAction == Custom; 4899 }; 4900 switch (Opc) { 4901 default: 4902 return UnableToLegalize; 4903 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 4904 // This trivially expands to CTLZ. 4905 Observer.changingInstr(MI); 4906 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 4907 Observer.changedInstr(MI); 4908 return Legalized; 4909 } 4910 case TargetOpcode::G_CTLZ: { 4911 Register DstReg = MI.getOperand(0).getReg(); 4912 Register SrcReg = MI.getOperand(1).getReg(); 4913 LLT DstTy = MRI.getType(DstReg); 4914 LLT SrcTy = MRI.getType(SrcReg); 4915 unsigned Len = SrcTy.getSizeInBits(); 4916 4917 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 4918 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 4919 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 4920 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 4921 auto ICmp = MIRBuilder.buildICmp( 4922 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 4923 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 4924 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 4925 MI.eraseFromParent(); 4926 return Legalized; 4927 } 4928 // for now, we do this: 4929 // NewLen = NextPowerOf2(Len); 4930 // x = x | (x >> 1); 4931 // x = x | (x >> 2); 4932 // ... 4933 // x = x | (x >>16); 4934 // x = x | (x >>32); // for 64-bit input 4935 // Upto NewLen/2 4936 // return Len - popcount(x); 4937 // 4938 // Ref: "Hacker's Delight" by Henry Warren 4939 Register Op = SrcReg; 4940 unsigned NewLen = PowerOf2Ceil(Len); 4941 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 4942 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 4943 auto MIBOp = MIRBuilder.buildOr( 4944 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 4945 Op = MIBOp.getReg(0); 4946 } 4947 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 4948 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 4949 MIBPop); 4950 MI.eraseFromParent(); 4951 return Legalized; 4952 } 4953 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 4954 // This trivially expands to CTTZ. 4955 Observer.changingInstr(MI); 4956 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 4957 Observer.changedInstr(MI); 4958 return Legalized; 4959 } 4960 case TargetOpcode::G_CTTZ: { 4961 Register DstReg = MI.getOperand(0).getReg(); 4962 Register SrcReg = MI.getOperand(1).getReg(); 4963 LLT DstTy = MRI.getType(DstReg); 4964 LLT SrcTy = MRI.getType(SrcReg); 4965 4966 unsigned Len = SrcTy.getSizeInBits(); 4967 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 4968 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 4969 // zero. 4970 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 4971 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 4972 auto ICmp = MIRBuilder.buildICmp( 4973 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 4974 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 4975 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 4976 MI.eraseFromParent(); 4977 return Legalized; 4978 } 4979 // for now, we use: { return popcount(~x & (x - 1)); } 4980 // unless the target has ctlz but not ctpop, in which case we use: 4981 // { return 32 - nlz(~x & (x-1)); } 4982 // Ref: "Hacker's Delight" by Henry Warren 4983 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 4984 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 4985 auto MIBTmp = MIRBuilder.buildAnd( 4986 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 4987 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 4988 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 4989 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 4990 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 4991 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 4992 MI.eraseFromParent(); 4993 return Legalized; 4994 } 4995 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 4996 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 4997 return Legalized; 4998 } 4999 case TargetOpcode::G_CTPOP: { 5000 Register SrcReg = MI.getOperand(1).getReg(); 5001 LLT Ty = MRI.getType(SrcReg); 5002 unsigned Size = Ty.getSizeInBits(); 5003 MachineIRBuilder &B = MIRBuilder; 5004 5005 // Count set bits in blocks of 2 bits. Default approach would be 5006 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5007 // We use following formula instead: 5008 // B2Count = val - { (val >> 1) & 0x55555555 } 5009 // since it gives same result in blocks of 2 with one instruction less. 5010 auto C_1 = B.buildConstant(Ty, 1); 5011 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5012 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5013 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5014 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5015 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5016 5017 // In order to get count in blocks of 4 add values from adjacent block of 2. 5018 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5019 auto C_2 = B.buildConstant(Ty, 2); 5020 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5021 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5022 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5023 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5024 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5025 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5026 5027 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5028 // addition since count value sits in range {0,...,8} and 4 bits are enough 5029 // to hold such binary values. After addition high 4 bits still hold count 5030 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5031 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5032 auto C_4 = B.buildConstant(Ty, 4); 5033 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5034 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5035 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5036 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5037 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5038 5039 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5040 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5041 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5042 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5043 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5044 5045 // Shift count result from 8 high bits to low bits. 5046 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5047 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5048 5049 MI.eraseFromParent(); 5050 return Legalized; 5051 } 5052 } 5053 } 5054 5055 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5056 // representation. 5057 LegalizerHelper::LegalizeResult 5058 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5059 Register Dst = MI.getOperand(0).getReg(); 5060 Register Src = MI.getOperand(1).getReg(); 5061 const LLT S64 = LLT::scalar(64); 5062 const LLT S32 = LLT::scalar(32); 5063 const LLT S1 = LLT::scalar(1); 5064 5065 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5066 5067 // unsigned cul2f(ulong u) { 5068 // uint lz = clz(u); 5069 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5070 // u = (u << lz) & 0x7fffffffffffffffUL; 5071 // ulong t = u & 0xffffffffffUL; 5072 // uint v = (e << 23) | (uint)(u >> 40); 5073 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5074 // return as_float(v + r); 5075 // } 5076 5077 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5078 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5079 5080 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5081 5082 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5083 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5084 5085 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5086 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5087 5088 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5089 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5090 5091 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5092 5093 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5094 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5095 5096 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5097 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5098 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5099 5100 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5101 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5102 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5103 auto One = MIRBuilder.buildConstant(S32, 1); 5104 5105 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5106 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5107 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5108 MIRBuilder.buildAdd(Dst, V, R); 5109 5110 MI.eraseFromParent(); 5111 return Legalized; 5112 } 5113 5114 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5115 Register Dst = MI.getOperand(0).getReg(); 5116 Register Src = MI.getOperand(1).getReg(); 5117 LLT DstTy = MRI.getType(Dst); 5118 LLT SrcTy = MRI.getType(Src); 5119 5120 if (SrcTy == LLT::scalar(1)) { 5121 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5122 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5123 MIRBuilder.buildSelect(Dst, Src, True, False); 5124 MI.eraseFromParent(); 5125 return Legalized; 5126 } 5127 5128 if (SrcTy != LLT::scalar(64)) 5129 return UnableToLegalize; 5130 5131 if (DstTy == LLT::scalar(32)) { 5132 // TODO: SelectionDAG has several alternative expansions to port which may 5133 // be more reasonble depending on the available instructions. If a target 5134 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5135 // intermediate type, this is probably worse. 5136 return lowerU64ToF32BitOps(MI); 5137 } 5138 5139 return UnableToLegalize; 5140 } 5141 5142 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5143 Register Dst = MI.getOperand(0).getReg(); 5144 Register Src = MI.getOperand(1).getReg(); 5145 LLT DstTy = MRI.getType(Dst); 5146 LLT SrcTy = MRI.getType(Src); 5147 5148 const LLT S64 = LLT::scalar(64); 5149 const LLT S32 = LLT::scalar(32); 5150 const LLT S1 = LLT::scalar(1); 5151 5152 if (SrcTy == S1) { 5153 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 5154 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5155 MIRBuilder.buildSelect(Dst, Src, True, False); 5156 MI.eraseFromParent(); 5157 return Legalized; 5158 } 5159 5160 if (SrcTy != S64) 5161 return UnableToLegalize; 5162 5163 if (DstTy == S32) { 5164 // signed cl2f(long l) { 5165 // long s = l >> 63; 5166 // float r = cul2f((l + s) ^ s); 5167 // return s ? -r : r; 5168 // } 5169 Register L = Src; 5170 auto SignBit = MIRBuilder.buildConstant(S64, 63); 5171 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 5172 5173 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 5174 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 5175 auto R = MIRBuilder.buildUITOFP(S32, Xor); 5176 5177 auto RNeg = MIRBuilder.buildFNeg(S32, R); 5178 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 5179 MIRBuilder.buildConstant(S64, 0)); 5180 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 5181 MI.eraseFromParent(); 5182 return Legalized; 5183 } 5184 5185 return UnableToLegalize; 5186 } 5187 5188 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 5189 Register Dst = MI.getOperand(0).getReg(); 5190 Register Src = MI.getOperand(1).getReg(); 5191 LLT DstTy = MRI.getType(Dst); 5192 LLT SrcTy = MRI.getType(Src); 5193 const LLT S64 = LLT::scalar(64); 5194 const LLT S32 = LLT::scalar(32); 5195 5196 if (SrcTy != S64 && SrcTy != S32) 5197 return UnableToLegalize; 5198 if (DstTy != S32 && DstTy != S64) 5199 return UnableToLegalize; 5200 5201 // FPTOSI gives same result as FPTOUI for positive signed integers. 5202 // FPTOUI needs to deal with fp values that convert to unsigned integers 5203 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 5204 5205 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 5206 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 5207 : APFloat::IEEEdouble(), 5208 APInt::getNullValue(SrcTy.getSizeInBits())); 5209 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 5210 5211 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 5212 5213 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 5214 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 5215 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 5216 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 5217 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 5218 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 5219 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 5220 5221 const LLT S1 = LLT::scalar(1); 5222 5223 MachineInstrBuilder FCMP = 5224 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 5225 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 5226 5227 MI.eraseFromParent(); 5228 return Legalized; 5229 } 5230 5231 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 5232 Register Dst = MI.getOperand(0).getReg(); 5233 Register Src = MI.getOperand(1).getReg(); 5234 LLT DstTy = MRI.getType(Dst); 5235 LLT SrcTy = MRI.getType(Src); 5236 const LLT S64 = LLT::scalar(64); 5237 const LLT S32 = LLT::scalar(32); 5238 5239 // FIXME: Only f32 to i64 conversions are supported. 5240 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 5241 return UnableToLegalize; 5242 5243 // Expand f32 -> i64 conversion 5244 // This algorithm comes from compiler-rt's implementation of fixsfdi: 5245 // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c 5246 5247 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 5248 5249 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 5250 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 5251 5252 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 5253 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 5254 5255 auto SignMask = MIRBuilder.buildConstant(SrcTy, 5256 APInt::getSignMask(SrcEltBits)); 5257 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 5258 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 5259 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 5260 Sign = MIRBuilder.buildSExt(DstTy, Sign); 5261 5262 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 5263 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 5264 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 5265 5266 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 5267 R = MIRBuilder.buildZExt(DstTy, R); 5268 5269 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 5270 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 5271 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 5272 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 5273 5274 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 5275 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 5276 5277 const LLT S1 = LLT::scalar(1); 5278 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 5279 S1, Exponent, ExponentLoBit); 5280 5281 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 5282 5283 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 5284 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 5285 5286 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 5287 5288 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 5289 S1, Exponent, ZeroSrcTy); 5290 5291 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 5292 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 5293 5294 MI.eraseFromParent(); 5295 return Legalized; 5296 } 5297 5298 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 5299 LegalizerHelper::LegalizeResult 5300 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 5301 Register Dst = MI.getOperand(0).getReg(); 5302 Register Src = MI.getOperand(1).getReg(); 5303 5304 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 5305 return UnableToLegalize; 5306 5307 const unsigned ExpMask = 0x7ff; 5308 const unsigned ExpBiasf64 = 1023; 5309 const unsigned ExpBiasf16 = 15; 5310 const LLT S32 = LLT::scalar(32); 5311 const LLT S1 = LLT::scalar(1); 5312 5313 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 5314 Register U = Unmerge.getReg(0); 5315 Register UH = Unmerge.getReg(1); 5316 5317 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 5318 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 5319 5320 // Subtract the fp64 exponent bias (1023) to get the real exponent and 5321 // add the f16 bias (15) to get the biased exponent for the f16 format. 5322 E = MIRBuilder.buildAdd( 5323 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 5324 5325 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 5326 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 5327 5328 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 5329 MIRBuilder.buildConstant(S32, 0x1ff)); 5330 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 5331 5332 auto Zero = MIRBuilder.buildConstant(S32, 0); 5333 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 5334 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 5335 M = MIRBuilder.buildOr(S32, M, Lo40Set); 5336 5337 // (M != 0 ? 0x0200 : 0) | 0x7c00; 5338 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 5339 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 5340 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 5341 5342 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 5343 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 5344 5345 // N = M | (E << 12); 5346 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 5347 auto N = MIRBuilder.buildOr(S32, M, EShl12); 5348 5349 // B = clamp(1-E, 0, 13); 5350 auto One = MIRBuilder.buildConstant(S32, 1); 5351 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 5352 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 5353 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 5354 5355 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 5356 MIRBuilder.buildConstant(S32, 0x1000)); 5357 5358 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 5359 auto D0 = MIRBuilder.buildShl(S32, D, B); 5360 5361 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 5362 D0, SigSetHigh); 5363 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 5364 D = MIRBuilder.buildOr(S32, D, D1); 5365 5366 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 5367 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 5368 5369 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 5370 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 5371 5372 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 5373 MIRBuilder.buildConstant(S32, 3)); 5374 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 5375 5376 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 5377 MIRBuilder.buildConstant(S32, 5)); 5378 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 5379 5380 V1 = MIRBuilder.buildOr(S32, V0, V1); 5381 V = MIRBuilder.buildAdd(S32, V, V1); 5382 5383 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 5384 E, MIRBuilder.buildConstant(S32, 30)); 5385 V = MIRBuilder.buildSelect(S32, CmpEGt30, 5386 MIRBuilder.buildConstant(S32, 0x7c00), V); 5387 5388 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 5389 E, MIRBuilder.buildConstant(S32, 1039)); 5390 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 5391 5392 // Extract the sign bit. 5393 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 5394 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 5395 5396 // Insert the sign bit 5397 V = MIRBuilder.buildOr(S32, Sign, V); 5398 5399 MIRBuilder.buildTrunc(Dst, V); 5400 MI.eraseFromParent(); 5401 return Legalized; 5402 } 5403 5404 LegalizerHelper::LegalizeResult 5405 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 5406 Register Dst = MI.getOperand(0).getReg(); 5407 Register Src = MI.getOperand(1).getReg(); 5408 5409 LLT DstTy = MRI.getType(Dst); 5410 LLT SrcTy = MRI.getType(Src); 5411 const LLT S64 = LLT::scalar(64); 5412 const LLT S16 = LLT::scalar(16); 5413 5414 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 5415 return lowerFPTRUNC_F64_TO_F16(MI); 5416 5417 return UnableToLegalize; 5418 } 5419 5420 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 5421 // multiplication tree. 5422 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 5423 Register Dst = MI.getOperand(0).getReg(); 5424 Register Src0 = MI.getOperand(1).getReg(); 5425 Register Src1 = MI.getOperand(2).getReg(); 5426 LLT Ty = MRI.getType(Dst); 5427 5428 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 5429 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 5430 MI.eraseFromParent(); 5431 return Legalized; 5432 } 5433 5434 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 5435 switch (Opc) { 5436 case TargetOpcode::G_SMIN: 5437 return CmpInst::ICMP_SLT; 5438 case TargetOpcode::G_SMAX: 5439 return CmpInst::ICMP_SGT; 5440 case TargetOpcode::G_UMIN: 5441 return CmpInst::ICMP_ULT; 5442 case TargetOpcode::G_UMAX: 5443 return CmpInst::ICMP_UGT; 5444 default: 5445 llvm_unreachable("not in integer min/max"); 5446 } 5447 } 5448 5449 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 5450 Register Dst = MI.getOperand(0).getReg(); 5451 Register Src0 = MI.getOperand(1).getReg(); 5452 Register Src1 = MI.getOperand(2).getReg(); 5453 5454 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 5455 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 5456 5457 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 5458 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 5459 5460 MI.eraseFromParent(); 5461 return Legalized; 5462 } 5463 5464 LegalizerHelper::LegalizeResult 5465 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 5466 Register Dst = MI.getOperand(0).getReg(); 5467 Register Src0 = MI.getOperand(1).getReg(); 5468 Register Src1 = MI.getOperand(2).getReg(); 5469 5470 const LLT Src0Ty = MRI.getType(Src0); 5471 const LLT Src1Ty = MRI.getType(Src1); 5472 5473 const int Src0Size = Src0Ty.getScalarSizeInBits(); 5474 const int Src1Size = Src1Ty.getScalarSizeInBits(); 5475 5476 auto SignBitMask = MIRBuilder.buildConstant( 5477 Src0Ty, APInt::getSignMask(Src0Size)); 5478 5479 auto NotSignBitMask = MIRBuilder.buildConstant( 5480 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 5481 5482 auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask); 5483 MachineInstr *Or; 5484 5485 if (Src0Ty == Src1Ty) { 5486 auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask); 5487 Or = MIRBuilder.buildOr(Dst, And0, And1); 5488 } else if (Src0Size > Src1Size) { 5489 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 5490 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 5491 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 5492 auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask); 5493 Or = MIRBuilder.buildOr(Dst, And0, And1); 5494 } else { 5495 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 5496 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 5497 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 5498 auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask); 5499 Or = MIRBuilder.buildOr(Dst, And0, And1); 5500 } 5501 5502 // Be careful about setting nsz/nnan/ninf on every instruction, since the 5503 // constants are a nan and -0.0, but the final result should preserve 5504 // everything. 5505 if (unsigned Flags = MI.getFlags()) 5506 Or->setFlags(Flags); 5507 5508 MI.eraseFromParent(); 5509 return Legalized; 5510 } 5511 5512 LegalizerHelper::LegalizeResult 5513 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 5514 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 5515 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 5516 5517 Register Dst = MI.getOperand(0).getReg(); 5518 Register Src0 = MI.getOperand(1).getReg(); 5519 Register Src1 = MI.getOperand(2).getReg(); 5520 LLT Ty = MRI.getType(Dst); 5521 5522 if (!MI.getFlag(MachineInstr::FmNoNans)) { 5523 // Insert canonicalizes if it's possible we need to quiet to get correct 5524 // sNaN behavior. 5525 5526 // Note this must be done here, and not as an optimization combine in the 5527 // absence of a dedicate quiet-snan instruction as we're using an 5528 // omni-purpose G_FCANONICALIZE. 5529 if (!isKnownNeverSNaN(Src0, MRI)) 5530 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 5531 5532 if (!isKnownNeverSNaN(Src1, MRI)) 5533 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 5534 } 5535 5536 // If there are no nans, it's safe to simply replace this with the non-IEEE 5537 // version. 5538 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 5539 MI.eraseFromParent(); 5540 return Legalized; 5541 } 5542 5543 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 5544 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 5545 Register DstReg = MI.getOperand(0).getReg(); 5546 LLT Ty = MRI.getType(DstReg); 5547 unsigned Flags = MI.getFlags(); 5548 5549 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 5550 Flags); 5551 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 5552 MI.eraseFromParent(); 5553 return Legalized; 5554 } 5555 5556 LegalizerHelper::LegalizeResult 5557 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 5558 Register DstReg = MI.getOperand(0).getReg(); 5559 Register X = MI.getOperand(1).getReg(); 5560 const unsigned Flags = MI.getFlags(); 5561 const LLT Ty = MRI.getType(DstReg); 5562 const LLT CondTy = Ty.changeElementSize(1); 5563 5564 // round(x) => 5565 // t = trunc(x); 5566 // d = fabs(x - t); 5567 // o = copysign(1.0f, x); 5568 // return t + (d >= 0.5 ? o : 0.0); 5569 5570 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 5571 5572 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 5573 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 5574 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5575 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 5576 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 5577 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 5578 5579 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 5580 Flags); 5581 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 5582 5583 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 5584 5585 MI.eraseFromParent(); 5586 return Legalized; 5587 } 5588 5589 LegalizerHelper::LegalizeResult 5590 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 5591 Register DstReg = MI.getOperand(0).getReg(); 5592 Register SrcReg = MI.getOperand(1).getReg(); 5593 unsigned Flags = MI.getFlags(); 5594 LLT Ty = MRI.getType(DstReg); 5595 const LLT CondTy = Ty.changeElementSize(1); 5596 5597 // result = trunc(src); 5598 // if (src < 0.0 && src != result) 5599 // result += -1.0. 5600 5601 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 5602 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5603 5604 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 5605 SrcReg, Zero, Flags); 5606 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 5607 SrcReg, Trunc, Flags); 5608 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 5609 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 5610 5611 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 5612 MI.eraseFromParent(); 5613 return Legalized; 5614 } 5615 5616 LegalizerHelper::LegalizeResult 5617 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 5618 const unsigned NumOps = MI.getNumOperands(); 5619 Register DstReg = MI.getOperand(0).getReg(); 5620 Register Src0Reg = MI.getOperand(1).getReg(); 5621 LLT DstTy = MRI.getType(DstReg); 5622 LLT SrcTy = MRI.getType(Src0Reg); 5623 unsigned PartSize = SrcTy.getSizeInBits(); 5624 5625 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 5626 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 5627 5628 for (unsigned I = 2; I != NumOps; ++I) { 5629 const unsigned Offset = (I - 1) * PartSize; 5630 5631 Register SrcReg = MI.getOperand(I).getReg(); 5632 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 5633 5634 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 5635 MRI.createGenericVirtualRegister(WideTy); 5636 5637 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 5638 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 5639 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 5640 ResultReg = NextResult; 5641 } 5642 5643 if (DstTy.isPointer()) { 5644 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 5645 DstTy.getAddressSpace())) { 5646 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 5647 return UnableToLegalize; 5648 } 5649 5650 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 5651 } 5652 5653 MI.eraseFromParent(); 5654 return Legalized; 5655 } 5656 5657 LegalizerHelper::LegalizeResult 5658 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 5659 const unsigned NumDst = MI.getNumOperands() - 1; 5660 Register SrcReg = MI.getOperand(NumDst).getReg(); 5661 Register Dst0Reg = MI.getOperand(0).getReg(); 5662 LLT DstTy = MRI.getType(Dst0Reg); 5663 if (DstTy.isPointer()) 5664 return UnableToLegalize; // TODO 5665 5666 SrcReg = coerceToScalar(SrcReg); 5667 if (!SrcReg) 5668 return UnableToLegalize; 5669 5670 // Expand scalarizing unmerge as bitcast to integer and shift. 5671 LLT IntTy = MRI.getType(SrcReg); 5672 5673 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 5674 5675 const unsigned DstSize = DstTy.getSizeInBits(); 5676 unsigned Offset = DstSize; 5677 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 5678 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 5679 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 5680 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 5681 } 5682 5683 MI.eraseFromParent(); 5684 return Legalized; 5685 } 5686 5687 /// Lower a vector extract or insert by writing the vector to a stack temporary 5688 /// and reloading the element or vector. 5689 /// 5690 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 5691 /// => 5692 /// %stack_temp = G_FRAME_INDEX 5693 /// G_STORE %vec, %stack_temp 5694 /// %idx = clamp(%idx, %vec.getNumElements()) 5695 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 5696 /// %dst = G_LOAD %element_ptr 5697 LegalizerHelper::LegalizeResult 5698 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 5699 Register DstReg = MI.getOperand(0).getReg(); 5700 Register SrcVec = MI.getOperand(1).getReg(); 5701 Register InsertVal; 5702 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 5703 InsertVal = MI.getOperand(2).getReg(); 5704 5705 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 5706 5707 LLT VecTy = MRI.getType(SrcVec); 5708 LLT EltTy = VecTy.getElementType(); 5709 if (!EltTy.isByteSized()) { // Not implemented. 5710 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 5711 return UnableToLegalize; 5712 } 5713 5714 unsigned EltBytes = EltTy.getSizeInBytes(); 5715 Align VecAlign = getStackTemporaryAlignment(VecTy); 5716 Align EltAlign; 5717 5718 MachinePointerInfo PtrInfo; 5719 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 5720 VecAlign, PtrInfo); 5721 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 5722 5723 // Get the pointer to the element, and be sure not to hit undefined behavior 5724 // if the index is out of bounds. 5725 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 5726 5727 int64_t IdxVal; 5728 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 5729 int64_t Offset = IdxVal * EltBytes; 5730 PtrInfo = PtrInfo.getWithOffset(Offset); 5731 EltAlign = commonAlignment(VecAlign, Offset); 5732 } else { 5733 // We lose information with a variable offset. 5734 EltAlign = getStackTemporaryAlignment(EltTy); 5735 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 5736 } 5737 5738 if (InsertVal) { 5739 // Write the inserted element 5740 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 5741 5742 // Reload the whole vector. 5743 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 5744 } else { 5745 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 5746 } 5747 5748 MI.eraseFromParent(); 5749 return Legalized; 5750 } 5751 5752 LegalizerHelper::LegalizeResult 5753 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 5754 Register DstReg = MI.getOperand(0).getReg(); 5755 Register Src0Reg = MI.getOperand(1).getReg(); 5756 Register Src1Reg = MI.getOperand(2).getReg(); 5757 LLT Src0Ty = MRI.getType(Src0Reg); 5758 LLT DstTy = MRI.getType(DstReg); 5759 LLT IdxTy = LLT::scalar(32); 5760 5761 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 5762 5763 if (DstTy.isScalar()) { 5764 if (Src0Ty.isVector()) 5765 return UnableToLegalize; 5766 5767 // This is just a SELECT. 5768 assert(Mask.size() == 1 && "Expected a single mask element"); 5769 Register Val; 5770 if (Mask[0] < 0 || Mask[0] > 1) 5771 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 5772 else 5773 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 5774 MIRBuilder.buildCopy(DstReg, Val); 5775 MI.eraseFromParent(); 5776 return Legalized; 5777 } 5778 5779 Register Undef; 5780 SmallVector<Register, 32> BuildVec; 5781 LLT EltTy = DstTy.getElementType(); 5782 5783 for (int Idx : Mask) { 5784 if (Idx < 0) { 5785 if (!Undef.isValid()) 5786 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 5787 BuildVec.push_back(Undef); 5788 continue; 5789 } 5790 5791 if (Src0Ty.isScalar()) { 5792 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 5793 } else { 5794 int NumElts = Src0Ty.getNumElements(); 5795 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 5796 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 5797 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 5798 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 5799 BuildVec.push_back(Extract.getReg(0)); 5800 } 5801 } 5802 5803 MIRBuilder.buildBuildVector(DstReg, BuildVec); 5804 MI.eraseFromParent(); 5805 return Legalized; 5806 } 5807 5808 LegalizerHelper::LegalizeResult 5809 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 5810 const auto &MF = *MI.getMF(); 5811 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 5812 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 5813 return UnableToLegalize; 5814 5815 Register Dst = MI.getOperand(0).getReg(); 5816 Register AllocSize = MI.getOperand(1).getReg(); 5817 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 5818 5819 LLT PtrTy = MRI.getType(Dst); 5820 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 5821 5822 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 5823 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 5824 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 5825 5826 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 5827 // have to generate an extra instruction to negate the alloc and then use 5828 // G_PTR_ADD to add the negative offset. 5829 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 5830 if (Alignment > Align(1)) { 5831 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 5832 AlignMask.negate(); 5833 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 5834 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 5835 } 5836 5837 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 5838 MIRBuilder.buildCopy(SPReg, SPTmp); 5839 MIRBuilder.buildCopy(Dst, SPTmp); 5840 5841 MI.eraseFromParent(); 5842 return Legalized; 5843 } 5844 5845 LegalizerHelper::LegalizeResult 5846 LegalizerHelper::lowerExtract(MachineInstr &MI) { 5847 Register Dst = MI.getOperand(0).getReg(); 5848 Register Src = MI.getOperand(1).getReg(); 5849 unsigned Offset = MI.getOperand(2).getImm(); 5850 5851 LLT DstTy = MRI.getType(Dst); 5852 LLT SrcTy = MRI.getType(Src); 5853 5854 if (DstTy.isScalar() && 5855 (SrcTy.isScalar() || 5856 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 5857 LLT SrcIntTy = SrcTy; 5858 if (!SrcTy.isScalar()) { 5859 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 5860 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 5861 } 5862 5863 if (Offset == 0) 5864 MIRBuilder.buildTrunc(Dst, Src); 5865 else { 5866 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 5867 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 5868 MIRBuilder.buildTrunc(Dst, Shr); 5869 } 5870 5871 MI.eraseFromParent(); 5872 return Legalized; 5873 } 5874 5875 return UnableToLegalize; 5876 } 5877 5878 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 5879 Register Dst = MI.getOperand(0).getReg(); 5880 Register Src = MI.getOperand(1).getReg(); 5881 Register InsertSrc = MI.getOperand(2).getReg(); 5882 uint64_t Offset = MI.getOperand(3).getImm(); 5883 5884 LLT DstTy = MRI.getType(Src); 5885 LLT InsertTy = MRI.getType(InsertSrc); 5886 5887 if (InsertTy.isVector() || 5888 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 5889 return UnableToLegalize; 5890 5891 const DataLayout &DL = MIRBuilder.getDataLayout(); 5892 if ((DstTy.isPointer() && 5893 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 5894 (InsertTy.isPointer() && 5895 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 5896 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 5897 return UnableToLegalize; 5898 } 5899 5900 LLT IntDstTy = DstTy; 5901 5902 if (!DstTy.isScalar()) { 5903 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 5904 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 5905 } 5906 5907 if (!InsertTy.isScalar()) { 5908 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 5909 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 5910 } 5911 5912 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 5913 if (Offset != 0) { 5914 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 5915 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 5916 } 5917 5918 APInt MaskVal = APInt::getBitsSetWithWrap( 5919 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 5920 5921 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 5922 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 5923 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 5924 5925 MIRBuilder.buildCast(Dst, Or); 5926 MI.eraseFromParent(); 5927 return Legalized; 5928 } 5929 5930 LegalizerHelper::LegalizeResult 5931 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 5932 Register Dst0 = MI.getOperand(0).getReg(); 5933 Register Dst1 = MI.getOperand(1).getReg(); 5934 Register LHS = MI.getOperand(2).getReg(); 5935 Register RHS = MI.getOperand(3).getReg(); 5936 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 5937 5938 LLT Ty = MRI.getType(Dst0); 5939 LLT BoolTy = MRI.getType(Dst1); 5940 5941 if (IsAdd) 5942 MIRBuilder.buildAdd(Dst0, LHS, RHS); 5943 else 5944 MIRBuilder.buildSub(Dst0, LHS, RHS); 5945 5946 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 5947 5948 auto Zero = MIRBuilder.buildConstant(Ty, 0); 5949 5950 // For an addition, the result should be less than one of the operands (LHS) 5951 // if and only if the other operand (RHS) is negative, otherwise there will 5952 // be overflow. 5953 // For a subtraction, the result should be less than one of the operands 5954 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 5955 // otherwise there will be overflow. 5956 auto ResultLowerThanLHS = 5957 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 5958 auto ConditionRHS = MIRBuilder.buildICmp( 5959 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 5960 5961 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 5962 MI.eraseFromParent(); 5963 return Legalized; 5964 } 5965 5966 LegalizerHelper::LegalizeResult 5967 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 5968 Register Res = MI.getOperand(0).getReg(); 5969 Register LHS = MI.getOperand(1).getReg(); 5970 Register RHS = MI.getOperand(2).getReg(); 5971 LLT Ty = MRI.getType(Res); 5972 bool IsSigned; 5973 bool IsAdd; 5974 unsigned BaseOp; 5975 switch (MI.getOpcode()) { 5976 default: 5977 llvm_unreachable("unexpected addsat/subsat opcode"); 5978 case TargetOpcode::G_UADDSAT: 5979 IsSigned = false; 5980 IsAdd = true; 5981 BaseOp = TargetOpcode::G_ADD; 5982 break; 5983 case TargetOpcode::G_SADDSAT: 5984 IsSigned = true; 5985 IsAdd = true; 5986 BaseOp = TargetOpcode::G_ADD; 5987 break; 5988 case TargetOpcode::G_USUBSAT: 5989 IsSigned = false; 5990 IsAdd = false; 5991 BaseOp = TargetOpcode::G_SUB; 5992 break; 5993 case TargetOpcode::G_SSUBSAT: 5994 IsSigned = true; 5995 IsAdd = false; 5996 BaseOp = TargetOpcode::G_SUB; 5997 break; 5998 } 5999 6000 if (IsSigned) { 6001 // sadd.sat(a, b) -> 6002 // hi = 0x7fffffff - smax(a, 0) 6003 // lo = 0x80000000 - smin(a, 0) 6004 // a + smin(smax(lo, b), hi) 6005 // ssub.sat(a, b) -> 6006 // lo = smax(a, -1) - 0x7fffffff 6007 // hi = smin(a, -1) - 0x80000000 6008 // a - smin(smax(lo, b), hi) 6009 // TODO: AMDGPU can use a "median of 3" instruction here: 6010 // a +/- med3(lo, b, hi) 6011 uint64_t NumBits = Ty.getScalarSizeInBits(); 6012 auto MaxVal = 6013 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6014 auto MinVal = 6015 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6016 MachineInstrBuilder Hi, Lo; 6017 if (IsAdd) { 6018 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6019 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6020 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6021 } else { 6022 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6023 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6024 MaxVal); 6025 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6026 MinVal); 6027 } 6028 auto RHSClamped = 6029 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6030 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6031 } else { 6032 // uadd.sat(a, b) -> a + umin(~a, b) 6033 // usub.sat(a, b) -> a - umin(a, b) 6034 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6035 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6036 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6037 } 6038 6039 MI.eraseFromParent(); 6040 return Legalized; 6041 } 6042 6043 LegalizerHelper::LegalizeResult 6044 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6045 Register Res = MI.getOperand(0).getReg(); 6046 Register LHS = MI.getOperand(1).getReg(); 6047 Register RHS = MI.getOperand(2).getReg(); 6048 LLT Ty = MRI.getType(Res); 6049 LLT BoolTy = Ty.changeElementSize(1); 6050 bool IsSigned; 6051 bool IsAdd; 6052 unsigned OverflowOp; 6053 switch (MI.getOpcode()) { 6054 default: 6055 llvm_unreachable("unexpected addsat/subsat opcode"); 6056 case TargetOpcode::G_UADDSAT: 6057 IsSigned = false; 6058 IsAdd = true; 6059 OverflowOp = TargetOpcode::G_UADDO; 6060 break; 6061 case TargetOpcode::G_SADDSAT: 6062 IsSigned = true; 6063 IsAdd = true; 6064 OverflowOp = TargetOpcode::G_SADDO; 6065 break; 6066 case TargetOpcode::G_USUBSAT: 6067 IsSigned = false; 6068 IsAdd = false; 6069 OverflowOp = TargetOpcode::G_USUBO; 6070 break; 6071 case TargetOpcode::G_SSUBSAT: 6072 IsSigned = true; 6073 IsAdd = false; 6074 OverflowOp = TargetOpcode::G_SSUBO; 6075 break; 6076 } 6077 6078 auto OverflowRes = 6079 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6080 Register Tmp = OverflowRes.getReg(0); 6081 Register Ov = OverflowRes.getReg(1); 6082 MachineInstrBuilder Clamp; 6083 if (IsSigned) { 6084 // sadd.sat(a, b) -> 6085 // {tmp, ov} = saddo(a, b) 6086 // ov ? (tmp >>s 31) + 0x80000000 : r 6087 // ssub.sat(a, b) -> 6088 // {tmp, ov} = ssubo(a, b) 6089 // ov ? (tmp >>s 31) + 0x80000000 : r 6090 uint64_t NumBits = Ty.getScalarSizeInBits(); 6091 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6092 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6093 auto MinVal = 6094 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6095 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6096 } else { 6097 // uadd.sat(a, b) -> 6098 // {tmp, ov} = uaddo(a, b) 6099 // ov ? 0xffffffff : tmp 6100 // usub.sat(a, b) -> 6101 // {tmp, ov} = usubo(a, b) 6102 // ov ? 0 : tmp 6103 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6104 } 6105 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6106 6107 MI.eraseFromParent(); 6108 return Legalized; 6109 } 6110 6111 LegalizerHelper::LegalizeResult 6112 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6113 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6114 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6115 "Expected shlsat opcode!"); 6116 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6117 Register Res = MI.getOperand(0).getReg(); 6118 Register LHS = MI.getOperand(1).getReg(); 6119 Register RHS = MI.getOperand(2).getReg(); 6120 LLT Ty = MRI.getType(Res); 6121 LLT BoolTy = Ty.changeElementSize(1); 6122 6123 unsigned BW = Ty.getScalarSizeInBits(); 6124 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6125 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6126 : MIRBuilder.buildLShr(Ty, Result, RHS); 6127 6128 MachineInstrBuilder SatVal; 6129 if (IsSigned) { 6130 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6131 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6132 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6133 MIRBuilder.buildConstant(Ty, 0)); 6134 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6135 } else { 6136 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6137 } 6138 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6139 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6140 6141 MI.eraseFromParent(); 6142 return Legalized; 6143 } 6144 6145 LegalizerHelper::LegalizeResult 6146 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6147 Register Dst = MI.getOperand(0).getReg(); 6148 Register Src = MI.getOperand(1).getReg(); 6149 const LLT Ty = MRI.getType(Src); 6150 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6151 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6152 6153 // Swap most and least significant byte, set remaining bytes in Res to zero. 6154 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6155 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 6156 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6157 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 6158 6159 // Set i-th high/low byte in Res to i-th low/high byte from Src. 6160 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 6161 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 6162 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 6163 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 6164 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 6165 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 6166 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 6167 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 6168 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 6169 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 6170 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6171 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 6172 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 6173 } 6174 Res.getInstr()->getOperand(0).setReg(Dst); 6175 6176 MI.eraseFromParent(); 6177 return Legalized; 6178 } 6179 6180 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 6181 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 6182 MachineInstrBuilder Src, APInt Mask) { 6183 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 6184 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 6185 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 6186 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 6187 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 6188 return B.buildOr(Dst, LHS, RHS); 6189 } 6190 6191 LegalizerHelper::LegalizeResult 6192 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 6193 Register Dst = MI.getOperand(0).getReg(); 6194 Register Src = MI.getOperand(1).getReg(); 6195 const LLT Ty = MRI.getType(Src); 6196 unsigned Size = Ty.getSizeInBits(); 6197 6198 MachineInstrBuilder BSWAP = 6199 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 6200 6201 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 6202 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 6203 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 6204 MachineInstrBuilder Swap4 = 6205 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 6206 6207 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 6208 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 6209 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 6210 MachineInstrBuilder Swap2 = 6211 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 6212 6213 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 6214 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 6215 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 6216 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 6217 6218 MI.eraseFromParent(); 6219 return Legalized; 6220 } 6221 6222 LegalizerHelper::LegalizeResult 6223 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 6224 MachineFunction &MF = MIRBuilder.getMF(); 6225 6226 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 6227 int NameOpIdx = IsRead ? 1 : 0; 6228 int ValRegIndex = IsRead ? 0 : 1; 6229 6230 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 6231 const LLT Ty = MRI.getType(ValReg); 6232 const MDString *RegStr = cast<MDString>( 6233 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 6234 6235 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 6236 if (!PhysReg.isValid()) 6237 return UnableToLegalize; 6238 6239 if (IsRead) 6240 MIRBuilder.buildCopy(ValReg, PhysReg); 6241 else 6242 MIRBuilder.buildCopy(PhysReg, ValReg); 6243 6244 MI.eraseFromParent(); 6245 return Legalized; 6246 } 6247 6248 LegalizerHelper::LegalizeResult 6249 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 6250 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 6251 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 6252 Register Result = MI.getOperand(0).getReg(); 6253 LLT OrigTy = MRI.getType(Result); 6254 auto SizeInBits = OrigTy.getScalarSizeInBits(); 6255 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 6256 6257 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 6258 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 6259 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 6260 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 6261 6262 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 6263 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 6264 MIRBuilder.buildTrunc(Result, Shifted); 6265 6266 MI.eraseFromParent(); 6267 return Legalized; 6268 } 6269 6270 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 6271 // Implement vector G_SELECT in terms of XOR, AND, OR. 6272 Register DstReg = MI.getOperand(0).getReg(); 6273 Register MaskReg = MI.getOperand(1).getReg(); 6274 Register Op1Reg = MI.getOperand(2).getReg(); 6275 Register Op2Reg = MI.getOperand(3).getReg(); 6276 LLT DstTy = MRI.getType(DstReg); 6277 LLT MaskTy = MRI.getType(MaskReg); 6278 LLT Op1Ty = MRI.getType(Op1Reg); 6279 if (!DstTy.isVector()) 6280 return UnableToLegalize; 6281 6282 // Vector selects can have a scalar predicate. If so, splat into a vector and 6283 // finish for later legalization attempts to try again. 6284 if (MaskTy.isScalar()) { 6285 Register MaskElt = MaskReg; 6286 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 6287 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 6288 // Generate a vector splat idiom to be pattern matched later. 6289 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 6290 Observer.changingInstr(MI); 6291 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 6292 Observer.changedInstr(MI); 6293 return Legalized; 6294 } 6295 6296 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 6297 return UnableToLegalize; 6298 } 6299 6300 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 6301 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 6302 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 6303 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 6304 MI.eraseFromParent(); 6305 return Legalized; 6306 } 6307