1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
86       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
87     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
88                                                      : UnableToLegalize;
89   auto Step = LI.getAction(MI, MRI);
90   switch (Step.Action) {
91   case Legal:
92     LLVM_DEBUG(dbgs() << ".. Already legal\n");
93     return AlreadyLegal;
94   case Libcall:
95     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
96     return libcall(MI);
97   case NarrowScalar:
98     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
99     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
100   case WidenScalar:
101     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
102     return widenScalar(MI, Step.TypeIdx, Step.NewType);
103   case Lower:
104     LLVM_DEBUG(dbgs() << ".. Lower\n");
105     return lower(MI, Step.TypeIdx, Step.NewType);
106   case FewerElements:
107     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
108     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
109   case MoreElements:
110     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
111     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
112   case Custom:
113     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
114     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
115                                                             : UnableToLegalize;
116   default:
117     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
118     return UnableToLegalize;
119   }
120 }
121 
122 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
123                                    SmallVectorImpl<Register> &VRegs) {
124   for (int i = 0; i < NumParts; ++i)
125     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
126   MIRBuilder.buildUnmerge(VRegs, Reg);
127 }
128 
129 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
130                                    LLT MainTy, LLT &LeftoverTy,
131                                    SmallVectorImpl<Register> &VRegs,
132                                    SmallVectorImpl<Register> &LeftoverRegs) {
133   assert(!LeftoverTy.isValid() && "this is an out argument");
134 
135   unsigned RegSize = RegTy.getSizeInBits();
136   unsigned MainSize = MainTy.getSizeInBits();
137   unsigned NumParts = RegSize / MainSize;
138   unsigned LeftoverSize = RegSize - NumParts * MainSize;
139 
140   // Use an unmerge when possible.
141   if (LeftoverSize == 0) {
142     for (unsigned I = 0; I < NumParts; ++I)
143       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
144     MIRBuilder.buildUnmerge(VRegs, Reg);
145     return true;
146   }
147 
148   if (MainTy.isVector()) {
149     unsigned EltSize = MainTy.getScalarSizeInBits();
150     if (LeftoverSize % EltSize != 0)
151       return false;
152     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
153   } else {
154     LeftoverTy = LLT::scalar(LeftoverSize);
155   }
156 
157   // For irregular sizes, extract the individual parts.
158   for (unsigned I = 0; I != NumParts; ++I) {
159     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
160     VRegs.push_back(NewReg);
161     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
162   }
163 
164   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
165        Offset += LeftoverSize) {
166     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
167     LeftoverRegs.push_back(NewReg);
168     MIRBuilder.buildExtract(NewReg, Reg, Offset);
169   }
170 
171   return true;
172 }
173 
174 void LegalizerHelper::insertParts(Register DstReg,
175                                   LLT ResultTy, LLT PartTy,
176                                   ArrayRef<Register> PartRegs,
177                                   LLT LeftoverTy,
178                                   ArrayRef<Register> LeftoverRegs) {
179   if (!LeftoverTy.isValid()) {
180     assert(LeftoverRegs.empty());
181 
182     if (!ResultTy.isVector()) {
183       MIRBuilder.buildMerge(DstReg, PartRegs);
184       return;
185     }
186 
187     if (PartTy.isVector())
188       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
189     else
190       MIRBuilder.buildBuildVector(DstReg, PartRegs);
191     return;
192   }
193 
194   unsigned PartSize = PartTy.getSizeInBits();
195   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
196 
197   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
198   MIRBuilder.buildUndef(CurResultReg);
199 
200   unsigned Offset = 0;
201   for (Register PartReg : PartRegs) {
202     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
203     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
204     CurResultReg = NewResultReg;
205     Offset += PartSize;
206   }
207 
208   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
209     // Use the original output register for the final insert to avoid a copy.
210     Register NewResultReg = (I + 1 == E) ?
211       DstReg : MRI.createGenericVirtualRegister(ResultTy);
212 
213     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
214     CurResultReg = NewResultReg;
215     Offset += LeftoverPartSize;
216   }
217 }
218 
219 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
220   switch (Opcode) {
221   case TargetOpcode::G_SDIV:
222     assert((Size == 32 || Size == 64) && "Unsupported size");
223     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
224   case TargetOpcode::G_UDIV:
225     assert((Size == 32 || Size == 64) && "Unsupported size");
226     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
227   case TargetOpcode::G_SREM:
228     assert((Size == 32 || Size == 64) && "Unsupported size");
229     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
230   case TargetOpcode::G_UREM:
231     assert((Size == 32 || Size == 64) && "Unsupported size");
232     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
233   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
234     assert(Size == 32 && "Unsupported size");
235     return RTLIB::CTLZ_I32;
236   case TargetOpcode::G_FADD:
237     assert((Size == 32 || Size == 64) && "Unsupported size");
238     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
239   case TargetOpcode::G_FSUB:
240     assert((Size == 32 || Size == 64) && "Unsupported size");
241     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
242   case TargetOpcode::G_FMUL:
243     assert((Size == 32 || Size == 64) && "Unsupported size");
244     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
245   case TargetOpcode::G_FDIV:
246     assert((Size == 32 || Size == 64) && "Unsupported size");
247     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
248   case TargetOpcode::G_FEXP:
249     assert((Size == 32 || Size == 64) && "Unsupported size");
250     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
251   case TargetOpcode::G_FEXP2:
252     assert((Size == 32 || Size == 64) && "Unsupported size");
253     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
254   case TargetOpcode::G_FREM:
255     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
256   case TargetOpcode::G_FPOW:
257     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
258   case TargetOpcode::G_FMA:
259     assert((Size == 32 || Size == 64) && "Unsupported size");
260     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
261   case TargetOpcode::G_FSIN:
262     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
263     return Size == 128 ? RTLIB::SIN_F128
264                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
265   case TargetOpcode::G_FCOS:
266     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
267     return Size == 128 ? RTLIB::COS_F128
268                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
269   case TargetOpcode::G_FLOG10:
270     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
271     return Size == 128 ? RTLIB::LOG10_F128
272                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
273   case TargetOpcode::G_FLOG:
274     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
275     return Size == 128 ? RTLIB::LOG_F128
276                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
277   case TargetOpcode::G_FLOG2:
278     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
279     return Size == 128 ? RTLIB::LOG2_F128
280                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
281   case TargetOpcode::G_FCEIL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
284   case TargetOpcode::G_FFLOOR:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
287   }
288   llvm_unreachable("Unknown libcall function");
289 }
290 
291 LegalizerHelper::LegalizeResult
292 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
293                     const CallLowering::ArgInfo &Result,
294                     ArrayRef<CallLowering::ArgInfo> Args) {
295   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
296   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
297   const char *Name = TLI.getLibcallName(Libcall);
298 
299   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
300   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
301                      MachineOperand::CreateES(Name), Result, Args))
302     return LegalizerHelper::UnableToLegalize;
303 
304   return LegalizerHelper::Legalized;
305 }
306 
307 // Useful for libcalls where all operands have the same type.
308 static LegalizerHelper::LegalizeResult
309 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
310               Type *OpType) {
311   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
312 
313   SmallVector<CallLowering::ArgInfo, 3> Args;
314   for (unsigned i = 1; i < MI.getNumOperands(); i++)
315     Args.push_back({MI.getOperand(i).getReg(), OpType});
316   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
317                        Args);
318 }
319 
320 LegalizerHelper::LegalizeResult
321 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
322                        MachineInstr &MI) {
323   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
324   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
325 
326   SmallVector<CallLowering::ArgInfo, 3> Args;
327   for (unsigned i = 1; i < MI.getNumOperands(); i++) {
328     Register Reg = MI.getOperand(i).getReg();
329 
330     // Need derive an IR type for call lowering.
331     LLT OpLLT = MRI.getType(Reg);
332     Type *OpTy = nullptr;
333     if (OpLLT.isPointer())
334       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
335     else
336       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
337     Args.push_back({Reg, OpTy});
338   }
339 
340   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
341   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
342   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
343   RTLIB::Libcall RTLibcall;
344   switch (ID) {
345   case Intrinsic::memcpy:
346     RTLibcall = RTLIB::MEMCPY;
347     break;
348   case Intrinsic::memset:
349     RTLibcall = RTLIB::MEMSET;
350     break;
351   case Intrinsic::memmove:
352     RTLibcall = RTLIB::MEMMOVE;
353     break;
354   default:
355     return LegalizerHelper::UnableToLegalize;
356   }
357   const char *Name = TLI.getLibcallName(RTLibcall);
358 
359   MIRBuilder.setInstr(MI);
360   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
361   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(RTLibcall),
362                      MachineOperand::CreateES(Name),
363                      CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)), Args))
364     return LegalizerHelper::UnableToLegalize;
365 
366   return LegalizerHelper::Legalized;
367 }
368 
369 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
370                                        Type *FromType) {
371   auto ToMVT = MVT::getVT(ToType);
372   auto FromMVT = MVT::getVT(FromType);
373 
374   switch (Opcode) {
375   case TargetOpcode::G_FPEXT:
376     return RTLIB::getFPEXT(FromMVT, ToMVT);
377   case TargetOpcode::G_FPTRUNC:
378     return RTLIB::getFPROUND(FromMVT, ToMVT);
379   case TargetOpcode::G_FPTOSI:
380     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
381   case TargetOpcode::G_FPTOUI:
382     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
383   case TargetOpcode::G_SITOFP:
384     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
385   case TargetOpcode::G_UITOFP:
386     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
387   }
388   llvm_unreachable("Unsupported libcall function");
389 }
390 
391 static LegalizerHelper::LegalizeResult
392 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
393                   Type *FromType) {
394   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
395   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
396                        {{MI.getOperand(1).getReg(), FromType}});
397 }
398 
399 LegalizerHelper::LegalizeResult
400 LegalizerHelper::libcall(MachineInstr &MI) {
401   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
402   unsigned Size = LLTy.getSizeInBits();
403   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
404 
405   MIRBuilder.setInstr(MI);
406 
407   switch (MI.getOpcode()) {
408   default:
409     return UnableToLegalize;
410   case TargetOpcode::G_SDIV:
411   case TargetOpcode::G_UDIV:
412   case TargetOpcode::G_SREM:
413   case TargetOpcode::G_UREM:
414   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
415     Type *HLTy = IntegerType::get(Ctx, Size);
416     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
417     if (Status != Legalized)
418       return Status;
419     break;
420   }
421   case TargetOpcode::G_FADD:
422   case TargetOpcode::G_FSUB:
423   case TargetOpcode::G_FMUL:
424   case TargetOpcode::G_FDIV:
425   case TargetOpcode::G_FMA:
426   case TargetOpcode::G_FPOW:
427   case TargetOpcode::G_FREM:
428   case TargetOpcode::G_FCOS:
429   case TargetOpcode::G_FSIN:
430   case TargetOpcode::G_FLOG10:
431   case TargetOpcode::G_FLOG:
432   case TargetOpcode::G_FLOG2:
433   case TargetOpcode::G_FEXP:
434   case TargetOpcode::G_FEXP2:
435   case TargetOpcode::G_FCEIL:
436   case TargetOpcode::G_FFLOOR: {
437     if (Size > 64) {
438       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
439       return UnableToLegalize;
440     }
441     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
442     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
443     if (Status != Legalized)
444       return Status;
445     break;
446   }
447   case TargetOpcode::G_FPEXT: {
448     // FIXME: Support other floating point types (half, fp128 etc)
449     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
450     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
451     if (ToSize != 64 || FromSize != 32)
452       return UnableToLegalize;
453     LegalizeResult Status = conversionLibcall(
454         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
455     if (Status != Legalized)
456       return Status;
457     break;
458   }
459   case TargetOpcode::G_FPTRUNC: {
460     // FIXME: Support other floating point types (half, fp128 etc)
461     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
462     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
463     if (ToSize != 32 || FromSize != 64)
464       return UnableToLegalize;
465     LegalizeResult Status = conversionLibcall(
466         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
467     if (Status != Legalized)
468       return Status;
469     break;
470   }
471   case TargetOpcode::G_FPTOSI:
472   case TargetOpcode::G_FPTOUI: {
473     // FIXME: Support other types
474     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
475     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
476     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
477       return UnableToLegalize;
478     LegalizeResult Status = conversionLibcall(
479         MI, MIRBuilder,
480         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
481         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
482     if (Status != Legalized)
483       return Status;
484     break;
485   }
486   case TargetOpcode::G_SITOFP:
487   case TargetOpcode::G_UITOFP: {
488     // FIXME: Support other types
489     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
490     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
491     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
492       return UnableToLegalize;
493     LegalizeResult Status = conversionLibcall(
494         MI, MIRBuilder,
495         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
496         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
497     if (Status != Legalized)
498       return Status;
499     break;
500   }
501   }
502 
503   MI.eraseFromParent();
504   return Legalized;
505 }
506 
507 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
508                                                               unsigned TypeIdx,
509                                                               LLT NarrowTy) {
510   MIRBuilder.setInstr(MI);
511 
512   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
513   uint64_t NarrowSize = NarrowTy.getSizeInBits();
514 
515   switch (MI.getOpcode()) {
516   default:
517     return UnableToLegalize;
518   case TargetOpcode::G_IMPLICIT_DEF: {
519     // FIXME: add support for when SizeOp0 isn't an exact multiple of
520     // NarrowSize.
521     if (SizeOp0 % NarrowSize != 0)
522       return UnableToLegalize;
523     int NumParts = SizeOp0 / NarrowSize;
524 
525     SmallVector<Register, 2> DstRegs;
526     for (int i = 0; i < NumParts; ++i)
527       DstRegs.push_back(
528           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
529 
530     Register DstReg = MI.getOperand(0).getReg();
531     if(MRI.getType(DstReg).isVector())
532       MIRBuilder.buildBuildVector(DstReg, DstRegs);
533     else
534       MIRBuilder.buildMerge(DstReg, DstRegs);
535     MI.eraseFromParent();
536     return Legalized;
537   }
538   case TargetOpcode::G_CONSTANT: {
539     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
540     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
541     unsigned TotalSize = Ty.getSizeInBits();
542     unsigned NarrowSize = NarrowTy.getSizeInBits();
543     int NumParts = TotalSize / NarrowSize;
544 
545     SmallVector<Register, 4> PartRegs;
546     for (int I = 0; I != NumParts; ++I) {
547       unsigned Offset = I * NarrowSize;
548       auto K = MIRBuilder.buildConstant(NarrowTy,
549                                         Val.lshr(Offset).trunc(NarrowSize));
550       PartRegs.push_back(K.getReg(0));
551     }
552 
553     LLT LeftoverTy;
554     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
555     SmallVector<Register, 1> LeftoverRegs;
556     if (LeftoverBits != 0) {
557       LeftoverTy = LLT::scalar(LeftoverBits);
558       auto K = MIRBuilder.buildConstant(
559         LeftoverTy,
560         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
561       LeftoverRegs.push_back(K.getReg(0));
562     }
563 
564     insertParts(MI.getOperand(0).getReg(),
565                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
566 
567     MI.eraseFromParent();
568     return Legalized;
569   }
570   case TargetOpcode::G_SEXT: {
571     if (TypeIdx != 0)
572       return UnableToLegalize;
573 
574     if (NarrowTy.getSizeInBits() != SizeOp0 / 2) {
575       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
576       return UnableToLegalize;
577     }
578 
579     Register SrcReg = MI.getOperand(1).getReg();
580 
581     // Shift the sign bit of the low register through the high register.
582     auto ShiftAmt =
583         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
584     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
585     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
586     MI.eraseFromParent();
587     return Legalized;
588   }
589 
590   case TargetOpcode::G_ADD: {
591     // FIXME: add support for when SizeOp0 isn't an exact multiple of
592     // NarrowSize.
593     if (SizeOp0 % NarrowSize != 0)
594       return UnableToLegalize;
595     // Expand in terms of carry-setting/consuming G_ADDE instructions.
596     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
597 
598     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
599     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
600     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
601 
602     Register CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
603     MIRBuilder.buildConstant(CarryIn, 0);
604 
605     for (int i = 0; i < NumParts; ++i) {
606       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
607       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
608 
609       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
610                             Src2Regs[i], CarryIn);
611 
612       DstRegs.push_back(DstReg);
613       CarryIn = CarryOut;
614     }
615     Register DstReg = MI.getOperand(0).getReg();
616     if(MRI.getType(DstReg).isVector())
617       MIRBuilder.buildBuildVector(DstReg, DstRegs);
618     else
619       MIRBuilder.buildMerge(DstReg, DstRegs);
620     MI.eraseFromParent();
621     return Legalized;
622   }
623   case TargetOpcode::G_SUB: {
624     // FIXME: add support for when SizeOp0 isn't an exact multiple of
625     // NarrowSize.
626     if (SizeOp0 % NarrowSize != 0)
627       return UnableToLegalize;
628 
629     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
630 
631     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
632     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
633     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
634 
635     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
636     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
637     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
638                           {Src1Regs[0], Src2Regs[0]});
639     DstRegs.push_back(DstReg);
640     Register BorrowIn = BorrowOut;
641     for (int i = 1; i < NumParts; ++i) {
642       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
643       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
644 
645       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
646                             {Src1Regs[i], Src2Regs[i], BorrowIn});
647 
648       DstRegs.push_back(DstReg);
649       BorrowIn = BorrowOut;
650     }
651     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
652     MI.eraseFromParent();
653     return Legalized;
654   }
655   case TargetOpcode::G_MUL:
656   case TargetOpcode::G_UMULH:
657     return narrowScalarMul(MI, NarrowTy);
658   case TargetOpcode::G_EXTRACT:
659     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
660   case TargetOpcode::G_INSERT:
661     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
662   case TargetOpcode::G_LOAD: {
663     const auto &MMO = **MI.memoperands_begin();
664     Register DstReg = MI.getOperand(0).getReg();
665     LLT DstTy = MRI.getType(DstReg);
666     if (DstTy.isVector())
667       return UnableToLegalize;
668 
669     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
670       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
671       auto &MMO = **MI.memoperands_begin();
672       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
673       MIRBuilder.buildAnyExt(DstReg, TmpReg);
674       MI.eraseFromParent();
675       return Legalized;
676     }
677 
678     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
679   }
680   case TargetOpcode::G_ZEXTLOAD:
681   case TargetOpcode::G_SEXTLOAD: {
682     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
683     Register DstReg = MI.getOperand(0).getReg();
684     Register PtrReg = MI.getOperand(1).getReg();
685 
686     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
687     auto &MMO = **MI.memoperands_begin();
688     if (MMO.getSizeInBits() == NarrowSize) {
689       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
690     } else {
691       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
692         : TargetOpcode::G_SEXTLOAD;
693       MIRBuilder.buildInstr(ExtLoad)
694         .addDef(TmpReg)
695         .addUse(PtrReg)
696         .addMemOperand(&MMO);
697     }
698 
699     if (ZExt)
700       MIRBuilder.buildZExt(DstReg, TmpReg);
701     else
702       MIRBuilder.buildSExt(DstReg, TmpReg);
703 
704     MI.eraseFromParent();
705     return Legalized;
706   }
707   case TargetOpcode::G_STORE: {
708     const auto &MMO = **MI.memoperands_begin();
709 
710     Register SrcReg = MI.getOperand(0).getReg();
711     LLT SrcTy = MRI.getType(SrcReg);
712     if (SrcTy.isVector())
713       return UnableToLegalize;
714 
715     int NumParts = SizeOp0 / NarrowSize;
716     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
717     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
718     if (SrcTy.isVector() && LeftoverBits != 0)
719       return UnableToLegalize;
720 
721     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
722       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
723       auto &MMO = **MI.memoperands_begin();
724       MIRBuilder.buildTrunc(TmpReg, SrcReg);
725       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
726       MI.eraseFromParent();
727       return Legalized;
728     }
729 
730     return reduceLoadStoreWidth(MI, 0, NarrowTy);
731   }
732   case TargetOpcode::G_SELECT:
733     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
734   case TargetOpcode::G_AND:
735   case TargetOpcode::G_OR:
736   case TargetOpcode::G_XOR: {
737     // Legalize bitwise operation:
738     // A = BinOp<Ty> B, C
739     // into:
740     // B1, ..., BN = G_UNMERGE_VALUES B
741     // C1, ..., CN = G_UNMERGE_VALUES C
742     // A1 = BinOp<Ty/N> B1, C2
743     // ...
744     // AN = BinOp<Ty/N> BN, CN
745     // A = G_MERGE_VALUES A1, ..., AN
746     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
747   }
748   case TargetOpcode::G_SHL:
749   case TargetOpcode::G_LSHR:
750   case TargetOpcode::G_ASHR:
751     return narrowScalarShift(MI, TypeIdx, NarrowTy);
752   case TargetOpcode::G_CTLZ:
753   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
754   case TargetOpcode::G_CTTZ:
755   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
756   case TargetOpcode::G_CTPOP:
757     if (TypeIdx != 0)
758       return UnableToLegalize; // TODO
759 
760     Observer.changingInstr(MI);
761     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
762     Observer.changedInstr(MI);
763     return Legalized;
764   case TargetOpcode::G_INTTOPTR:
765     if (TypeIdx != 1)
766       return UnableToLegalize;
767 
768     Observer.changingInstr(MI);
769     narrowScalarSrc(MI, NarrowTy, 1);
770     Observer.changedInstr(MI);
771     return Legalized;
772   case TargetOpcode::G_PTRTOINT:
773     if (TypeIdx != 0)
774       return UnableToLegalize;
775 
776     Observer.changingInstr(MI);
777     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
778     Observer.changedInstr(MI);
779     return Legalized;
780   case TargetOpcode::G_PHI: {
781     unsigned NumParts = SizeOp0 / NarrowSize;
782     SmallVector<Register, 2> DstRegs;
783     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
784     DstRegs.resize(NumParts);
785     SrcRegs.resize(MI.getNumOperands() / 2);
786     Observer.changingInstr(MI);
787     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
788       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
789       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
790       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
791                    SrcRegs[i / 2]);
792     }
793     MachineBasicBlock &MBB = *MI.getParent();
794     MIRBuilder.setInsertPt(MBB, MI);
795     for (unsigned i = 0; i < NumParts; ++i) {
796       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
797       MachineInstrBuilder MIB =
798           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
799       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
800         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
801     }
802     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
803     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
804     Observer.changedInstr(MI);
805     MI.eraseFromParent();
806     return Legalized;
807   }
808   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
809   case TargetOpcode::G_INSERT_VECTOR_ELT: {
810     if (TypeIdx != 2)
811       return UnableToLegalize;
812 
813     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
814     Observer.changingInstr(MI);
815     narrowScalarSrc(MI, NarrowTy, OpIdx);
816     Observer.changedInstr(MI);
817     return Legalized;
818   }
819   case TargetOpcode::G_ICMP: {
820     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
821     if (NarrowSize * 2 != SrcSize)
822       return UnableToLegalize;
823 
824     Observer.changingInstr(MI);
825     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
826     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
827     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
828 
829     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
830     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
831     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
832 
833     CmpInst::Predicate Pred =
834         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
835     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
836 
837     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
838       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
839       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
840       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
841       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
842       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
843     } else {
844       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
845       MachineInstrBuilder CmpHEQ =
846           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
847       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
848           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
849       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
850     }
851     Observer.changedInstr(MI);
852     MI.eraseFromParent();
853     return Legalized;
854   }
855   }
856 }
857 
858 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
859                                      unsigned OpIdx, unsigned ExtOpcode) {
860   MachineOperand &MO = MI.getOperand(OpIdx);
861   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
862   MO.setReg(ExtB->getOperand(0).getReg());
863 }
864 
865 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
866                                       unsigned OpIdx) {
867   MachineOperand &MO = MI.getOperand(OpIdx);
868   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
869                                     {MO.getReg()});
870   MO.setReg(ExtB->getOperand(0).getReg());
871 }
872 
873 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
874                                      unsigned OpIdx, unsigned TruncOpcode) {
875   MachineOperand &MO = MI.getOperand(OpIdx);
876   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
877   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
878   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
879   MO.setReg(DstExt);
880 }
881 
882 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
883                                       unsigned OpIdx, unsigned ExtOpcode) {
884   MachineOperand &MO = MI.getOperand(OpIdx);
885   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
886   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
887   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
888   MO.setReg(DstTrunc);
889 }
890 
891 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
892                                             unsigned OpIdx) {
893   MachineOperand &MO = MI.getOperand(OpIdx);
894   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
895   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
896   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
897   MO.setReg(DstExt);
898 }
899 
900 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
901                                             unsigned OpIdx) {
902   MachineOperand &MO = MI.getOperand(OpIdx);
903 
904   LLT OldTy = MRI.getType(MO.getReg());
905   unsigned OldElts = OldTy.getNumElements();
906   unsigned NewElts = MoreTy.getNumElements();
907 
908   unsigned NumParts = NewElts / OldElts;
909 
910   // Use concat_vectors if the result is a multiple of the number of elements.
911   if (NumParts * OldElts == NewElts) {
912     SmallVector<Register, 8> Parts;
913     Parts.push_back(MO.getReg());
914 
915     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
916     for (unsigned I = 1; I != NumParts; ++I)
917       Parts.push_back(ImpDef);
918 
919     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
920     MO.setReg(Concat.getReg(0));
921     return;
922   }
923 
924   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
925   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
926   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
927   MO.setReg(MoreReg);
928 }
929 
930 LegalizerHelper::LegalizeResult
931 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
932                                         LLT WideTy) {
933   if (TypeIdx != 1)
934     return UnableToLegalize;
935 
936   Register DstReg = MI.getOperand(0).getReg();
937   LLT DstTy = MRI.getType(DstReg);
938   if (DstTy.isVector())
939     return UnableToLegalize;
940 
941   Register Src1 = MI.getOperand(1).getReg();
942   LLT SrcTy = MRI.getType(Src1);
943   const int DstSize = DstTy.getSizeInBits();
944   const int SrcSize = SrcTy.getSizeInBits();
945   const int WideSize = WideTy.getSizeInBits();
946   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
947 
948   unsigned NumOps = MI.getNumOperands();
949   unsigned NumSrc = MI.getNumOperands() - 1;
950   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
951 
952   if (WideSize >= DstSize) {
953     // Directly pack the bits in the target type.
954     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
955 
956     for (unsigned I = 2; I != NumOps; ++I) {
957       const unsigned Offset = (I - 1) * PartSize;
958 
959       Register SrcReg = MI.getOperand(I).getReg();
960       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
961 
962       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
963 
964       Register NextResult = I + 1 == NumOps && WideSize == DstSize ? DstReg :
965         MRI.createGenericVirtualRegister(WideTy);
966 
967       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
968       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
969       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
970       ResultReg = NextResult;
971     }
972 
973     if (WideSize > DstSize)
974       MIRBuilder.buildTrunc(DstReg, ResultReg);
975 
976     MI.eraseFromParent();
977     return Legalized;
978   }
979 
980   // Unmerge the original values to the GCD type, and recombine to the next
981   // multiple greater than the original type.
982   //
983   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
984   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
985   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
986   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
987   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
988   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
989   // %12:_(s12) = G_MERGE_VALUES %10, %11
990   //
991   // Padding with undef if necessary:
992   //
993   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
994   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
995   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
996   // %7:_(s2) = G_IMPLICIT_DEF
997   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
998   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
999   // %10:_(s12) = G_MERGE_VALUES %8, %9
1000 
1001   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1002   LLT GCDTy = LLT::scalar(GCD);
1003 
1004   SmallVector<Register, 8> Parts;
1005   SmallVector<Register, 8> NewMergeRegs;
1006   SmallVector<Register, 8> Unmerges;
1007   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1008 
1009   // Decompose the original operands if they don't evenly divide.
1010   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1011     Register SrcReg = MI.getOperand(I).getReg();
1012     if (GCD == SrcSize) {
1013       Unmerges.push_back(SrcReg);
1014     } else {
1015       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1016       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1017         Unmerges.push_back(Unmerge.getReg(J));
1018     }
1019   }
1020 
1021   // Pad with undef to the next size that is a multiple of the requested size.
1022   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1023     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1024     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1025       Unmerges.push_back(UndefReg);
1026   }
1027 
1028   const int PartsPerGCD = WideSize / GCD;
1029 
1030   // Build merges of each piece.
1031   ArrayRef<Register> Slicer(Unmerges);
1032   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1033     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1034     NewMergeRegs.push_back(Merge.getReg(0));
1035   }
1036 
1037   // A truncate may be necessary if the requested type doesn't evenly divide the
1038   // original result type.
1039   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1040     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1041   } else {
1042     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1043     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1044   }
1045 
1046   MI.eraseFromParent();
1047   return Legalized;
1048 }
1049 
1050 LegalizerHelper::LegalizeResult
1051 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1052                                           LLT WideTy) {
1053   if (TypeIdx != 0)
1054     return UnableToLegalize;
1055 
1056   unsigned NumDst = MI.getNumOperands() - 1;
1057   Register SrcReg = MI.getOperand(NumDst).getReg();
1058   LLT SrcTy = MRI.getType(SrcReg);
1059   if (!SrcTy.isScalar())
1060     return UnableToLegalize;
1061 
1062   Register Dst0Reg = MI.getOperand(0).getReg();
1063   LLT DstTy = MRI.getType(Dst0Reg);
1064   if (!DstTy.isScalar())
1065     return UnableToLegalize;
1066 
1067   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1068   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1069   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1070 
1071   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1072 
1073   for (unsigned I = 1; I != NumDst; ++I) {
1074     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1075     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1076     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1077   }
1078 
1079   Observer.changingInstr(MI);
1080 
1081   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1082   for (unsigned I = 0; I != NumDst; ++I)
1083     widenScalarDst(MI, WideTy, I);
1084 
1085   Observer.changedInstr(MI);
1086 
1087   return Legalized;
1088 }
1089 
1090 LegalizerHelper::LegalizeResult
1091 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1092                                     LLT WideTy) {
1093   Register DstReg = MI.getOperand(0).getReg();
1094   Register SrcReg = MI.getOperand(1).getReg();
1095   LLT SrcTy = MRI.getType(SrcReg);
1096 
1097   LLT DstTy = MRI.getType(DstReg);
1098   unsigned Offset = MI.getOperand(2).getImm();
1099 
1100   if (TypeIdx == 0) {
1101     if (SrcTy.isVector() || DstTy.isVector())
1102       return UnableToLegalize;
1103 
1104     SrcOp Src(SrcReg);
1105     if (SrcTy.isPointer()) {
1106       // Extracts from pointers can be handled only if they are really just
1107       // simple integers.
1108       const DataLayout &DL = MIRBuilder.getDataLayout();
1109       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1110         return UnableToLegalize;
1111 
1112       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1113       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1114       SrcTy = SrcAsIntTy;
1115     }
1116 
1117     if (DstTy.isPointer())
1118       return UnableToLegalize;
1119 
1120     if (Offset == 0) {
1121       // Avoid a shift in the degenerate case.
1122       MIRBuilder.buildTrunc(DstReg,
1123                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1124       MI.eraseFromParent();
1125       return Legalized;
1126     }
1127 
1128     // Do a shift in the source type.
1129     LLT ShiftTy = SrcTy;
1130     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1131       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1132       ShiftTy = WideTy;
1133     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1134       return UnableToLegalize;
1135 
1136     auto LShr = MIRBuilder.buildLShr(
1137       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1138     MIRBuilder.buildTrunc(DstReg, LShr);
1139     MI.eraseFromParent();
1140     return Legalized;
1141   }
1142 
1143   if (SrcTy.isScalar()) {
1144     Observer.changingInstr(MI);
1145     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1146     Observer.changedInstr(MI);
1147     return Legalized;
1148   }
1149 
1150   if (!SrcTy.isVector())
1151     return UnableToLegalize;
1152 
1153   if (DstTy != SrcTy.getElementType())
1154     return UnableToLegalize;
1155 
1156   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1157     return UnableToLegalize;
1158 
1159   Observer.changingInstr(MI);
1160   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1161 
1162   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1163                           Offset);
1164   widenScalarDst(MI, WideTy.getScalarType(), 0);
1165   Observer.changedInstr(MI);
1166   return Legalized;
1167 }
1168 
1169 LegalizerHelper::LegalizeResult
1170 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1171                                    LLT WideTy) {
1172   if (TypeIdx != 0)
1173     return UnableToLegalize;
1174   Observer.changingInstr(MI);
1175   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1176   widenScalarDst(MI, WideTy);
1177   Observer.changedInstr(MI);
1178   return Legalized;
1179 }
1180 
1181 LegalizerHelper::LegalizeResult
1182 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1183   MIRBuilder.setInstr(MI);
1184 
1185   switch (MI.getOpcode()) {
1186   default:
1187     return UnableToLegalize;
1188   case TargetOpcode::G_EXTRACT:
1189     return widenScalarExtract(MI, TypeIdx, WideTy);
1190   case TargetOpcode::G_INSERT:
1191     return widenScalarInsert(MI, TypeIdx, WideTy);
1192   case TargetOpcode::G_MERGE_VALUES:
1193     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1194   case TargetOpcode::G_UNMERGE_VALUES:
1195     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1196   case TargetOpcode::G_UADDO:
1197   case TargetOpcode::G_USUBO: {
1198     if (TypeIdx == 1)
1199       return UnableToLegalize; // TODO
1200     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1201                                          {MI.getOperand(2).getReg()});
1202     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1203                                          {MI.getOperand(3).getReg()});
1204     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1205                           ? TargetOpcode::G_ADD
1206                           : TargetOpcode::G_SUB;
1207     // Do the arithmetic in the larger type.
1208     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1209     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1210     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1211     auto AndOp = MIRBuilder.buildInstr(
1212         TargetOpcode::G_AND, {WideTy},
1213         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1214     // There is no overflow if the AndOp is the same as NewOp.
1215     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1216                          AndOp);
1217     // Now trunc the NewOp to the original result.
1218     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1219     MI.eraseFromParent();
1220     return Legalized;
1221   }
1222   case TargetOpcode::G_CTTZ:
1223   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1224   case TargetOpcode::G_CTLZ:
1225   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1226   case TargetOpcode::G_CTPOP: {
1227     if (TypeIdx == 0) {
1228       Observer.changingInstr(MI);
1229       widenScalarDst(MI, WideTy, 0);
1230       Observer.changedInstr(MI);
1231       return Legalized;
1232     }
1233 
1234     Register SrcReg = MI.getOperand(1).getReg();
1235 
1236     // First ZEXT the input.
1237     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1238     LLT CurTy = MRI.getType(SrcReg);
1239     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1240       // The count is the same in the larger type except if the original
1241       // value was zero.  This can be handled by setting the bit just off
1242       // the top of the original type.
1243       auto TopBit =
1244           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1245       MIBSrc = MIRBuilder.buildOr(
1246         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1247     }
1248 
1249     // Perform the operation at the larger size.
1250     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1251     // This is already the correct result for CTPOP and CTTZs
1252     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1253         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1254       // The correct result is NewOp - (Difference in widety and current ty).
1255       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1256       MIBNewOp = MIRBuilder.buildInstr(
1257           TargetOpcode::G_SUB, {WideTy},
1258           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1259     }
1260 
1261     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1262     MI.eraseFromParent();
1263     return Legalized;
1264   }
1265   case TargetOpcode::G_BSWAP: {
1266     Observer.changingInstr(MI);
1267     Register DstReg = MI.getOperand(0).getReg();
1268 
1269     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1270     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1271     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1272     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1273 
1274     MI.getOperand(0).setReg(DstExt);
1275 
1276     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1277 
1278     LLT Ty = MRI.getType(DstReg);
1279     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1280     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1281     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1282       .addDef(ShrReg)
1283       .addUse(DstExt)
1284       .addUse(ShiftAmtReg);
1285 
1286     MIRBuilder.buildTrunc(DstReg, ShrReg);
1287     Observer.changedInstr(MI);
1288     return Legalized;
1289   }
1290   case TargetOpcode::G_ADD:
1291   case TargetOpcode::G_AND:
1292   case TargetOpcode::G_MUL:
1293   case TargetOpcode::G_OR:
1294   case TargetOpcode::G_XOR:
1295   case TargetOpcode::G_SUB:
1296     // Perform operation at larger width (any extension is fines here, high bits
1297     // don't affect the result) and then truncate the result back to the
1298     // original type.
1299     Observer.changingInstr(MI);
1300     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1301     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1302     widenScalarDst(MI, WideTy);
1303     Observer.changedInstr(MI);
1304     return Legalized;
1305 
1306   case TargetOpcode::G_SHL:
1307     Observer.changingInstr(MI);
1308 
1309     if (TypeIdx == 0) {
1310       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1311       widenScalarDst(MI, WideTy);
1312     } else {
1313       assert(TypeIdx == 1);
1314       // The "number of bits to shift" operand must preserve its value as an
1315       // unsigned integer:
1316       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1317     }
1318 
1319     Observer.changedInstr(MI);
1320     return Legalized;
1321 
1322   case TargetOpcode::G_SDIV:
1323   case TargetOpcode::G_SREM:
1324   case TargetOpcode::G_SMIN:
1325   case TargetOpcode::G_SMAX:
1326     Observer.changingInstr(MI);
1327     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1328     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1329     widenScalarDst(MI, WideTy);
1330     Observer.changedInstr(MI);
1331     return Legalized;
1332 
1333   case TargetOpcode::G_ASHR:
1334   case TargetOpcode::G_LSHR:
1335     Observer.changingInstr(MI);
1336 
1337     if (TypeIdx == 0) {
1338       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1339         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1340 
1341       widenScalarSrc(MI, WideTy, 1, CvtOp);
1342       widenScalarDst(MI, WideTy);
1343     } else {
1344       assert(TypeIdx == 1);
1345       // The "number of bits to shift" operand must preserve its value as an
1346       // unsigned integer:
1347       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1348     }
1349 
1350     Observer.changedInstr(MI);
1351     return Legalized;
1352   case TargetOpcode::G_UDIV:
1353   case TargetOpcode::G_UREM:
1354   case TargetOpcode::G_UMIN:
1355   case TargetOpcode::G_UMAX:
1356     Observer.changingInstr(MI);
1357     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1358     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1359     widenScalarDst(MI, WideTy);
1360     Observer.changedInstr(MI);
1361     return Legalized;
1362 
1363   case TargetOpcode::G_SELECT:
1364     Observer.changingInstr(MI);
1365     if (TypeIdx == 0) {
1366       // Perform operation at larger width (any extension is fine here, high
1367       // bits don't affect the result) and then truncate the result back to the
1368       // original type.
1369       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1370       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1371       widenScalarDst(MI, WideTy);
1372     } else {
1373       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1374       // Explicit extension is required here since high bits affect the result.
1375       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1376     }
1377     Observer.changedInstr(MI);
1378     return Legalized;
1379 
1380   case TargetOpcode::G_FPTOSI:
1381   case TargetOpcode::G_FPTOUI:
1382     if (TypeIdx != 0)
1383       return UnableToLegalize;
1384     Observer.changingInstr(MI);
1385     widenScalarDst(MI, WideTy);
1386     Observer.changedInstr(MI);
1387     return Legalized;
1388 
1389   case TargetOpcode::G_SITOFP:
1390     if (TypeIdx != 1)
1391       return UnableToLegalize;
1392     Observer.changingInstr(MI);
1393     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1394     Observer.changedInstr(MI);
1395     return Legalized;
1396 
1397   case TargetOpcode::G_UITOFP:
1398     if (TypeIdx != 1)
1399       return UnableToLegalize;
1400     Observer.changingInstr(MI);
1401     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1402     Observer.changedInstr(MI);
1403     return Legalized;
1404 
1405   case TargetOpcode::G_LOAD:
1406   case TargetOpcode::G_SEXTLOAD:
1407   case TargetOpcode::G_ZEXTLOAD:
1408     Observer.changingInstr(MI);
1409     widenScalarDst(MI, WideTy);
1410     Observer.changedInstr(MI);
1411     return Legalized;
1412 
1413   case TargetOpcode::G_STORE: {
1414     if (TypeIdx != 0)
1415       return UnableToLegalize;
1416 
1417     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1418     if (!isPowerOf2_32(Ty.getSizeInBits()))
1419       return UnableToLegalize;
1420 
1421     Observer.changingInstr(MI);
1422 
1423     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1424       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1425     widenScalarSrc(MI, WideTy, 0, ExtType);
1426 
1427     Observer.changedInstr(MI);
1428     return Legalized;
1429   }
1430   case TargetOpcode::G_CONSTANT: {
1431     MachineOperand &SrcMO = MI.getOperand(1);
1432     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1433     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1434     Observer.changingInstr(MI);
1435     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1436 
1437     widenScalarDst(MI, WideTy);
1438     Observer.changedInstr(MI);
1439     return Legalized;
1440   }
1441   case TargetOpcode::G_FCONSTANT: {
1442     MachineOperand &SrcMO = MI.getOperand(1);
1443     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1444     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1445     bool LosesInfo;
1446     switch (WideTy.getSizeInBits()) {
1447     case 32:
1448       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1449                   &LosesInfo);
1450       break;
1451     case 64:
1452       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1453                   &LosesInfo);
1454       break;
1455     default:
1456       return UnableToLegalize;
1457     }
1458 
1459     assert(!LosesInfo && "extend should always be lossless");
1460 
1461     Observer.changingInstr(MI);
1462     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1463 
1464     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1465     Observer.changedInstr(MI);
1466     return Legalized;
1467   }
1468   case TargetOpcode::G_IMPLICIT_DEF: {
1469     Observer.changingInstr(MI);
1470     widenScalarDst(MI, WideTy);
1471     Observer.changedInstr(MI);
1472     return Legalized;
1473   }
1474   case TargetOpcode::G_BRCOND:
1475     Observer.changingInstr(MI);
1476     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1477     Observer.changedInstr(MI);
1478     return Legalized;
1479 
1480   case TargetOpcode::G_FCMP:
1481     Observer.changingInstr(MI);
1482     if (TypeIdx == 0)
1483       widenScalarDst(MI, WideTy);
1484     else {
1485       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1486       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1487     }
1488     Observer.changedInstr(MI);
1489     return Legalized;
1490 
1491   case TargetOpcode::G_ICMP:
1492     Observer.changingInstr(MI);
1493     if (TypeIdx == 0)
1494       widenScalarDst(MI, WideTy);
1495     else {
1496       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1497                                MI.getOperand(1).getPredicate()))
1498                                ? TargetOpcode::G_SEXT
1499                                : TargetOpcode::G_ZEXT;
1500       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1501       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1502     }
1503     Observer.changedInstr(MI);
1504     return Legalized;
1505 
1506   case TargetOpcode::G_GEP:
1507     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1508     Observer.changingInstr(MI);
1509     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1510     Observer.changedInstr(MI);
1511     return Legalized;
1512 
1513   case TargetOpcode::G_PHI: {
1514     assert(TypeIdx == 0 && "Expecting only Idx 0");
1515 
1516     Observer.changingInstr(MI);
1517     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1518       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1519       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1520       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1521     }
1522 
1523     MachineBasicBlock &MBB = *MI.getParent();
1524     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1525     widenScalarDst(MI, WideTy);
1526     Observer.changedInstr(MI);
1527     return Legalized;
1528   }
1529   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1530     if (TypeIdx == 0) {
1531       Register VecReg = MI.getOperand(1).getReg();
1532       LLT VecTy = MRI.getType(VecReg);
1533       Observer.changingInstr(MI);
1534 
1535       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1536                                      WideTy.getSizeInBits()),
1537                      1, TargetOpcode::G_SEXT);
1538 
1539       widenScalarDst(MI, WideTy, 0);
1540       Observer.changedInstr(MI);
1541       return Legalized;
1542     }
1543 
1544     if (TypeIdx != 2)
1545       return UnableToLegalize;
1546     Observer.changingInstr(MI);
1547     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1548     Observer.changedInstr(MI);
1549     return Legalized;
1550   }
1551   case TargetOpcode::G_FADD:
1552   case TargetOpcode::G_FMUL:
1553   case TargetOpcode::G_FSUB:
1554   case TargetOpcode::G_FMA:
1555   case TargetOpcode::G_FNEG:
1556   case TargetOpcode::G_FABS:
1557   case TargetOpcode::G_FCANONICALIZE:
1558   case TargetOpcode::G_FMINNUM:
1559   case TargetOpcode::G_FMAXNUM:
1560   case TargetOpcode::G_FMINNUM_IEEE:
1561   case TargetOpcode::G_FMAXNUM_IEEE:
1562   case TargetOpcode::G_FMINIMUM:
1563   case TargetOpcode::G_FMAXIMUM:
1564   case TargetOpcode::G_FDIV:
1565   case TargetOpcode::G_FREM:
1566   case TargetOpcode::G_FCEIL:
1567   case TargetOpcode::G_FFLOOR:
1568   case TargetOpcode::G_FCOS:
1569   case TargetOpcode::G_FSIN:
1570   case TargetOpcode::G_FLOG10:
1571   case TargetOpcode::G_FLOG:
1572   case TargetOpcode::G_FLOG2:
1573   case TargetOpcode::G_FRINT:
1574   case TargetOpcode::G_FNEARBYINT:
1575   case TargetOpcode::G_FSQRT:
1576   case TargetOpcode::G_FEXP:
1577   case TargetOpcode::G_FEXP2:
1578   case TargetOpcode::G_FPOW:
1579   case TargetOpcode::G_INTRINSIC_TRUNC:
1580   case TargetOpcode::G_INTRINSIC_ROUND:
1581     assert(TypeIdx == 0);
1582     Observer.changingInstr(MI);
1583 
1584     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1585       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1586 
1587     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1588     Observer.changedInstr(MI);
1589     return Legalized;
1590   case TargetOpcode::G_INTTOPTR:
1591     if (TypeIdx != 1)
1592       return UnableToLegalize;
1593 
1594     Observer.changingInstr(MI);
1595     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1596     Observer.changedInstr(MI);
1597     return Legalized;
1598   case TargetOpcode::G_PTRTOINT:
1599     if (TypeIdx != 0)
1600       return UnableToLegalize;
1601 
1602     Observer.changingInstr(MI);
1603     widenScalarDst(MI, WideTy, 0);
1604     Observer.changedInstr(MI);
1605     return Legalized;
1606   case TargetOpcode::G_BUILD_VECTOR: {
1607     Observer.changingInstr(MI);
1608 
1609     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1610     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1611       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1612 
1613     // Avoid changing the result vector type if the source element type was
1614     // requested.
1615     if (TypeIdx == 1) {
1616       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1617       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1618     } else {
1619       widenScalarDst(MI, WideTy, 0);
1620     }
1621 
1622     Observer.changedInstr(MI);
1623     return Legalized;
1624   }
1625   }
1626 }
1627 
1628 LegalizerHelper::LegalizeResult
1629 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1630   using namespace TargetOpcode;
1631   MIRBuilder.setInstr(MI);
1632 
1633   switch(MI.getOpcode()) {
1634   default:
1635     return UnableToLegalize;
1636   case TargetOpcode::G_SREM:
1637   case TargetOpcode::G_UREM: {
1638     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1639     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1640         .addDef(QuotReg)
1641         .addUse(MI.getOperand(1).getReg())
1642         .addUse(MI.getOperand(2).getReg());
1643 
1644     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1645     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1646     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1647                         ProdReg);
1648     MI.eraseFromParent();
1649     return Legalized;
1650   }
1651   case TargetOpcode::G_SMULO:
1652   case TargetOpcode::G_UMULO: {
1653     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1654     // result.
1655     Register Res = MI.getOperand(0).getReg();
1656     Register Overflow = MI.getOperand(1).getReg();
1657     Register LHS = MI.getOperand(2).getReg();
1658     Register RHS = MI.getOperand(3).getReg();
1659 
1660     MIRBuilder.buildMul(Res, LHS, RHS);
1661 
1662     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1663                           ? TargetOpcode::G_SMULH
1664                           : TargetOpcode::G_UMULH;
1665 
1666     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1667     MIRBuilder.buildInstr(Opcode)
1668       .addDef(HiPart)
1669       .addUse(LHS)
1670       .addUse(RHS);
1671 
1672     Register Zero = MRI.createGenericVirtualRegister(Ty);
1673     MIRBuilder.buildConstant(Zero, 0);
1674 
1675     // For *signed* multiply, overflow is detected by checking:
1676     // (hi != (lo >> bitwidth-1))
1677     if (Opcode == TargetOpcode::G_SMULH) {
1678       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1679       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1680       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1681       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1682         .addDef(Shifted)
1683         .addUse(Res)
1684         .addUse(ShiftAmt);
1685       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1686     } else {
1687       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1688     }
1689     MI.eraseFromParent();
1690     return Legalized;
1691   }
1692   case TargetOpcode::G_FNEG: {
1693     // TODO: Handle vector types once we are able to
1694     // represent them.
1695     if (Ty.isVector())
1696       return UnableToLegalize;
1697     Register Res = MI.getOperand(0).getReg();
1698     Type *ZeroTy;
1699     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1700     switch (Ty.getSizeInBits()) {
1701     case 16:
1702       ZeroTy = Type::getHalfTy(Ctx);
1703       break;
1704     case 32:
1705       ZeroTy = Type::getFloatTy(Ctx);
1706       break;
1707     case 64:
1708       ZeroTy = Type::getDoubleTy(Ctx);
1709       break;
1710     case 128:
1711       ZeroTy = Type::getFP128Ty(Ctx);
1712       break;
1713     default:
1714       llvm_unreachable("unexpected floating-point type");
1715     }
1716     ConstantFP &ZeroForNegation =
1717         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1718     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1719     Register SubByReg = MI.getOperand(1).getReg();
1720     Register ZeroReg = Zero->getOperand(0).getReg();
1721     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1722                           MI.getFlags());
1723     MI.eraseFromParent();
1724     return Legalized;
1725   }
1726   case TargetOpcode::G_FSUB: {
1727     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1728     // First, check if G_FNEG is marked as Lower. If so, we may
1729     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1730     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1731       return UnableToLegalize;
1732     Register Res = MI.getOperand(0).getReg();
1733     Register LHS = MI.getOperand(1).getReg();
1734     Register RHS = MI.getOperand(2).getReg();
1735     Register Neg = MRI.createGenericVirtualRegister(Ty);
1736     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1737     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1738     MI.eraseFromParent();
1739     return Legalized;
1740   }
1741   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1742     Register OldValRes = MI.getOperand(0).getReg();
1743     Register SuccessRes = MI.getOperand(1).getReg();
1744     Register Addr = MI.getOperand(2).getReg();
1745     Register CmpVal = MI.getOperand(3).getReg();
1746     Register NewVal = MI.getOperand(4).getReg();
1747     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1748                                   **MI.memoperands_begin());
1749     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1750     MI.eraseFromParent();
1751     return Legalized;
1752   }
1753   case TargetOpcode::G_LOAD:
1754   case TargetOpcode::G_SEXTLOAD:
1755   case TargetOpcode::G_ZEXTLOAD: {
1756     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1757     Register DstReg = MI.getOperand(0).getReg();
1758     Register PtrReg = MI.getOperand(1).getReg();
1759     LLT DstTy = MRI.getType(DstReg);
1760     auto &MMO = **MI.memoperands_begin();
1761 
1762     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1763       // In the case of G_LOAD, this was a non-extending load already and we're
1764       // about to lower to the same instruction.
1765       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1766           return UnableToLegalize;
1767       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1768       MI.eraseFromParent();
1769       return Legalized;
1770     }
1771 
1772     if (DstTy.isScalar()) {
1773       Register TmpReg =
1774           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
1775       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1776       switch (MI.getOpcode()) {
1777       default:
1778         llvm_unreachable("Unexpected opcode");
1779       case TargetOpcode::G_LOAD:
1780         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1781         break;
1782       case TargetOpcode::G_SEXTLOAD:
1783         MIRBuilder.buildSExt(DstReg, TmpReg);
1784         break;
1785       case TargetOpcode::G_ZEXTLOAD:
1786         MIRBuilder.buildZExt(DstReg, TmpReg);
1787         break;
1788       }
1789       MI.eraseFromParent();
1790       return Legalized;
1791     }
1792 
1793     return UnableToLegalize;
1794   }
1795   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1796   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1797   case TargetOpcode::G_CTLZ:
1798   case TargetOpcode::G_CTTZ:
1799   case TargetOpcode::G_CTPOP:
1800     return lowerBitCount(MI, TypeIdx, Ty);
1801   case G_UADDO: {
1802     Register Res = MI.getOperand(0).getReg();
1803     Register CarryOut = MI.getOperand(1).getReg();
1804     Register LHS = MI.getOperand(2).getReg();
1805     Register RHS = MI.getOperand(3).getReg();
1806 
1807     MIRBuilder.buildAdd(Res, LHS, RHS);
1808     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1809 
1810     MI.eraseFromParent();
1811     return Legalized;
1812   }
1813   case G_UADDE: {
1814     Register Res = MI.getOperand(0).getReg();
1815     Register CarryOut = MI.getOperand(1).getReg();
1816     Register LHS = MI.getOperand(2).getReg();
1817     Register RHS = MI.getOperand(3).getReg();
1818     Register CarryIn = MI.getOperand(4).getReg();
1819 
1820     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1821     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1822 
1823     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1824     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1825     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1826     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1827 
1828     MI.eraseFromParent();
1829     return Legalized;
1830   }
1831   case G_USUBO: {
1832     Register Res = MI.getOperand(0).getReg();
1833     Register BorrowOut = MI.getOperand(1).getReg();
1834     Register LHS = MI.getOperand(2).getReg();
1835     Register RHS = MI.getOperand(3).getReg();
1836 
1837     MIRBuilder.buildSub(Res, LHS, RHS);
1838     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1839 
1840     MI.eraseFromParent();
1841     return Legalized;
1842   }
1843   case G_USUBE: {
1844     Register Res = MI.getOperand(0).getReg();
1845     Register BorrowOut = MI.getOperand(1).getReg();
1846     Register LHS = MI.getOperand(2).getReg();
1847     Register RHS = MI.getOperand(3).getReg();
1848     Register BorrowIn = MI.getOperand(4).getReg();
1849 
1850     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1851     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1852     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1853     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1854 
1855     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1856     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1857     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1858     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1859     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1860     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1861 
1862     MI.eraseFromParent();
1863     return Legalized;
1864   }
1865   case G_UITOFP:
1866     return lowerUITOFP(MI, TypeIdx, Ty);
1867   case G_SITOFP:
1868     return lowerSITOFP(MI, TypeIdx, Ty);
1869   case G_SMIN:
1870   case G_SMAX:
1871   case G_UMIN:
1872   case G_UMAX:
1873     return lowerMinMax(MI, TypeIdx, Ty);
1874   case G_FCOPYSIGN:
1875     return lowerFCopySign(MI, TypeIdx, Ty);
1876   case G_FMINNUM:
1877   case G_FMAXNUM:
1878     return lowerFMinNumMaxNum(MI);
1879   }
1880 }
1881 
1882 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1883     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1884   SmallVector<Register, 2> DstRegs;
1885 
1886   unsigned NarrowSize = NarrowTy.getSizeInBits();
1887   Register DstReg = MI.getOperand(0).getReg();
1888   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1889   int NumParts = Size / NarrowSize;
1890   // FIXME: Don't know how to handle the situation where the small vectors
1891   // aren't all the same size yet.
1892   if (Size % NarrowSize != 0)
1893     return UnableToLegalize;
1894 
1895   for (int i = 0; i < NumParts; ++i) {
1896     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1897     MIRBuilder.buildUndef(TmpReg);
1898     DstRegs.push_back(TmpReg);
1899   }
1900 
1901   if (NarrowTy.isVector())
1902     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1903   else
1904     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1905 
1906   MI.eraseFromParent();
1907   return Legalized;
1908 }
1909 
1910 LegalizerHelper::LegalizeResult
1911 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1912                                           LLT NarrowTy) {
1913   const unsigned Opc = MI.getOpcode();
1914   const unsigned NumOps = MI.getNumOperands() - 1;
1915   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1916   const Register DstReg = MI.getOperand(0).getReg();
1917   const unsigned Flags = MI.getFlags();
1918   const LLT DstTy = MRI.getType(DstReg);
1919   const unsigned Size = DstTy.getSizeInBits();
1920   const int NumParts = Size / NarrowSize;
1921   const LLT EltTy = DstTy.getElementType();
1922   const unsigned EltSize = EltTy.getSizeInBits();
1923   const unsigned BitsForNumParts = NarrowSize * NumParts;
1924 
1925   // Check if we have any leftovers. If we do, then only handle the case where
1926   // the leftover is one element.
1927   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1928     return UnableToLegalize;
1929 
1930   if (BitsForNumParts != Size) {
1931     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1932     MIRBuilder.buildUndef(AccumDstReg);
1933 
1934     // Handle the pieces which evenly divide into the requested type with
1935     // extract/op/insert sequence.
1936     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1937       SmallVector<SrcOp, 4> SrcOps;
1938       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1939         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1940         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1941         SrcOps.push_back(PartOpReg);
1942       }
1943 
1944       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1945       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1946 
1947       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1948       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1949       AccumDstReg = PartInsertReg;
1950     }
1951 
1952     // Handle the remaining element sized leftover piece.
1953     SmallVector<SrcOp, 4> SrcOps;
1954     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1955       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1956       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1957                               BitsForNumParts);
1958       SrcOps.push_back(PartOpReg);
1959     }
1960 
1961     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1962     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1963     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1964     MI.eraseFromParent();
1965 
1966     return Legalized;
1967   }
1968 
1969   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1970 
1971   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1972 
1973   if (NumOps >= 2)
1974     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1975 
1976   if (NumOps >= 3)
1977     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1978 
1979   for (int i = 0; i < NumParts; ++i) {
1980     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1981 
1982     if (NumOps == 1)
1983       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1984     else if (NumOps == 2) {
1985       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1986     } else if (NumOps == 3) {
1987       MIRBuilder.buildInstr(Opc, {DstReg},
1988                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1989     }
1990 
1991     DstRegs.push_back(DstReg);
1992   }
1993 
1994   if (NarrowTy.isVector())
1995     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1996   else
1997     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1998 
1999   MI.eraseFromParent();
2000   return Legalized;
2001 }
2002 
2003 // Handle splitting vector operations which need to have the same number of
2004 // elements in each type index, but each type index may have a different element
2005 // type.
2006 //
2007 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2008 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2009 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2010 //
2011 // Also handles some irregular breakdown cases, e.g.
2012 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2013 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2014 //             s64 = G_SHL s64, s32
2015 LegalizerHelper::LegalizeResult
2016 LegalizerHelper::fewerElementsVectorMultiEltType(
2017   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2018   if (TypeIdx != 0)
2019     return UnableToLegalize;
2020 
2021   const LLT NarrowTy0 = NarrowTyArg;
2022   const unsigned NewNumElts =
2023       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2024 
2025   const Register DstReg = MI.getOperand(0).getReg();
2026   LLT DstTy = MRI.getType(DstReg);
2027   LLT LeftoverTy0;
2028 
2029   // All of the operands need to have the same number of elements, so if we can
2030   // determine a type breakdown for the result type, we can for all of the
2031   // source types.
2032   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2033   if (NumParts < 0)
2034     return UnableToLegalize;
2035 
2036   SmallVector<MachineInstrBuilder, 4> NewInsts;
2037 
2038   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2039   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2040 
2041   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2042     LLT LeftoverTy;
2043     Register SrcReg = MI.getOperand(I).getReg();
2044     LLT SrcTyI = MRI.getType(SrcReg);
2045     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2046     LLT LeftoverTyI;
2047 
2048     // Split this operand into the requested typed registers, and any leftover
2049     // required to reproduce the original type.
2050     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2051                       LeftoverRegs))
2052       return UnableToLegalize;
2053 
2054     if (I == 1) {
2055       // For the first operand, create an instruction for each part and setup
2056       // the result.
2057       for (Register PartReg : PartRegs) {
2058         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2059         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2060                                .addDef(PartDstReg)
2061                                .addUse(PartReg));
2062         DstRegs.push_back(PartDstReg);
2063       }
2064 
2065       for (Register LeftoverReg : LeftoverRegs) {
2066         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2067         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2068                                .addDef(PartDstReg)
2069                                .addUse(LeftoverReg));
2070         LeftoverDstRegs.push_back(PartDstReg);
2071       }
2072     } else {
2073       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2074 
2075       // Add the newly created operand splits to the existing instructions. The
2076       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2077       // pieces.
2078       unsigned InstCount = 0;
2079       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2080         NewInsts[InstCount++].addUse(PartRegs[J]);
2081       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2082         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2083     }
2084 
2085     PartRegs.clear();
2086     LeftoverRegs.clear();
2087   }
2088 
2089   // Insert the newly built operations and rebuild the result register.
2090   for (auto &MIB : NewInsts)
2091     MIRBuilder.insertInstr(MIB);
2092 
2093   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2094 
2095   MI.eraseFromParent();
2096   return Legalized;
2097 }
2098 
2099 LegalizerHelper::LegalizeResult
2100 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2101                                           LLT NarrowTy) {
2102   if (TypeIdx != 0)
2103     return UnableToLegalize;
2104 
2105   Register DstReg = MI.getOperand(0).getReg();
2106   Register SrcReg = MI.getOperand(1).getReg();
2107   LLT DstTy = MRI.getType(DstReg);
2108   LLT SrcTy = MRI.getType(SrcReg);
2109 
2110   LLT NarrowTy0 = NarrowTy;
2111   LLT NarrowTy1;
2112   unsigned NumParts;
2113 
2114   if (NarrowTy.isVector()) {
2115     // Uneven breakdown not handled.
2116     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2117     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2118       return UnableToLegalize;
2119 
2120     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2121   } else {
2122     NumParts = DstTy.getNumElements();
2123     NarrowTy1 = SrcTy.getElementType();
2124   }
2125 
2126   SmallVector<Register, 4> SrcRegs, DstRegs;
2127   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2128 
2129   for (unsigned I = 0; I < NumParts; ++I) {
2130     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2131     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2132       .addDef(DstReg)
2133       .addUse(SrcRegs[I]);
2134 
2135     NewInst->setFlags(MI.getFlags());
2136     DstRegs.push_back(DstReg);
2137   }
2138 
2139   if (NarrowTy.isVector())
2140     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2141   else
2142     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2143 
2144   MI.eraseFromParent();
2145   return Legalized;
2146 }
2147 
2148 LegalizerHelper::LegalizeResult
2149 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2150                                         LLT NarrowTy) {
2151   Register DstReg = MI.getOperand(0).getReg();
2152   Register Src0Reg = MI.getOperand(2).getReg();
2153   LLT DstTy = MRI.getType(DstReg);
2154   LLT SrcTy = MRI.getType(Src0Reg);
2155 
2156   unsigned NumParts;
2157   LLT NarrowTy0, NarrowTy1;
2158 
2159   if (TypeIdx == 0) {
2160     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2161     unsigned OldElts = DstTy.getNumElements();
2162 
2163     NarrowTy0 = NarrowTy;
2164     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2165     NarrowTy1 = NarrowTy.isVector() ?
2166       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2167       SrcTy.getElementType();
2168 
2169   } else {
2170     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2171     unsigned OldElts = SrcTy.getNumElements();
2172 
2173     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2174       NarrowTy.getNumElements();
2175     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2176                             DstTy.getScalarSizeInBits());
2177     NarrowTy1 = NarrowTy;
2178   }
2179 
2180   // FIXME: Don't know how to handle the situation where the small vectors
2181   // aren't all the same size yet.
2182   if (NarrowTy1.isVector() &&
2183       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2184     return UnableToLegalize;
2185 
2186   CmpInst::Predicate Pred
2187     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2188 
2189   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2190   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2191   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2192 
2193   for (unsigned I = 0; I < NumParts; ++I) {
2194     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2195     DstRegs.push_back(DstReg);
2196 
2197     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2198       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2199     else {
2200       MachineInstr *NewCmp
2201         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2202       NewCmp->setFlags(MI.getFlags());
2203     }
2204   }
2205 
2206   if (NarrowTy1.isVector())
2207     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2208   else
2209     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2210 
2211   MI.eraseFromParent();
2212   return Legalized;
2213 }
2214 
2215 LegalizerHelper::LegalizeResult
2216 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2217                                            LLT NarrowTy) {
2218   Register DstReg = MI.getOperand(0).getReg();
2219   Register CondReg = MI.getOperand(1).getReg();
2220 
2221   unsigned NumParts = 0;
2222   LLT NarrowTy0, NarrowTy1;
2223 
2224   LLT DstTy = MRI.getType(DstReg);
2225   LLT CondTy = MRI.getType(CondReg);
2226   unsigned Size = DstTy.getSizeInBits();
2227 
2228   assert(TypeIdx == 0 || CondTy.isVector());
2229 
2230   if (TypeIdx == 0) {
2231     NarrowTy0 = NarrowTy;
2232     NarrowTy1 = CondTy;
2233 
2234     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2235     // FIXME: Don't know how to handle the situation where the small vectors
2236     // aren't all the same size yet.
2237     if (Size % NarrowSize != 0)
2238       return UnableToLegalize;
2239 
2240     NumParts = Size / NarrowSize;
2241 
2242     // Need to break down the condition type
2243     if (CondTy.isVector()) {
2244       if (CondTy.getNumElements() == NumParts)
2245         NarrowTy1 = CondTy.getElementType();
2246       else
2247         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2248                                 CondTy.getScalarSizeInBits());
2249     }
2250   } else {
2251     NumParts = CondTy.getNumElements();
2252     if (NarrowTy.isVector()) {
2253       // TODO: Handle uneven breakdown.
2254       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2255         return UnableToLegalize;
2256 
2257       return UnableToLegalize;
2258     } else {
2259       NarrowTy0 = DstTy.getElementType();
2260       NarrowTy1 = NarrowTy;
2261     }
2262   }
2263 
2264   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2265   if (CondTy.isVector())
2266     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2267 
2268   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2269   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2270 
2271   for (unsigned i = 0; i < NumParts; ++i) {
2272     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2273     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2274                            Src1Regs[i], Src2Regs[i]);
2275     DstRegs.push_back(DstReg);
2276   }
2277 
2278   if (NarrowTy0.isVector())
2279     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2280   else
2281     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2282 
2283   MI.eraseFromParent();
2284   return Legalized;
2285 }
2286 
2287 LegalizerHelper::LegalizeResult
2288 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2289                                         LLT NarrowTy) {
2290   const Register DstReg = MI.getOperand(0).getReg();
2291   LLT PhiTy = MRI.getType(DstReg);
2292   LLT LeftoverTy;
2293 
2294   // All of the operands need to have the same number of elements, so if we can
2295   // determine a type breakdown for the result type, we can for all of the
2296   // source types.
2297   int NumParts, NumLeftover;
2298   std::tie(NumParts, NumLeftover)
2299     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2300   if (NumParts < 0)
2301     return UnableToLegalize;
2302 
2303   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2304   SmallVector<MachineInstrBuilder, 4> NewInsts;
2305 
2306   const int TotalNumParts = NumParts + NumLeftover;
2307 
2308   // Insert the new phis in the result block first.
2309   for (int I = 0; I != TotalNumParts; ++I) {
2310     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2311     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2312     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2313                        .addDef(PartDstReg));
2314     if (I < NumParts)
2315       DstRegs.push_back(PartDstReg);
2316     else
2317       LeftoverDstRegs.push_back(PartDstReg);
2318   }
2319 
2320   MachineBasicBlock *MBB = MI.getParent();
2321   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2322   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2323 
2324   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2325 
2326   // Insert code to extract the incoming values in each predecessor block.
2327   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2328     PartRegs.clear();
2329     LeftoverRegs.clear();
2330 
2331     Register SrcReg = MI.getOperand(I).getReg();
2332     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2333     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2334 
2335     LLT Unused;
2336     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2337                       LeftoverRegs))
2338       return UnableToLegalize;
2339 
2340     // Add the newly created operand splits to the existing instructions. The
2341     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2342     // pieces.
2343     for (int J = 0; J != TotalNumParts; ++J) {
2344       MachineInstrBuilder MIB = NewInsts[J];
2345       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2346       MIB.addMBB(&OpMBB);
2347     }
2348   }
2349 
2350   MI.eraseFromParent();
2351   return Legalized;
2352 }
2353 
2354 LegalizerHelper::LegalizeResult
2355 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2356                                       LLT NarrowTy) {
2357   // FIXME: Don't know how to handle secondary types yet.
2358   if (TypeIdx != 0)
2359     return UnableToLegalize;
2360 
2361   MachineMemOperand *MMO = *MI.memoperands_begin();
2362 
2363   // This implementation doesn't work for atomics. Give up instead of doing
2364   // something invalid.
2365   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2366       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2367     return UnableToLegalize;
2368 
2369   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2370   Register ValReg = MI.getOperand(0).getReg();
2371   Register AddrReg = MI.getOperand(1).getReg();
2372   LLT ValTy = MRI.getType(ValReg);
2373 
2374   int NumParts = -1;
2375   int NumLeftover = -1;
2376   LLT LeftoverTy;
2377   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2378   if (IsLoad) {
2379     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2380   } else {
2381     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2382                      NarrowLeftoverRegs)) {
2383       NumParts = NarrowRegs.size();
2384       NumLeftover = NarrowLeftoverRegs.size();
2385     }
2386   }
2387 
2388   if (NumParts == -1)
2389     return UnableToLegalize;
2390 
2391   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2392 
2393   unsigned TotalSize = ValTy.getSizeInBits();
2394 
2395   // Split the load/store into PartTy sized pieces starting at Offset. If this
2396   // is a load, return the new registers in ValRegs. For a store, each elements
2397   // of ValRegs should be PartTy. Returns the next offset that needs to be
2398   // handled.
2399   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2400                              unsigned Offset) -> unsigned {
2401     MachineFunction &MF = MIRBuilder.getMF();
2402     unsigned PartSize = PartTy.getSizeInBits();
2403     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2404          Offset += PartSize, ++Idx) {
2405       unsigned ByteSize = PartSize / 8;
2406       unsigned ByteOffset = Offset / 8;
2407       Register NewAddrReg;
2408 
2409       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2410 
2411       MachineMemOperand *NewMMO =
2412         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2413 
2414       if (IsLoad) {
2415         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2416         ValRegs.push_back(Dst);
2417         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2418       } else {
2419         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2420       }
2421     }
2422 
2423     return Offset;
2424   };
2425 
2426   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2427 
2428   // Handle the rest of the register if this isn't an even type breakdown.
2429   if (LeftoverTy.isValid())
2430     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2431 
2432   if (IsLoad) {
2433     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2434                 LeftoverTy, NarrowLeftoverRegs);
2435   }
2436 
2437   MI.eraseFromParent();
2438   return Legalized;
2439 }
2440 
2441 LegalizerHelper::LegalizeResult
2442 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2443                                      LLT NarrowTy) {
2444   using namespace TargetOpcode;
2445 
2446   MIRBuilder.setInstr(MI);
2447   switch (MI.getOpcode()) {
2448   case G_IMPLICIT_DEF:
2449     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2450   case G_AND:
2451   case G_OR:
2452   case G_XOR:
2453   case G_ADD:
2454   case G_SUB:
2455   case G_MUL:
2456   case G_SMULH:
2457   case G_UMULH:
2458   case G_FADD:
2459   case G_FMUL:
2460   case G_FSUB:
2461   case G_FNEG:
2462   case G_FABS:
2463   case G_FCANONICALIZE:
2464   case G_FDIV:
2465   case G_FREM:
2466   case G_FMA:
2467   case G_FPOW:
2468   case G_FEXP:
2469   case G_FEXP2:
2470   case G_FLOG:
2471   case G_FLOG2:
2472   case G_FLOG10:
2473   case G_FNEARBYINT:
2474   case G_FCEIL:
2475   case G_FFLOOR:
2476   case G_FRINT:
2477   case G_INTRINSIC_ROUND:
2478   case G_INTRINSIC_TRUNC:
2479   case G_FCOS:
2480   case G_FSIN:
2481   case G_FSQRT:
2482   case G_BSWAP:
2483   case G_SDIV:
2484   case G_SMIN:
2485   case G_SMAX:
2486   case G_UMIN:
2487   case G_UMAX:
2488   case G_FMINNUM:
2489   case G_FMAXNUM:
2490   case G_FMINNUM_IEEE:
2491   case G_FMAXNUM_IEEE:
2492   case G_FMINIMUM:
2493   case G_FMAXIMUM:
2494     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2495   case G_SHL:
2496   case G_LSHR:
2497   case G_ASHR:
2498   case G_CTLZ:
2499   case G_CTLZ_ZERO_UNDEF:
2500   case G_CTTZ:
2501   case G_CTTZ_ZERO_UNDEF:
2502   case G_CTPOP:
2503   case G_FCOPYSIGN:
2504     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2505   case G_ZEXT:
2506   case G_SEXT:
2507   case G_ANYEXT:
2508   case G_FPEXT:
2509   case G_FPTRUNC:
2510   case G_SITOFP:
2511   case G_UITOFP:
2512   case G_FPTOSI:
2513   case G_FPTOUI:
2514   case G_INTTOPTR:
2515   case G_PTRTOINT:
2516   case G_ADDRSPACE_CAST:
2517     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2518   case G_ICMP:
2519   case G_FCMP:
2520     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2521   case G_SELECT:
2522     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2523   case G_PHI:
2524     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2525   case G_LOAD:
2526   case G_STORE:
2527     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2528   default:
2529     return UnableToLegalize;
2530   }
2531 }
2532 
2533 LegalizerHelper::LegalizeResult
2534 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2535                                              const LLT HalfTy, const LLT AmtTy) {
2536 
2537   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2538   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2539   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2540 
2541   if (Amt.isNullValue()) {
2542     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2543     MI.eraseFromParent();
2544     return Legalized;
2545   }
2546 
2547   LLT NVT = HalfTy;
2548   unsigned NVTBits = HalfTy.getSizeInBits();
2549   unsigned VTBits = 2 * NVTBits;
2550 
2551   SrcOp Lo(Register(0)), Hi(Register(0));
2552   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2553     if (Amt.ugt(VTBits)) {
2554       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2555     } else if (Amt.ugt(NVTBits)) {
2556       Lo = MIRBuilder.buildConstant(NVT, 0);
2557       Hi = MIRBuilder.buildShl(NVT, InL,
2558                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2559     } else if (Amt == NVTBits) {
2560       Lo = MIRBuilder.buildConstant(NVT, 0);
2561       Hi = InL;
2562     } else {
2563       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2564       auto OrLHS =
2565           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2566       auto OrRHS = MIRBuilder.buildLShr(
2567           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2568       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2569     }
2570   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2571     if (Amt.ugt(VTBits)) {
2572       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2573     } else if (Amt.ugt(NVTBits)) {
2574       Lo = MIRBuilder.buildLShr(NVT, InH,
2575                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2576       Hi = MIRBuilder.buildConstant(NVT, 0);
2577     } else if (Amt == NVTBits) {
2578       Lo = InH;
2579       Hi = MIRBuilder.buildConstant(NVT, 0);
2580     } else {
2581       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2582 
2583       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2584       auto OrRHS = MIRBuilder.buildShl(
2585           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2586 
2587       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2588       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2589     }
2590   } else {
2591     if (Amt.ugt(VTBits)) {
2592       Hi = Lo = MIRBuilder.buildAShr(
2593           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2594     } else if (Amt.ugt(NVTBits)) {
2595       Lo = MIRBuilder.buildAShr(NVT, InH,
2596                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2597       Hi = MIRBuilder.buildAShr(NVT, InH,
2598                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2599     } else if (Amt == NVTBits) {
2600       Lo = InH;
2601       Hi = MIRBuilder.buildAShr(NVT, InH,
2602                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2603     } else {
2604       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2605 
2606       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2607       auto OrRHS = MIRBuilder.buildShl(
2608           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2609 
2610       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2611       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2612     }
2613   }
2614 
2615   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2616   MI.eraseFromParent();
2617 
2618   return Legalized;
2619 }
2620 
2621 // TODO: Optimize if constant shift amount.
2622 LegalizerHelper::LegalizeResult
2623 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2624                                    LLT RequestedTy) {
2625   if (TypeIdx == 1) {
2626     Observer.changingInstr(MI);
2627     narrowScalarSrc(MI, RequestedTy, 2);
2628     Observer.changedInstr(MI);
2629     return Legalized;
2630   }
2631 
2632   Register DstReg = MI.getOperand(0).getReg();
2633   LLT DstTy = MRI.getType(DstReg);
2634   if (DstTy.isVector())
2635     return UnableToLegalize;
2636 
2637   Register Amt = MI.getOperand(2).getReg();
2638   LLT ShiftAmtTy = MRI.getType(Amt);
2639   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2640   if (DstEltSize % 2 != 0)
2641     return UnableToLegalize;
2642 
2643   // Ignore the input type. We can only go to exactly half the size of the
2644   // input. If that isn't small enough, the resulting pieces will be further
2645   // legalized.
2646   const unsigned NewBitSize = DstEltSize / 2;
2647   const LLT HalfTy = LLT::scalar(NewBitSize);
2648   const LLT CondTy = LLT::scalar(1);
2649 
2650   if (const MachineInstr *KShiftAmt =
2651           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2652     return narrowScalarShiftByConstant(
2653         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2654   }
2655 
2656   // TODO: Expand with known bits.
2657 
2658   // Handle the fully general expansion by an unknown amount.
2659   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2660 
2661   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2662   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2663   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2664 
2665   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2666   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2667 
2668   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2669   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2670   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2671 
2672   Register ResultRegs[2];
2673   switch (MI.getOpcode()) {
2674   case TargetOpcode::G_SHL: {
2675     // Short: ShAmt < NewBitSize
2676     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2677 
2678     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2679     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2680     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2681 
2682     // Long: ShAmt >= NewBitSize
2683     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2684     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2685 
2686     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2687     auto Hi = MIRBuilder.buildSelect(
2688         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2689 
2690     ResultRegs[0] = Lo.getReg(0);
2691     ResultRegs[1] = Hi.getReg(0);
2692     break;
2693   }
2694   case TargetOpcode::G_LSHR: {
2695     // Short: ShAmt < NewBitSize
2696     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2697 
2698     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2699     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2700     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2701 
2702     // Long: ShAmt >= NewBitSize
2703     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2704     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2705 
2706     auto Lo = MIRBuilder.buildSelect(
2707         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2708     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2709 
2710     ResultRegs[0] = Lo.getReg(0);
2711     ResultRegs[1] = Hi.getReg(0);
2712     break;
2713   }
2714   case TargetOpcode::G_ASHR: {
2715     // Short: ShAmt < NewBitSize
2716     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2717 
2718     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2719     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2720     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2721 
2722     // Long: ShAmt >= NewBitSize
2723 
2724     // Sign of Hi part.
2725     auto HiL = MIRBuilder.buildAShr(
2726         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2727 
2728     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2729 
2730     auto Lo = MIRBuilder.buildSelect(
2731         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2732 
2733     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2734 
2735     ResultRegs[0] = Lo.getReg(0);
2736     ResultRegs[1] = Hi.getReg(0);
2737     break;
2738   }
2739   default:
2740     llvm_unreachable("not a shift");
2741   }
2742 
2743   MIRBuilder.buildMerge(DstReg, ResultRegs);
2744   MI.eraseFromParent();
2745   return Legalized;
2746 }
2747 
2748 LegalizerHelper::LegalizeResult
2749 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2750                                        LLT MoreTy) {
2751   assert(TypeIdx == 0 && "Expecting only Idx 0");
2752 
2753   Observer.changingInstr(MI);
2754   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2755     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2756     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2757     moreElementsVectorSrc(MI, MoreTy, I);
2758   }
2759 
2760   MachineBasicBlock &MBB = *MI.getParent();
2761   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2762   moreElementsVectorDst(MI, MoreTy, 0);
2763   Observer.changedInstr(MI);
2764   return Legalized;
2765 }
2766 
2767 LegalizerHelper::LegalizeResult
2768 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2769                                     LLT MoreTy) {
2770   MIRBuilder.setInstr(MI);
2771   unsigned Opc = MI.getOpcode();
2772   switch (Opc) {
2773   case TargetOpcode::G_IMPLICIT_DEF: {
2774     Observer.changingInstr(MI);
2775     moreElementsVectorDst(MI, MoreTy, 0);
2776     Observer.changedInstr(MI);
2777     return Legalized;
2778   }
2779   case TargetOpcode::G_AND:
2780   case TargetOpcode::G_OR:
2781   case TargetOpcode::G_XOR:
2782   case TargetOpcode::G_SMIN:
2783   case TargetOpcode::G_SMAX:
2784   case TargetOpcode::G_UMIN:
2785   case TargetOpcode::G_UMAX: {
2786     Observer.changingInstr(MI);
2787     moreElementsVectorSrc(MI, MoreTy, 1);
2788     moreElementsVectorSrc(MI, MoreTy, 2);
2789     moreElementsVectorDst(MI, MoreTy, 0);
2790     Observer.changedInstr(MI);
2791     return Legalized;
2792   }
2793   case TargetOpcode::G_EXTRACT:
2794     if (TypeIdx != 1)
2795       return UnableToLegalize;
2796     Observer.changingInstr(MI);
2797     moreElementsVectorSrc(MI, MoreTy, 1);
2798     Observer.changedInstr(MI);
2799     return Legalized;
2800   case TargetOpcode::G_INSERT:
2801     if (TypeIdx != 0)
2802       return UnableToLegalize;
2803     Observer.changingInstr(MI);
2804     moreElementsVectorSrc(MI, MoreTy, 1);
2805     moreElementsVectorDst(MI, MoreTy, 0);
2806     Observer.changedInstr(MI);
2807     return Legalized;
2808   case TargetOpcode::G_SELECT:
2809     if (TypeIdx != 0)
2810       return UnableToLegalize;
2811     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2812       return UnableToLegalize;
2813 
2814     Observer.changingInstr(MI);
2815     moreElementsVectorSrc(MI, MoreTy, 2);
2816     moreElementsVectorSrc(MI, MoreTy, 3);
2817     moreElementsVectorDst(MI, MoreTy, 0);
2818     Observer.changedInstr(MI);
2819     return Legalized;
2820   case TargetOpcode::G_PHI:
2821     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2822   default:
2823     return UnableToLegalize;
2824   }
2825 }
2826 
2827 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
2828                                         ArrayRef<Register> Src1Regs,
2829                                         ArrayRef<Register> Src2Regs,
2830                                         LLT NarrowTy) {
2831   MachineIRBuilder &B = MIRBuilder;
2832   unsigned SrcParts = Src1Regs.size();
2833   unsigned DstParts = DstRegs.size();
2834 
2835   unsigned DstIdx = 0; // Low bits of the result.
2836   Register FactorSum =
2837       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
2838   DstRegs[DstIdx] = FactorSum;
2839 
2840   unsigned CarrySumPrevDstIdx;
2841   SmallVector<Register, 4> Factors;
2842 
2843   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
2844     // Collect low parts of muls for DstIdx.
2845     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
2846          i <= std::min(DstIdx, SrcParts - 1); ++i) {
2847       MachineInstrBuilder Mul =
2848           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
2849       Factors.push_back(Mul.getReg(0));
2850     }
2851     // Collect high parts of muls from previous DstIdx.
2852     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
2853          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
2854       MachineInstrBuilder Umulh =
2855           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
2856       Factors.push_back(Umulh.getReg(0));
2857     }
2858     // Add CarrySum from additons calculated for previous DstIdx.
2859     if (DstIdx != 1) {
2860       Factors.push_back(CarrySumPrevDstIdx);
2861     }
2862 
2863     Register CarrySum;
2864     // Add all factors and accumulate all carries into CarrySum.
2865     if (DstIdx != DstParts - 1) {
2866       MachineInstrBuilder Uaddo =
2867           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
2868       FactorSum = Uaddo.getReg(0);
2869       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
2870       for (unsigned i = 2; i < Factors.size(); ++i) {
2871         MachineInstrBuilder Uaddo =
2872             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
2873         FactorSum = Uaddo.getReg(0);
2874         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
2875         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
2876       }
2877     } else {
2878       // Since value for the next index is not calculated, neither is CarrySum.
2879       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
2880       for (unsigned i = 2; i < Factors.size(); ++i)
2881         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
2882     }
2883 
2884     CarrySumPrevDstIdx = CarrySum;
2885     DstRegs[DstIdx] = FactorSum;
2886     Factors.clear();
2887   }
2888 }
2889 
2890 LegalizerHelper::LegalizeResult
2891 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
2892   Register DstReg = MI.getOperand(0).getReg();
2893   Register Src1 = MI.getOperand(1).getReg();
2894   Register Src2 = MI.getOperand(2).getReg();
2895 
2896   LLT Ty = MRI.getType(DstReg);
2897   if (Ty.isVector())
2898     return UnableToLegalize;
2899 
2900   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
2901   unsigned DstSize = Ty.getSizeInBits();
2902   unsigned NarrowSize = NarrowTy.getSizeInBits();
2903   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
2904     return UnableToLegalize;
2905 
2906   unsigned NumDstParts = DstSize / NarrowSize;
2907   unsigned NumSrcParts = SrcSize / NarrowSize;
2908   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
2909   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
2910 
2911   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
2912   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
2913   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
2914   DstTmpRegs.resize(DstTmpParts);
2915   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
2916 
2917   // Take only high half of registers if this is high mul.
2918   ArrayRef<Register> DstRegs(
2919       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
2920   MIRBuilder.buildMerge(DstReg, DstRegs);
2921   MI.eraseFromParent();
2922   return Legalized;
2923 }
2924 
2925 LegalizerHelper::LegalizeResult
2926 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2927                                      LLT NarrowTy) {
2928   if (TypeIdx != 1)
2929     return UnableToLegalize;
2930 
2931   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2932 
2933   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2934   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2935   // NarrowSize.
2936   if (SizeOp1 % NarrowSize != 0)
2937     return UnableToLegalize;
2938   int NumParts = SizeOp1 / NarrowSize;
2939 
2940   SmallVector<Register, 2> SrcRegs, DstRegs;
2941   SmallVector<uint64_t, 2> Indexes;
2942   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2943 
2944   Register OpReg = MI.getOperand(0).getReg();
2945   uint64_t OpStart = MI.getOperand(2).getImm();
2946   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2947   for (int i = 0; i < NumParts; ++i) {
2948     unsigned SrcStart = i * NarrowSize;
2949 
2950     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2951       // No part of the extract uses this subregister, ignore it.
2952       continue;
2953     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2954       // The entire subregister is extracted, forward the value.
2955       DstRegs.push_back(SrcRegs[i]);
2956       continue;
2957     }
2958 
2959     // OpSegStart is where this destination segment would start in OpReg if it
2960     // extended infinitely in both directions.
2961     int64_t ExtractOffset;
2962     uint64_t SegSize;
2963     if (OpStart < SrcStart) {
2964       ExtractOffset = 0;
2965       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2966     } else {
2967       ExtractOffset = OpStart - SrcStart;
2968       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2969     }
2970 
2971     Register SegReg = SrcRegs[i];
2972     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2973       // A genuine extract is needed.
2974       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2975       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2976     }
2977 
2978     DstRegs.push_back(SegReg);
2979   }
2980 
2981   Register DstReg = MI.getOperand(0).getReg();
2982   if(MRI.getType(DstReg).isVector())
2983     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2984   else
2985     MIRBuilder.buildMerge(DstReg, DstRegs);
2986   MI.eraseFromParent();
2987   return Legalized;
2988 }
2989 
2990 LegalizerHelper::LegalizeResult
2991 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2992                                     LLT NarrowTy) {
2993   // FIXME: Don't know how to handle secondary types yet.
2994   if (TypeIdx != 0)
2995     return UnableToLegalize;
2996 
2997   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2998   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2999 
3000   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3001   // NarrowSize.
3002   if (SizeOp0 % NarrowSize != 0)
3003     return UnableToLegalize;
3004 
3005   int NumParts = SizeOp0 / NarrowSize;
3006 
3007   SmallVector<Register, 2> SrcRegs, DstRegs;
3008   SmallVector<uint64_t, 2> Indexes;
3009   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3010 
3011   Register OpReg = MI.getOperand(2).getReg();
3012   uint64_t OpStart = MI.getOperand(3).getImm();
3013   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3014   for (int i = 0; i < NumParts; ++i) {
3015     unsigned DstStart = i * NarrowSize;
3016 
3017     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3018       // No part of the insert affects this subregister, forward the original.
3019       DstRegs.push_back(SrcRegs[i]);
3020       continue;
3021     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3022       // The entire subregister is defined by this insert, forward the new
3023       // value.
3024       DstRegs.push_back(OpReg);
3025       continue;
3026     }
3027 
3028     // OpSegStart is where this destination segment would start in OpReg if it
3029     // extended infinitely in both directions.
3030     int64_t ExtractOffset, InsertOffset;
3031     uint64_t SegSize;
3032     if (OpStart < DstStart) {
3033       InsertOffset = 0;
3034       ExtractOffset = DstStart - OpStart;
3035       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3036     } else {
3037       InsertOffset = OpStart - DstStart;
3038       ExtractOffset = 0;
3039       SegSize =
3040         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3041     }
3042 
3043     Register SegReg = OpReg;
3044     if (ExtractOffset != 0 || SegSize != OpSize) {
3045       // A genuine extract is needed.
3046       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3047       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3048     }
3049 
3050     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3051     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3052     DstRegs.push_back(DstReg);
3053   }
3054 
3055   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3056   Register DstReg = MI.getOperand(0).getReg();
3057   if(MRI.getType(DstReg).isVector())
3058     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3059   else
3060     MIRBuilder.buildMerge(DstReg, DstRegs);
3061   MI.eraseFromParent();
3062   return Legalized;
3063 }
3064 
3065 LegalizerHelper::LegalizeResult
3066 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3067                                    LLT NarrowTy) {
3068   Register DstReg = MI.getOperand(0).getReg();
3069   LLT DstTy = MRI.getType(DstReg);
3070 
3071   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3072 
3073   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3074   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3075   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3076   LLT LeftoverTy;
3077   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3078                     Src0Regs, Src0LeftoverRegs))
3079     return UnableToLegalize;
3080 
3081   LLT Unused;
3082   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3083                     Src1Regs, Src1LeftoverRegs))
3084     llvm_unreachable("inconsistent extractParts result");
3085 
3086   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3087     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3088                                         {Src0Regs[I], Src1Regs[I]});
3089     DstRegs.push_back(Inst->getOperand(0).getReg());
3090   }
3091 
3092   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3093     auto Inst = MIRBuilder.buildInstr(
3094       MI.getOpcode(),
3095       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3096     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3097   }
3098 
3099   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3100               LeftoverTy, DstLeftoverRegs);
3101 
3102   MI.eraseFromParent();
3103   return Legalized;
3104 }
3105 
3106 LegalizerHelper::LegalizeResult
3107 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3108                                     LLT NarrowTy) {
3109   if (TypeIdx != 0)
3110     return UnableToLegalize;
3111 
3112   Register CondReg = MI.getOperand(1).getReg();
3113   LLT CondTy = MRI.getType(CondReg);
3114   if (CondTy.isVector()) // TODO: Handle vselect
3115     return UnableToLegalize;
3116 
3117   Register DstReg = MI.getOperand(0).getReg();
3118   LLT DstTy = MRI.getType(DstReg);
3119 
3120   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3121   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3122   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3123   LLT LeftoverTy;
3124   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3125                     Src1Regs, Src1LeftoverRegs))
3126     return UnableToLegalize;
3127 
3128   LLT Unused;
3129   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3130                     Src2Regs, Src2LeftoverRegs))
3131     llvm_unreachable("inconsistent extractParts result");
3132 
3133   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3134     auto Select = MIRBuilder.buildSelect(NarrowTy,
3135                                          CondReg, Src1Regs[I], Src2Regs[I]);
3136     DstRegs.push_back(Select->getOperand(0).getReg());
3137   }
3138 
3139   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3140     auto Select = MIRBuilder.buildSelect(
3141       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3142     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3143   }
3144 
3145   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3146               LeftoverTy, DstLeftoverRegs);
3147 
3148   MI.eraseFromParent();
3149   return Legalized;
3150 }
3151 
3152 LegalizerHelper::LegalizeResult
3153 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3154   unsigned Opc = MI.getOpcode();
3155   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3156   auto isSupported = [this](const LegalityQuery &Q) {
3157     auto QAction = LI.getAction(Q).Action;
3158     return QAction == Legal || QAction == Libcall || QAction == Custom;
3159   };
3160   switch (Opc) {
3161   default:
3162     return UnableToLegalize;
3163   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3164     // This trivially expands to CTLZ.
3165     Observer.changingInstr(MI);
3166     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3167     Observer.changedInstr(MI);
3168     return Legalized;
3169   }
3170   case TargetOpcode::G_CTLZ: {
3171     Register SrcReg = MI.getOperand(1).getReg();
3172     unsigned Len = Ty.getSizeInBits();
3173     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3174       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3175       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3176                                              {Ty}, {SrcReg});
3177       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3178       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3179       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3180                                           SrcReg, MIBZero);
3181       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3182                              MIBCtlzZU);
3183       MI.eraseFromParent();
3184       return Legalized;
3185     }
3186     // for now, we do this:
3187     // NewLen = NextPowerOf2(Len);
3188     // x = x | (x >> 1);
3189     // x = x | (x >> 2);
3190     // ...
3191     // x = x | (x >>16);
3192     // x = x | (x >>32); // for 64-bit input
3193     // Upto NewLen/2
3194     // return Len - popcount(x);
3195     //
3196     // Ref: "Hacker's Delight" by Henry Warren
3197     Register Op = SrcReg;
3198     unsigned NewLen = PowerOf2Ceil(Len);
3199     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3200       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3201       auto MIBOp = MIRBuilder.buildInstr(
3202           TargetOpcode::G_OR, {Ty},
3203           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3204                                      {Op, MIBShiftAmt})});
3205       Op = MIBOp->getOperand(0).getReg();
3206     }
3207     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3208     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3209                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3210     MI.eraseFromParent();
3211     return Legalized;
3212   }
3213   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3214     // This trivially expands to CTTZ.
3215     Observer.changingInstr(MI);
3216     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3217     Observer.changedInstr(MI);
3218     return Legalized;
3219   }
3220   case TargetOpcode::G_CTTZ: {
3221     Register SrcReg = MI.getOperand(1).getReg();
3222     unsigned Len = Ty.getSizeInBits();
3223     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3224       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3225       // zero.
3226       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3227                                              {Ty}, {SrcReg});
3228       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3229       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3230       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3231                                           SrcReg, MIBZero);
3232       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3233                              MIBCttzZU);
3234       MI.eraseFromParent();
3235       return Legalized;
3236     }
3237     // for now, we use: { return popcount(~x & (x - 1)); }
3238     // unless the target has ctlz but not ctpop, in which case we use:
3239     // { return 32 - nlz(~x & (x-1)); }
3240     // Ref: "Hacker's Delight" by Henry Warren
3241     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3242     auto MIBNot =
3243         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3244     auto MIBTmp = MIRBuilder.buildInstr(
3245         TargetOpcode::G_AND, {Ty},
3246         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3247                                        {SrcReg, MIBCstNeg1})});
3248     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3249         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3250       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3251       MIRBuilder.buildInstr(
3252           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3253           {MIBCstLen,
3254            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3255       MI.eraseFromParent();
3256       return Legalized;
3257     }
3258     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3259     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3260     return Legalized;
3261   }
3262   }
3263 }
3264 
3265 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3266 // representation.
3267 LegalizerHelper::LegalizeResult
3268 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3269   Register Dst = MI.getOperand(0).getReg();
3270   Register Src = MI.getOperand(1).getReg();
3271   const LLT S64 = LLT::scalar(64);
3272   const LLT S32 = LLT::scalar(32);
3273   const LLT S1 = LLT::scalar(1);
3274 
3275   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3276 
3277   // unsigned cul2f(ulong u) {
3278   //   uint lz = clz(u);
3279   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3280   //   u = (u << lz) & 0x7fffffffffffffffUL;
3281   //   ulong t = u & 0xffffffffffUL;
3282   //   uint v = (e << 23) | (uint)(u >> 40);
3283   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3284   //   return as_float(v + r);
3285   // }
3286 
3287   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3288   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3289 
3290   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3291 
3292   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3293   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3294 
3295   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3296   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3297 
3298   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3299   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3300 
3301   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3302 
3303   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3304   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3305 
3306   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3307   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3308   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3309 
3310   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3311   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3312   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3313   auto One = MIRBuilder.buildConstant(S32, 1);
3314 
3315   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3316   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3317   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3318   MIRBuilder.buildAdd(Dst, V, R);
3319 
3320   return Legalized;
3321 }
3322 
3323 LegalizerHelper::LegalizeResult
3324 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3325   Register Dst = MI.getOperand(0).getReg();
3326   Register Src = MI.getOperand(1).getReg();
3327   LLT DstTy = MRI.getType(Dst);
3328   LLT SrcTy = MRI.getType(Src);
3329 
3330   if (SrcTy != LLT::scalar(64))
3331     return UnableToLegalize;
3332 
3333   if (DstTy == LLT::scalar(32)) {
3334     // TODO: SelectionDAG has several alternative expansions to port which may
3335     // be more reasonble depending on the available instructions. If a target
3336     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3337     // intermediate type, this is probably worse.
3338     return lowerU64ToF32BitOps(MI);
3339   }
3340 
3341   return UnableToLegalize;
3342 }
3343 
3344 LegalizerHelper::LegalizeResult
3345 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3346   Register Dst = MI.getOperand(0).getReg();
3347   Register Src = MI.getOperand(1).getReg();
3348   LLT DstTy = MRI.getType(Dst);
3349   LLT SrcTy = MRI.getType(Src);
3350 
3351   const LLT S64 = LLT::scalar(64);
3352   const LLT S32 = LLT::scalar(32);
3353   const LLT S1 = LLT::scalar(1);
3354 
3355   if (SrcTy != S64)
3356     return UnableToLegalize;
3357 
3358   if (DstTy == S32) {
3359     // signed cl2f(long l) {
3360     //   long s = l >> 63;
3361     //   float r = cul2f((l + s) ^ s);
3362     //   return s ? -r : r;
3363     // }
3364     Register L = Src;
3365     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3366     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3367 
3368     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3369     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3370     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3371 
3372     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3373     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3374                                             MIRBuilder.buildConstant(S64, 0));
3375     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3376     return Legalized;
3377   }
3378 
3379   return UnableToLegalize;
3380 }
3381 
3382 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
3383   switch (Opc) {
3384   case TargetOpcode::G_SMIN:
3385     return CmpInst::ICMP_SLT;
3386   case TargetOpcode::G_SMAX:
3387     return CmpInst::ICMP_SGT;
3388   case TargetOpcode::G_UMIN:
3389     return CmpInst::ICMP_ULT;
3390   case TargetOpcode::G_UMAX:
3391     return CmpInst::ICMP_UGT;
3392   default:
3393     llvm_unreachable("not in integer min/max");
3394   }
3395 }
3396 
3397 LegalizerHelper::LegalizeResult
3398 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3399   Register Dst = MI.getOperand(0).getReg();
3400   Register Src0 = MI.getOperand(1).getReg();
3401   Register Src1 = MI.getOperand(2).getReg();
3402 
3403   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
3404   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
3405 
3406   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3407   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
3408 
3409   MI.eraseFromParent();
3410   return Legalized;
3411 }
3412 
3413 LegalizerHelper::LegalizeResult
3414 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3415   Register Dst = MI.getOperand(0).getReg();
3416   Register Src0 = MI.getOperand(1).getReg();
3417   Register Src1 = MI.getOperand(2).getReg();
3418 
3419   const LLT Src0Ty = MRI.getType(Src0);
3420   const LLT Src1Ty = MRI.getType(Src1);
3421 
3422   const int Src0Size = Src0Ty.getScalarSizeInBits();
3423   const int Src1Size = Src1Ty.getScalarSizeInBits();
3424 
3425   auto SignBitMask = MIRBuilder.buildConstant(
3426     Src0Ty, APInt::getSignMask(Src0Size));
3427 
3428   auto NotSignBitMask = MIRBuilder.buildConstant(
3429     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
3430 
3431   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
3432   MachineInstr *Or;
3433 
3434   if (Src0Ty == Src1Ty) {
3435     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
3436     Or = MIRBuilder.buildOr(Dst, And0, And1);
3437   } else if (Src0Size > Src1Size) {
3438     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
3439     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
3440     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
3441     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
3442     Or = MIRBuilder.buildOr(Dst, And0, And1);
3443   } else {
3444     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
3445     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
3446     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
3447     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
3448     Or = MIRBuilder.buildOr(Dst, And0, And1);
3449   }
3450 
3451   // Be careful about setting nsz/nnan/ninf on every instruction, since the
3452   // constants are a nan and -0.0, but the final result should preserve
3453   // everything.
3454   if (unsigned Flags = MI.getFlags())
3455     Or->setFlags(Flags);
3456 
3457   MI.eraseFromParent();
3458   return Legalized;
3459 }
3460 
3461 LegalizerHelper::LegalizeResult
3462 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
3463   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
3464     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
3465 
3466   Register Dst = MI.getOperand(0).getReg();
3467   Register Src0 = MI.getOperand(1).getReg();
3468   Register Src1 = MI.getOperand(2).getReg();
3469   LLT Ty = MRI.getType(Dst);
3470 
3471   if (!MI.getFlag(MachineInstr::FmNoNans)) {
3472     // Insert canonicalizes if it's possible we need to quiet to get correct
3473     // sNaN behavior.
3474 
3475     // Note this must be done here, and not as an optimization combine in the
3476     // absence of a dedicate quiet-snan instruction as we're using an
3477     // omni-purpose G_FCANONICALIZE.
3478     if (!isKnownNeverSNaN(Src0, MRI))
3479       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
3480 
3481     if (!isKnownNeverSNaN(Src1, MRI))
3482       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
3483   }
3484 
3485   // If there are no nans, it's safe to simply replace this with the non-IEEE
3486   // version.
3487   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
3488   MI.eraseFromParent();
3489   return Legalized;
3490 }
3491