1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   auto Step = LI.getAction(MI, MRI);
86   switch (Step.Action) {
87   case Legal:
88     LLVM_DEBUG(dbgs() << ".. Already legal\n");
89     return AlreadyLegal;
90   case Libcall:
91     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
92     return libcall(MI);
93   case NarrowScalar:
94     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
95     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
96   case WidenScalar:
97     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
98     return widenScalar(MI, Step.TypeIdx, Step.NewType);
99   case Lower:
100     LLVM_DEBUG(dbgs() << ".. Lower\n");
101     return lower(MI, Step.TypeIdx, Step.NewType);
102   case FewerElements:
103     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
104     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
105   case MoreElements:
106     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
107     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
108   case Custom:
109     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
110     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
111                                                             : UnableToLegalize;
112   default:
113     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
114     return UnableToLegalize;
115   }
116 }
117 
118 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
119                                    SmallVectorImpl<unsigned> &VRegs) {
120   for (int i = 0; i < NumParts; ++i)
121     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
122   MIRBuilder.buildUnmerge(VRegs, Reg);
123 }
124 
125 bool LegalizerHelper::extractParts(unsigned Reg, LLT RegTy,
126                                    LLT MainTy, LLT &LeftoverTy,
127                                    SmallVectorImpl<unsigned> &VRegs,
128                                    SmallVectorImpl<unsigned> &LeftoverRegs) {
129   assert(!LeftoverTy.isValid() && "this is an out argument");
130 
131   unsigned RegSize = RegTy.getSizeInBits();
132   unsigned MainSize = MainTy.getSizeInBits();
133   unsigned NumParts = RegSize / MainSize;
134   unsigned LeftoverSize = RegSize - NumParts * MainSize;
135 
136   // Use an unmerge when possible.
137   if (LeftoverSize == 0) {
138     for (unsigned I = 0; I < NumParts; ++I)
139       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
140     MIRBuilder.buildUnmerge(VRegs, Reg);
141     return true;
142   }
143 
144   if (MainTy.isVector()) {
145     unsigned EltSize = MainTy.getScalarSizeInBits();
146     if (LeftoverSize % EltSize != 0)
147       return false;
148     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
149   } else {
150     LeftoverTy = LLT::scalar(LeftoverSize);
151   }
152 
153   // For irregular sizes, extract the individual parts.
154   for (unsigned I = 0; I != NumParts; ++I) {
155     unsigned NewReg = MRI.createGenericVirtualRegister(MainTy);
156     VRegs.push_back(NewReg);
157     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
158   }
159 
160   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
161        Offset += LeftoverSize) {
162     unsigned NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
163     LeftoverRegs.push_back(NewReg);
164     MIRBuilder.buildExtract(NewReg, Reg, Offset);
165   }
166 
167   return true;
168 }
169 
170 void LegalizerHelper::insertParts(unsigned DstReg,
171                                   LLT ResultTy, LLT PartTy,
172                                   ArrayRef<unsigned> PartRegs,
173                                   LLT LeftoverTy,
174                                   ArrayRef<unsigned> LeftoverRegs) {
175   if (!LeftoverTy.isValid()) {
176     assert(LeftoverRegs.empty());
177 
178     if (!ResultTy.isVector()) {
179       MIRBuilder.buildMerge(DstReg, PartRegs);
180       return;
181     }
182 
183     if (PartTy.isVector())
184       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
185     else
186       MIRBuilder.buildBuildVector(DstReg, PartRegs);
187     return;
188   }
189 
190   unsigned PartSize = PartTy.getSizeInBits();
191   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
192 
193   unsigned CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
194   MIRBuilder.buildUndef(CurResultReg);
195 
196   unsigned Offset = 0;
197   for (unsigned PartReg : PartRegs) {
198     unsigned NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
199     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
200     CurResultReg = NewResultReg;
201     Offset += PartSize;
202   }
203 
204   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
205     // Use the original output register for the final insert to avoid a copy.
206     unsigned NewResultReg = (I + 1 == E) ?
207       DstReg : MRI.createGenericVirtualRegister(ResultTy);
208 
209     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
210     CurResultReg = NewResultReg;
211     Offset += LeftoverPartSize;
212   }
213 }
214 
215 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
216   switch (Opcode) {
217   case TargetOpcode::G_SDIV:
218     assert((Size == 32 || Size == 64) && "Unsupported size");
219     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
220   case TargetOpcode::G_UDIV:
221     assert((Size == 32 || Size == 64) && "Unsupported size");
222     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
223   case TargetOpcode::G_SREM:
224     assert((Size == 32 || Size == 64) && "Unsupported size");
225     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
226   case TargetOpcode::G_UREM:
227     assert((Size == 32 || Size == 64) && "Unsupported size");
228     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
229   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
230     assert(Size == 32 && "Unsupported size");
231     return RTLIB::CTLZ_I32;
232   case TargetOpcode::G_FADD:
233     assert((Size == 32 || Size == 64) && "Unsupported size");
234     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
235   case TargetOpcode::G_FSUB:
236     assert((Size == 32 || Size == 64) && "Unsupported size");
237     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
238   case TargetOpcode::G_FMUL:
239     assert((Size == 32 || Size == 64) && "Unsupported size");
240     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
241   case TargetOpcode::G_FDIV:
242     assert((Size == 32 || Size == 64) && "Unsupported size");
243     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
244   case TargetOpcode::G_FEXP:
245     assert((Size == 32 || Size == 64) && "Unsupported size");
246     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
247   case TargetOpcode::G_FEXP2:
248     assert((Size == 32 || Size == 64) && "Unsupported size");
249     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
250   case TargetOpcode::G_FREM:
251     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
252   case TargetOpcode::G_FPOW:
253     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
254   case TargetOpcode::G_FMA:
255     assert((Size == 32 || Size == 64) && "Unsupported size");
256     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
257   case TargetOpcode::G_FSIN:
258     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
259     return Size == 128 ? RTLIB::SIN_F128
260                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
261   case TargetOpcode::G_FCOS:
262     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
263     return Size == 128 ? RTLIB::COS_F128
264                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
265   case TargetOpcode::G_FLOG10:
266     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
267     return Size == 128 ? RTLIB::LOG10_F128
268                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
269   case TargetOpcode::G_FLOG:
270     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
271     return Size == 128 ? RTLIB::LOG_F128
272                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
273   case TargetOpcode::G_FLOG2:
274     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
275     return Size == 128 ? RTLIB::LOG2_F128
276                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
277   }
278   llvm_unreachable("Unknown libcall function");
279 }
280 
281 LegalizerHelper::LegalizeResult
282 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
283                     const CallLowering::ArgInfo &Result,
284                     ArrayRef<CallLowering::ArgInfo> Args) {
285   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
286   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
287   const char *Name = TLI.getLibcallName(Libcall);
288 
289   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
290   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
291                      MachineOperand::CreateES(Name), Result, Args))
292     return LegalizerHelper::UnableToLegalize;
293 
294   return LegalizerHelper::Legalized;
295 }
296 
297 // Useful for libcalls where all operands have the same type.
298 static LegalizerHelper::LegalizeResult
299 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
300               Type *OpType) {
301   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
302 
303   SmallVector<CallLowering::ArgInfo, 3> Args;
304   for (unsigned i = 1; i < MI.getNumOperands(); i++)
305     Args.push_back({MI.getOperand(i).getReg(), OpType});
306   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
307                        Args);
308 }
309 
310 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
311                                        Type *FromType) {
312   auto ToMVT = MVT::getVT(ToType);
313   auto FromMVT = MVT::getVT(FromType);
314 
315   switch (Opcode) {
316   case TargetOpcode::G_FPEXT:
317     return RTLIB::getFPEXT(FromMVT, ToMVT);
318   case TargetOpcode::G_FPTRUNC:
319     return RTLIB::getFPROUND(FromMVT, ToMVT);
320   case TargetOpcode::G_FPTOSI:
321     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
322   case TargetOpcode::G_FPTOUI:
323     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
324   case TargetOpcode::G_SITOFP:
325     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
326   case TargetOpcode::G_UITOFP:
327     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
328   }
329   llvm_unreachable("Unsupported libcall function");
330 }
331 
332 static LegalizerHelper::LegalizeResult
333 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
334                   Type *FromType) {
335   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
336   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
337                        {{MI.getOperand(1).getReg(), FromType}});
338 }
339 
340 LegalizerHelper::LegalizeResult
341 LegalizerHelper::libcall(MachineInstr &MI) {
342   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
343   unsigned Size = LLTy.getSizeInBits();
344   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
345 
346   MIRBuilder.setInstr(MI);
347 
348   switch (MI.getOpcode()) {
349   default:
350     return UnableToLegalize;
351   case TargetOpcode::G_SDIV:
352   case TargetOpcode::G_UDIV:
353   case TargetOpcode::G_SREM:
354   case TargetOpcode::G_UREM:
355   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
356     Type *HLTy = IntegerType::get(Ctx, Size);
357     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
358     if (Status != Legalized)
359       return Status;
360     break;
361   }
362   case TargetOpcode::G_FADD:
363   case TargetOpcode::G_FSUB:
364   case TargetOpcode::G_FMUL:
365   case TargetOpcode::G_FDIV:
366   case TargetOpcode::G_FMA:
367   case TargetOpcode::G_FPOW:
368   case TargetOpcode::G_FREM:
369   case TargetOpcode::G_FCOS:
370   case TargetOpcode::G_FSIN:
371   case TargetOpcode::G_FLOG10:
372   case TargetOpcode::G_FLOG:
373   case TargetOpcode::G_FLOG2:
374   case TargetOpcode::G_FEXP:
375   case TargetOpcode::G_FEXP2: {
376     if (Size > 64) {
377       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
378       return UnableToLegalize;
379     }
380     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
381     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
382     if (Status != Legalized)
383       return Status;
384     break;
385   }
386   case TargetOpcode::G_FPEXT: {
387     // FIXME: Support other floating point types (half, fp128 etc)
388     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
389     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
390     if (ToSize != 64 || FromSize != 32)
391       return UnableToLegalize;
392     LegalizeResult Status = conversionLibcall(
393         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
394     if (Status != Legalized)
395       return Status;
396     break;
397   }
398   case TargetOpcode::G_FPTRUNC: {
399     // FIXME: Support other floating point types (half, fp128 etc)
400     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
401     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
402     if (ToSize != 32 || FromSize != 64)
403       return UnableToLegalize;
404     LegalizeResult Status = conversionLibcall(
405         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
406     if (Status != Legalized)
407       return Status;
408     break;
409   }
410   case TargetOpcode::G_FPTOSI:
411   case TargetOpcode::G_FPTOUI: {
412     // FIXME: Support other types
413     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
414     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
415     if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
416       return UnableToLegalize;
417     LegalizeResult Status = conversionLibcall(
418         MI, MIRBuilder, Type::getInt32Ty(Ctx),
419         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
420     if (Status != Legalized)
421       return Status;
422     break;
423   }
424   case TargetOpcode::G_SITOFP:
425   case TargetOpcode::G_UITOFP: {
426     // FIXME: Support other types
427     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
428     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
429     if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
430       return UnableToLegalize;
431     LegalizeResult Status = conversionLibcall(
432         MI, MIRBuilder,
433         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
434         Type::getInt32Ty(Ctx));
435     if (Status != Legalized)
436       return Status;
437     break;
438   }
439   }
440 
441   MI.eraseFromParent();
442   return Legalized;
443 }
444 
445 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
446                                                               unsigned TypeIdx,
447                                                               LLT NarrowTy) {
448   MIRBuilder.setInstr(MI);
449 
450   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
451   uint64_t NarrowSize = NarrowTy.getSizeInBits();
452 
453   switch (MI.getOpcode()) {
454   default:
455     return UnableToLegalize;
456   case TargetOpcode::G_IMPLICIT_DEF: {
457     // FIXME: add support for when SizeOp0 isn't an exact multiple of
458     // NarrowSize.
459     if (SizeOp0 % NarrowSize != 0)
460       return UnableToLegalize;
461     int NumParts = SizeOp0 / NarrowSize;
462 
463     SmallVector<unsigned, 2> DstRegs;
464     for (int i = 0; i < NumParts; ++i)
465       DstRegs.push_back(
466           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
467 
468     unsigned DstReg = MI.getOperand(0).getReg();
469     if(MRI.getType(DstReg).isVector())
470       MIRBuilder.buildBuildVector(DstReg, DstRegs);
471     else
472       MIRBuilder.buildMerge(DstReg, DstRegs);
473     MI.eraseFromParent();
474     return Legalized;
475   }
476   case TargetOpcode::G_CONSTANT: {
477     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
478     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
479     unsigned TotalSize = Ty.getSizeInBits();
480     unsigned NarrowSize = NarrowTy.getSizeInBits();
481     int NumParts = TotalSize / NarrowSize;
482 
483     SmallVector<unsigned, 4> PartRegs;
484     for (int I = 0; I != NumParts; ++I) {
485       unsigned Offset = I * NarrowSize;
486       auto K = MIRBuilder.buildConstant(NarrowTy,
487                                         Val.lshr(Offset).trunc(NarrowSize));
488       PartRegs.push_back(K.getReg(0));
489     }
490 
491     LLT LeftoverTy;
492     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
493     SmallVector<unsigned, 1> LeftoverRegs;
494     if (LeftoverBits != 0) {
495       LeftoverTy = LLT::scalar(LeftoverBits);
496       auto K = MIRBuilder.buildConstant(
497         LeftoverTy,
498         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
499       LeftoverRegs.push_back(K.getReg(0));
500     }
501 
502     insertParts(MI.getOperand(0).getReg(),
503                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
504 
505     MI.eraseFromParent();
506     return Legalized;
507   }
508   case TargetOpcode::G_ADD: {
509     // FIXME: add support for when SizeOp0 isn't an exact multiple of
510     // NarrowSize.
511     if (SizeOp0 % NarrowSize != 0)
512       return UnableToLegalize;
513     // Expand in terms of carry-setting/consuming G_ADDE instructions.
514     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
515 
516     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
517     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
518     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
519 
520     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
521     MIRBuilder.buildConstant(CarryIn, 0);
522 
523     for (int i = 0; i < NumParts; ++i) {
524       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
525       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
526 
527       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
528                             Src2Regs[i], CarryIn);
529 
530       DstRegs.push_back(DstReg);
531       CarryIn = CarryOut;
532     }
533     unsigned DstReg = MI.getOperand(0).getReg();
534     if(MRI.getType(DstReg).isVector())
535       MIRBuilder.buildBuildVector(DstReg, DstRegs);
536     else
537       MIRBuilder.buildMerge(DstReg, DstRegs);
538     MI.eraseFromParent();
539     return Legalized;
540   }
541   case TargetOpcode::G_SUB: {
542     // FIXME: add support for when SizeOp0 isn't an exact multiple of
543     // NarrowSize.
544     if (SizeOp0 % NarrowSize != 0)
545       return UnableToLegalize;
546 
547     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
548 
549     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
550     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
551     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
552 
553     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
554     unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
555     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
556                           {Src1Regs[0], Src2Regs[0]});
557     DstRegs.push_back(DstReg);
558     unsigned BorrowIn = BorrowOut;
559     for (int i = 1; i < NumParts; ++i) {
560       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
561       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
562 
563       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
564                             {Src1Regs[i], Src2Regs[i], BorrowIn});
565 
566       DstRegs.push_back(DstReg);
567       BorrowIn = BorrowOut;
568     }
569     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
570     MI.eraseFromParent();
571     return Legalized;
572   }
573   case TargetOpcode::G_MUL:
574   case TargetOpcode::G_UMULH:
575     return narrowScalarMul(MI, NarrowTy);
576   case TargetOpcode::G_EXTRACT:
577     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
578   case TargetOpcode::G_INSERT:
579     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
580   case TargetOpcode::G_LOAD: {
581     const auto &MMO = **MI.memoperands_begin();
582     unsigned DstReg = MI.getOperand(0).getReg();
583     LLT DstTy = MRI.getType(DstReg);
584     if (DstTy.isVector())
585       return UnableToLegalize;
586 
587     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
588       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
589       auto &MMO = **MI.memoperands_begin();
590       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
591       MIRBuilder.buildAnyExt(DstReg, TmpReg);
592       MI.eraseFromParent();
593       return Legalized;
594     }
595 
596     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
597   }
598   case TargetOpcode::G_ZEXTLOAD:
599   case TargetOpcode::G_SEXTLOAD: {
600     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
601     unsigned DstReg = MI.getOperand(0).getReg();
602     unsigned PtrReg = MI.getOperand(1).getReg();
603 
604     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
605     auto &MMO = **MI.memoperands_begin();
606     if (MMO.getSizeInBits() == NarrowSize) {
607       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
608     } else {
609       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
610         : TargetOpcode::G_SEXTLOAD;
611       MIRBuilder.buildInstr(ExtLoad)
612         .addDef(TmpReg)
613         .addUse(PtrReg)
614         .addMemOperand(&MMO);
615     }
616 
617     if (ZExt)
618       MIRBuilder.buildZExt(DstReg, TmpReg);
619     else
620       MIRBuilder.buildSExt(DstReg, TmpReg);
621 
622     MI.eraseFromParent();
623     return Legalized;
624   }
625   case TargetOpcode::G_STORE: {
626     const auto &MMO = **MI.memoperands_begin();
627 
628     unsigned SrcReg = MI.getOperand(0).getReg();
629     LLT SrcTy = MRI.getType(SrcReg);
630     if (SrcTy.isVector())
631       return UnableToLegalize;
632 
633     int NumParts = SizeOp0 / NarrowSize;
634     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
635     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
636     if (SrcTy.isVector() && LeftoverBits != 0)
637       return UnableToLegalize;
638 
639     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
640       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
641       auto &MMO = **MI.memoperands_begin();
642       MIRBuilder.buildTrunc(TmpReg, SrcReg);
643       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
644       MI.eraseFromParent();
645       return Legalized;
646     }
647 
648     return reduceLoadStoreWidth(MI, 0, NarrowTy);
649   }
650   case TargetOpcode::G_SELECT:
651     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
652   case TargetOpcode::G_AND:
653   case TargetOpcode::G_OR:
654   case TargetOpcode::G_XOR: {
655     // Legalize bitwise operation:
656     // A = BinOp<Ty> B, C
657     // into:
658     // B1, ..., BN = G_UNMERGE_VALUES B
659     // C1, ..., CN = G_UNMERGE_VALUES C
660     // A1 = BinOp<Ty/N> B1, C2
661     // ...
662     // AN = BinOp<Ty/N> BN, CN
663     // A = G_MERGE_VALUES A1, ..., AN
664     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
665   }
666   case TargetOpcode::G_SHL:
667   case TargetOpcode::G_LSHR:
668   case TargetOpcode::G_ASHR:
669     return narrowScalarShift(MI, TypeIdx, NarrowTy);
670   case TargetOpcode::G_CTLZ:
671   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
672   case TargetOpcode::G_CTTZ:
673   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
674   case TargetOpcode::G_CTPOP:
675     if (TypeIdx != 0)
676       return UnableToLegalize; // TODO
677 
678     Observer.changingInstr(MI);
679     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
680     Observer.changedInstr(MI);
681     return Legalized;
682   case TargetOpcode::G_INTTOPTR:
683     if (TypeIdx != 1)
684       return UnableToLegalize;
685 
686     Observer.changingInstr(MI);
687     narrowScalarSrc(MI, NarrowTy, 1);
688     Observer.changedInstr(MI);
689     return Legalized;
690   case TargetOpcode::G_PTRTOINT:
691     if (TypeIdx != 0)
692       return UnableToLegalize;
693 
694     Observer.changingInstr(MI);
695     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
696     Observer.changedInstr(MI);
697     return Legalized;
698   }
699 }
700 
701 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
702                                      unsigned OpIdx, unsigned ExtOpcode) {
703   MachineOperand &MO = MI.getOperand(OpIdx);
704   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
705   MO.setReg(ExtB->getOperand(0).getReg());
706 }
707 
708 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
709                                       unsigned OpIdx) {
710   MachineOperand &MO = MI.getOperand(OpIdx);
711   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
712                                     {MO.getReg()});
713   MO.setReg(ExtB->getOperand(0).getReg());
714 }
715 
716 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
717                                      unsigned OpIdx, unsigned TruncOpcode) {
718   MachineOperand &MO = MI.getOperand(OpIdx);
719   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
720   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
721   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
722   MO.setReg(DstExt);
723 }
724 
725 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
726                                       unsigned OpIdx, unsigned ExtOpcode) {
727   MachineOperand &MO = MI.getOperand(OpIdx);
728   unsigned DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
729   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
730   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
731   MO.setReg(DstTrunc);
732 }
733 
734 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
735                                             unsigned OpIdx) {
736   MachineOperand &MO = MI.getOperand(OpIdx);
737   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
738   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
739   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
740   MO.setReg(DstExt);
741 }
742 
743 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
744                                             unsigned OpIdx) {
745   MachineOperand &MO = MI.getOperand(OpIdx);
746 
747   LLT OldTy = MRI.getType(MO.getReg());
748   unsigned OldElts = OldTy.getNumElements();
749   unsigned NewElts = MoreTy.getNumElements();
750 
751   unsigned NumParts = NewElts / OldElts;
752 
753   // Use concat_vectors if the result is a multiple of the number of elements.
754   if (NumParts * OldElts == NewElts) {
755     SmallVector<unsigned, 8> Parts;
756     Parts.push_back(MO.getReg());
757 
758     unsigned ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
759     for (unsigned I = 1; I != NumParts; ++I)
760       Parts.push_back(ImpDef);
761 
762     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
763     MO.setReg(Concat.getReg(0));
764     return;
765   }
766 
767   unsigned MoreReg = MRI.createGenericVirtualRegister(MoreTy);
768   unsigned ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
769   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
770   MO.setReg(MoreReg);
771 }
772 
773 LegalizerHelper::LegalizeResult
774 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
775                                         LLT WideTy) {
776   if (TypeIdx != 1)
777     return UnableToLegalize;
778 
779   unsigned DstReg = MI.getOperand(0).getReg();
780   LLT DstTy = MRI.getType(DstReg);
781   if (!DstTy.isScalar())
782     return UnableToLegalize;
783 
784   unsigned NumOps = MI.getNumOperands();
785   unsigned NumSrc = MI.getNumOperands() - 1;
786   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
787 
788   unsigned Src1 = MI.getOperand(1).getReg();
789   unsigned ResultReg = MIRBuilder.buildZExt(DstTy, Src1)->getOperand(0).getReg();
790 
791   for (unsigned I = 2; I != NumOps; ++I) {
792     const unsigned Offset = (I - 1) * PartSize;
793 
794     unsigned SrcReg = MI.getOperand(I).getReg();
795     assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
796 
797     auto ZextInput = MIRBuilder.buildZExt(DstTy, SrcReg);
798 
799     unsigned NextResult = I + 1 == NumOps ? DstReg :
800       MRI.createGenericVirtualRegister(DstTy);
801 
802     auto ShiftAmt = MIRBuilder.buildConstant(DstTy, Offset);
803     auto Shl = MIRBuilder.buildShl(DstTy, ZextInput, ShiftAmt);
804     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
805     ResultReg = NextResult;
806   }
807 
808   MI.eraseFromParent();
809   return Legalized;
810 }
811 
812 LegalizerHelper::LegalizeResult
813 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
814                                           LLT WideTy) {
815   if (TypeIdx != 0)
816     return UnableToLegalize;
817 
818   unsigned NumDst = MI.getNumOperands() - 1;
819   unsigned SrcReg = MI.getOperand(NumDst).getReg();
820   LLT SrcTy = MRI.getType(SrcReg);
821   if (!SrcTy.isScalar())
822     return UnableToLegalize;
823 
824   unsigned Dst0Reg = MI.getOperand(0).getReg();
825   LLT DstTy = MRI.getType(Dst0Reg);
826   if (!DstTy.isScalar())
827     return UnableToLegalize;
828 
829   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
830   LLT NewSrcTy = LLT::scalar(NewSrcSize);
831   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
832 
833   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
834 
835   for (unsigned I = 1; I != NumDst; ++I) {
836     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
837     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
838     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
839   }
840 
841   Observer.changingInstr(MI);
842 
843   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
844   for (unsigned I = 0; I != NumDst; ++I)
845     widenScalarDst(MI, WideTy, I);
846 
847   Observer.changedInstr(MI);
848 
849   return Legalized;
850 }
851 
852 LegalizerHelper::LegalizeResult
853 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
854                                     LLT WideTy) {
855   unsigned DstReg = MI.getOperand(0).getReg();
856   unsigned SrcReg = MI.getOperand(1).getReg();
857   LLT SrcTy = MRI.getType(SrcReg);
858 
859   LLT DstTy = MRI.getType(DstReg);
860   unsigned Offset = MI.getOperand(2).getImm();
861 
862   if (TypeIdx == 0) {
863     if (SrcTy.isVector() || DstTy.isVector())
864       return UnableToLegalize;
865 
866     SrcOp Src(SrcReg);
867     if (SrcTy.isPointer()) {
868       // Extracts from pointers can be handled only if they are really just
869       // simple integers.
870       const DataLayout &DL = MIRBuilder.getDataLayout();
871       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
872         return UnableToLegalize;
873 
874       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
875       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
876       SrcTy = SrcAsIntTy;
877     }
878 
879     if (DstTy.isPointer())
880       return UnableToLegalize;
881 
882     if (Offset == 0) {
883       // Avoid a shift in the degenerate case.
884       MIRBuilder.buildTrunc(DstReg,
885                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
886       MI.eraseFromParent();
887       return Legalized;
888     }
889 
890     // Do a shift in the source type.
891     LLT ShiftTy = SrcTy;
892     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
893       Src = MIRBuilder.buildAnyExt(WideTy, Src);
894       ShiftTy = WideTy;
895     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
896       return UnableToLegalize;
897 
898     auto LShr = MIRBuilder.buildLShr(
899       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
900     MIRBuilder.buildTrunc(DstReg, LShr);
901     MI.eraseFromParent();
902     return Legalized;
903   }
904 
905   if (SrcTy.isScalar()) {
906     Observer.changingInstr(MI);
907     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
908     Observer.changedInstr(MI);
909     return Legalized;
910   }
911 
912   if (!SrcTy.isVector())
913     return UnableToLegalize;
914 
915   if (DstTy != SrcTy.getElementType())
916     return UnableToLegalize;
917 
918   if (Offset % SrcTy.getScalarSizeInBits() != 0)
919     return UnableToLegalize;
920 
921   Observer.changingInstr(MI);
922   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
923 
924   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
925                           Offset);
926   widenScalarDst(MI, WideTy.getScalarType(), 0);
927   Observer.changedInstr(MI);
928   return Legalized;
929 }
930 
931 LegalizerHelper::LegalizeResult
932 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
933                                    LLT WideTy) {
934   if (TypeIdx != 0)
935     return UnableToLegalize;
936   Observer.changingInstr(MI);
937   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
938   widenScalarDst(MI, WideTy);
939   Observer.changedInstr(MI);
940   return Legalized;
941 }
942 
943 LegalizerHelper::LegalizeResult
944 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
945   MIRBuilder.setInstr(MI);
946 
947   switch (MI.getOpcode()) {
948   default:
949     return UnableToLegalize;
950   case TargetOpcode::G_EXTRACT:
951     return widenScalarExtract(MI, TypeIdx, WideTy);
952   case TargetOpcode::G_INSERT:
953     return widenScalarInsert(MI, TypeIdx, WideTy);
954   case TargetOpcode::G_MERGE_VALUES:
955     return widenScalarMergeValues(MI, TypeIdx, WideTy);
956   case TargetOpcode::G_UNMERGE_VALUES:
957     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
958   case TargetOpcode::G_UADDO:
959   case TargetOpcode::G_USUBO: {
960     if (TypeIdx == 1)
961       return UnableToLegalize; // TODO
962     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
963                                          {MI.getOperand(2).getReg()});
964     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
965                                          {MI.getOperand(3).getReg()});
966     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
967                           ? TargetOpcode::G_ADD
968                           : TargetOpcode::G_SUB;
969     // Do the arithmetic in the larger type.
970     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
971     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
972     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
973     auto AndOp = MIRBuilder.buildInstr(
974         TargetOpcode::G_AND, {WideTy},
975         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
976     // There is no overflow if the AndOp is the same as NewOp.
977     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
978                          AndOp);
979     // Now trunc the NewOp to the original result.
980     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
981     MI.eraseFromParent();
982     return Legalized;
983   }
984   case TargetOpcode::G_CTTZ:
985   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
986   case TargetOpcode::G_CTLZ:
987   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
988   case TargetOpcode::G_CTPOP: {
989     if (TypeIdx == 0) {
990       Observer.changingInstr(MI);
991       widenScalarDst(MI, WideTy, 0);
992       Observer.changedInstr(MI);
993       return Legalized;
994     }
995 
996     unsigned SrcReg = MI.getOperand(1).getReg();
997 
998     // First ZEXT the input.
999     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1000     LLT CurTy = MRI.getType(SrcReg);
1001     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1002       // The count is the same in the larger type except if the original
1003       // value was zero.  This can be handled by setting the bit just off
1004       // the top of the original type.
1005       auto TopBit =
1006           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1007       MIBSrc = MIRBuilder.buildOr(
1008         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1009     }
1010 
1011     // Perform the operation at the larger size.
1012     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1013     // This is already the correct result for CTPOP and CTTZs
1014     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1015         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1016       // The correct result is NewOp - (Difference in widety and current ty).
1017       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1018       MIBNewOp = MIRBuilder.buildInstr(
1019           TargetOpcode::G_SUB, {WideTy},
1020           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1021     }
1022 
1023     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1024     MI.eraseFromParent();
1025     return Legalized;
1026   }
1027   case TargetOpcode::G_BSWAP: {
1028     Observer.changingInstr(MI);
1029     unsigned DstReg = MI.getOperand(0).getReg();
1030 
1031     unsigned ShrReg = MRI.createGenericVirtualRegister(WideTy);
1032     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
1033     unsigned ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1034     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1035 
1036     MI.getOperand(0).setReg(DstExt);
1037 
1038     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1039 
1040     LLT Ty = MRI.getType(DstReg);
1041     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1042     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1043     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1044       .addDef(ShrReg)
1045       .addUse(DstExt)
1046       .addUse(ShiftAmtReg);
1047 
1048     MIRBuilder.buildTrunc(DstReg, ShrReg);
1049     Observer.changedInstr(MI);
1050     return Legalized;
1051   }
1052   case TargetOpcode::G_ADD:
1053   case TargetOpcode::G_AND:
1054   case TargetOpcode::G_MUL:
1055   case TargetOpcode::G_OR:
1056   case TargetOpcode::G_XOR:
1057   case TargetOpcode::G_SUB:
1058     // Perform operation at larger width (any extension is fines here, high bits
1059     // don't affect the result) and then truncate the result back to the
1060     // original type.
1061     Observer.changingInstr(MI);
1062     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1063     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1064     widenScalarDst(MI, WideTy);
1065     Observer.changedInstr(MI);
1066     return Legalized;
1067 
1068   case TargetOpcode::G_SHL:
1069       Observer.changingInstr(MI);
1070 
1071     if (TypeIdx == 0) {
1072       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1073       widenScalarDst(MI, WideTy);
1074     } else {
1075       assert(TypeIdx == 1);
1076       // The "number of bits to shift" operand must preserve its value as an
1077       // unsigned integer:
1078       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1079     }
1080 
1081     Observer.changedInstr(MI);
1082     return Legalized;
1083 
1084   case TargetOpcode::G_SDIV:
1085   case TargetOpcode::G_SREM:
1086     Observer.changingInstr(MI);
1087     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1088     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1089     widenScalarDst(MI, WideTy);
1090     Observer.changedInstr(MI);
1091     return Legalized;
1092 
1093   case TargetOpcode::G_ASHR:
1094   case TargetOpcode::G_LSHR:
1095     Observer.changingInstr(MI);
1096 
1097     if (TypeIdx == 0) {
1098       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1099         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1100 
1101       widenScalarSrc(MI, WideTy, 1, CvtOp);
1102       widenScalarDst(MI, WideTy);
1103     } else {
1104       assert(TypeIdx == 1);
1105       // The "number of bits to shift" operand must preserve its value as an
1106       // unsigned integer:
1107       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1108     }
1109 
1110     Observer.changedInstr(MI);
1111     return Legalized;
1112   case TargetOpcode::G_UDIV:
1113   case TargetOpcode::G_UREM:
1114     Observer.changingInstr(MI);
1115     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1116     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1117     widenScalarDst(MI, WideTy);
1118     Observer.changedInstr(MI);
1119     return Legalized;
1120 
1121   case TargetOpcode::G_SELECT:
1122     Observer.changingInstr(MI);
1123     if (TypeIdx == 0) {
1124       // Perform operation at larger width (any extension is fine here, high
1125       // bits don't affect the result) and then truncate the result back to the
1126       // original type.
1127       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1128       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1129       widenScalarDst(MI, WideTy);
1130     } else {
1131       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1132       // Explicit extension is required here since high bits affect the result.
1133       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1134     }
1135     Observer.changedInstr(MI);
1136     return Legalized;
1137 
1138   case TargetOpcode::G_FPTOSI:
1139   case TargetOpcode::G_FPTOUI:
1140     if (TypeIdx != 0)
1141       return UnableToLegalize;
1142     Observer.changingInstr(MI);
1143     widenScalarDst(MI, WideTy);
1144     Observer.changedInstr(MI);
1145     return Legalized;
1146 
1147   case TargetOpcode::G_SITOFP:
1148     if (TypeIdx != 1)
1149       return UnableToLegalize;
1150     Observer.changingInstr(MI);
1151     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1152     Observer.changedInstr(MI);
1153     return Legalized;
1154 
1155   case TargetOpcode::G_UITOFP:
1156     if (TypeIdx != 1)
1157       return UnableToLegalize;
1158     Observer.changingInstr(MI);
1159     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1160     Observer.changedInstr(MI);
1161     return Legalized;
1162 
1163   case TargetOpcode::G_LOAD:
1164   case TargetOpcode::G_SEXTLOAD:
1165   case TargetOpcode::G_ZEXTLOAD:
1166     Observer.changingInstr(MI);
1167     widenScalarDst(MI, WideTy);
1168     Observer.changedInstr(MI);
1169     return Legalized;
1170 
1171   case TargetOpcode::G_STORE: {
1172     if (TypeIdx != 0)
1173       return UnableToLegalize;
1174 
1175     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1176     if (!isPowerOf2_32(Ty.getSizeInBits()))
1177       return UnableToLegalize;
1178 
1179     Observer.changingInstr(MI);
1180 
1181     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1182       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1183     widenScalarSrc(MI, WideTy, 0, ExtType);
1184 
1185     Observer.changedInstr(MI);
1186     return Legalized;
1187   }
1188   case TargetOpcode::G_CONSTANT: {
1189     MachineOperand &SrcMO = MI.getOperand(1);
1190     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1191     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1192     Observer.changingInstr(MI);
1193     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1194 
1195     widenScalarDst(MI, WideTy);
1196     Observer.changedInstr(MI);
1197     return Legalized;
1198   }
1199   case TargetOpcode::G_FCONSTANT: {
1200     MachineOperand &SrcMO = MI.getOperand(1);
1201     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1202     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1203     bool LosesInfo;
1204     switch (WideTy.getSizeInBits()) {
1205     case 32:
1206       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1207                   &LosesInfo);
1208       break;
1209     case 64:
1210       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1211                   &LosesInfo);
1212       break;
1213     default:
1214       return UnableToLegalize;
1215     }
1216 
1217     assert(!LosesInfo && "extend should always be lossless");
1218 
1219     Observer.changingInstr(MI);
1220     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1221 
1222     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1223     Observer.changedInstr(MI);
1224     return Legalized;
1225   }
1226   case TargetOpcode::G_IMPLICIT_DEF: {
1227     Observer.changingInstr(MI);
1228     widenScalarDst(MI, WideTy);
1229     Observer.changedInstr(MI);
1230     return Legalized;
1231   }
1232   case TargetOpcode::G_BRCOND:
1233     Observer.changingInstr(MI);
1234     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1235     Observer.changedInstr(MI);
1236     return Legalized;
1237 
1238   case TargetOpcode::G_FCMP:
1239     Observer.changingInstr(MI);
1240     if (TypeIdx == 0)
1241       widenScalarDst(MI, WideTy);
1242     else {
1243       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1244       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1245     }
1246     Observer.changedInstr(MI);
1247     return Legalized;
1248 
1249   case TargetOpcode::G_ICMP:
1250     Observer.changingInstr(MI);
1251     if (TypeIdx == 0)
1252       widenScalarDst(MI, WideTy);
1253     else {
1254       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1255                                MI.getOperand(1).getPredicate()))
1256                                ? TargetOpcode::G_SEXT
1257                                : TargetOpcode::G_ZEXT;
1258       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1259       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1260     }
1261     Observer.changedInstr(MI);
1262     return Legalized;
1263 
1264   case TargetOpcode::G_GEP:
1265     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1266     Observer.changingInstr(MI);
1267     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1268     Observer.changedInstr(MI);
1269     return Legalized;
1270 
1271   case TargetOpcode::G_PHI: {
1272     assert(TypeIdx == 0 && "Expecting only Idx 0");
1273 
1274     Observer.changingInstr(MI);
1275     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1276       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1277       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1278       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1279     }
1280 
1281     MachineBasicBlock &MBB = *MI.getParent();
1282     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1283     widenScalarDst(MI, WideTy);
1284     Observer.changedInstr(MI);
1285     return Legalized;
1286   }
1287   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1288     if (TypeIdx == 0) {
1289       unsigned VecReg = MI.getOperand(1).getReg();
1290       LLT VecTy = MRI.getType(VecReg);
1291       Observer.changingInstr(MI);
1292 
1293       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1294                                      WideTy.getSizeInBits()),
1295                      1, TargetOpcode::G_SEXT);
1296 
1297       widenScalarDst(MI, WideTy, 0);
1298       Observer.changedInstr(MI);
1299       return Legalized;
1300     }
1301 
1302     if (TypeIdx != 2)
1303       return UnableToLegalize;
1304     Observer.changingInstr(MI);
1305     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1306     Observer.changedInstr(MI);
1307     return Legalized;
1308   }
1309   case TargetOpcode::G_FADD:
1310   case TargetOpcode::G_FMUL:
1311   case TargetOpcode::G_FSUB:
1312   case TargetOpcode::G_FMA:
1313   case TargetOpcode::G_FNEG:
1314   case TargetOpcode::G_FABS:
1315   case TargetOpcode::G_FCANONICALIZE:
1316   case TargetOpcode::G_FDIV:
1317   case TargetOpcode::G_FREM:
1318   case TargetOpcode::G_FCEIL:
1319   case TargetOpcode::G_FFLOOR:
1320   case TargetOpcode::G_FCOS:
1321   case TargetOpcode::G_FSIN:
1322   case TargetOpcode::G_FLOG10:
1323   case TargetOpcode::G_FLOG:
1324   case TargetOpcode::G_FLOG2:
1325   case TargetOpcode::G_FRINT:
1326   case TargetOpcode::G_FSQRT:
1327   case TargetOpcode::G_FEXP:
1328   case TargetOpcode::G_FEXP2:
1329   case TargetOpcode::G_FPOW:
1330     assert(TypeIdx == 0);
1331     Observer.changingInstr(MI);
1332 
1333     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1334       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1335 
1336     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1337     Observer.changedInstr(MI);
1338     return Legalized;
1339   case TargetOpcode::G_INTTOPTR:
1340     if (TypeIdx != 1)
1341       return UnableToLegalize;
1342 
1343     Observer.changingInstr(MI);
1344     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1345     Observer.changedInstr(MI);
1346     return Legalized;
1347   case TargetOpcode::G_PTRTOINT:
1348     if (TypeIdx != 0)
1349       return UnableToLegalize;
1350 
1351     Observer.changingInstr(MI);
1352     widenScalarDst(MI, WideTy, 0);
1353     Observer.changedInstr(MI);
1354     return Legalized;
1355   }
1356 }
1357 
1358 LegalizerHelper::LegalizeResult
1359 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1360   using namespace TargetOpcode;
1361   MIRBuilder.setInstr(MI);
1362 
1363   switch(MI.getOpcode()) {
1364   default:
1365     return UnableToLegalize;
1366   case TargetOpcode::G_SREM:
1367   case TargetOpcode::G_UREM: {
1368     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
1369     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1370         .addDef(QuotReg)
1371         .addUse(MI.getOperand(1).getReg())
1372         .addUse(MI.getOperand(2).getReg());
1373 
1374     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
1375     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1376     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1377                         ProdReg);
1378     MI.eraseFromParent();
1379     return Legalized;
1380   }
1381   case TargetOpcode::G_SMULO:
1382   case TargetOpcode::G_UMULO: {
1383     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1384     // result.
1385     unsigned Res = MI.getOperand(0).getReg();
1386     unsigned Overflow = MI.getOperand(1).getReg();
1387     unsigned LHS = MI.getOperand(2).getReg();
1388     unsigned RHS = MI.getOperand(3).getReg();
1389 
1390     MIRBuilder.buildMul(Res, LHS, RHS);
1391 
1392     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1393                           ? TargetOpcode::G_SMULH
1394                           : TargetOpcode::G_UMULH;
1395 
1396     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
1397     MIRBuilder.buildInstr(Opcode)
1398       .addDef(HiPart)
1399       .addUse(LHS)
1400       .addUse(RHS);
1401 
1402     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
1403     MIRBuilder.buildConstant(Zero, 0);
1404 
1405     // For *signed* multiply, overflow is detected by checking:
1406     // (hi != (lo >> bitwidth-1))
1407     if (Opcode == TargetOpcode::G_SMULH) {
1408       unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
1409       unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1410       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1411       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1412         .addDef(Shifted)
1413         .addUse(Res)
1414         .addUse(ShiftAmt);
1415       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1416     } else {
1417       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1418     }
1419     MI.eraseFromParent();
1420     return Legalized;
1421   }
1422   case TargetOpcode::G_FNEG: {
1423     // TODO: Handle vector types once we are able to
1424     // represent them.
1425     if (Ty.isVector())
1426       return UnableToLegalize;
1427     unsigned Res = MI.getOperand(0).getReg();
1428     Type *ZeroTy;
1429     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1430     switch (Ty.getSizeInBits()) {
1431     case 16:
1432       ZeroTy = Type::getHalfTy(Ctx);
1433       break;
1434     case 32:
1435       ZeroTy = Type::getFloatTy(Ctx);
1436       break;
1437     case 64:
1438       ZeroTy = Type::getDoubleTy(Ctx);
1439       break;
1440     case 128:
1441       ZeroTy = Type::getFP128Ty(Ctx);
1442       break;
1443     default:
1444       llvm_unreachable("unexpected floating-point type");
1445     }
1446     ConstantFP &ZeroForNegation =
1447         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1448     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1449     unsigned SubByReg = MI.getOperand(1).getReg();
1450     unsigned ZeroReg = Zero->getOperand(0).getReg();
1451     MachineInstr *SrcMI = MRI.getVRegDef(SubByReg);
1452     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1453                           SrcMI->getFlags());
1454     MI.eraseFromParent();
1455     return Legalized;
1456   }
1457   case TargetOpcode::G_FSUB: {
1458     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1459     // First, check if G_FNEG is marked as Lower. If so, we may
1460     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1461     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1462       return UnableToLegalize;
1463     unsigned Res = MI.getOperand(0).getReg();
1464     unsigned LHS = MI.getOperand(1).getReg();
1465     unsigned RHS = MI.getOperand(2).getReg();
1466     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1467     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1468     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1469     MI.eraseFromParent();
1470     return Legalized;
1471   }
1472   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1473     unsigned OldValRes = MI.getOperand(0).getReg();
1474     unsigned SuccessRes = MI.getOperand(1).getReg();
1475     unsigned Addr = MI.getOperand(2).getReg();
1476     unsigned CmpVal = MI.getOperand(3).getReg();
1477     unsigned NewVal = MI.getOperand(4).getReg();
1478     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1479                                   **MI.memoperands_begin());
1480     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1481     MI.eraseFromParent();
1482     return Legalized;
1483   }
1484   case TargetOpcode::G_LOAD:
1485   case TargetOpcode::G_SEXTLOAD:
1486   case TargetOpcode::G_ZEXTLOAD: {
1487     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1488     unsigned DstReg = MI.getOperand(0).getReg();
1489     unsigned PtrReg = MI.getOperand(1).getReg();
1490     LLT DstTy = MRI.getType(DstReg);
1491     auto &MMO = **MI.memoperands_begin();
1492 
1493     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1494       // In the case of G_LOAD, this was a non-extending load already and we're
1495       // about to lower to the same instruction.
1496       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1497           return UnableToLegalize;
1498       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1499       MI.eraseFromParent();
1500       return Legalized;
1501     }
1502 
1503     if (DstTy.isScalar()) {
1504       unsigned TmpReg =
1505           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
1506       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1507       switch (MI.getOpcode()) {
1508       default:
1509         llvm_unreachable("Unexpected opcode");
1510       case TargetOpcode::G_LOAD:
1511         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1512         break;
1513       case TargetOpcode::G_SEXTLOAD:
1514         MIRBuilder.buildSExt(DstReg, TmpReg);
1515         break;
1516       case TargetOpcode::G_ZEXTLOAD:
1517         MIRBuilder.buildZExt(DstReg, TmpReg);
1518         break;
1519       }
1520       MI.eraseFromParent();
1521       return Legalized;
1522     }
1523 
1524     return UnableToLegalize;
1525   }
1526   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1527   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1528   case TargetOpcode::G_CTLZ:
1529   case TargetOpcode::G_CTTZ:
1530   case TargetOpcode::G_CTPOP:
1531     return lowerBitCount(MI, TypeIdx, Ty);
1532   case G_UADDO: {
1533     unsigned Res = MI.getOperand(0).getReg();
1534     unsigned CarryOut = MI.getOperand(1).getReg();
1535     unsigned LHS = MI.getOperand(2).getReg();
1536     unsigned RHS = MI.getOperand(3).getReg();
1537 
1538     MIRBuilder.buildAdd(Res, LHS, RHS);
1539     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1540 
1541     MI.eraseFromParent();
1542     return Legalized;
1543   }
1544   case G_UADDE: {
1545     unsigned Res = MI.getOperand(0).getReg();
1546     unsigned CarryOut = MI.getOperand(1).getReg();
1547     unsigned LHS = MI.getOperand(2).getReg();
1548     unsigned RHS = MI.getOperand(3).getReg();
1549     unsigned CarryIn = MI.getOperand(4).getReg();
1550 
1551     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1552     unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1553 
1554     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1555     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1556     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1557     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1558 
1559     MI.eraseFromParent();
1560     return Legalized;
1561   }
1562   case G_USUBO: {
1563     unsigned Res = MI.getOperand(0).getReg();
1564     unsigned BorrowOut = MI.getOperand(1).getReg();
1565     unsigned LHS = MI.getOperand(2).getReg();
1566     unsigned RHS = MI.getOperand(3).getReg();
1567 
1568     MIRBuilder.buildSub(Res, LHS, RHS);
1569     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1570 
1571     MI.eraseFromParent();
1572     return Legalized;
1573   }
1574   case G_USUBE: {
1575     unsigned Res = MI.getOperand(0).getReg();
1576     unsigned BorrowOut = MI.getOperand(1).getReg();
1577     unsigned LHS = MI.getOperand(2).getReg();
1578     unsigned RHS = MI.getOperand(3).getReg();
1579     unsigned BorrowIn = MI.getOperand(4).getReg();
1580 
1581     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1582     unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1583     unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1584     unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1585 
1586     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1587     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1588     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1589     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1590     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1591     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1592 
1593     MI.eraseFromParent();
1594     return Legalized;
1595   }
1596   }
1597 }
1598 
1599 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1600     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1601   SmallVector<unsigned, 2> DstRegs;
1602 
1603   unsigned NarrowSize = NarrowTy.getSizeInBits();
1604   unsigned DstReg = MI.getOperand(0).getReg();
1605   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1606   int NumParts = Size / NarrowSize;
1607   // FIXME: Don't know how to handle the situation where the small vectors
1608   // aren't all the same size yet.
1609   if (Size % NarrowSize != 0)
1610     return UnableToLegalize;
1611 
1612   for (int i = 0; i < NumParts; ++i) {
1613     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1614     MIRBuilder.buildUndef(TmpReg);
1615     DstRegs.push_back(TmpReg);
1616   }
1617 
1618   if (NarrowTy.isVector())
1619     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1620   else
1621     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1622 
1623   MI.eraseFromParent();
1624   return Legalized;
1625 }
1626 
1627 LegalizerHelper::LegalizeResult
1628 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1629                                           LLT NarrowTy) {
1630   const unsigned Opc = MI.getOpcode();
1631   const unsigned NumOps = MI.getNumOperands() - 1;
1632   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1633   const unsigned DstReg = MI.getOperand(0).getReg();
1634   const unsigned Flags = MI.getFlags();
1635   const LLT DstTy = MRI.getType(DstReg);
1636   const unsigned Size = DstTy.getSizeInBits();
1637   const int NumParts = Size / NarrowSize;
1638   const LLT EltTy = DstTy.getElementType();
1639   const unsigned EltSize = EltTy.getSizeInBits();
1640   const unsigned BitsForNumParts = NarrowSize * NumParts;
1641 
1642   // Check if we have any leftovers. If we do, then only handle the case where
1643   // the leftover is one element.
1644   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1645     return UnableToLegalize;
1646 
1647   if (BitsForNumParts != Size) {
1648     unsigned AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1649     MIRBuilder.buildUndef(AccumDstReg);
1650 
1651     // Handle the pieces which evenly divide into the requested type with
1652     // extract/op/insert sequence.
1653     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1654       SmallVector<SrcOp, 4> SrcOps;
1655       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1656         unsigned PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1657         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1658         SrcOps.push_back(PartOpReg);
1659       }
1660 
1661       unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1662       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1663 
1664       unsigned PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1665       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1666       AccumDstReg = PartInsertReg;
1667     }
1668 
1669     // Handle the remaining element sized leftover piece.
1670     SmallVector<SrcOp, 4> SrcOps;
1671     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1672       unsigned PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1673       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1674                               BitsForNumParts);
1675       SrcOps.push_back(PartOpReg);
1676     }
1677 
1678     unsigned PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1679     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1680     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1681     MI.eraseFromParent();
1682 
1683     return Legalized;
1684   }
1685 
1686   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1687 
1688   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1689 
1690   if (NumOps >= 2)
1691     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1692 
1693   if (NumOps >= 3)
1694     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1695 
1696   for (int i = 0; i < NumParts; ++i) {
1697     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1698 
1699     if (NumOps == 1)
1700       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1701     else if (NumOps == 2) {
1702       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1703     } else if (NumOps == 3) {
1704       MIRBuilder.buildInstr(Opc, {DstReg},
1705                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1706     }
1707 
1708     DstRegs.push_back(DstReg);
1709   }
1710 
1711   if (NarrowTy.isVector())
1712     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1713   else
1714     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1715 
1716   MI.eraseFromParent();
1717   return Legalized;
1718 }
1719 
1720 // Handle splitting vector operations which need to have the same number of
1721 // elements in each type index, but each type index may have a different element
1722 // type.
1723 //
1724 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
1725 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1726 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1727 //
1728 // Also handles some irregular breakdown cases, e.g.
1729 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
1730 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1731 //             s64 = G_SHL s64, s32
1732 LegalizerHelper::LegalizeResult
1733 LegalizerHelper::fewerElementsVectorMultiEltType(
1734   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
1735   if (TypeIdx != 0)
1736     return UnableToLegalize;
1737 
1738   const LLT NarrowTy0 = NarrowTyArg;
1739   const unsigned NewNumElts =
1740       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
1741 
1742   const unsigned DstReg = MI.getOperand(0).getReg();
1743   LLT DstTy = MRI.getType(DstReg);
1744   LLT LeftoverTy0;
1745 
1746   int NumParts, NumLeftover;
1747   // All of the operands need to have the same number of elements, so if we can
1748   // determine a type breakdown for the result type, we can for all of the
1749   // source types.
1750   std::tie(NumParts, NumLeftover)
1751     = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1752   if (NumParts < 0)
1753     return UnableToLegalize;
1754 
1755   SmallVector<MachineInstrBuilder, 4> NewInsts;
1756 
1757   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
1758   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
1759 
1760   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1761     LLT LeftoverTy;
1762     unsigned SrcReg = MI.getOperand(I).getReg();
1763     LLT SrcTyI = MRI.getType(SrcReg);
1764     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
1765     LLT LeftoverTyI;
1766 
1767     // Split this operand into the requested typed registers, and any leftover
1768     // required to reproduce the original type.
1769     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
1770                       LeftoverRegs))
1771       return UnableToLegalize;
1772 
1773     if (I == 1) {
1774       // For the first operand, create an instruction for each part and setup
1775       // the result.
1776       for (unsigned PartReg : PartRegs) {
1777         unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1778         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1779                                .addDef(PartDstReg)
1780                                .addUse(PartReg));
1781         DstRegs.push_back(PartDstReg);
1782       }
1783 
1784       for (unsigned LeftoverReg : LeftoverRegs) {
1785         unsigned PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1786         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1787                                .addDef(PartDstReg)
1788                                .addUse(LeftoverReg));
1789         LeftoverDstRegs.push_back(PartDstReg);
1790       }
1791     } else {
1792       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
1793 
1794       // Add the newly created operand splits to the existing instructions. The
1795       // odd-sized pieces are ordered after the requested NarrowTyArg sized
1796       // pieces.
1797       unsigned InstCount = 0;
1798       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
1799         NewInsts[InstCount++].addUse(PartRegs[J]);
1800       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
1801         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
1802     }
1803 
1804     PartRegs.clear();
1805     LeftoverRegs.clear();
1806   }
1807 
1808   // Insert the newly built operations and rebuild the result register.
1809   for (auto &MIB : NewInsts)
1810     MIRBuilder.insertInstr(MIB);
1811 
1812   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
1813 
1814   MI.eraseFromParent();
1815   return Legalized;
1816 }
1817 
1818 LegalizerHelper::LegalizeResult
1819 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
1820                                           LLT NarrowTy) {
1821   if (TypeIdx != 0)
1822     return UnableToLegalize;
1823 
1824   unsigned DstReg = MI.getOperand(0).getReg();
1825   unsigned SrcReg = MI.getOperand(1).getReg();
1826   LLT DstTy = MRI.getType(DstReg);
1827   LLT SrcTy = MRI.getType(SrcReg);
1828 
1829   LLT NarrowTy0 = NarrowTy;
1830   LLT NarrowTy1;
1831   unsigned NumParts;
1832 
1833   if (NarrowTy.isVector()) {
1834     // Uneven breakdown not handled.
1835     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
1836     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
1837       return UnableToLegalize;
1838 
1839     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
1840   } else {
1841     NumParts = DstTy.getNumElements();
1842     NarrowTy1 = SrcTy.getElementType();
1843   }
1844 
1845   SmallVector<unsigned, 4> SrcRegs, DstRegs;
1846   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
1847 
1848   for (unsigned I = 0; I < NumParts; ++I) {
1849     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1850     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
1851       .addDef(DstReg)
1852       .addUse(SrcRegs[I]);
1853 
1854     NewInst->setFlags(MI.getFlags());
1855     DstRegs.push_back(DstReg);
1856   }
1857 
1858   if (NarrowTy.isVector())
1859     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1860   else
1861     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1862 
1863   MI.eraseFromParent();
1864   return Legalized;
1865 }
1866 
1867 LegalizerHelper::LegalizeResult
1868 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
1869                                         LLT NarrowTy) {
1870   unsigned DstReg = MI.getOperand(0).getReg();
1871   unsigned Src0Reg = MI.getOperand(2).getReg();
1872   LLT DstTy = MRI.getType(DstReg);
1873   LLT SrcTy = MRI.getType(Src0Reg);
1874 
1875   unsigned NumParts;
1876   LLT NarrowTy0, NarrowTy1;
1877 
1878   if (TypeIdx == 0) {
1879     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1880     unsigned OldElts = DstTy.getNumElements();
1881 
1882     NarrowTy0 = NarrowTy;
1883     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
1884     NarrowTy1 = NarrowTy.isVector() ?
1885       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
1886       SrcTy.getElementType();
1887 
1888   } else {
1889     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1890     unsigned OldElts = SrcTy.getNumElements();
1891 
1892     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
1893       NarrowTy.getNumElements();
1894     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
1895                             DstTy.getScalarSizeInBits());
1896     NarrowTy1 = NarrowTy;
1897   }
1898 
1899   // FIXME: Don't know how to handle the situation where the small vectors
1900   // aren't all the same size yet.
1901   if (NarrowTy1.isVector() &&
1902       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
1903     return UnableToLegalize;
1904 
1905   CmpInst::Predicate Pred
1906     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1907 
1908   SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
1909   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
1910   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
1911 
1912   for (unsigned I = 0; I < NumParts; ++I) {
1913     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1914     DstRegs.push_back(DstReg);
1915 
1916     if (MI.getOpcode() == TargetOpcode::G_ICMP)
1917       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1918     else {
1919       MachineInstr *NewCmp
1920         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1921       NewCmp->setFlags(MI.getFlags());
1922     }
1923   }
1924 
1925   if (NarrowTy1.isVector())
1926     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1927   else
1928     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1929 
1930   MI.eraseFromParent();
1931   return Legalized;
1932 }
1933 
1934 LegalizerHelper::LegalizeResult
1935 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
1936                                            LLT NarrowTy) {
1937   unsigned DstReg = MI.getOperand(0).getReg();
1938   unsigned CondReg = MI.getOperand(1).getReg();
1939 
1940   unsigned NumParts = 0;
1941   LLT NarrowTy0, NarrowTy1;
1942 
1943   LLT DstTy = MRI.getType(DstReg);
1944   LLT CondTy = MRI.getType(CondReg);
1945   unsigned Size = DstTy.getSizeInBits();
1946 
1947   assert(TypeIdx == 0 || CondTy.isVector());
1948 
1949   if (TypeIdx == 0) {
1950     NarrowTy0 = NarrowTy;
1951     NarrowTy1 = CondTy;
1952 
1953     unsigned NarrowSize = NarrowTy0.getSizeInBits();
1954     // FIXME: Don't know how to handle the situation where the small vectors
1955     // aren't all the same size yet.
1956     if (Size % NarrowSize != 0)
1957       return UnableToLegalize;
1958 
1959     NumParts = Size / NarrowSize;
1960 
1961     // Need to break down the condition type
1962     if (CondTy.isVector()) {
1963       if (CondTy.getNumElements() == NumParts)
1964         NarrowTy1 = CondTy.getElementType();
1965       else
1966         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
1967                                 CondTy.getScalarSizeInBits());
1968     }
1969   } else {
1970     NumParts = CondTy.getNumElements();
1971     if (NarrowTy.isVector()) {
1972       // TODO: Handle uneven breakdown.
1973       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
1974         return UnableToLegalize;
1975 
1976       return UnableToLegalize;
1977     } else {
1978       NarrowTy0 = DstTy.getElementType();
1979       NarrowTy1 = NarrowTy;
1980     }
1981   }
1982 
1983   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1984   if (CondTy.isVector())
1985     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
1986 
1987   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
1988   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
1989 
1990   for (unsigned i = 0; i < NumParts; ++i) {
1991     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1992     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
1993                            Src1Regs[i], Src2Regs[i]);
1994     DstRegs.push_back(DstReg);
1995   }
1996 
1997   if (NarrowTy0.isVector())
1998     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1999   else
2000     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2001 
2002   MI.eraseFromParent();
2003   return Legalized;
2004 }
2005 
2006 LegalizerHelper::LegalizeResult
2007 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2008                                         LLT NarrowTy) {
2009   const unsigned DstReg = MI.getOperand(0).getReg();
2010   LLT PhiTy = MRI.getType(DstReg);
2011   LLT LeftoverTy;
2012 
2013   // All of the operands need to have the same number of elements, so if we can
2014   // determine a type breakdown for the result type, we can for all of the
2015   // source types.
2016   int NumParts, NumLeftover;
2017   std::tie(NumParts, NumLeftover)
2018     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2019   if (NumParts < 0)
2020     return UnableToLegalize;
2021 
2022   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
2023   SmallVector<MachineInstrBuilder, 4> NewInsts;
2024 
2025   const int TotalNumParts = NumParts + NumLeftover;
2026 
2027   // Insert the new phis in the result block first.
2028   for (int I = 0; I != TotalNumParts; ++I) {
2029     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2030     unsigned PartDstReg = MRI.createGenericVirtualRegister(Ty);
2031     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2032                        .addDef(PartDstReg));
2033     if (I < NumParts)
2034       DstRegs.push_back(PartDstReg);
2035     else
2036       LeftoverDstRegs.push_back(PartDstReg);
2037   }
2038 
2039   MachineBasicBlock *MBB = MI.getParent();
2040   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2041   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2042 
2043   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
2044 
2045   // Insert code to extract the incoming values in each predecessor block.
2046   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2047     PartRegs.clear();
2048     LeftoverRegs.clear();
2049 
2050     unsigned SrcReg = MI.getOperand(I).getReg();
2051     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2052     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2053 
2054     LLT Unused;
2055     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2056                       LeftoverRegs))
2057       return UnableToLegalize;
2058 
2059     // Add the newly created operand splits to the existing instructions. The
2060     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2061     // pieces.
2062     for (int J = 0; J != TotalNumParts; ++J) {
2063       MachineInstrBuilder MIB = NewInsts[J];
2064       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2065       MIB.addMBB(&OpMBB);
2066     }
2067   }
2068 
2069   MI.eraseFromParent();
2070   return Legalized;
2071 }
2072 
2073 LegalizerHelper::LegalizeResult
2074 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2075                                       LLT NarrowTy) {
2076   // FIXME: Don't know how to handle secondary types yet.
2077   if (TypeIdx != 0)
2078     return UnableToLegalize;
2079 
2080   MachineMemOperand *MMO = *MI.memoperands_begin();
2081 
2082   // This implementation doesn't work for atomics. Give up instead of doing
2083   // something invalid.
2084   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2085       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2086     return UnableToLegalize;
2087 
2088   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2089   unsigned ValReg = MI.getOperand(0).getReg();
2090   unsigned AddrReg = MI.getOperand(1).getReg();
2091   LLT ValTy = MRI.getType(ValReg);
2092 
2093   int NumParts = -1;
2094   int NumLeftover = -1;
2095   LLT LeftoverTy;
2096   SmallVector<unsigned, 8> NarrowRegs, NarrowLeftoverRegs;
2097   if (IsLoad) {
2098     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2099   } else {
2100     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2101                      NarrowLeftoverRegs)) {
2102       NumParts = NarrowRegs.size();
2103       NumLeftover = NarrowLeftoverRegs.size();
2104     }
2105   }
2106 
2107   if (NumParts == -1)
2108     return UnableToLegalize;
2109 
2110   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2111 
2112   unsigned TotalSize = ValTy.getSizeInBits();
2113 
2114   // Split the load/store into PartTy sized pieces starting at Offset. If this
2115   // is a load, return the new registers in ValRegs. For a store, each elements
2116   // of ValRegs should be PartTy. Returns the next offset that needs to be
2117   // handled.
2118   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<unsigned> &ValRegs,
2119                              unsigned Offset) -> unsigned {
2120     MachineFunction &MF = MIRBuilder.getMF();
2121     unsigned PartSize = PartTy.getSizeInBits();
2122     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2123          Offset += PartSize, ++Idx) {
2124       unsigned ByteSize = PartSize / 8;
2125       unsigned ByteOffset = Offset / 8;
2126       unsigned NewAddrReg = 0;
2127 
2128       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2129 
2130       MachineMemOperand *NewMMO =
2131         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2132 
2133       if (IsLoad) {
2134         unsigned Dst = MRI.createGenericVirtualRegister(PartTy);
2135         ValRegs.push_back(Dst);
2136         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2137       } else {
2138         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2139       }
2140     }
2141 
2142     return Offset;
2143   };
2144 
2145   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2146 
2147   // Handle the rest of the register if this isn't an even type breakdown.
2148   if (LeftoverTy.isValid())
2149     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2150 
2151   if (IsLoad) {
2152     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2153                 LeftoverTy, NarrowLeftoverRegs);
2154   }
2155 
2156   MI.eraseFromParent();
2157   return Legalized;
2158 }
2159 
2160 LegalizerHelper::LegalizeResult
2161 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2162                                      LLT NarrowTy) {
2163   using namespace TargetOpcode;
2164 
2165   MIRBuilder.setInstr(MI);
2166   switch (MI.getOpcode()) {
2167   case G_IMPLICIT_DEF:
2168     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2169   case G_AND:
2170   case G_OR:
2171   case G_XOR:
2172   case G_ADD:
2173   case G_SUB:
2174   case G_MUL:
2175   case G_SMULH:
2176   case G_UMULH:
2177   case G_FADD:
2178   case G_FMUL:
2179   case G_FSUB:
2180   case G_FNEG:
2181   case G_FABS:
2182   case G_FCANONICALIZE:
2183   case G_FDIV:
2184   case G_FREM:
2185   case G_FMA:
2186   case G_FPOW:
2187   case G_FEXP:
2188   case G_FEXP2:
2189   case G_FLOG:
2190   case G_FLOG2:
2191   case G_FLOG10:
2192   case G_FCEIL:
2193   case G_FFLOOR:
2194   case G_FRINT:
2195   case G_INTRINSIC_ROUND:
2196   case G_INTRINSIC_TRUNC:
2197   case G_FCOS:
2198   case G_FSIN:
2199   case G_FSQRT:
2200   case G_BSWAP:
2201   case G_SDIV:
2202     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2203   case G_SHL:
2204   case G_LSHR:
2205   case G_ASHR:
2206   case G_CTLZ:
2207   case G_CTLZ_ZERO_UNDEF:
2208   case G_CTTZ:
2209   case G_CTTZ_ZERO_UNDEF:
2210   case G_CTPOP:
2211     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2212   case G_ZEXT:
2213   case G_SEXT:
2214   case G_ANYEXT:
2215   case G_FPEXT:
2216   case G_FPTRUNC:
2217   case G_SITOFP:
2218   case G_UITOFP:
2219   case G_FPTOSI:
2220   case G_FPTOUI:
2221   case G_INTTOPTR:
2222   case G_PTRTOINT:
2223   case G_ADDRSPACE_CAST:
2224     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2225   case G_ICMP:
2226   case G_FCMP:
2227     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2228   case G_SELECT:
2229     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2230   case G_PHI:
2231     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2232   case G_LOAD:
2233   case G_STORE:
2234     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2235   default:
2236     return UnableToLegalize;
2237   }
2238 }
2239 
2240 LegalizerHelper::LegalizeResult
2241 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2242                                              const LLT HalfTy, const LLT AmtTy) {
2243 
2244   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2245   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2246   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2247 
2248   if (Amt.isNullValue()) {
2249     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2250     MI.eraseFromParent();
2251     return Legalized;
2252   }
2253 
2254   LLT NVT = HalfTy;
2255   unsigned NVTBits = HalfTy.getSizeInBits();
2256   unsigned VTBits = 2 * NVTBits;
2257 
2258   SrcOp Lo(0), Hi(0);
2259   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2260     if (Amt.ugt(VTBits)) {
2261       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2262     } else if (Amt.ugt(NVTBits)) {
2263       Lo = MIRBuilder.buildConstant(NVT, 0);
2264       Hi = MIRBuilder.buildShl(NVT, InL,
2265                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2266     } else if (Amt == NVTBits) {
2267       Lo = MIRBuilder.buildConstant(NVT, 0);
2268       Hi = InL;
2269     } else {
2270       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2271       auto OrLHS =
2272           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2273       auto OrRHS = MIRBuilder.buildLShr(
2274           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2275       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2276     }
2277   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2278     if (Amt.ugt(VTBits)) {
2279       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2280     } else if (Amt.ugt(NVTBits)) {
2281       Lo = MIRBuilder.buildLShr(NVT, InH,
2282                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2283       Hi = MIRBuilder.buildConstant(NVT, 0);
2284     } else if (Amt == NVTBits) {
2285       Lo = InH;
2286       Hi = MIRBuilder.buildConstant(NVT, 0);
2287     } else {
2288       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2289 
2290       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2291       auto OrRHS = MIRBuilder.buildShl(
2292           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2293 
2294       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2295       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2296     }
2297   } else {
2298     if (Amt.ugt(VTBits)) {
2299       Hi = Lo = MIRBuilder.buildAShr(
2300           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2301     } else if (Amt.ugt(NVTBits)) {
2302       Lo = MIRBuilder.buildAShr(NVT, InH,
2303                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2304       Hi = MIRBuilder.buildAShr(NVT, InH,
2305                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2306     } else if (Amt == NVTBits) {
2307       Lo = InH;
2308       Hi = MIRBuilder.buildAShr(NVT, InH,
2309                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2310     } else {
2311       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2312 
2313       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2314       auto OrRHS = MIRBuilder.buildShl(
2315           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2316 
2317       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2318       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2319     }
2320   }
2321 
2322   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2323   MI.eraseFromParent();
2324 
2325   return Legalized;
2326 }
2327 
2328 // TODO: Optimize if constant shift amount.
2329 LegalizerHelper::LegalizeResult
2330 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2331                                    LLT RequestedTy) {
2332   if (TypeIdx == 1) {
2333     Observer.changingInstr(MI);
2334     narrowScalarSrc(MI, RequestedTy, 2);
2335     Observer.changedInstr(MI);
2336     return Legalized;
2337   }
2338 
2339   unsigned DstReg = MI.getOperand(0).getReg();
2340   LLT DstTy = MRI.getType(DstReg);
2341   if (DstTy.isVector())
2342     return UnableToLegalize;
2343 
2344   unsigned Amt = MI.getOperand(2).getReg();
2345   LLT ShiftAmtTy = MRI.getType(Amt);
2346   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2347   if (DstEltSize % 2 != 0)
2348     return UnableToLegalize;
2349 
2350   // Ignore the input type. We can only go to exactly half the size of the
2351   // input. If that isn't small enough, the resulting pieces will be further
2352   // legalized.
2353   const unsigned NewBitSize = DstEltSize / 2;
2354   const LLT HalfTy = LLT::scalar(NewBitSize);
2355   const LLT CondTy = LLT::scalar(1);
2356 
2357   if (const MachineInstr *KShiftAmt =
2358           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2359     return narrowScalarShiftByConstant(
2360         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2361   }
2362 
2363   // TODO: Expand with known bits.
2364 
2365   // Handle the fully general expansion by an unknown amount.
2366   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2367 
2368   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2369   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2370   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2371 
2372   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2373   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2374 
2375   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2376   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2377   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2378 
2379   unsigned ResultRegs[2];
2380   switch (MI.getOpcode()) {
2381   case TargetOpcode::G_SHL: {
2382     // Short: ShAmt < NewBitSize
2383     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2384 
2385     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2386     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2387     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2388 
2389     // Long: ShAmt >= NewBitSize
2390     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2391     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2392 
2393     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2394     auto Hi = MIRBuilder.buildSelect(
2395         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2396 
2397     ResultRegs[0] = Lo.getReg(0);
2398     ResultRegs[1] = Hi.getReg(0);
2399     break;
2400   }
2401   case TargetOpcode::G_LSHR: {
2402     // Short: ShAmt < NewBitSize
2403     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2404 
2405     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2406     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2407     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2408 
2409     // Long: ShAmt >= NewBitSize
2410     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2411     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2412 
2413     auto Lo = MIRBuilder.buildSelect(
2414         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2415     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2416 
2417     ResultRegs[0] = Lo.getReg(0);
2418     ResultRegs[1] = Hi.getReg(0);
2419     break;
2420   }
2421   case TargetOpcode::G_ASHR: {
2422     // Short: ShAmt < NewBitSize
2423     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2424 
2425     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2426     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2427     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2428 
2429     // Long: ShAmt >= NewBitSize
2430 
2431     // Sign of Hi part.
2432     auto HiL = MIRBuilder.buildAShr(
2433         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2434 
2435     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2436 
2437     auto Lo = MIRBuilder.buildSelect(
2438         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2439 
2440     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2441 
2442     ResultRegs[0] = Lo.getReg(0);
2443     ResultRegs[1] = Hi.getReg(0);
2444     break;
2445   }
2446   default:
2447     llvm_unreachable("not a shift");
2448   }
2449 
2450   MIRBuilder.buildMerge(DstReg, ResultRegs);
2451   MI.eraseFromParent();
2452   return Legalized;
2453 }
2454 
2455 LegalizerHelper::LegalizeResult
2456 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2457                                        LLT MoreTy) {
2458   assert(TypeIdx == 0 && "Expecting only Idx 0");
2459 
2460   Observer.changingInstr(MI);
2461   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2462     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2463     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2464     moreElementsVectorSrc(MI, MoreTy, I);
2465   }
2466 
2467   MachineBasicBlock &MBB = *MI.getParent();
2468   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2469   moreElementsVectorDst(MI, MoreTy, 0);
2470   Observer.changedInstr(MI);
2471   return Legalized;
2472 }
2473 
2474 LegalizerHelper::LegalizeResult
2475 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2476                                     LLT MoreTy) {
2477   MIRBuilder.setInstr(MI);
2478   unsigned Opc = MI.getOpcode();
2479   switch (Opc) {
2480   case TargetOpcode::G_IMPLICIT_DEF: {
2481     Observer.changingInstr(MI);
2482     moreElementsVectorDst(MI, MoreTy, 0);
2483     Observer.changedInstr(MI);
2484     return Legalized;
2485   }
2486   case TargetOpcode::G_AND:
2487   case TargetOpcode::G_OR:
2488   case TargetOpcode::G_XOR: {
2489     Observer.changingInstr(MI);
2490     moreElementsVectorSrc(MI, MoreTy, 1);
2491     moreElementsVectorSrc(MI, MoreTy, 2);
2492     moreElementsVectorDst(MI, MoreTy, 0);
2493     Observer.changedInstr(MI);
2494     return Legalized;
2495   }
2496   case TargetOpcode::G_EXTRACT:
2497     if (TypeIdx != 1)
2498       return UnableToLegalize;
2499     Observer.changingInstr(MI);
2500     moreElementsVectorSrc(MI, MoreTy, 1);
2501     Observer.changedInstr(MI);
2502     return Legalized;
2503   case TargetOpcode::G_INSERT:
2504     if (TypeIdx != 0)
2505       return UnableToLegalize;
2506     Observer.changingInstr(MI);
2507     moreElementsVectorSrc(MI, MoreTy, 1);
2508     moreElementsVectorDst(MI, MoreTy, 0);
2509     Observer.changedInstr(MI);
2510     return Legalized;
2511   case TargetOpcode::G_SELECT:
2512     if (TypeIdx != 0)
2513       return UnableToLegalize;
2514     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2515       return UnableToLegalize;
2516 
2517     Observer.changingInstr(MI);
2518     moreElementsVectorSrc(MI, MoreTy, 2);
2519     moreElementsVectorSrc(MI, MoreTy, 3);
2520     moreElementsVectorDst(MI, MoreTy, 0);
2521     Observer.changedInstr(MI);
2522     return Legalized;
2523   case TargetOpcode::G_PHI:
2524     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2525   default:
2526     return UnableToLegalize;
2527   }
2528 }
2529 
2530 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<unsigned> &DstRegs,
2531                                         ArrayRef<unsigned> Src1Regs,
2532                                         ArrayRef<unsigned> Src2Regs,
2533                                         LLT NarrowTy) {
2534   MachineIRBuilder &B = MIRBuilder;
2535   unsigned SrcParts = Src1Regs.size();
2536   unsigned DstParts = DstRegs.size();
2537 
2538   unsigned DstIdx = 0; // Low bits of the result.
2539   unsigned FactorSum =
2540       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
2541   DstRegs[DstIdx] = FactorSum;
2542 
2543   unsigned CarrySumPrevDstIdx;
2544   SmallVector<unsigned, 4> Factors;
2545 
2546   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
2547     // Collect low parts of muls for DstIdx.
2548     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
2549          i <= std::min(DstIdx, SrcParts - 1); ++i) {
2550       MachineInstrBuilder Mul =
2551           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
2552       Factors.push_back(Mul.getReg(0));
2553     }
2554     // Collect high parts of muls from previous DstIdx.
2555     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
2556          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
2557       MachineInstrBuilder Umulh =
2558           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
2559       Factors.push_back(Umulh.getReg(0));
2560     }
2561     // Add CarrySum from additons calculated for previous DstIdx.
2562     if (DstIdx != 1) {
2563       Factors.push_back(CarrySumPrevDstIdx);
2564     }
2565 
2566     unsigned CarrySum = 0;
2567     // Add all factors and accumulate all carries into CarrySum.
2568     if (DstIdx != DstParts - 1) {
2569       MachineInstrBuilder Uaddo =
2570           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
2571       FactorSum = Uaddo.getReg(0);
2572       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
2573       for (unsigned i = 2; i < Factors.size(); ++i) {
2574         MachineInstrBuilder Uaddo =
2575             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
2576         FactorSum = Uaddo.getReg(0);
2577         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
2578         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
2579       }
2580     } else {
2581       // Since value for the next index is not calculated, neither is CarrySum.
2582       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
2583       for (unsigned i = 2; i < Factors.size(); ++i)
2584         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
2585     }
2586 
2587     CarrySumPrevDstIdx = CarrySum;
2588     DstRegs[DstIdx] = FactorSum;
2589     Factors.clear();
2590   }
2591 }
2592 
2593 LegalizerHelper::LegalizeResult
2594 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
2595   unsigned DstReg = MI.getOperand(0).getReg();
2596   unsigned Src1 = MI.getOperand(1).getReg();
2597   unsigned Src2 = MI.getOperand(2).getReg();
2598 
2599   LLT Ty = MRI.getType(DstReg);
2600   if (Ty.isVector())
2601     return UnableToLegalize;
2602 
2603   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
2604   unsigned DstSize = Ty.getSizeInBits();
2605   unsigned NarrowSize = NarrowTy.getSizeInBits();
2606   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
2607     return UnableToLegalize;
2608 
2609   unsigned NumDstParts = DstSize / NarrowSize;
2610   unsigned NumSrcParts = SrcSize / NarrowSize;
2611   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
2612   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
2613 
2614   SmallVector<unsigned, 2> Src1Parts, Src2Parts, DstTmpRegs;
2615   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
2616   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
2617   DstTmpRegs.resize(DstTmpParts);
2618   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
2619 
2620   // Take only high half of registers if this is high mul.
2621   ArrayRef<unsigned> DstRegs(
2622       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
2623   MIRBuilder.buildMerge(DstReg, DstRegs);
2624   MI.eraseFromParent();
2625   return Legalized;
2626 }
2627 
2628 LegalizerHelper::LegalizeResult
2629 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2630                                      LLT NarrowTy) {
2631   if (TypeIdx != 1)
2632     return UnableToLegalize;
2633 
2634   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2635 
2636   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2637   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2638   // NarrowSize.
2639   if (SizeOp1 % NarrowSize != 0)
2640     return UnableToLegalize;
2641   int NumParts = SizeOp1 / NarrowSize;
2642 
2643   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2644   SmallVector<uint64_t, 2> Indexes;
2645   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2646 
2647   unsigned OpReg = MI.getOperand(0).getReg();
2648   uint64_t OpStart = MI.getOperand(2).getImm();
2649   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2650   for (int i = 0; i < NumParts; ++i) {
2651     unsigned SrcStart = i * NarrowSize;
2652 
2653     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2654       // No part of the extract uses this subregister, ignore it.
2655       continue;
2656     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2657       // The entire subregister is extracted, forward the value.
2658       DstRegs.push_back(SrcRegs[i]);
2659       continue;
2660     }
2661 
2662     // OpSegStart is where this destination segment would start in OpReg if it
2663     // extended infinitely in both directions.
2664     int64_t ExtractOffset;
2665     uint64_t SegSize;
2666     if (OpStart < SrcStart) {
2667       ExtractOffset = 0;
2668       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2669     } else {
2670       ExtractOffset = OpStart - SrcStart;
2671       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2672     }
2673 
2674     unsigned SegReg = SrcRegs[i];
2675     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2676       // A genuine extract is needed.
2677       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2678       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2679     }
2680 
2681     DstRegs.push_back(SegReg);
2682   }
2683 
2684   unsigned DstReg = MI.getOperand(0).getReg();
2685   if(MRI.getType(DstReg).isVector())
2686     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2687   else
2688     MIRBuilder.buildMerge(DstReg, DstRegs);
2689   MI.eraseFromParent();
2690   return Legalized;
2691 }
2692 
2693 LegalizerHelper::LegalizeResult
2694 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2695                                     LLT NarrowTy) {
2696   // FIXME: Don't know how to handle secondary types yet.
2697   if (TypeIdx != 0)
2698     return UnableToLegalize;
2699 
2700   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2701   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2702 
2703   // FIXME: add support for when SizeOp0 isn't an exact multiple of
2704   // NarrowSize.
2705   if (SizeOp0 % NarrowSize != 0)
2706     return UnableToLegalize;
2707 
2708   int NumParts = SizeOp0 / NarrowSize;
2709 
2710   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2711   SmallVector<uint64_t, 2> Indexes;
2712   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2713 
2714   unsigned OpReg = MI.getOperand(2).getReg();
2715   uint64_t OpStart = MI.getOperand(3).getImm();
2716   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2717   for (int i = 0; i < NumParts; ++i) {
2718     unsigned DstStart = i * NarrowSize;
2719 
2720     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
2721       // No part of the insert affects this subregister, forward the original.
2722       DstRegs.push_back(SrcRegs[i]);
2723       continue;
2724     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2725       // The entire subregister is defined by this insert, forward the new
2726       // value.
2727       DstRegs.push_back(OpReg);
2728       continue;
2729     }
2730 
2731     // OpSegStart is where this destination segment would start in OpReg if it
2732     // extended infinitely in both directions.
2733     int64_t ExtractOffset, InsertOffset;
2734     uint64_t SegSize;
2735     if (OpStart < DstStart) {
2736       InsertOffset = 0;
2737       ExtractOffset = DstStart - OpStart;
2738       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
2739     } else {
2740       InsertOffset = OpStart - DstStart;
2741       ExtractOffset = 0;
2742       SegSize =
2743         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
2744     }
2745 
2746     unsigned SegReg = OpReg;
2747     if (ExtractOffset != 0 || SegSize != OpSize) {
2748       // A genuine extract is needed.
2749       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2750       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
2751     }
2752 
2753     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2754     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
2755     DstRegs.push_back(DstReg);
2756   }
2757 
2758   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2759   unsigned DstReg = MI.getOperand(0).getReg();
2760   if(MRI.getType(DstReg).isVector())
2761     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2762   else
2763     MIRBuilder.buildMerge(DstReg, DstRegs);
2764   MI.eraseFromParent();
2765   return Legalized;
2766 }
2767 
2768 LegalizerHelper::LegalizeResult
2769 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
2770                                    LLT NarrowTy) {
2771   unsigned DstReg = MI.getOperand(0).getReg();
2772   LLT DstTy = MRI.getType(DstReg);
2773 
2774   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
2775 
2776   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2777   SmallVector<unsigned, 4> Src0Regs, Src0LeftoverRegs;
2778   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2779   LLT LeftoverTy;
2780   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
2781                     Src0Regs, Src0LeftoverRegs))
2782     return UnableToLegalize;
2783 
2784   LLT Unused;
2785   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
2786                     Src1Regs, Src1LeftoverRegs))
2787     llvm_unreachable("inconsistent extractParts result");
2788 
2789   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2790     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
2791                                         {Src0Regs[I], Src1Regs[I]});
2792     DstRegs.push_back(Inst->getOperand(0).getReg());
2793   }
2794 
2795   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2796     auto Inst = MIRBuilder.buildInstr(
2797       MI.getOpcode(),
2798       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
2799     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
2800   }
2801 
2802   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2803               LeftoverTy, DstLeftoverRegs);
2804 
2805   MI.eraseFromParent();
2806   return Legalized;
2807 }
2808 
2809 LegalizerHelper::LegalizeResult
2810 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
2811                                     LLT NarrowTy) {
2812   if (TypeIdx != 0)
2813     return UnableToLegalize;
2814 
2815   unsigned CondReg = MI.getOperand(1).getReg();
2816   LLT CondTy = MRI.getType(CondReg);
2817   if (CondTy.isVector()) // TODO: Handle vselect
2818     return UnableToLegalize;
2819 
2820   unsigned DstReg = MI.getOperand(0).getReg();
2821   LLT DstTy = MRI.getType(DstReg);
2822 
2823   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2824   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2825   SmallVector<unsigned, 4> Src2Regs, Src2LeftoverRegs;
2826   LLT LeftoverTy;
2827   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
2828                     Src1Regs, Src1LeftoverRegs))
2829     return UnableToLegalize;
2830 
2831   LLT Unused;
2832   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
2833                     Src2Regs, Src2LeftoverRegs))
2834     llvm_unreachable("inconsistent extractParts result");
2835 
2836   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2837     auto Select = MIRBuilder.buildSelect(NarrowTy,
2838                                          CondReg, Src1Regs[I], Src2Regs[I]);
2839     DstRegs.push_back(Select->getOperand(0).getReg());
2840   }
2841 
2842   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2843     auto Select = MIRBuilder.buildSelect(
2844       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
2845     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
2846   }
2847 
2848   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2849               LeftoverTy, DstLeftoverRegs);
2850 
2851   MI.eraseFromParent();
2852   return Legalized;
2853 }
2854 
2855 LegalizerHelper::LegalizeResult
2856 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2857   unsigned Opc = MI.getOpcode();
2858   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2859   auto isSupported = [this](const LegalityQuery &Q) {
2860     auto QAction = LI.getAction(Q).Action;
2861     return QAction == Legal || QAction == Libcall || QAction == Custom;
2862   };
2863   switch (Opc) {
2864   default:
2865     return UnableToLegalize;
2866   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
2867     // This trivially expands to CTLZ.
2868     Observer.changingInstr(MI);
2869     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
2870     Observer.changedInstr(MI);
2871     return Legalized;
2872   }
2873   case TargetOpcode::G_CTLZ: {
2874     unsigned SrcReg = MI.getOperand(1).getReg();
2875     unsigned Len = Ty.getSizeInBits();
2876     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
2877       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
2878       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
2879                                              {Ty}, {SrcReg});
2880       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2881       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2882       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2883                                           SrcReg, MIBZero);
2884       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2885                              MIBCtlzZU);
2886       MI.eraseFromParent();
2887       return Legalized;
2888     }
2889     // for now, we do this:
2890     // NewLen = NextPowerOf2(Len);
2891     // x = x | (x >> 1);
2892     // x = x | (x >> 2);
2893     // ...
2894     // x = x | (x >>16);
2895     // x = x | (x >>32); // for 64-bit input
2896     // Upto NewLen/2
2897     // return Len - popcount(x);
2898     //
2899     // Ref: "Hacker's Delight" by Henry Warren
2900     unsigned Op = SrcReg;
2901     unsigned NewLen = PowerOf2Ceil(Len);
2902     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
2903       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
2904       auto MIBOp = MIRBuilder.buildInstr(
2905           TargetOpcode::G_OR, {Ty},
2906           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
2907                                      {Op, MIBShiftAmt})});
2908       Op = MIBOp->getOperand(0).getReg();
2909     }
2910     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
2911     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2912                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
2913     MI.eraseFromParent();
2914     return Legalized;
2915   }
2916   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
2917     // This trivially expands to CTTZ.
2918     Observer.changingInstr(MI);
2919     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
2920     Observer.changedInstr(MI);
2921     return Legalized;
2922   }
2923   case TargetOpcode::G_CTTZ: {
2924     unsigned SrcReg = MI.getOperand(1).getReg();
2925     unsigned Len = Ty.getSizeInBits();
2926     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
2927       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
2928       // zero.
2929       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
2930                                              {Ty}, {SrcReg});
2931       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2932       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2933       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2934                                           SrcReg, MIBZero);
2935       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2936                              MIBCttzZU);
2937       MI.eraseFromParent();
2938       return Legalized;
2939     }
2940     // for now, we use: { return popcount(~x & (x - 1)); }
2941     // unless the target has ctlz but not ctpop, in which case we use:
2942     // { return 32 - nlz(~x & (x-1)); }
2943     // Ref: "Hacker's Delight" by Henry Warren
2944     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
2945     auto MIBNot =
2946         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
2947     auto MIBTmp = MIRBuilder.buildInstr(
2948         TargetOpcode::G_AND, {Ty},
2949         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
2950                                        {SrcReg, MIBCstNeg1})});
2951     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
2952         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
2953       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
2954       MIRBuilder.buildInstr(
2955           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2956           {MIBCstLen,
2957            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
2958       MI.eraseFromParent();
2959       return Legalized;
2960     }
2961     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
2962     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
2963     return Legalized;
2964   }
2965   }
2966 }
2967