1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
67                                  GISelChangeObserver &Observer,
68                                  MachineIRBuilder &Builder)
69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
70       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
71   MIRBuilder.setMF(MF);
72   MIRBuilder.setChangeObserver(Observer);
73 }
74 
75 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
76                                  GISelChangeObserver &Observer,
77                                  MachineIRBuilder &B)
78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
79   MIRBuilder.setMF(MF);
80   MIRBuilder.setChangeObserver(Observer);
81 }
82 LegalizerHelper::LegalizeResult
83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
84   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
85 
86   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
87       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
88     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
89                                                      : UnableToLegalize;
90   auto Step = LI.getAction(MI, MRI);
91   switch (Step.Action) {
92   case Legal:
93     LLVM_DEBUG(dbgs() << ".. Already legal\n");
94     return AlreadyLegal;
95   case Libcall:
96     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
97     return libcall(MI);
98   case NarrowScalar:
99     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
100     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
101   case WidenScalar:
102     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
103     return widenScalar(MI, Step.TypeIdx, Step.NewType);
104   case Lower:
105     LLVM_DEBUG(dbgs() << ".. Lower\n");
106     return lower(MI, Step.TypeIdx, Step.NewType);
107   case FewerElements:
108     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
109     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
110   case MoreElements:
111     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
112     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
113   case Custom:
114     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
115     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
116                                                             : UnableToLegalize;
117   default:
118     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
119     return UnableToLegalize;
120   }
121 }
122 
123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124                                    SmallVectorImpl<Register> &VRegs) {
125   for (int i = 0; i < NumParts; ++i)
126     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
127   MIRBuilder.buildUnmerge(VRegs, Reg);
128 }
129 
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
131                                    LLT MainTy, LLT &LeftoverTy,
132                                    SmallVectorImpl<Register> &VRegs,
133                                    SmallVectorImpl<Register> &LeftoverRegs) {
134   assert(!LeftoverTy.isValid() && "this is an out argument");
135 
136   unsigned RegSize = RegTy.getSizeInBits();
137   unsigned MainSize = MainTy.getSizeInBits();
138   unsigned NumParts = RegSize / MainSize;
139   unsigned LeftoverSize = RegSize - NumParts * MainSize;
140 
141   // Use an unmerge when possible.
142   if (LeftoverSize == 0) {
143     for (unsigned I = 0; I < NumParts; ++I)
144       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
145     MIRBuilder.buildUnmerge(VRegs, Reg);
146     return true;
147   }
148 
149   if (MainTy.isVector()) {
150     unsigned EltSize = MainTy.getScalarSizeInBits();
151     if (LeftoverSize % EltSize != 0)
152       return false;
153     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
154   } else {
155     LeftoverTy = LLT::scalar(LeftoverSize);
156   }
157 
158   // For irregular sizes, extract the individual parts.
159   for (unsigned I = 0; I != NumParts; ++I) {
160     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
161     VRegs.push_back(NewReg);
162     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
163   }
164 
165   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
166        Offset += LeftoverSize) {
167     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
168     LeftoverRegs.push_back(NewReg);
169     MIRBuilder.buildExtract(NewReg, Reg, Offset);
170   }
171 
172   return true;
173 }
174 
175 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
176   if (OrigTy.isVector() && TargetTy.isVector()) {
177     assert(OrigTy.getElementType() == TargetTy.getElementType());
178     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
179                                     TargetTy.getNumElements());
180     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
181   }
182 
183   if (OrigTy.isVector() && !TargetTy.isVector()) {
184     assert(OrigTy.getElementType() == TargetTy);
185     return TargetTy;
186   }
187 
188   assert(!OrigTy.isVector() && !TargetTy.isVector());
189 
190   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
191                                   TargetTy.getSizeInBits());
192   return LLT::scalar(GCD);
193 }
194 
195 void LegalizerHelper::insertParts(Register DstReg,
196                                   LLT ResultTy, LLT PartTy,
197                                   ArrayRef<Register> PartRegs,
198                                   LLT LeftoverTy,
199                                   ArrayRef<Register> LeftoverRegs) {
200   if (!LeftoverTy.isValid()) {
201     assert(LeftoverRegs.empty());
202 
203     if (!ResultTy.isVector()) {
204       MIRBuilder.buildMerge(DstReg, PartRegs);
205       return;
206     }
207 
208     if (PartTy.isVector())
209       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
210     else
211       MIRBuilder.buildBuildVector(DstReg, PartRegs);
212     return;
213   }
214 
215   unsigned PartSize = PartTy.getSizeInBits();
216   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
217 
218   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
219   MIRBuilder.buildUndef(CurResultReg);
220 
221   unsigned Offset = 0;
222   for (Register PartReg : PartRegs) {
223     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
224     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
225     CurResultReg = NewResultReg;
226     Offset += PartSize;
227   }
228 
229   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
230     // Use the original output register for the final insert to avoid a copy.
231     Register NewResultReg = (I + 1 == E) ?
232       DstReg : MRI.createGenericVirtualRegister(ResultTy);
233 
234     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
235     CurResultReg = NewResultReg;
236     Offset += LeftoverPartSize;
237   }
238 }
239 
240 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
241   switch (Opcode) {
242   case TargetOpcode::G_SDIV:
243     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
244     switch (Size) {
245     case 32:
246       return RTLIB::SDIV_I32;
247     case 64:
248       return RTLIB::SDIV_I64;
249     case 128:
250       return RTLIB::SDIV_I128;
251     default:
252       llvm_unreachable("unexpected size");
253     }
254   case TargetOpcode::G_UDIV:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     switch (Size) {
257     case 32:
258       return RTLIB::UDIV_I32;
259     case 64:
260       return RTLIB::UDIV_I64;
261     case 128:
262       return RTLIB::UDIV_I128;
263     default:
264       llvm_unreachable("unexpected size");
265     }
266   case TargetOpcode::G_SREM:
267     assert((Size == 32 || Size == 64) && "Unsupported size");
268     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
269   case TargetOpcode::G_UREM:
270     assert((Size == 32 || Size == 64) && "Unsupported size");
271     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
272   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
273     assert(Size == 32 && "Unsupported size");
274     return RTLIB::CTLZ_I32;
275   case TargetOpcode::G_FADD:
276     assert((Size == 32 || Size == 64) && "Unsupported size");
277     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
278   case TargetOpcode::G_FSUB:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
281   case TargetOpcode::G_FMUL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
284   case TargetOpcode::G_FDIV:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
287   case TargetOpcode::G_FEXP:
288     assert((Size == 32 || Size == 64) && "Unsupported size");
289     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
290   case TargetOpcode::G_FEXP2:
291     assert((Size == 32 || Size == 64) && "Unsupported size");
292     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
293   case TargetOpcode::G_FREM:
294     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
295   case TargetOpcode::G_FPOW:
296     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
297   case TargetOpcode::G_FMA:
298     assert((Size == 32 || Size == 64) && "Unsupported size");
299     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
300   case TargetOpcode::G_FSIN:
301     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
302     return Size == 128 ? RTLIB::SIN_F128
303                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
304   case TargetOpcode::G_FCOS:
305     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
306     return Size == 128 ? RTLIB::COS_F128
307                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
308   case TargetOpcode::G_FLOG10:
309     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
310     return Size == 128 ? RTLIB::LOG10_F128
311                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
312   case TargetOpcode::G_FLOG:
313     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
314     return Size == 128 ? RTLIB::LOG_F128
315                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
316   case TargetOpcode::G_FLOG2:
317     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
318     return Size == 128 ? RTLIB::LOG2_F128
319                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
320   case TargetOpcode::G_FCEIL:
321     assert((Size == 32 || Size == 64) && "Unsupported size");
322     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
323   case TargetOpcode::G_FFLOOR:
324     assert((Size == 32 || Size == 64) && "Unsupported size");
325     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
326   }
327   llvm_unreachable("Unknown libcall function");
328 }
329 
330 /// True if an instruction is in tail position in its caller. Intended for
331 /// legalizing libcalls as tail calls when possible.
332 static bool isLibCallInTailPosition(MachineInstr &MI) {
333   const Function &F = MI.getParent()->getParent()->getFunction();
334 
335   // Conservatively require the attributes of the call to match those of
336   // the return. Ignore NoAlias and NonNull because they don't affect the
337   // call sequence.
338   AttributeList CallerAttrs = F.getAttributes();
339   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
340           .removeAttribute(Attribute::NoAlias)
341           .removeAttribute(Attribute::NonNull)
342           .hasAttributes())
343     return false;
344 
345   // It's not safe to eliminate the sign / zero extension of the return value.
346   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
347       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
348     return false;
349 
350   // Only tail call if the following instruction is a standard return.
351   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
352   MachineInstr *Next = MI.getNextNode();
353   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
354     return false;
355 
356   return true;
357 }
358 
359 LegalizerHelper::LegalizeResult
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
361                     const CallLowering::ArgInfo &Result,
362                     ArrayRef<CallLowering::ArgInfo> Args) {
363   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
365   const char *Name = TLI.getLibcallName(Libcall);
366 
367   CallLowering::CallLoweringInfo Info;
368   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
369   Info.Callee = MachineOperand::CreateES(Name);
370   Info.OrigRet = Result;
371   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
372   if (!CLI.lowerCall(MIRBuilder, Info))
373     return LegalizerHelper::UnableToLegalize;
374 
375   return LegalizerHelper::Legalized;
376 }
377 
378 // Useful for libcalls where all operands have the same type.
379 static LegalizerHelper::LegalizeResult
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
381               Type *OpType) {
382   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
383 
384   SmallVector<CallLowering::ArgInfo, 3> Args;
385   for (unsigned i = 1; i < MI.getNumOperands(); i++)
386     Args.push_back({MI.getOperand(i).getReg(), OpType});
387   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
388                        Args);
389 }
390 
391 LegalizerHelper::LegalizeResult
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
393                        MachineInstr &MI) {
394   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
395   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
396 
397   SmallVector<CallLowering::ArgInfo, 3> Args;
398   // Add all the args, except for the last which is an imm denoting 'tail'.
399   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
400     Register Reg = MI.getOperand(i).getReg();
401 
402     // Need derive an IR type for call lowering.
403     LLT OpLLT = MRI.getType(Reg);
404     Type *OpTy = nullptr;
405     if (OpLLT.isPointer())
406       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
407     else
408       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
409     Args.push_back({Reg, OpTy});
410   }
411 
412   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
414   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
415   RTLIB::Libcall RTLibcall;
416   switch (ID) {
417   case Intrinsic::memcpy:
418     RTLibcall = RTLIB::MEMCPY;
419     break;
420   case Intrinsic::memset:
421     RTLibcall = RTLIB::MEMSET;
422     break;
423   case Intrinsic::memmove:
424     RTLibcall = RTLIB::MEMMOVE;
425     break;
426   default:
427     return LegalizerHelper::UnableToLegalize;
428   }
429   const char *Name = TLI.getLibcallName(RTLibcall);
430 
431   MIRBuilder.setInstr(MI);
432 
433   CallLowering::CallLoweringInfo Info;
434   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
435   Info.Callee = MachineOperand::CreateES(Name);
436   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
437   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
438                     isLibCallInTailPosition(MI);
439 
440   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
441   if (!CLI.lowerCall(MIRBuilder, Info))
442     return LegalizerHelper::UnableToLegalize;
443 
444   if (Info.LoweredTailCall) {
445     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
446     // We must have a return following the call to get past
447     // isLibCallInTailPosition.
448     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
449            "Expected instr following MI to be a return?");
450 
451     // We lowered a tail call, so the call is now the return from the block.
452     // Delete the old return.
453     MI.getNextNode()->eraseFromParent();
454   }
455 
456   return LegalizerHelper::Legalized;
457 }
458 
459 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
460                                        Type *FromType) {
461   auto ToMVT = MVT::getVT(ToType);
462   auto FromMVT = MVT::getVT(FromType);
463 
464   switch (Opcode) {
465   case TargetOpcode::G_FPEXT:
466     return RTLIB::getFPEXT(FromMVT, ToMVT);
467   case TargetOpcode::G_FPTRUNC:
468     return RTLIB::getFPROUND(FromMVT, ToMVT);
469   case TargetOpcode::G_FPTOSI:
470     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
471   case TargetOpcode::G_FPTOUI:
472     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
473   case TargetOpcode::G_SITOFP:
474     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
475   case TargetOpcode::G_UITOFP:
476     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
477   }
478   llvm_unreachable("Unsupported libcall function");
479 }
480 
481 static LegalizerHelper::LegalizeResult
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
483                   Type *FromType) {
484   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
485   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486                        {{MI.getOperand(1).getReg(), FromType}});
487 }
488 
489 LegalizerHelper::LegalizeResult
490 LegalizerHelper::libcall(MachineInstr &MI) {
491   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
492   unsigned Size = LLTy.getSizeInBits();
493   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
494 
495   MIRBuilder.setInstr(MI);
496 
497   switch (MI.getOpcode()) {
498   default:
499     return UnableToLegalize;
500   case TargetOpcode::G_SDIV:
501   case TargetOpcode::G_UDIV:
502   case TargetOpcode::G_SREM:
503   case TargetOpcode::G_UREM:
504   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
505     Type *HLTy = IntegerType::get(Ctx, Size);
506     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
507     if (Status != Legalized)
508       return Status;
509     break;
510   }
511   case TargetOpcode::G_FADD:
512   case TargetOpcode::G_FSUB:
513   case TargetOpcode::G_FMUL:
514   case TargetOpcode::G_FDIV:
515   case TargetOpcode::G_FMA:
516   case TargetOpcode::G_FPOW:
517   case TargetOpcode::G_FREM:
518   case TargetOpcode::G_FCOS:
519   case TargetOpcode::G_FSIN:
520   case TargetOpcode::G_FLOG10:
521   case TargetOpcode::G_FLOG:
522   case TargetOpcode::G_FLOG2:
523   case TargetOpcode::G_FEXP:
524   case TargetOpcode::G_FEXP2:
525   case TargetOpcode::G_FCEIL:
526   case TargetOpcode::G_FFLOOR: {
527     if (Size > 64) {
528       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
529       return UnableToLegalize;
530     }
531     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
532     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
533     if (Status != Legalized)
534       return Status;
535     break;
536   }
537   case TargetOpcode::G_FPEXT: {
538     // FIXME: Support other floating point types (half, fp128 etc)
539     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
541     if (ToSize != 64 || FromSize != 32)
542       return UnableToLegalize;
543     LegalizeResult Status = conversionLibcall(
544         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
545     if (Status != Legalized)
546       return Status;
547     break;
548   }
549   case TargetOpcode::G_FPTRUNC: {
550     // FIXME: Support other floating point types (half, fp128 etc)
551     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
553     if (ToSize != 32 || FromSize != 64)
554       return UnableToLegalize;
555     LegalizeResult Status = conversionLibcall(
556         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
557     if (Status != Legalized)
558       return Status;
559     break;
560   }
561   case TargetOpcode::G_FPTOSI:
562   case TargetOpcode::G_FPTOUI: {
563     // FIXME: Support other types
564     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
566     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
567       return UnableToLegalize;
568     LegalizeResult Status = conversionLibcall(
569         MI, MIRBuilder,
570         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
571         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
572     if (Status != Legalized)
573       return Status;
574     break;
575   }
576   case TargetOpcode::G_SITOFP:
577   case TargetOpcode::G_UITOFP: {
578     // FIXME: Support other types
579     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
581     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
582       return UnableToLegalize;
583     LegalizeResult Status = conversionLibcall(
584         MI, MIRBuilder,
585         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
586         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
587     if (Status != Legalized)
588       return Status;
589     break;
590   }
591   }
592 
593   MI.eraseFromParent();
594   return Legalized;
595 }
596 
597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
598                                                               unsigned TypeIdx,
599                                                               LLT NarrowTy) {
600   MIRBuilder.setInstr(MI);
601 
602   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
603   uint64_t NarrowSize = NarrowTy.getSizeInBits();
604 
605   switch (MI.getOpcode()) {
606   default:
607     return UnableToLegalize;
608   case TargetOpcode::G_IMPLICIT_DEF: {
609     // FIXME: add support for when SizeOp0 isn't an exact multiple of
610     // NarrowSize.
611     if (SizeOp0 % NarrowSize != 0)
612       return UnableToLegalize;
613     int NumParts = SizeOp0 / NarrowSize;
614 
615     SmallVector<Register, 2> DstRegs;
616     for (int i = 0; i < NumParts; ++i)
617       DstRegs.push_back(
618           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
619 
620     Register DstReg = MI.getOperand(0).getReg();
621     if(MRI.getType(DstReg).isVector())
622       MIRBuilder.buildBuildVector(DstReg, DstRegs);
623     else
624       MIRBuilder.buildMerge(DstReg, DstRegs);
625     MI.eraseFromParent();
626     return Legalized;
627   }
628   case TargetOpcode::G_CONSTANT: {
629     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
631     unsigned TotalSize = Ty.getSizeInBits();
632     unsigned NarrowSize = NarrowTy.getSizeInBits();
633     int NumParts = TotalSize / NarrowSize;
634 
635     SmallVector<Register, 4> PartRegs;
636     for (int I = 0; I != NumParts; ++I) {
637       unsigned Offset = I * NarrowSize;
638       auto K = MIRBuilder.buildConstant(NarrowTy,
639                                         Val.lshr(Offset).trunc(NarrowSize));
640       PartRegs.push_back(K.getReg(0));
641     }
642 
643     LLT LeftoverTy;
644     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
645     SmallVector<Register, 1> LeftoverRegs;
646     if (LeftoverBits != 0) {
647       LeftoverTy = LLT::scalar(LeftoverBits);
648       auto K = MIRBuilder.buildConstant(
649         LeftoverTy,
650         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
651       LeftoverRegs.push_back(K.getReg(0));
652     }
653 
654     insertParts(MI.getOperand(0).getReg(),
655                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
656 
657     MI.eraseFromParent();
658     return Legalized;
659   }
660   case TargetOpcode::G_SEXT: {
661     if (TypeIdx != 0)
662       return UnableToLegalize;
663 
664     Register SrcReg = MI.getOperand(1).getReg();
665     LLT SrcTy = MRI.getType(SrcReg);
666 
667     // FIXME: support the general case where the requested NarrowTy may not be
668     // the same as the source type. E.g. s128 = sext(s32)
669     if ((SrcTy.getSizeInBits() != SizeOp0 / 2) ||
670         SrcTy.getSizeInBits() != NarrowTy.getSizeInBits()) {
671       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
672       return UnableToLegalize;
673     }
674 
675     // Shift the sign bit of the low register through the high register.
676     auto ShiftAmt =
677         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
678     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
679     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
680     MI.eraseFromParent();
681     return Legalized;
682   }
683   case TargetOpcode::G_ZEXT: {
684     if (TypeIdx != 0)
685       return UnableToLegalize;
686 
687     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
688     uint64_t SizeOp1 = SrcTy.getSizeInBits();
689     if (SizeOp0 % SizeOp1 != 0)
690       return UnableToLegalize;
691 
692     // Generate a merge where the bottom bits are taken from the source, and
693     // zero everything else.
694     Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
695     unsigned NumParts = SizeOp0 / SizeOp1;
696     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
697     for (unsigned Part = 1; Part < NumParts; ++Part)
698       Srcs.push_back(ZeroReg);
699     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
700     MI.eraseFromParent();
701     return Legalized;
702   }
703   case TargetOpcode::G_TRUNC: {
704     if (TypeIdx != 1)
705       return UnableToLegalize;
706 
707     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
708     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
709       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
710       return UnableToLegalize;
711     }
712 
713     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
714     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
715     MI.eraseFromParent();
716     return Legalized;
717   }
718 
719   case TargetOpcode::G_ADD: {
720     // FIXME: add support for when SizeOp0 isn't an exact multiple of
721     // NarrowSize.
722     if (SizeOp0 % NarrowSize != 0)
723       return UnableToLegalize;
724     // Expand in terms of carry-setting/consuming G_ADDE instructions.
725     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
726 
727     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
728     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
729     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
730 
731     Register CarryIn;
732     for (int i = 0; i < NumParts; ++i) {
733       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
734       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
735 
736       if (i == 0)
737         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
738       else {
739         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
740                               Src2Regs[i], CarryIn);
741       }
742 
743       DstRegs.push_back(DstReg);
744       CarryIn = CarryOut;
745     }
746     Register DstReg = MI.getOperand(0).getReg();
747     if(MRI.getType(DstReg).isVector())
748       MIRBuilder.buildBuildVector(DstReg, DstRegs);
749     else
750       MIRBuilder.buildMerge(DstReg, DstRegs);
751     MI.eraseFromParent();
752     return Legalized;
753   }
754   case TargetOpcode::G_SUB: {
755     // FIXME: add support for when SizeOp0 isn't an exact multiple of
756     // NarrowSize.
757     if (SizeOp0 % NarrowSize != 0)
758       return UnableToLegalize;
759 
760     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
761 
762     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
763     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
764     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
765 
766     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
767     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
768     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
769                           {Src1Regs[0], Src2Regs[0]});
770     DstRegs.push_back(DstReg);
771     Register BorrowIn = BorrowOut;
772     for (int i = 1; i < NumParts; ++i) {
773       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
774       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
775 
776       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
777                             {Src1Regs[i], Src2Regs[i], BorrowIn});
778 
779       DstRegs.push_back(DstReg);
780       BorrowIn = BorrowOut;
781     }
782     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
783     MI.eraseFromParent();
784     return Legalized;
785   }
786   case TargetOpcode::G_MUL:
787   case TargetOpcode::G_UMULH:
788     return narrowScalarMul(MI, NarrowTy);
789   case TargetOpcode::G_EXTRACT:
790     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
791   case TargetOpcode::G_INSERT:
792     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
793   case TargetOpcode::G_LOAD: {
794     const auto &MMO = **MI.memoperands_begin();
795     Register DstReg = MI.getOperand(0).getReg();
796     LLT DstTy = MRI.getType(DstReg);
797     if (DstTy.isVector())
798       return UnableToLegalize;
799 
800     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
801       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
802       auto &MMO = **MI.memoperands_begin();
803       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
804       MIRBuilder.buildAnyExt(DstReg, TmpReg);
805       MI.eraseFromParent();
806       return Legalized;
807     }
808 
809     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
810   }
811   case TargetOpcode::G_ZEXTLOAD:
812   case TargetOpcode::G_SEXTLOAD: {
813     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
814     Register DstReg = MI.getOperand(0).getReg();
815     Register PtrReg = MI.getOperand(1).getReg();
816 
817     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
818     auto &MMO = **MI.memoperands_begin();
819     if (MMO.getSizeInBits() == NarrowSize) {
820       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
821     } else {
822       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
823         : TargetOpcode::G_SEXTLOAD;
824       MIRBuilder.buildInstr(ExtLoad)
825         .addDef(TmpReg)
826         .addUse(PtrReg)
827         .addMemOperand(&MMO);
828     }
829 
830     if (ZExt)
831       MIRBuilder.buildZExt(DstReg, TmpReg);
832     else
833       MIRBuilder.buildSExt(DstReg, TmpReg);
834 
835     MI.eraseFromParent();
836     return Legalized;
837   }
838   case TargetOpcode::G_STORE: {
839     const auto &MMO = **MI.memoperands_begin();
840 
841     Register SrcReg = MI.getOperand(0).getReg();
842     LLT SrcTy = MRI.getType(SrcReg);
843     if (SrcTy.isVector())
844       return UnableToLegalize;
845 
846     int NumParts = SizeOp0 / NarrowSize;
847     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
848     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
849     if (SrcTy.isVector() && LeftoverBits != 0)
850       return UnableToLegalize;
851 
852     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
853       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
854       auto &MMO = **MI.memoperands_begin();
855       MIRBuilder.buildTrunc(TmpReg, SrcReg);
856       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
857       MI.eraseFromParent();
858       return Legalized;
859     }
860 
861     return reduceLoadStoreWidth(MI, 0, NarrowTy);
862   }
863   case TargetOpcode::G_SELECT:
864     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
865   case TargetOpcode::G_AND:
866   case TargetOpcode::G_OR:
867   case TargetOpcode::G_XOR: {
868     // Legalize bitwise operation:
869     // A = BinOp<Ty> B, C
870     // into:
871     // B1, ..., BN = G_UNMERGE_VALUES B
872     // C1, ..., CN = G_UNMERGE_VALUES C
873     // A1 = BinOp<Ty/N> B1, C2
874     // ...
875     // AN = BinOp<Ty/N> BN, CN
876     // A = G_MERGE_VALUES A1, ..., AN
877     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
878   }
879   case TargetOpcode::G_SHL:
880   case TargetOpcode::G_LSHR:
881   case TargetOpcode::G_ASHR:
882     return narrowScalarShift(MI, TypeIdx, NarrowTy);
883   case TargetOpcode::G_CTLZ:
884   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
885   case TargetOpcode::G_CTTZ:
886   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
887   case TargetOpcode::G_CTPOP:
888     if (TypeIdx != 0)
889       return UnableToLegalize; // TODO
890 
891     Observer.changingInstr(MI);
892     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
893     Observer.changedInstr(MI);
894     return Legalized;
895   case TargetOpcode::G_INTTOPTR:
896     if (TypeIdx != 1)
897       return UnableToLegalize;
898 
899     Observer.changingInstr(MI);
900     narrowScalarSrc(MI, NarrowTy, 1);
901     Observer.changedInstr(MI);
902     return Legalized;
903   case TargetOpcode::G_PTRTOINT:
904     if (TypeIdx != 0)
905       return UnableToLegalize;
906 
907     Observer.changingInstr(MI);
908     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
909     Observer.changedInstr(MI);
910     return Legalized;
911   case TargetOpcode::G_PHI: {
912     unsigned NumParts = SizeOp0 / NarrowSize;
913     SmallVector<Register, 2> DstRegs;
914     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
915     DstRegs.resize(NumParts);
916     SrcRegs.resize(MI.getNumOperands() / 2);
917     Observer.changingInstr(MI);
918     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
919       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
920       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
921       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
922                    SrcRegs[i / 2]);
923     }
924     MachineBasicBlock &MBB = *MI.getParent();
925     MIRBuilder.setInsertPt(MBB, MI);
926     for (unsigned i = 0; i < NumParts; ++i) {
927       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
928       MachineInstrBuilder MIB =
929           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
930       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
931         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
932     }
933     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
934     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
935     Observer.changedInstr(MI);
936     MI.eraseFromParent();
937     return Legalized;
938   }
939   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
940   case TargetOpcode::G_INSERT_VECTOR_ELT: {
941     if (TypeIdx != 2)
942       return UnableToLegalize;
943 
944     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
945     Observer.changingInstr(MI);
946     narrowScalarSrc(MI, NarrowTy, OpIdx);
947     Observer.changedInstr(MI);
948     return Legalized;
949   }
950   case TargetOpcode::G_ICMP: {
951     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
952     if (NarrowSize * 2 != SrcSize)
953       return UnableToLegalize;
954 
955     Observer.changingInstr(MI);
956     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
957     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
958     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
959 
960     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
961     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
962     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
963 
964     CmpInst::Predicate Pred =
965         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
966     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
967 
968     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
969       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
970       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
971       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
972       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
973       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
974     } else {
975       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
976       MachineInstrBuilder CmpHEQ =
977           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
978       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
979           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
980       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
981     }
982     Observer.changedInstr(MI);
983     MI.eraseFromParent();
984     return Legalized;
985   }
986   case TargetOpcode::G_SEXT_INREG: {
987     if (TypeIdx != 0)
988       return UnableToLegalize;
989 
990     if (!MI.getOperand(2).isImm())
991       return UnableToLegalize;
992     int64_t SizeInBits = MI.getOperand(2).getImm();
993 
994     // So long as the new type has more bits than the bits we're extending we
995     // don't need to break it apart.
996     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
997       Observer.changingInstr(MI);
998       // We don't lose any non-extension bits by truncating the src and
999       // sign-extending the dst.
1000       MachineOperand &MO1 = MI.getOperand(1);
1001       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1002       MO1.setReg(TruncMIB->getOperand(0).getReg());
1003 
1004       MachineOperand &MO2 = MI.getOperand(0);
1005       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1006       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1007       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1008       MO2.setReg(DstExt);
1009       Observer.changedInstr(MI);
1010       return Legalized;
1011     }
1012 
1013     // Break it apart. Components below the extension point are unmodified. The
1014     // component containing the extension point becomes a narrower SEXT_INREG.
1015     // Components above it are ashr'd from the component containing the
1016     // extension point.
1017     if (SizeOp0 % NarrowSize != 0)
1018       return UnableToLegalize;
1019     int NumParts = SizeOp0 / NarrowSize;
1020 
1021     // List the registers where the destination will be scattered.
1022     SmallVector<Register, 2> DstRegs;
1023     // List the registers where the source will be split.
1024     SmallVector<Register, 2> SrcRegs;
1025 
1026     // Create all the temporary registers.
1027     for (int i = 0; i < NumParts; ++i) {
1028       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1029 
1030       SrcRegs.push_back(SrcReg);
1031     }
1032 
1033     // Explode the big arguments into smaller chunks.
1034     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1035 
1036     Register AshrCstReg =
1037         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1038             ->getOperand(0)
1039             .getReg();
1040     Register FullExtensionReg = 0;
1041     Register PartialExtensionReg = 0;
1042 
1043     // Do the operation on each small part.
1044     for (int i = 0; i < NumParts; ++i) {
1045       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1046         DstRegs.push_back(SrcRegs[i]);
1047       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1048         assert(PartialExtensionReg &&
1049                "Expected to visit partial extension before full");
1050         if (FullExtensionReg) {
1051           DstRegs.push_back(FullExtensionReg);
1052           continue;
1053         }
1054         DstRegs.push_back(MIRBuilder
1055                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1056                                           {PartialExtensionReg, AshrCstReg})
1057                               ->getOperand(0)
1058                               .getReg());
1059         FullExtensionReg = DstRegs.back();
1060       } else {
1061         DstRegs.push_back(
1062             MIRBuilder
1063                 .buildInstr(
1064                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1065                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1066                 ->getOperand(0)
1067                 .getReg());
1068         PartialExtensionReg = DstRegs.back();
1069       }
1070     }
1071 
1072     // Gather the destination registers into the final destination.
1073     Register DstReg = MI.getOperand(0).getReg();
1074     MIRBuilder.buildMerge(DstReg, DstRegs);
1075     MI.eraseFromParent();
1076     return Legalized;
1077   }
1078   }
1079 }
1080 
1081 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1082                                      unsigned OpIdx, unsigned ExtOpcode) {
1083   MachineOperand &MO = MI.getOperand(OpIdx);
1084   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1085   MO.setReg(ExtB->getOperand(0).getReg());
1086 }
1087 
1088 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1089                                       unsigned OpIdx) {
1090   MachineOperand &MO = MI.getOperand(OpIdx);
1091   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1092                                     {MO.getReg()});
1093   MO.setReg(ExtB->getOperand(0).getReg());
1094 }
1095 
1096 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1097                                      unsigned OpIdx, unsigned TruncOpcode) {
1098   MachineOperand &MO = MI.getOperand(OpIdx);
1099   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1100   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1101   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1102   MO.setReg(DstExt);
1103 }
1104 
1105 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1106                                       unsigned OpIdx, unsigned ExtOpcode) {
1107   MachineOperand &MO = MI.getOperand(OpIdx);
1108   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1109   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1110   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1111   MO.setReg(DstTrunc);
1112 }
1113 
1114 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1115                                             unsigned OpIdx) {
1116   MachineOperand &MO = MI.getOperand(OpIdx);
1117   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1118   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1119   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1120   MO.setReg(DstExt);
1121 }
1122 
1123 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1124                                             unsigned OpIdx) {
1125   MachineOperand &MO = MI.getOperand(OpIdx);
1126 
1127   LLT OldTy = MRI.getType(MO.getReg());
1128   unsigned OldElts = OldTy.getNumElements();
1129   unsigned NewElts = MoreTy.getNumElements();
1130 
1131   unsigned NumParts = NewElts / OldElts;
1132 
1133   // Use concat_vectors if the result is a multiple of the number of elements.
1134   if (NumParts * OldElts == NewElts) {
1135     SmallVector<Register, 8> Parts;
1136     Parts.push_back(MO.getReg());
1137 
1138     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1139     for (unsigned I = 1; I != NumParts; ++I)
1140       Parts.push_back(ImpDef);
1141 
1142     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1143     MO.setReg(Concat.getReg(0));
1144     return;
1145   }
1146 
1147   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1148   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1149   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1150   MO.setReg(MoreReg);
1151 }
1152 
1153 LegalizerHelper::LegalizeResult
1154 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1155                                         LLT WideTy) {
1156   if (TypeIdx != 1)
1157     return UnableToLegalize;
1158 
1159   Register DstReg = MI.getOperand(0).getReg();
1160   LLT DstTy = MRI.getType(DstReg);
1161   if (DstTy.isVector())
1162     return UnableToLegalize;
1163 
1164   Register Src1 = MI.getOperand(1).getReg();
1165   LLT SrcTy = MRI.getType(Src1);
1166   const int DstSize = DstTy.getSizeInBits();
1167   const int SrcSize = SrcTy.getSizeInBits();
1168   const int WideSize = WideTy.getSizeInBits();
1169   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1170 
1171   unsigned NumOps = MI.getNumOperands();
1172   unsigned NumSrc = MI.getNumOperands() - 1;
1173   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1174 
1175   if (WideSize >= DstSize) {
1176     // Directly pack the bits in the target type.
1177     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1178 
1179     for (unsigned I = 2; I != NumOps; ++I) {
1180       const unsigned Offset = (I - 1) * PartSize;
1181 
1182       Register SrcReg = MI.getOperand(I).getReg();
1183       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1184 
1185       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1186 
1187       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1188         MRI.createGenericVirtualRegister(WideTy);
1189 
1190       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1191       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1192       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1193       ResultReg = NextResult;
1194     }
1195 
1196     if (WideSize > DstSize)
1197       MIRBuilder.buildTrunc(DstReg, ResultReg);
1198     else if (DstTy.isPointer())
1199       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1200 
1201     MI.eraseFromParent();
1202     return Legalized;
1203   }
1204 
1205   // Unmerge the original values to the GCD type, and recombine to the next
1206   // multiple greater than the original type.
1207   //
1208   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1209   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1210   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1211   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1212   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1213   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1214   // %12:_(s12) = G_MERGE_VALUES %10, %11
1215   //
1216   // Padding with undef if necessary:
1217   //
1218   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1219   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1220   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1221   // %7:_(s2) = G_IMPLICIT_DEF
1222   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1223   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1224   // %10:_(s12) = G_MERGE_VALUES %8, %9
1225 
1226   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1227   LLT GCDTy = LLT::scalar(GCD);
1228 
1229   SmallVector<Register, 8> Parts;
1230   SmallVector<Register, 8> NewMergeRegs;
1231   SmallVector<Register, 8> Unmerges;
1232   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1233 
1234   // Decompose the original operands if they don't evenly divide.
1235   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1236     Register SrcReg = MI.getOperand(I).getReg();
1237     if (GCD == SrcSize) {
1238       Unmerges.push_back(SrcReg);
1239     } else {
1240       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1241       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1242         Unmerges.push_back(Unmerge.getReg(J));
1243     }
1244   }
1245 
1246   // Pad with undef to the next size that is a multiple of the requested size.
1247   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1248     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1249     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1250       Unmerges.push_back(UndefReg);
1251   }
1252 
1253   const int PartsPerGCD = WideSize / GCD;
1254 
1255   // Build merges of each piece.
1256   ArrayRef<Register> Slicer(Unmerges);
1257   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1258     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1259     NewMergeRegs.push_back(Merge.getReg(0));
1260   }
1261 
1262   // A truncate may be necessary if the requested type doesn't evenly divide the
1263   // original result type.
1264   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1265     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1266   } else {
1267     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1268     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1269   }
1270 
1271   MI.eraseFromParent();
1272   return Legalized;
1273 }
1274 
1275 LegalizerHelper::LegalizeResult
1276 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1277                                           LLT WideTy) {
1278   if (TypeIdx != 0)
1279     return UnableToLegalize;
1280 
1281   unsigned NumDst = MI.getNumOperands() - 1;
1282   Register SrcReg = MI.getOperand(NumDst).getReg();
1283   LLT SrcTy = MRI.getType(SrcReg);
1284   if (!SrcTy.isScalar())
1285     return UnableToLegalize;
1286 
1287   Register Dst0Reg = MI.getOperand(0).getReg();
1288   LLT DstTy = MRI.getType(Dst0Reg);
1289   if (!DstTy.isScalar())
1290     return UnableToLegalize;
1291 
1292   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1293   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1294   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1295 
1296   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1297 
1298   for (unsigned I = 1; I != NumDst; ++I) {
1299     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1300     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1301     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1302   }
1303 
1304   Observer.changingInstr(MI);
1305 
1306   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1307   for (unsigned I = 0; I != NumDst; ++I)
1308     widenScalarDst(MI, WideTy, I);
1309 
1310   Observer.changedInstr(MI);
1311 
1312   return Legalized;
1313 }
1314 
1315 LegalizerHelper::LegalizeResult
1316 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1317                                     LLT WideTy) {
1318   Register DstReg = MI.getOperand(0).getReg();
1319   Register SrcReg = MI.getOperand(1).getReg();
1320   LLT SrcTy = MRI.getType(SrcReg);
1321 
1322   LLT DstTy = MRI.getType(DstReg);
1323   unsigned Offset = MI.getOperand(2).getImm();
1324 
1325   if (TypeIdx == 0) {
1326     if (SrcTy.isVector() || DstTy.isVector())
1327       return UnableToLegalize;
1328 
1329     SrcOp Src(SrcReg);
1330     if (SrcTy.isPointer()) {
1331       // Extracts from pointers can be handled only if they are really just
1332       // simple integers.
1333       const DataLayout &DL = MIRBuilder.getDataLayout();
1334       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1335         return UnableToLegalize;
1336 
1337       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1338       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1339       SrcTy = SrcAsIntTy;
1340     }
1341 
1342     if (DstTy.isPointer())
1343       return UnableToLegalize;
1344 
1345     if (Offset == 0) {
1346       // Avoid a shift in the degenerate case.
1347       MIRBuilder.buildTrunc(DstReg,
1348                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1349       MI.eraseFromParent();
1350       return Legalized;
1351     }
1352 
1353     // Do a shift in the source type.
1354     LLT ShiftTy = SrcTy;
1355     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1356       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1357       ShiftTy = WideTy;
1358     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1359       return UnableToLegalize;
1360 
1361     auto LShr = MIRBuilder.buildLShr(
1362       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1363     MIRBuilder.buildTrunc(DstReg, LShr);
1364     MI.eraseFromParent();
1365     return Legalized;
1366   }
1367 
1368   if (SrcTy.isScalar()) {
1369     Observer.changingInstr(MI);
1370     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1371     Observer.changedInstr(MI);
1372     return Legalized;
1373   }
1374 
1375   if (!SrcTy.isVector())
1376     return UnableToLegalize;
1377 
1378   if (DstTy != SrcTy.getElementType())
1379     return UnableToLegalize;
1380 
1381   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1382     return UnableToLegalize;
1383 
1384   Observer.changingInstr(MI);
1385   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1386 
1387   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1388                           Offset);
1389   widenScalarDst(MI, WideTy.getScalarType(), 0);
1390   Observer.changedInstr(MI);
1391   return Legalized;
1392 }
1393 
1394 LegalizerHelper::LegalizeResult
1395 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1396                                    LLT WideTy) {
1397   if (TypeIdx != 0)
1398     return UnableToLegalize;
1399   Observer.changingInstr(MI);
1400   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1401   widenScalarDst(MI, WideTy);
1402   Observer.changedInstr(MI);
1403   return Legalized;
1404 }
1405 
1406 LegalizerHelper::LegalizeResult
1407 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1408   MIRBuilder.setInstr(MI);
1409 
1410   switch (MI.getOpcode()) {
1411   default:
1412     return UnableToLegalize;
1413   case TargetOpcode::G_EXTRACT:
1414     return widenScalarExtract(MI, TypeIdx, WideTy);
1415   case TargetOpcode::G_INSERT:
1416     return widenScalarInsert(MI, TypeIdx, WideTy);
1417   case TargetOpcode::G_MERGE_VALUES:
1418     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1419   case TargetOpcode::G_UNMERGE_VALUES:
1420     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1421   case TargetOpcode::G_UADDO:
1422   case TargetOpcode::G_USUBO: {
1423     if (TypeIdx == 1)
1424       return UnableToLegalize; // TODO
1425     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1426                                          {MI.getOperand(2).getReg()});
1427     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1428                                          {MI.getOperand(3).getReg()});
1429     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1430                           ? TargetOpcode::G_ADD
1431                           : TargetOpcode::G_SUB;
1432     // Do the arithmetic in the larger type.
1433     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1434     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1435     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1436     auto AndOp = MIRBuilder.buildInstr(
1437         TargetOpcode::G_AND, {WideTy},
1438         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1439     // There is no overflow if the AndOp is the same as NewOp.
1440     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1441                          AndOp);
1442     // Now trunc the NewOp to the original result.
1443     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1444     MI.eraseFromParent();
1445     return Legalized;
1446   }
1447   case TargetOpcode::G_CTTZ:
1448   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1449   case TargetOpcode::G_CTLZ:
1450   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1451   case TargetOpcode::G_CTPOP: {
1452     if (TypeIdx == 0) {
1453       Observer.changingInstr(MI);
1454       widenScalarDst(MI, WideTy, 0);
1455       Observer.changedInstr(MI);
1456       return Legalized;
1457     }
1458 
1459     Register SrcReg = MI.getOperand(1).getReg();
1460 
1461     // First ZEXT the input.
1462     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1463     LLT CurTy = MRI.getType(SrcReg);
1464     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1465       // The count is the same in the larger type except if the original
1466       // value was zero.  This can be handled by setting the bit just off
1467       // the top of the original type.
1468       auto TopBit =
1469           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1470       MIBSrc = MIRBuilder.buildOr(
1471         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1472     }
1473 
1474     // Perform the operation at the larger size.
1475     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1476     // This is already the correct result for CTPOP and CTTZs
1477     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1478         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1479       // The correct result is NewOp - (Difference in widety and current ty).
1480       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1481       MIBNewOp = MIRBuilder.buildInstr(
1482           TargetOpcode::G_SUB, {WideTy},
1483           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1484     }
1485 
1486     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1487     MI.eraseFromParent();
1488     return Legalized;
1489   }
1490   case TargetOpcode::G_BSWAP: {
1491     Observer.changingInstr(MI);
1492     Register DstReg = MI.getOperand(0).getReg();
1493 
1494     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1495     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1496     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1497     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1498 
1499     MI.getOperand(0).setReg(DstExt);
1500 
1501     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1502 
1503     LLT Ty = MRI.getType(DstReg);
1504     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1505     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1506     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1507       .addDef(ShrReg)
1508       .addUse(DstExt)
1509       .addUse(ShiftAmtReg);
1510 
1511     MIRBuilder.buildTrunc(DstReg, ShrReg);
1512     Observer.changedInstr(MI);
1513     return Legalized;
1514   }
1515   case TargetOpcode::G_BITREVERSE: {
1516     Observer.changingInstr(MI);
1517 
1518     Register DstReg = MI.getOperand(0).getReg();
1519     LLT Ty = MRI.getType(DstReg);
1520     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1521 
1522     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1523     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1524     MI.getOperand(0).setReg(DstExt);
1525     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1526 
1527     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1528     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1529     MIRBuilder.buildTrunc(DstReg, Shift);
1530     Observer.changedInstr(MI);
1531     return Legalized;
1532   }
1533   case TargetOpcode::G_ADD:
1534   case TargetOpcode::G_AND:
1535   case TargetOpcode::G_MUL:
1536   case TargetOpcode::G_OR:
1537   case TargetOpcode::G_XOR:
1538   case TargetOpcode::G_SUB:
1539     // Perform operation at larger width (any extension is fines here, high bits
1540     // don't affect the result) and then truncate the result back to the
1541     // original type.
1542     Observer.changingInstr(MI);
1543     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1544     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1545     widenScalarDst(MI, WideTy);
1546     Observer.changedInstr(MI);
1547     return Legalized;
1548 
1549   case TargetOpcode::G_SHL:
1550     Observer.changingInstr(MI);
1551 
1552     if (TypeIdx == 0) {
1553       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1554       widenScalarDst(MI, WideTy);
1555     } else {
1556       assert(TypeIdx == 1);
1557       // The "number of bits to shift" operand must preserve its value as an
1558       // unsigned integer:
1559       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1560     }
1561 
1562     Observer.changedInstr(MI);
1563     return Legalized;
1564 
1565   case TargetOpcode::G_SDIV:
1566   case TargetOpcode::G_SREM:
1567   case TargetOpcode::G_SMIN:
1568   case TargetOpcode::G_SMAX:
1569     Observer.changingInstr(MI);
1570     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1571     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1572     widenScalarDst(MI, WideTy);
1573     Observer.changedInstr(MI);
1574     return Legalized;
1575 
1576   case TargetOpcode::G_ASHR:
1577   case TargetOpcode::G_LSHR:
1578     Observer.changingInstr(MI);
1579 
1580     if (TypeIdx == 0) {
1581       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1582         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1583 
1584       widenScalarSrc(MI, WideTy, 1, CvtOp);
1585       widenScalarDst(MI, WideTy);
1586     } else {
1587       assert(TypeIdx == 1);
1588       // The "number of bits to shift" operand must preserve its value as an
1589       // unsigned integer:
1590       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1591     }
1592 
1593     Observer.changedInstr(MI);
1594     return Legalized;
1595   case TargetOpcode::G_UDIV:
1596   case TargetOpcode::G_UREM:
1597   case TargetOpcode::G_UMIN:
1598   case TargetOpcode::G_UMAX:
1599     Observer.changingInstr(MI);
1600     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1601     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1602     widenScalarDst(MI, WideTy);
1603     Observer.changedInstr(MI);
1604     return Legalized;
1605 
1606   case TargetOpcode::G_SELECT:
1607     Observer.changingInstr(MI);
1608     if (TypeIdx == 0) {
1609       // Perform operation at larger width (any extension is fine here, high
1610       // bits don't affect the result) and then truncate the result back to the
1611       // original type.
1612       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1613       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1614       widenScalarDst(MI, WideTy);
1615     } else {
1616       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1617       // Explicit extension is required here since high bits affect the result.
1618       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1619     }
1620     Observer.changedInstr(MI);
1621     return Legalized;
1622 
1623   case TargetOpcode::G_FPTOSI:
1624   case TargetOpcode::G_FPTOUI:
1625     Observer.changingInstr(MI);
1626 
1627     if (TypeIdx == 0)
1628       widenScalarDst(MI, WideTy);
1629     else
1630       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1631 
1632     Observer.changedInstr(MI);
1633     return Legalized;
1634   case TargetOpcode::G_SITOFP:
1635     if (TypeIdx != 1)
1636       return UnableToLegalize;
1637     Observer.changingInstr(MI);
1638     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1639     Observer.changedInstr(MI);
1640     return Legalized;
1641 
1642   case TargetOpcode::G_UITOFP:
1643     if (TypeIdx != 1)
1644       return UnableToLegalize;
1645     Observer.changingInstr(MI);
1646     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1647     Observer.changedInstr(MI);
1648     return Legalized;
1649 
1650   case TargetOpcode::G_LOAD:
1651   case TargetOpcode::G_SEXTLOAD:
1652   case TargetOpcode::G_ZEXTLOAD:
1653     Observer.changingInstr(MI);
1654     widenScalarDst(MI, WideTy);
1655     Observer.changedInstr(MI);
1656     return Legalized;
1657 
1658   case TargetOpcode::G_STORE: {
1659     if (TypeIdx != 0)
1660       return UnableToLegalize;
1661 
1662     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1663     if (!isPowerOf2_32(Ty.getSizeInBits()))
1664       return UnableToLegalize;
1665 
1666     Observer.changingInstr(MI);
1667 
1668     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1669       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1670     widenScalarSrc(MI, WideTy, 0, ExtType);
1671 
1672     Observer.changedInstr(MI);
1673     return Legalized;
1674   }
1675   case TargetOpcode::G_CONSTANT: {
1676     MachineOperand &SrcMO = MI.getOperand(1);
1677     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1678     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1679         MRI.getType(MI.getOperand(0).getReg()));
1680     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1681             ExtOpc == TargetOpcode::G_ANYEXT) &&
1682            "Illegal Extend");
1683     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1684     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1685                            ? SrcVal.sext(WideTy.getSizeInBits())
1686                            : SrcVal.zext(WideTy.getSizeInBits());
1687     Observer.changingInstr(MI);
1688     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1689 
1690     widenScalarDst(MI, WideTy);
1691     Observer.changedInstr(MI);
1692     return Legalized;
1693   }
1694   case TargetOpcode::G_FCONSTANT: {
1695     MachineOperand &SrcMO = MI.getOperand(1);
1696     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1697     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1698     bool LosesInfo;
1699     switch (WideTy.getSizeInBits()) {
1700     case 32:
1701       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1702                   &LosesInfo);
1703       break;
1704     case 64:
1705       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1706                   &LosesInfo);
1707       break;
1708     default:
1709       return UnableToLegalize;
1710     }
1711 
1712     assert(!LosesInfo && "extend should always be lossless");
1713 
1714     Observer.changingInstr(MI);
1715     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1716 
1717     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1718     Observer.changedInstr(MI);
1719     return Legalized;
1720   }
1721   case TargetOpcode::G_IMPLICIT_DEF: {
1722     Observer.changingInstr(MI);
1723     widenScalarDst(MI, WideTy);
1724     Observer.changedInstr(MI);
1725     return Legalized;
1726   }
1727   case TargetOpcode::G_BRCOND:
1728     Observer.changingInstr(MI);
1729     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1730     Observer.changedInstr(MI);
1731     return Legalized;
1732 
1733   case TargetOpcode::G_FCMP:
1734     Observer.changingInstr(MI);
1735     if (TypeIdx == 0)
1736       widenScalarDst(MI, WideTy);
1737     else {
1738       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1739       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1740     }
1741     Observer.changedInstr(MI);
1742     return Legalized;
1743 
1744   case TargetOpcode::G_ICMP:
1745     Observer.changingInstr(MI);
1746     if (TypeIdx == 0)
1747       widenScalarDst(MI, WideTy);
1748     else {
1749       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1750                                MI.getOperand(1).getPredicate()))
1751                                ? TargetOpcode::G_SEXT
1752                                : TargetOpcode::G_ZEXT;
1753       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1754       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1755     }
1756     Observer.changedInstr(MI);
1757     return Legalized;
1758 
1759   case TargetOpcode::G_PTR_ADD:
1760     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1761     Observer.changingInstr(MI);
1762     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1763     Observer.changedInstr(MI);
1764     return Legalized;
1765 
1766   case TargetOpcode::G_PHI: {
1767     assert(TypeIdx == 0 && "Expecting only Idx 0");
1768 
1769     Observer.changingInstr(MI);
1770     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1771       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1772       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1773       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1774     }
1775 
1776     MachineBasicBlock &MBB = *MI.getParent();
1777     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1778     widenScalarDst(MI, WideTy);
1779     Observer.changedInstr(MI);
1780     return Legalized;
1781   }
1782   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1783     if (TypeIdx == 0) {
1784       Register VecReg = MI.getOperand(1).getReg();
1785       LLT VecTy = MRI.getType(VecReg);
1786       Observer.changingInstr(MI);
1787 
1788       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1789                                      WideTy.getSizeInBits()),
1790                      1, TargetOpcode::G_SEXT);
1791 
1792       widenScalarDst(MI, WideTy, 0);
1793       Observer.changedInstr(MI);
1794       return Legalized;
1795     }
1796 
1797     if (TypeIdx != 2)
1798       return UnableToLegalize;
1799     Observer.changingInstr(MI);
1800     // TODO: Probably should be zext
1801     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1802     Observer.changedInstr(MI);
1803     return Legalized;
1804   }
1805   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1806     if (TypeIdx == 1) {
1807       Observer.changingInstr(MI);
1808 
1809       Register VecReg = MI.getOperand(1).getReg();
1810       LLT VecTy = MRI.getType(VecReg);
1811       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
1812 
1813       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
1814       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1815       widenScalarDst(MI, WideVecTy, 0);
1816       Observer.changedInstr(MI);
1817       return Legalized;
1818     }
1819 
1820     if (TypeIdx == 2) {
1821       Observer.changingInstr(MI);
1822       // TODO: Probably should be zext
1823       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
1824       Observer.changedInstr(MI);
1825     }
1826 
1827     return Legalized;
1828   }
1829   case TargetOpcode::G_FADD:
1830   case TargetOpcode::G_FMUL:
1831   case TargetOpcode::G_FSUB:
1832   case TargetOpcode::G_FMA:
1833   case TargetOpcode::G_FMAD:
1834   case TargetOpcode::G_FNEG:
1835   case TargetOpcode::G_FABS:
1836   case TargetOpcode::G_FCANONICALIZE:
1837   case TargetOpcode::G_FMINNUM:
1838   case TargetOpcode::G_FMAXNUM:
1839   case TargetOpcode::G_FMINNUM_IEEE:
1840   case TargetOpcode::G_FMAXNUM_IEEE:
1841   case TargetOpcode::G_FMINIMUM:
1842   case TargetOpcode::G_FMAXIMUM:
1843   case TargetOpcode::G_FDIV:
1844   case TargetOpcode::G_FREM:
1845   case TargetOpcode::G_FCEIL:
1846   case TargetOpcode::G_FFLOOR:
1847   case TargetOpcode::G_FCOS:
1848   case TargetOpcode::G_FSIN:
1849   case TargetOpcode::G_FLOG10:
1850   case TargetOpcode::G_FLOG:
1851   case TargetOpcode::G_FLOG2:
1852   case TargetOpcode::G_FRINT:
1853   case TargetOpcode::G_FNEARBYINT:
1854   case TargetOpcode::G_FSQRT:
1855   case TargetOpcode::G_FEXP:
1856   case TargetOpcode::G_FEXP2:
1857   case TargetOpcode::G_FPOW:
1858   case TargetOpcode::G_INTRINSIC_TRUNC:
1859   case TargetOpcode::G_INTRINSIC_ROUND:
1860     assert(TypeIdx == 0);
1861     Observer.changingInstr(MI);
1862 
1863     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1864       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1865 
1866     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1867     Observer.changedInstr(MI);
1868     return Legalized;
1869   case TargetOpcode::G_INTTOPTR:
1870     if (TypeIdx != 1)
1871       return UnableToLegalize;
1872 
1873     Observer.changingInstr(MI);
1874     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1875     Observer.changedInstr(MI);
1876     return Legalized;
1877   case TargetOpcode::G_PTRTOINT:
1878     if (TypeIdx != 0)
1879       return UnableToLegalize;
1880 
1881     Observer.changingInstr(MI);
1882     widenScalarDst(MI, WideTy, 0);
1883     Observer.changedInstr(MI);
1884     return Legalized;
1885   case TargetOpcode::G_BUILD_VECTOR: {
1886     Observer.changingInstr(MI);
1887 
1888     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1889     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1890       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1891 
1892     // Avoid changing the result vector type if the source element type was
1893     // requested.
1894     if (TypeIdx == 1) {
1895       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1896       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1897     } else {
1898       widenScalarDst(MI, WideTy, 0);
1899     }
1900 
1901     Observer.changedInstr(MI);
1902     return Legalized;
1903   }
1904   case TargetOpcode::G_SEXT_INREG:
1905     if (TypeIdx != 0)
1906       return UnableToLegalize;
1907 
1908     Observer.changingInstr(MI);
1909     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1910     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1911     Observer.changedInstr(MI);
1912     return Legalized;
1913   }
1914 }
1915 
1916 LegalizerHelper::LegalizeResult
1917 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1918   using namespace TargetOpcode;
1919   MIRBuilder.setInstr(MI);
1920 
1921   switch(MI.getOpcode()) {
1922   default:
1923     return UnableToLegalize;
1924   case TargetOpcode::G_SREM:
1925   case TargetOpcode::G_UREM: {
1926     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1927     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1928         .addDef(QuotReg)
1929         .addUse(MI.getOperand(1).getReg())
1930         .addUse(MI.getOperand(2).getReg());
1931 
1932     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1933     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1934     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1935                         ProdReg);
1936     MI.eraseFromParent();
1937     return Legalized;
1938   }
1939   case TargetOpcode::G_SADDO:
1940   case TargetOpcode::G_SSUBO:
1941     return lowerSADDO_SSUBO(MI);
1942   case TargetOpcode::G_SMULO:
1943   case TargetOpcode::G_UMULO: {
1944     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1945     // result.
1946     Register Res = MI.getOperand(0).getReg();
1947     Register Overflow = MI.getOperand(1).getReg();
1948     Register LHS = MI.getOperand(2).getReg();
1949     Register RHS = MI.getOperand(3).getReg();
1950 
1951     MIRBuilder.buildMul(Res, LHS, RHS);
1952 
1953     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1954                           ? TargetOpcode::G_SMULH
1955                           : TargetOpcode::G_UMULH;
1956 
1957     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1958     MIRBuilder.buildInstr(Opcode)
1959       .addDef(HiPart)
1960       .addUse(LHS)
1961       .addUse(RHS);
1962 
1963     Register Zero = MRI.createGenericVirtualRegister(Ty);
1964     MIRBuilder.buildConstant(Zero, 0);
1965 
1966     // For *signed* multiply, overflow is detected by checking:
1967     // (hi != (lo >> bitwidth-1))
1968     if (Opcode == TargetOpcode::G_SMULH) {
1969       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1970       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1971       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1972       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1973         .addDef(Shifted)
1974         .addUse(Res)
1975         .addUse(ShiftAmt);
1976       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1977     } else {
1978       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1979     }
1980     MI.eraseFromParent();
1981     return Legalized;
1982   }
1983   case TargetOpcode::G_FNEG: {
1984     // TODO: Handle vector types once we are able to
1985     // represent them.
1986     if (Ty.isVector())
1987       return UnableToLegalize;
1988     Register Res = MI.getOperand(0).getReg();
1989     Type *ZeroTy;
1990     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1991     switch (Ty.getSizeInBits()) {
1992     case 16:
1993       ZeroTy = Type::getHalfTy(Ctx);
1994       break;
1995     case 32:
1996       ZeroTy = Type::getFloatTy(Ctx);
1997       break;
1998     case 64:
1999       ZeroTy = Type::getDoubleTy(Ctx);
2000       break;
2001     case 128:
2002       ZeroTy = Type::getFP128Ty(Ctx);
2003       break;
2004     default:
2005       llvm_unreachable("unexpected floating-point type");
2006     }
2007     ConstantFP &ZeroForNegation =
2008         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2009     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2010     Register SubByReg = MI.getOperand(1).getReg();
2011     Register ZeroReg = Zero->getOperand(0).getReg();
2012     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
2013                           MI.getFlags());
2014     MI.eraseFromParent();
2015     return Legalized;
2016   }
2017   case TargetOpcode::G_FSUB: {
2018     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2019     // First, check if G_FNEG is marked as Lower. If so, we may
2020     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2021     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2022       return UnableToLegalize;
2023     Register Res = MI.getOperand(0).getReg();
2024     Register LHS = MI.getOperand(1).getReg();
2025     Register RHS = MI.getOperand(2).getReg();
2026     Register Neg = MRI.createGenericVirtualRegister(Ty);
2027     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2028     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
2029     MI.eraseFromParent();
2030     return Legalized;
2031   }
2032   case TargetOpcode::G_FMAD:
2033     return lowerFMad(MI);
2034   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2035     Register OldValRes = MI.getOperand(0).getReg();
2036     Register SuccessRes = MI.getOperand(1).getReg();
2037     Register Addr = MI.getOperand(2).getReg();
2038     Register CmpVal = MI.getOperand(3).getReg();
2039     Register NewVal = MI.getOperand(4).getReg();
2040     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2041                                   **MI.memoperands_begin());
2042     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2043     MI.eraseFromParent();
2044     return Legalized;
2045   }
2046   case TargetOpcode::G_LOAD:
2047   case TargetOpcode::G_SEXTLOAD:
2048   case TargetOpcode::G_ZEXTLOAD: {
2049     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2050     Register DstReg = MI.getOperand(0).getReg();
2051     Register PtrReg = MI.getOperand(1).getReg();
2052     LLT DstTy = MRI.getType(DstReg);
2053     auto &MMO = **MI.memoperands_begin();
2054 
2055     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2056       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2057         // This load needs splitting into power of 2 sized loads.
2058         if (DstTy.isVector())
2059           return UnableToLegalize;
2060         if (isPowerOf2_32(DstTy.getSizeInBits()))
2061           return UnableToLegalize; // Don't know what we're being asked to do.
2062 
2063         // Our strategy here is to generate anyextending loads for the smaller
2064         // types up to next power-2 result type, and then combine the two larger
2065         // result values together, before truncating back down to the non-pow-2
2066         // type.
2067         // E.g. v1 = i24 load =>
2068         // v2 = i32 load (2 byte)
2069         // v3 = i32 load (1 byte)
2070         // v4 = i32 shl v3, 16
2071         // v5 = i32 or v4, v2
2072         // v1 = i24 trunc v5
2073         // By doing this we generate the correct truncate which should get
2074         // combined away as an artifact with a matching extend.
2075         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2076         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2077 
2078         MachineFunction &MF = MIRBuilder.getMF();
2079         MachineMemOperand *LargeMMO =
2080             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2081         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2082             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2083 
2084         LLT PtrTy = MRI.getType(PtrReg);
2085         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2086         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2087         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2088         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2089         auto LargeLoad =
2090             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
2091 
2092         auto OffsetCst =
2093             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2094         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2095         auto SmallPtr =
2096             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2097         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2098                                               *SmallMMO);
2099 
2100         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2101         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2102         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2103         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2104         MI.eraseFromParent();
2105         return Legalized;
2106       }
2107       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2108       MI.eraseFromParent();
2109       return Legalized;
2110     }
2111 
2112     if (DstTy.isScalar()) {
2113       Register TmpReg =
2114           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2115       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2116       switch (MI.getOpcode()) {
2117       default:
2118         llvm_unreachable("Unexpected opcode");
2119       case TargetOpcode::G_LOAD:
2120         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2121         break;
2122       case TargetOpcode::G_SEXTLOAD:
2123         MIRBuilder.buildSExt(DstReg, TmpReg);
2124         break;
2125       case TargetOpcode::G_ZEXTLOAD:
2126         MIRBuilder.buildZExt(DstReg, TmpReg);
2127         break;
2128       }
2129       MI.eraseFromParent();
2130       return Legalized;
2131     }
2132 
2133     return UnableToLegalize;
2134   }
2135   case TargetOpcode::G_STORE: {
2136     // Lower a non-power of 2 store into multiple pow-2 stores.
2137     // E.g. split an i24 store into an i16 store + i8 store.
2138     // We do this by first extending the stored value to the next largest power
2139     // of 2 type, and then using truncating stores to store the components.
2140     // By doing this, likewise with G_LOAD, generate an extend that can be
2141     // artifact-combined away instead of leaving behind extracts.
2142     Register SrcReg = MI.getOperand(0).getReg();
2143     Register PtrReg = MI.getOperand(1).getReg();
2144     LLT SrcTy = MRI.getType(SrcReg);
2145     MachineMemOperand &MMO = **MI.memoperands_begin();
2146     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2147       return UnableToLegalize;
2148     if (SrcTy.isVector())
2149       return UnableToLegalize;
2150     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2151       return UnableToLegalize; // Don't know what we're being asked to do.
2152 
2153     // Extend to the next pow-2.
2154     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2155     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2156 
2157     // Obtain the smaller value by shifting away the larger value.
2158     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2159     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2160     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2161     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2162 
2163     // Generate the PtrAdd and truncating stores.
2164     LLT PtrTy = MRI.getType(PtrReg);
2165     auto OffsetCst =
2166         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2167     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2168     auto SmallPtr =
2169         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2170 
2171     MachineFunction &MF = MIRBuilder.getMF();
2172     MachineMemOperand *LargeMMO =
2173         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2174     MachineMemOperand *SmallMMO =
2175         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2176     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2177     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2178     MI.eraseFromParent();
2179     return Legalized;
2180   }
2181   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2182   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2183   case TargetOpcode::G_CTLZ:
2184   case TargetOpcode::G_CTTZ:
2185   case TargetOpcode::G_CTPOP:
2186     return lowerBitCount(MI, TypeIdx, Ty);
2187   case G_UADDO: {
2188     Register Res = MI.getOperand(0).getReg();
2189     Register CarryOut = MI.getOperand(1).getReg();
2190     Register LHS = MI.getOperand(2).getReg();
2191     Register RHS = MI.getOperand(3).getReg();
2192 
2193     MIRBuilder.buildAdd(Res, LHS, RHS);
2194     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2195 
2196     MI.eraseFromParent();
2197     return Legalized;
2198   }
2199   case G_UADDE: {
2200     Register Res = MI.getOperand(0).getReg();
2201     Register CarryOut = MI.getOperand(1).getReg();
2202     Register LHS = MI.getOperand(2).getReg();
2203     Register RHS = MI.getOperand(3).getReg();
2204     Register CarryIn = MI.getOperand(4).getReg();
2205 
2206     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2207     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2208 
2209     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2210     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2211     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2212     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2213 
2214     MI.eraseFromParent();
2215     return Legalized;
2216   }
2217   case G_USUBO: {
2218     Register Res = MI.getOperand(0).getReg();
2219     Register BorrowOut = MI.getOperand(1).getReg();
2220     Register LHS = MI.getOperand(2).getReg();
2221     Register RHS = MI.getOperand(3).getReg();
2222 
2223     MIRBuilder.buildSub(Res, LHS, RHS);
2224     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2225 
2226     MI.eraseFromParent();
2227     return Legalized;
2228   }
2229   case G_USUBE: {
2230     Register Res = MI.getOperand(0).getReg();
2231     Register BorrowOut = MI.getOperand(1).getReg();
2232     Register LHS = MI.getOperand(2).getReg();
2233     Register RHS = MI.getOperand(3).getReg();
2234     Register BorrowIn = MI.getOperand(4).getReg();
2235 
2236     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2237     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2238     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2239     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2240 
2241     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2242     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2243     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2244     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2245     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2246     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2247 
2248     MI.eraseFromParent();
2249     return Legalized;
2250   }
2251   case G_UITOFP:
2252     return lowerUITOFP(MI, TypeIdx, Ty);
2253   case G_SITOFP:
2254     return lowerSITOFP(MI, TypeIdx, Ty);
2255   case G_FPTOUI:
2256     return lowerFPTOUI(MI, TypeIdx, Ty);
2257   case G_SMIN:
2258   case G_SMAX:
2259   case G_UMIN:
2260   case G_UMAX:
2261     return lowerMinMax(MI, TypeIdx, Ty);
2262   case G_FCOPYSIGN:
2263     return lowerFCopySign(MI, TypeIdx, Ty);
2264   case G_FMINNUM:
2265   case G_FMAXNUM:
2266     return lowerFMinNumMaxNum(MI);
2267   case G_UNMERGE_VALUES:
2268     return lowerUnmergeValues(MI);
2269   case TargetOpcode::G_SEXT_INREG: {
2270     assert(MI.getOperand(2).isImm() && "Expected immediate");
2271     int64_t SizeInBits = MI.getOperand(2).getImm();
2272 
2273     Register DstReg = MI.getOperand(0).getReg();
2274     Register SrcReg = MI.getOperand(1).getReg();
2275     LLT DstTy = MRI.getType(DstReg);
2276     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2277 
2278     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2279     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2280     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2281     MI.eraseFromParent();
2282     return Legalized;
2283   }
2284   case G_SHUFFLE_VECTOR:
2285     return lowerShuffleVector(MI);
2286   case G_DYN_STACKALLOC:
2287     return lowerDynStackAlloc(MI);
2288   case G_EXTRACT:
2289     return lowerExtract(MI);
2290   case G_INSERT:
2291     return lowerInsert(MI);
2292   }
2293 }
2294 
2295 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2296     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2297   SmallVector<Register, 2> DstRegs;
2298 
2299   unsigned NarrowSize = NarrowTy.getSizeInBits();
2300   Register DstReg = MI.getOperand(0).getReg();
2301   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2302   int NumParts = Size / NarrowSize;
2303   // FIXME: Don't know how to handle the situation where the small vectors
2304   // aren't all the same size yet.
2305   if (Size % NarrowSize != 0)
2306     return UnableToLegalize;
2307 
2308   for (int i = 0; i < NumParts; ++i) {
2309     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2310     MIRBuilder.buildUndef(TmpReg);
2311     DstRegs.push_back(TmpReg);
2312   }
2313 
2314   if (NarrowTy.isVector())
2315     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2316   else
2317     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2318 
2319   MI.eraseFromParent();
2320   return Legalized;
2321 }
2322 
2323 LegalizerHelper::LegalizeResult
2324 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2325                                           LLT NarrowTy) {
2326   const unsigned Opc = MI.getOpcode();
2327   const unsigned NumOps = MI.getNumOperands() - 1;
2328   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2329   const Register DstReg = MI.getOperand(0).getReg();
2330   const unsigned Flags = MI.getFlags();
2331   const LLT DstTy = MRI.getType(DstReg);
2332   const unsigned Size = DstTy.getSizeInBits();
2333   const int NumParts = Size / NarrowSize;
2334   const LLT EltTy = DstTy.getElementType();
2335   const unsigned EltSize = EltTy.getSizeInBits();
2336   const unsigned BitsForNumParts = NarrowSize * NumParts;
2337 
2338   // Check if we have any leftovers. If we do, then only handle the case where
2339   // the leftover is one element.
2340   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2341     return UnableToLegalize;
2342 
2343   if (BitsForNumParts != Size) {
2344     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2345     MIRBuilder.buildUndef(AccumDstReg);
2346 
2347     // Handle the pieces which evenly divide into the requested type with
2348     // extract/op/insert sequence.
2349     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2350       SmallVector<SrcOp, 4> SrcOps;
2351       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2352         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2353         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2354         SrcOps.push_back(PartOpReg);
2355       }
2356 
2357       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2358       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2359 
2360       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2361       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2362       AccumDstReg = PartInsertReg;
2363     }
2364 
2365     // Handle the remaining element sized leftover piece.
2366     SmallVector<SrcOp, 4> SrcOps;
2367     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2368       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2369       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2370                               BitsForNumParts);
2371       SrcOps.push_back(PartOpReg);
2372     }
2373 
2374     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2375     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2376     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2377     MI.eraseFromParent();
2378 
2379     return Legalized;
2380   }
2381 
2382   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2383 
2384   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2385 
2386   if (NumOps >= 2)
2387     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2388 
2389   if (NumOps >= 3)
2390     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2391 
2392   for (int i = 0; i < NumParts; ++i) {
2393     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2394 
2395     if (NumOps == 1)
2396       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2397     else if (NumOps == 2) {
2398       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2399     } else if (NumOps == 3) {
2400       MIRBuilder.buildInstr(Opc, {DstReg},
2401                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2402     }
2403 
2404     DstRegs.push_back(DstReg);
2405   }
2406 
2407   if (NarrowTy.isVector())
2408     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2409   else
2410     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2411 
2412   MI.eraseFromParent();
2413   return Legalized;
2414 }
2415 
2416 // Handle splitting vector operations which need to have the same number of
2417 // elements in each type index, but each type index may have a different element
2418 // type.
2419 //
2420 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2421 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2422 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2423 //
2424 // Also handles some irregular breakdown cases, e.g.
2425 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2426 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2427 //             s64 = G_SHL s64, s32
2428 LegalizerHelper::LegalizeResult
2429 LegalizerHelper::fewerElementsVectorMultiEltType(
2430   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2431   if (TypeIdx != 0)
2432     return UnableToLegalize;
2433 
2434   const LLT NarrowTy0 = NarrowTyArg;
2435   const unsigned NewNumElts =
2436       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2437 
2438   const Register DstReg = MI.getOperand(0).getReg();
2439   LLT DstTy = MRI.getType(DstReg);
2440   LLT LeftoverTy0;
2441 
2442   // All of the operands need to have the same number of elements, so if we can
2443   // determine a type breakdown for the result type, we can for all of the
2444   // source types.
2445   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2446   if (NumParts < 0)
2447     return UnableToLegalize;
2448 
2449   SmallVector<MachineInstrBuilder, 4> NewInsts;
2450 
2451   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2452   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2453 
2454   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2455     LLT LeftoverTy;
2456     Register SrcReg = MI.getOperand(I).getReg();
2457     LLT SrcTyI = MRI.getType(SrcReg);
2458     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2459     LLT LeftoverTyI;
2460 
2461     // Split this operand into the requested typed registers, and any leftover
2462     // required to reproduce the original type.
2463     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2464                       LeftoverRegs))
2465       return UnableToLegalize;
2466 
2467     if (I == 1) {
2468       // For the first operand, create an instruction for each part and setup
2469       // the result.
2470       for (Register PartReg : PartRegs) {
2471         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2472         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2473                                .addDef(PartDstReg)
2474                                .addUse(PartReg));
2475         DstRegs.push_back(PartDstReg);
2476       }
2477 
2478       for (Register LeftoverReg : LeftoverRegs) {
2479         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2480         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2481                                .addDef(PartDstReg)
2482                                .addUse(LeftoverReg));
2483         LeftoverDstRegs.push_back(PartDstReg);
2484       }
2485     } else {
2486       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2487 
2488       // Add the newly created operand splits to the existing instructions. The
2489       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2490       // pieces.
2491       unsigned InstCount = 0;
2492       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2493         NewInsts[InstCount++].addUse(PartRegs[J]);
2494       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2495         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2496     }
2497 
2498     PartRegs.clear();
2499     LeftoverRegs.clear();
2500   }
2501 
2502   // Insert the newly built operations and rebuild the result register.
2503   for (auto &MIB : NewInsts)
2504     MIRBuilder.insertInstr(MIB);
2505 
2506   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2507 
2508   MI.eraseFromParent();
2509   return Legalized;
2510 }
2511 
2512 LegalizerHelper::LegalizeResult
2513 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2514                                           LLT NarrowTy) {
2515   if (TypeIdx != 0)
2516     return UnableToLegalize;
2517 
2518   Register DstReg = MI.getOperand(0).getReg();
2519   Register SrcReg = MI.getOperand(1).getReg();
2520   LLT DstTy = MRI.getType(DstReg);
2521   LLT SrcTy = MRI.getType(SrcReg);
2522 
2523   LLT NarrowTy0 = NarrowTy;
2524   LLT NarrowTy1;
2525   unsigned NumParts;
2526 
2527   if (NarrowTy.isVector()) {
2528     // Uneven breakdown not handled.
2529     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2530     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2531       return UnableToLegalize;
2532 
2533     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2534   } else {
2535     NumParts = DstTy.getNumElements();
2536     NarrowTy1 = SrcTy.getElementType();
2537   }
2538 
2539   SmallVector<Register, 4> SrcRegs, DstRegs;
2540   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2541 
2542   for (unsigned I = 0; I < NumParts; ++I) {
2543     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2544     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2545       .addDef(DstReg)
2546       .addUse(SrcRegs[I]);
2547 
2548     NewInst->setFlags(MI.getFlags());
2549     DstRegs.push_back(DstReg);
2550   }
2551 
2552   if (NarrowTy.isVector())
2553     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2554   else
2555     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2556 
2557   MI.eraseFromParent();
2558   return Legalized;
2559 }
2560 
2561 LegalizerHelper::LegalizeResult
2562 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2563                                         LLT NarrowTy) {
2564   Register DstReg = MI.getOperand(0).getReg();
2565   Register Src0Reg = MI.getOperand(2).getReg();
2566   LLT DstTy = MRI.getType(DstReg);
2567   LLT SrcTy = MRI.getType(Src0Reg);
2568 
2569   unsigned NumParts;
2570   LLT NarrowTy0, NarrowTy1;
2571 
2572   if (TypeIdx == 0) {
2573     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2574     unsigned OldElts = DstTy.getNumElements();
2575 
2576     NarrowTy0 = NarrowTy;
2577     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2578     NarrowTy1 = NarrowTy.isVector() ?
2579       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2580       SrcTy.getElementType();
2581 
2582   } else {
2583     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2584     unsigned OldElts = SrcTy.getNumElements();
2585 
2586     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2587       NarrowTy.getNumElements();
2588     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2589                             DstTy.getScalarSizeInBits());
2590     NarrowTy1 = NarrowTy;
2591   }
2592 
2593   // FIXME: Don't know how to handle the situation where the small vectors
2594   // aren't all the same size yet.
2595   if (NarrowTy1.isVector() &&
2596       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2597     return UnableToLegalize;
2598 
2599   CmpInst::Predicate Pred
2600     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2601 
2602   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2603   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2604   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2605 
2606   for (unsigned I = 0; I < NumParts; ++I) {
2607     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2608     DstRegs.push_back(DstReg);
2609 
2610     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2611       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2612     else {
2613       MachineInstr *NewCmp
2614         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2615       NewCmp->setFlags(MI.getFlags());
2616     }
2617   }
2618 
2619   if (NarrowTy1.isVector())
2620     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2621   else
2622     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2623 
2624   MI.eraseFromParent();
2625   return Legalized;
2626 }
2627 
2628 LegalizerHelper::LegalizeResult
2629 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2630                                            LLT NarrowTy) {
2631   Register DstReg = MI.getOperand(0).getReg();
2632   Register CondReg = MI.getOperand(1).getReg();
2633 
2634   unsigned NumParts = 0;
2635   LLT NarrowTy0, NarrowTy1;
2636 
2637   LLT DstTy = MRI.getType(DstReg);
2638   LLT CondTy = MRI.getType(CondReg);
2639   unsigned Size = DstTy.getSizeInBits();
2640 
2641   assert(TypeIdx == 0 || CondTy.isVector());
2642 
2643   if (TypeIdx == 0) {
2644     NarrowTy0 = NarrowTy;
2645     NarrowTy1 = CondTy;
2646 
2647     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2648     // FIXME: Don't know how to handle the situation where the small vectors
2649     // aren't all the same size yet.
2650     if (Size % NarrowSize != 0)
2651       return UnableToLegalize;
2652 
2653     NumParts = Size / NarrowSize;
2654 
2655     // Need to break down the condition type
2656     if (CondTy.isVector()) {
2657       if (CondTy.getNumElements() == NumParts)
2658         NarrowTy1 = CondTy.getElementType();
2659       else
2660         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2661                                 CondTy.getScalarSizeInBits());
2662     }
2663   } else {
2664     NumParts = CondTy.getNumElements();
2665     if (NarrowTy.isVector()) {
2666       // TODO: Handle uneven breakdown.
2667       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2668         return UnableToLegalize;
2669 
2670       return UnableToLegalize;
2671     } else {
2672       NarrowTy0 = DstTy.getElementType();
2673       NarrowTy1 = NarrowTy;
2674     }
2675   }
2676 
2677   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2678   if (CondTy.isVector())
2679     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2680 
2681   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2682   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2683 
2684   for (unsigned i = 0; i < NumParts; ++i) {
2685     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2686     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2687                            Src1Regs[i], Src2Regs[i]);
2688     DstRegs.push_back(DstReg);
2689   }
2690 
2691   if (NarrowTy0.isVector())
2692     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2693   else
2694     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2695 
2696   MI.eraseFromParent();
2697   return Legalized;
2698 }
2699 
2700 LegalizerHelper::LegalizeResult
2701 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2702                                         LLT NarrowTy) {
2703   const Register DstReg = MI.getOperand(0).getReg();
2704   LLT PhiTy = MRI.getType(DstReg);
2705   LLT LeftoverTy;
2706 
2707   // All of the operands need to have the same number of elements, so if we can
2708   // determine a type breakdown for the result type, we can for all of the
2709   // source types.
2710   int NumParts, NumLeftover;
2711   std::tie(NumParts, NumLeftover)
2712     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2713   if (NumParts < 0)
2714     return UnableToLegalize;
2715 
2716   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2717   SmallVector<MachineInstrBuilder, 4> NewInsts;
2718 
2719   const int TotalNumParts = NumParts + NumLeftover;
2720 
2721   // Insert the new phis in the result block first.
2722   for (int I = 0; I != TotalNumParts; ++I) {
2723     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2724     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2725     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2726                        .addDef(PartDstReg));
2727     if (I < NumParts)
2728       DstRegs.push_back(PartDstReg);
2729     else
2730       LeftoverDstRegs.push_back(PartDstReg);
2731   }
2732 
2733   MachineBasicBlock *MBB = MI.getParent();
2734   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2735   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2736 
2737   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2738 
2739   // Insert code to extract the incoming values in each predecessor block.
2740   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2741     PartRegs.clear();
2742     LeftoverRegs.clear();
2743 
2744     Register SrcReg = MI.getOperand(I).getReg();
2745     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2746     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2747 
2748     LLT Unused;
2749     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2750                       LeftoverRegs))
2751       return UnableToLegalize;
2752 
2753     // Add the newly created operand splits to the existing instructions. The
2754     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2755     // pieces.
2756     for (int J = 0; J != TotalNumParts; ++J) {
2757       MachineInstrBuilder MIB = NewInsts[J];
2758       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2759       MIB.addMBB(&OpMBB);
2760     }
2761   }
2762 
2763   MI.eraseFromParent();
2764   return Legalized;
2765 }
2766 
2767 LegalizerHelper::LegalizeResult
2768 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2769                                                   unsigned TypeIdx,
2770                                                   LLT NarrowTy) {
2771   if (TypeIdx != 1)
2772     return UnableToLegalize;
2773 
2774   const int NumDst = MI.getNumOperands() - 1;
2775   const Register SrcReg = MI.getOperand(NumDst).getReg();
2776   LLT SrcTy = MRI.getType(SrcReg);
2777 
2778   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2779 
2780   // TODO: Create sequence of extracts.
2781   if (DstTy == NarrowTy)
2782     return UnableToLegalize;
2783 
2784   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2785   if (DstTy == GCDTy) {
2786     // This would just be a copy of the same unmerge.
2787     // TODO: Create extracts, pad with undef and create intermediate merges.
2788     return UnableToLegalize;
2789   }
2790 
2791   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2792   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2793   const int PartsPerUnmerge = NumDst / NumUnmerge;
2794 
2795   for (int I = 0; I != NumUnmerge; ++I) {
2796     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2797 
2798     for (int J = 0; J != PartsPerUnmerge; ++J)
2799       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2800     MIB.addUse(Unmerge.getReg(I));
2801   }
2802 
2803   MI.eraseFromParent();
2804   return Legalized;
2805 }
2806 
2807 LegalizerHelper::LegalizeResult
2808 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
2809                                                 unsigned TypeIdx,
2810                                                 LLT NarrowTy) {
2811   assert(TypeIdx == 0 && "not a vector type index");
2812   Register DstReg = MI.getOperand(0).getReg();
2813   LLT DstTy = MRI.getType(DstReg);
2814   LLT SrcTy = DstTy.getElementType();
2815 
2816   int DstNumElts = DstTy.getNumElements();
2817   int NarrowNumElts = NarrowTy.getNumElements();
2818   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
2819   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
2820 
2821   SmallVector<Register, 8> ConcatOps;
2822   SmallVector<Register, 8> SubBuildVector;
2823 
2824   Register UndefReg;
2825   if (WidenedDstTy != DstTy)
2826     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
2827 
2828   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
2829   // necessary.
2830   //
2831   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
2832   //   -> <2 x s16>
2833   //
2834   // %4:_(s16) = G_IMPLICIT_DEF
2835   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
2836   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
2837   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
2838   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
2839   for (int I = 0; I != NumConcat; ++I) {
2840     for (int J = 0; J != NarrowNumElts; ++J) {
2841       int SrcIdx = NarrowNumElts * I + J;
2842 
2843       if (SrcIdx < DstNumElts) {
2844         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2845         SubBuildVector.push_back(SrcReg);
2846       } else
2847         SubBuildVector.push_back(UndefReg);
2848     }
2849 
2850     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
2851     ConcatOps.push_back(BuildVec.getReg(0));
2852     SubBuildVector.clear();
2853   }
2854 
2855   if (DstTy == WidenedDstTy)
2856     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
2857   else {
2858     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
2859     MIRBuilder.buildExtract(DstReg, Concat, 0);
2860   }
2861 
2862   MI.eraseFromParent();
2863   return Legalized;
2864 }
2865 
2866 LegalizerHelper::LegalizeResult
2867 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2868                                       LLT NarrowTy) {
2869   // FIXME: Don't know how to handle secondary types yet.
2870   if (TypeIdx != 0)
2871     return UnableToLegalize;
2872 
2873   MachineMemOperand *MMO = *MI.memoperands_begin();
2874 
2875   // This implementation doesn't work for atomics. Give up instead of doing
2876   // something invalid.
2877   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2878       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2879     return UnableToLegalize;
2880 
2881   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2882   Register ValReg = MI.getOperand(0).getReg();
2883   Register AddrReg = MI.getOperand(1).getReg();
2884   LLT ValTy = MRI.getType(ValReg);
2885 
2886   int NumParts = -1;
2887   int NumLeftover = -1;
2888   LLT LeftoverTy;
2889   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2890   if (IsLoad) {
2891     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2892   } else {
2893     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2894                      NarrowLeftoverRegs)) {
2895       NumParts = NarrowRegs.size();
2896       NumLeftover = NarrowLeftoverRegs.size();
2897     }
2898   }
2899 
2900   if (NumParts == -1)
2901     return UnableToLegalize;
2902 
2903   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2904 
2905   unsigned TotalSize = ValTy.getSizeInBits();
2906 
2907   // Split the load/store into PartTy sized pieces starting at Offset. If this
2908   // is a load, return the new registers in ValRegs. For a store, each elements
2909   // of ValRegs should be PartTy. Returns the next offset that needs to be
2910   // handled.
2911   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2912                              unsigned Offset) -> unsigned {
2913     MachineFunction &MF = MIRBuilder.getMF();
2914     unsigned PartSize = PartTy.getSizeInBits();
2915     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2916          Offset += PartSize, ++Idx) {
2917       unsigned ByteSize = PartSize / 8;
2918       unsigned ByteOffset = Offset / 8;
2919       Register NewAddrReg;
2920 
2921       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2922 
2923       MachineMemOperand *NewMMO =
2924         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2925 
2926       if (IsLoad) {
2927         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2928         ValRegs.push_back(Dst);
2929         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2930       } else {
2931         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2932       }
2933     }
2934 
2935     return Offset;
2936   };
2937 
2938   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2939 
2940   // Handle the rest of the register if this isn't an even type breakdown.
2941   if (LeftoverTy.isValid())
2942     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2943 
2944   if (IsLoad) {
2945     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2946                 LeftoverTy, NarrowLeftoverRegs);
2947   }
2948 
2949   MI.eraseFromParent();
2950   return Legalized;
2951 }
2952 
2953 LegalizerHelper::LegalizeResult
2954 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2955                                      LLT NarrowTy) {
2956   using namespace TargetOpcode;
2957 
2958   MIRBuilder.setInstr(MI);
2959   switch (MI.getOpcode()) {
2960   case G_IMPLICIT_DEF:
2961     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2962   case G_AND:
2963   case G_OR:
2964   case G_XOR:
2965   case G_ADD:
2966   case G_SUB:
2967   case G_MUL:
2968   case G_SMULH:
2969   case G_UMULH:
2970   case G_FADD:
2971   case G_FMUL:
2972   case G_FSUB:
2973   case G_FNEG:
2974   case G_FABS:
2975   case G_FCANONICALIZE:
2976   case G_FDIV:
2977   case G_FREM:
2978   case G_FMA:
2979   case G_FMAD:
2980   case G_FPOW:
2981   case G_FEXP:
2982   case G_FEXP2:
2983   case G_FLOG:
2984   case G_FLOG2:
2985   case G_FLOG10:
2986   case G_FNEARBYINT:
2987   case G_FCEIL:
2988   case G_FFLOOR:
2989   case G_FRINT:
2990   case G_INTRINSIC_ROUND:
2991   case G_INTRINSIC_TRUNC:
2992   case G_FCOS:
2993   case G_FSIN:
2994   case G_FSQRT:
2995   case G_BSWAP:
2996   case G_BITREVERSE:
2997   case G_SDIV:
2998   case G_SMIN:
2999   case G_SMAX:
3000   case G_UMIN:
3001   case G_UMAX:
3002   case G_FMINNUM:
3003   case G_FMAXNUM:
3004   case G_FMINNUM_IEEE:
3005   case G_FMAXNUM_IEEE:
3006   case G_FMINIMUM:
3007   case G_FMAXIMUM:
3008     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3009   case G_SHL:
3010   case G_LSHR:
3011   case G_ASHR:
3012   case G_CTLZ:
3013   case G_CTLZ_ZERO_UNDEF:
3014   case G_CTTZ:
3015   case G_CTTZ_ZERO_UNDEF:
3016   case G_CTPOP:
3017   case G_FCOPYSIGN:
3018     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3019   case G_ZEXT:
3020   case G_SEXT:
3021   case G_ANYEXT:
3022   case G_FPEXT:
3023   case G_FPTRUNC:
3024   case G_SITOFP:
3025   case G_UITOFP:
3026   case G_FPTOSI:
3027   case G_FPTOUI:
3028   case G_INTTOPTR:
3029   case G_PTRTOINT:
3030   case G_ADDRSPACE_CAST:
3031     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3032   case G_ICMP:
3033   case G_FCMP:
3034     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3035   case G_SELECT:
3036     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3037   case G_PHI:
3038     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3039   case G_UNMERGE_VALUES:
3040     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3041   case G_BUILD_VECTOR:
3042     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3043   case G_LOAD:
3044   case G_STORE:
3045     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3046   default:
3047     return UnableToLegalize;
3048   }
3049 }
3050 
3051 LegalizerHelper::LegalizeResult
3052 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3053                                              const LLT HalfTy, const LLT AmtTy) {
3054 
3055   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3056   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3057   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3058 
3059   if (Amt.isNullValue()) {
3060     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3061     MI.eraseFromParent();
3062     return Legalized;
3063   }
3064 
3065   LLT NVT = HalfTy;
3066   unsigned NVTBits = HalfTy.getSizeInBits();
3067   unsigned VTBits = 2 * NVTBits;
3068 
3069   SrcOp Lo(Register(0)), Hi(Register(0));
3070   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3071     if (Amt.ugt(VTBits)) {
3072       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3073     } else if (Amt.ugt(NVTBits)) {
3074       Lo = MIRBuilder.buildConstant(NVT, 0);
3075       Hi = MIRBuilder.buildShl(NVT, InL,
3076                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3077     } else if (Amt == NVTBits) {
3078       Lo = MIRBuilder.buildConstant(NVT, 0);
3079       Hi = InL;
3080     } else {
3081       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3082       auto OrLHS =
3083           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3084       auto OrRHS = MIRBuilder.buildLShr(
3085           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3086       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3087     }
3088   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3089     if (Amt.ugt(VTBits)) {
3090       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3091     } else if (Amt.ugt(NVTBits)) {
3092       Lo = MIRBuilder.buildLShr(NVT, InH,
3093                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3094       Hi = MIRBuilder.buildConstant(NVT, 0);
3095     } else if (Amt == NVTBits) {
3096       Lo = InH;
3097       Hi = MIRBuilder.buildConstant(NVT, 0);
3098     } else {
3099       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3100 
3101       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3102       auto OrRHS = MIRBuilder.buildShl(
3103           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3104 
3105       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3106       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3107     }
3108   } else {
3109     if (Amt.ugt(VTBits)) {
3110       Hi = Lo = MIRBuilder.buildAShr(
3111           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3112     } else if (Amt.ugt(NVTBits)) {
3113       Lo = MIRBuilder.buildAShr(NVT, InH,
3114                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3115       Hi = MIRBuilder.buildAShr(NVT, InH,
3116                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3117     } else if (Amt == NVTBits) {
3118       Lo = InH;
3119       Hi = MIRBuilder.buildAShr(NVT, InH,
3120                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3121     } else {
3122       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3123 
3124       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3125       auto OrRHS = MIRBuilder.buildShl(
3126           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3127 
3128       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3129       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3130     }
3131   }
3132 
3133   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3134   MI.eraseFromParent();
3135 
3136   return Legalized;
3137 }
3138 
3139 // TODO: Optimize if constant shift amount.
3140 LegalizerHelper::LegalizeResult
3141 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3142                                    LLT RequestedTy) {
3143   if (TypeIdx == 1) {
3144     Observer.changingInstr(MI);
3145     narrowScalarSrc(MI, RequestedTy, 2);
3146     Observer.changedInstr(MI);
3147     return Legalized;
3148   }
3149 
3150   Register DstReg = MI.getOperand(0).getReg();
3151   LLT DstTy = MRI.getType(DstReg);
3152   if (DstTy.isVector())
3153     return UnableToLegalize;
3154 
3155   Register Amt = MI.getOperand(2).getReg();
3156   LLT ShiftAmtTy = MRI.getType(Amt);
3157   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3158   if (DstEltSize % 2 != 0)
3159     return UnableToLegalize;
3160 
3161   // Ignore the input type. We can only go to exactly half the size of the
3162   // input. If that isn't small enough, the resulting pieces will be further
3163   // legalized.
3164   const unsigned NewBitSize = DstEltSize / 2;
3165   const LLT HalfTy = LLT::scalar(NewBitSize);
3166   const LLT CondTy = LLT::scalar(1);
3167 
3168   if (const MachineInstr *KShiftAmt =
3169           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3170     return narrowScalarShiftByConstant(
3171         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3172   }
3173 
3174   // TODO: Expand with known bits.
3175 
3176   // Handle the fully general expansion by an unknown amount.
3177   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3178 
3179   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3180   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3181   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3182 
3183   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3184   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3185 
3186   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3187   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3188   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3189 
3190   Register ResultRegs[2];
3191   switch (MI.getOpcode()) {
3192   case TargetOpcode::G_SHL: {
3193     // Short: ShAmt < NewBitSize
3194     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3195 
3196     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3197     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3198     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3199 
3200     // Long: ShAmt >= NewBitSize
3201     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3202     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3203 
3204     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3205     auto Hi = MIRBuilder.buildSelect(
3206         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3207 
3208     ResultRegs[0] = Lo.getReg(0);
3209     ResultRegs[1] = Hi.getReg(0);
3210     break;
3211   }
3212   case TargetOpcode::G_LSHR:
3213   case TargetOpcode::G_ASHR: {
3214     // Short: ShAmt < NewBitSize
3215     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3216 
3217     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3218     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3219     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3220 
3221     // Long: ShAmt >= NewBitSize
3222     MachineInstrBuilder HiL;
3223     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3224       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3225     } else {
3226       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3227       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3228     }
3229     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3230                                      {InH, AmtExcess});     // Lo from Hi part.
3231 
3232     auto Lo = MIRBuilder.buildSelect(
3233         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3234 
3235     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3236 
3237     ResultRegs[0] = Lo.getReg(0);
3238     ResultRegs[1] = Hi.getReg(0);
3239     break;
3240   }
3241   default:
3242     llvm_unreachable("not a shift");
3243   }
3244 
3245   MIRBuilder.buildMerge(DstReg, ResultRegs);
3246   MI.eraseFromParent();
3247   return Legalized;
3248 }
3249 
3250 LegalizerHelper::LegalizeResult
3251 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3252                                        LLT MoreTy) {
3253   assert(TypeIdx == 0 && "Expecting only Idx 0");
3254 
3255   Observer.changingInstr(MI);
3256   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3257     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3258     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3259     moreElementsVectorSrc(MI, MoreTy, I);
3260   }
3261 
3262   MachineBasicBlock &MBB = *MI.getParent();
3263   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3264   moreElementsVectorDst(MI, MoreTy, 0);
3265   Observer.changedInstr(MI);
3266   return Legalized;
3267 }
3268 
3269 LegalizerHelper::LegalizeResult
3270 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3271                                     LLT MoreTy) {
3272   MIRBuilder.setInstr(MI);
3273   unsigned Opc = MI.getOpcode();
3274   switch (Opc) {
3275   case TargetOpcode::G_IMPLICIT_DEF:
3276   case TargetOpcode::G_LOAD: {
3277     if (TypeIdx != 0)
3278       return UnableToLegalize;
3279     Observer.changingInstr(MI);
3280     moreElementsVectorDst(MI, MoreTy, 0);
3281     Observer.changedInstr(MI);
3282     return Legalized;
3283   }
3284   case TargetOpcode::G_STORE:
3285     if (TypeIdx != 0)
3286       return UnableToLegalize;
3287     Observer.changingInstr(MI);
3288     moreElementsVectorSrc(MI, MoreTy, 0);
3289     Observer.changedInstr(MI);
3290     return Legalized;
3291   case TargetOpcode::G_AND:
3292   case TargetOpcode::G_OR:
3293   case TargetOpcode::G_XOR:
3294   case TargetOpcode::G_SMIN:
3295   case TargetOpcode::G_SMAX:
3296   case TargetOpcode::G_UMIN:
3297   case TargetOpcode::G_UMAX: {
3298     Observer.changingInstr(MI);
3299     moreElementsVectorSrc(MI, MoreTy, 1);
3300     moreElementsVectorSrc(MI, MoreTy, 2);
3301     moreElementsVectorDst(MI, MoreTy, 0);
3302     Observer.changedInstr(MI);
3303     return Legalized;
3304   }
3305   case TargetOpcode::G_EXTRACT:
3306     if (TypeIdx != 1)
3307       return UnableToLegalize;
3308     Observer.changingInstr(MI);
3309     moreElementsVectorSrc(MI, MoreTy, 1);
3310     Observer.changedInstr(MI);
3311     return Legalized;
3312   case TargetOpcode::G_INSERT:
3313     if (TypeIdx != 0)
3314       return UnableToLegalize;
3315     Observer.changingInstr(MI);
3316     moreElementsVectorSrc(MI, MoreTy, 1);
3317     moreElementsVectorDst(MI, MoreTy, 0);
3318     Observer.changedInstr(MI);
3319     return Legalized;
3320   case TargetOpcode::G_SELECT:
3321     if (TypeIdx != 0)
3322       return UnableToLegalize;
3323     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3324       return UnableToLegalize;
3325 
3326     Observer.changingInstr(MI);
3327     moreElementsVectorSrc(MI, MoreTy, 2);
3328     moreElementsVectorSrc(MI, MoreTy, 3);
3329     moreElementsVectorDst(MI, MoreTy, 0);
3330     Observer.changedInstr(MI);
3331     return Legalized;
3332   case TargetOpcode::G_UNMERGE_VALUES: {
3333     if (TypeIdx != 1)
3334       return UnableToLegalize;
3335 
3336     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3337     int NumDst = MI.getNumOperands() - 1;
3338     moreElementsVectorSrc(MI, MoreTy, NumDst);
3339 
3340     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3341     for (int I = 0; I != NumDst; ++I)
3342       MIB.addDef(MI.getOperand(I).getReg());
3343 
3344     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3345     for (int I = NumDst; I != NewNumDst; ++I)
3346       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3347 
3348     MIB.addUse(MI.getOperand(NumDst).getReg());
3349     MI.eraseFromParent();
3350     return Legalized;
3351   }
3352   case TargetOpcode::G_PHI:
3353     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3354   default:
3355     return UnableToLegalize;
3356   }
3357 }
3358 
3359 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3360                                         ArrayRef<Register> Src1Regs,
3361                                         ArrayRef<Register> Src2Regs,
3362                                         LLT NarrowTy) {
3363   MachineIRBuilder &B = MIRBuilder;
3364   unsigned SrcParts = Src1Regs.size();
3365   unsigned DstParts = DstRegs.size();
3366 
3367   unsigned DstIdx = 0; // Low bits of the result.
3368   Register FactorSum =
3369       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3370   DstRegs[DstIdx] = FactorSum;
3371 
3372   unsigned CarrySumPrevDstIdx;
3373   SmallVector<Register, 4> Factors;
3374 
3375   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3376     // Collect low parts of muls for DstIdx.
3377     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3378          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3379       MachineInstrBuilder Mul =
3380           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3381       Factors.push_back(Mul.getReg(0));
3382     }
3383     // Collect high parts of muls from previous DstIdx.
3384     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3385          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3386       MachineInstrBuilder Umulh =
3387           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3388       Factors.push_back(Umulh.getReg(0));
3389     }
3390     // Add CarrySum from additions calculated for previous DstIdx.
3391     if (DstIdx != 1) {
3392       Factors.push_back(CarrySumPrevDstIdx);
3393     }
3394 
3395     Register CarrySum;
3396     // Add all factors and accumulate all carries into CarrySum.
3397     if (DstIdx != DstParts - 1) {
3398       MachineInstrBuilder Uaddo =
3399           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3400       FactorSum = Uaddo.getReg(0);
3401       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3402       for (unsigned i = 2; i < Factors.size(); ++i) {
3403         MachineInstrBuilder Uaddo =
3404             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3405         FactorSum = Uaddo.getReg(0);
3406         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3407         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3408       }
3409     } else {
3410       // Since value for the next index is not calculated, neither is CarrySum.
3411       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3412       for (unsigned i = 2; i < Factors.size(); ++i)
3413         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3414     }
3415 
3416     CarrySumPrevDstIdx = CarrySum;
3417     DstRegs[DstIdx] = FactorSum;
3418     Factors.clear();
3419   }
3420 }
3421 
3422 LegalizerHelper::LegalizeResult
3423 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3424   Register DstReg = MI.getOperand(0).getReg();
3425   Register Src1 = MI.getOperand(1).getReg();
3426   Register Src2 = MI.getOperand(2).getReg();
3427 
3428   LLT Ty = MRI.getType(DstReg);
3429   if (Ty.isVector())
3430     return UnableToLegalize;
3431 
3432   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3433   unsigned DstSize = Ty.getSizeInBits();
3434   unsigned NarrowSize = NarrowTy.getSizeInBits();
3435   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3436     return UnableToLegalize;
3437 
3438   unsigned NumDstParts = DstSize / NarrowSize;
3439   unsigned NumSrcParts = SrcSize / NarrowSize;
3440   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3441   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3442 
3443   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3444   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3445   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3446   DstTmpRegs.resize(DstTmpParts);
3447   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3448 
3449   // Take only high half of registers if this is high mul.
3450   ArrayRef<Register> DstRegs(
3451       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3452   MIRBuilder.buildMerge(DstReg, DstRegs);
3453   MI.eraseFromParent();
3454   return Legalized;
3455 }
3456 
3457 LegalizerHelper::LegalizeResult
3458 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3459                                      LLT NarrowTy) {
3460   if (TypeIdx != 1)
3461     return UnableToLegalize;
3462 
3463   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3464 
3465   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3466   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3467   // NarrowSize.
3468   if (SizeOp1 % NarrowSize != 0)
3469     return UnableToLegalize;
3470   int NumParts = SizeOp1 / NarrowSize;
3471 
3472   SmallVector<Register, 2> SrcRegs, DstRegs;
3473   SmallVector<uint64_t, 2> Indexes;
3474   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3475 
3476   Register OpReg = MI.getOperand(0).getReg();
3477   uint64_t OpStart = MI.getOperand(2).getImm();
3478   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3479   for (int i = 0; i < NumParts; ++i) {
3480     unsigned SrcStart = i * NarrowSize;
3481 
3482     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3483       // No part of the extract uses this subregister, ignore it.
3484       continue;
3485     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3486       // The entire subregister is extracted, forward the value.
3487       DstRegs.push_back(SrcRegs[i]);
3488       continue;
3489     }
3490 
3491     // OpSegStart is where this destination segment would start in OpReg if it
3492     // extended infinitely in both directions.
3493     int64_t ExtractOffset;
3494     uint64_t SegSize;
3495     if (OpStart < SrcStart) {
3496       ExtractOffset = 0;
3497       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3498     } else {
3499       ExtractOffset = OpStart - SrcStart;
3500       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3501     }
3502 
3503     Register SegReg = SrcRegs[i];
3504     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3505       // A genuine extract is needed.
3506       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3507       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3508     }
3509 
3510     DstRegs.push_back(SegReg);
3511   }
3512 
3513   Register DstReg = MI.getOperand(0).getReg();
3514   if(MRI.getType(DstReg).isVector())
3515     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3516   else
3517     MIRBuilder.buildMerge(DstReg, DstRegs);
3518   MI.eraseFromParent();
3519   return Legalized;
3520 }
3521 
3522 LegalizerHelper::LegalizeResult
3523 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3524                                     LLT NarrowTy) {
3525   // FIXME: Don't know how to handle secondary types yet.
3526   if (TypeIdx != 0)
3527     return UnableToLegalize;
3528 
3529   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3530   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3531 
3532   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3533   // NarrowSize.
3534   if (SizeOp0 % NarrowSize != 0)
3535     return UnableToLegalize;
3536 
3537   int NumParts = SizeOp0 / NarrowSize;
3538 
3539   SmallVector<Register, 2> SrcRegs, DstRegs;
3540   SmallVector<uint64_t, 2> Indexes;
3541   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3542 
3543   Register OpReg = MI.getOperand(2).getReg();
3544   uint64_t OpStart = MI.getOperand(3).getImm();
3545   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3546   for (int i = 0; i < NumParts; ++i) {
3547     unsigned DstStart = i * NarrowSize;
3548 
3549     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3550       // No part of the insert affects this subregister, forward the original.
3551       DstRegs.push_back(SrcRegs[i]);
3552       continue;
3553     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3554       // The entire subregister is defined by this insert, forward the new
3555       // value.
3556       DstRegs.push_back(OpReg);
3557       continue;
3558     }
3559 
3560     // OpSegStart is where this destination segment would start in OpReg if it
3561     // extended infinitely in both directions.
3562     int64_t ExtractOffset, InsertOffset;
3563     uint64_t SegSize;
3564     if (OpStart < DstStart) {
3565       InsertOffset = 0;
3566       ExtractOffset = DstStart - OpStart;
3567       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3568     } else {
3569       InsertOffset = OpStart - DstStart;
3570       ExtractOffset = 0;
3571       SegSize =
3572         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3573     }
3574 
3575     Register SegReg = OpReg;
3576     if (ExtractOffset != 0 || SegSize != OpSize) {
3577       // A genuine extract is needed.
3578       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3579       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3580     }
3581 
3582     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3583     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3584     DstRegs.push_back(DstReg);
3585   }
3586 
3587   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3588   Register DstReg = MI.getOperand(0).getReg();
3589   if(MRI.getType(DstReg).isVector())
3590     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3591   else
3592     MIRBuilder.buildMerge(DstReg, DstRegs);
3593   MI.eraseFromParent();
3594   return Legalized;
3595 }
3596 
3597 LegalizerHelper::LegalizeResult
3598 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3599                                    LLT NarrowTy) {
3600   Register DstReg = MI.getOperand(0).getReg();
3601   LLT DstTy = MRI.getType(DstReg);
3602 
3603   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3604 
3605   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3606   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3607   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3608   LLT LeftoverTy;
3609   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3610                     Src0Regs, Src0LeftoverRegs))
3611     return UnableToLegalize;
3612 
3613   LLT Unused;
3614   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3615                     Src1Regs, Src1LeftoverRegs))
3616     llvm_unreachable("inconsistent extractParts result");
3617 
3618   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3619     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3620                                         {Src0Regs[I], Src1Regs[I]});
3621     DstRegs.push_back(Inst->getOperand(0).getReg());
3622   }
3623 
3624   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3625     auto Inst = MIRBuilder.buildInstr(
3626       MI.getOpcode(),
3627       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3628     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3629   }
3630 
3631   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3632               LeftoverTy, DstLeftoverRegs);
3633 
3634   MI.eraseFromParent();
3635   return Legalized;
3636 }
3637 
3638 LegalizerHelper::LegalizeResult
3639 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3640                                     LLT NarrowTy) {
3641   if (TypeIdx != 0)
3642     return UnableToLegalize;
3643 
3644   Register CondReg = MI.getOperand(1).getReg();
3645   LLT CondTy = MRI.getType(CondReg);
3646   if (CondTy.isVector()) // TODO: Handle vselect
3647     return UnableToLegalize;
3648 
3649   Register DstReg = MI.getOperand(0).getReg();
3650   LLT DstTy = MRI.getType(DstReg);
3651 
3652   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3653   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3654   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3655   LLT LeftoverTy;
3656   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3657                     Src1Regs, Src1LeftoverRegs))
3658     return UnableToLegalize;
3659 
3660   LLT Unused;
3661   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3662                     Src2Regs, Src2LeftoverRegs))
3663     llvm_unreachable("inconsistent extractParts result");
3664 
3665   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3666     auto Select = MIRBuilder.buildSelect(NarrowTy,
3667                                          CondReg, Src1Regs[I], Src2Regs[I]);
3668     DstRegs.push_back(Select->getOperand(0).getReg());
3669   }
3670 
3671   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3672     auto Select = MIRBuilder.buildSelect(
3673       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3674     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3675   }
3676 
3677   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3678               LeftoverTy, DstLeftoverRegs);
3679 
3680   MI.eraseFromParent();
3681   return Legalized;
3682 }
3683 
3684 LegalizerHelper::LegalizeResult
3685 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3686   unsigned Opc = MI.getOpcode();
3687   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3688   auto isSupported = [this](const LegalityQuery &Q) {
3689     auto QAction = LI.getAction(Q).Action;
3690     return QAction == Legal || QAction == Libcall || QAction == Custom;
3691   };
3692   switch (Opc) {
3693   default:
3694     return UnableToLegalize;
3695   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3696     // This trivially expands to CTLZ.
3697     Observer.changingInstr(MI);
3698     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3699     Observer.changedInstr(MI);
3700     return Legalized;
3701   }
3702   case TargetOpcode::G_CTLZ: {
3703     Register SrcReg = MI.getOperand(1).getReg();
3704     unsigned Len = Ty.getSizeInBits();
3705     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3706       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3707       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3708                                              {Ty}, {SrcReg});
3709       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3710       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3711       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3712                                           SrcReg, MIBZero);
3713       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3714                              MIBCtlzZU);
3715       MI.eraseFromParent();
3716       return Legalized;
3717     }
3718     // for now, we do this:
3719     // NewLen = NextPowerOf2(Len);
3720     // x = x | (x >> 1);
3721     // x = x | (x >> 2);
3722     // ...
3723     // x = x | (x >>16);
3724     // x = x | (x >>32); // for 64-bit input
3725     // Upto NewLen/2
3726     // return Len - popcount(x);
3727     //
3728     // Ref: "Hacker's Delight" by Henry Warren
3729     Register Op = SrcReg;
3730     unsigned NewLen = PowerOf2Ceil(Len);
3731     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3732       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3733       auto MIBOp = MIRBuilder.buildInstr(
3734           TargetOpcode::G_OR, {Ty},
3735           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3736                                      {Op, MIBShiftAmt})});
3737       Op = MIBOp->getOperand(0).getReg();
3738     }
3739     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3740     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3741                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3742     MI.eraseFromParent();
3743     return Legalized;
3744   }
3745   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3746     // This trivially expands to CTTZ.
3747     Observer.changingInstr(MI);
3748     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3749     Observer.changedInstr(MI);
3750     return Legalized;
3751   }
3752   case TargetOpcode::G_CTTZ: {
3753     Register SrcReg = MI.getOperand(1).getReg();
3754     unsigned Len = Ty.getSizeInBits();
3755     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3756       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3757       // zero.
3758       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3759                                              {Ty}, {SrcReg});
3760       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3761       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3762       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3763                                           SrcReg, MIBZero);
3764       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3765                              MIBCttzZU);
3766       MI.eraseFromParent();
3767       return Legalized;
3768     }
3769     // for now, we use: { return popcount(~x & (x - 1)); }
3770     // unless the target has ctlz but not ctpop, in which case we use:
3771     // { return 32 - nlz(~x & (x-1)); }
3772     // Ref: "Hacker's Delight" by Henry Warren
3773     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3774     auto MIBNot =
3775         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3776     auto MIBTmp = MIRBuilder.buildInstr(
3777         TargetOpcode::G_AND, {Ty},
3778         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3779                                        {SrcReg, MIBCstNeg1})});
3780     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3781         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3782       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3783       MIRBuilder.buildInstr(
3784           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3785           {MIBCstLen,
3786            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3787       MI.eraseFromParent();
3788       return Legalized;
3789     }
3790     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3791     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3792     return Legalized;
3793   }
3794   }
3795 }
3796 
3797 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3798 // representation.
3799 LegalizerHelper::LegalizeResult
3800 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3801   Register Dst = MI.getOperand(0).getReg();
3802   Register Src = MI.getOperand(1).getReg();
3803   const LLT S64 = LLT::scalar(64);
3804   const LLT S32 = LLT::scalar(32);
3805   const LLT S1 = LLT::scalar(1);
3806 
3807   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3808 
3809   // unsigned cul2f(ulong u) {
3810   //   uint lz = clz(u);
3811   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3812   //   u = (u << lz) & 0x7fffffffffffffffUL;
3813   //   ulong t = u & 0xffffffffffUL;
3814   //   uint v = (e << 23) | (uint)(u >> 40);
3815   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3816   //   return as_float(v + r);
3817   // }
3818 
3819   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3820   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3821 
3822   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3823 
3824   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3825   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3826 
3827   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3828   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3829 
3830   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3831   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3832 
3833   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3834 
3835   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3836   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3837 
3838   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3839   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3840   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3841 
3842   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3843   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3844   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3845   auto One = MIRBuilder.buildConstant(S32, 1);
3846 
3847   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3848   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3849   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3850   MIRBuilder.buildAdd(Dst, V, R);
3851 
3852   return Legalized;
3853 }
3854 
3855 LegalizerHelper::LegalizeResult
3856 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3857   Register Dst = MI.getOperand(0).getReg();
3858   Register Src = MI.getOperand(1).getReg();
3859   LLT DstTy = MRI.getType(Dst);
3860   LLT SrcTy = MRI.getType(Src);
3861 
3862   if (SrcTy == LLT::scalar(1)) {
3863     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
3864     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3865     MIRBuilder.buildSelect(Dst, Src, True, False);
3866     MI.eraseFromParent();
3867     return Legalized;
3868   }
3869 
3870   if (SrcTy != LLT::scalar(64))
3871     return UnableToLegalize;
3872 
3873   if (DstTy == LLT::scalar(32)) {
3874     // TODO: SelectionDAG has several alternative expansions to port which may
3875     // be more reasonble depending on the available instructions. If a target
3876     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3877     // intermediate type, this is probably worse.
3878     return lowerU64ToF32BitOps(MI);
3879   }
3880 
3881   return UnableToLegalize;
3882 }
3883 
3884 LegalizerHelper::LegalizeResult
3885 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3886   Register Dst = MI.getOperand(0).getReg();
3887   Register Src = MI.getOperand(1).getReg();
3888   LLT DstTy = MRI.getType(Dst);
3889   LLT SrcTy = MRI.getType(Src);
3890 
3891   const LLT S64 = LLT::scalar(64);
3892   const LLT S32 = LLT::scalar(32);
3893   const LLT S1 = LLT::scalar(1);
3894 
3895   if (SrcTy == S1) {
3896     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
3897     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3898     MIRBuilder.buildSelect(Dst, Src, True, False);
3899     MI.eraseFromParent();
3900     return Legalized;
3901   }
3902 
3903   if (SrcTy != S64)
3904     return UnableToLegalize;
3905 
3906   if (DstTy == S32) {
3907     // signed cl2f(long l) {
3908     //   long s = l >> 63;
3909     //   float r = cul2f((l + s) ^ s);
3910     //   return s ? -r : r;
3911     // }
3912     Register L = Src;
3913     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3914     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3915 
3916     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3917     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3918     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3919 
3920     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3921     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3922                                             MIRBuilder.buildConstant(S64, 0));
3923     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3924     return Legalized;
3925   }
3926 
3927   return UnableToLegalize;
3928 }
3929 
3930 LegalizerHelper::LegalizeResult
3931 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3932   Register Dst = MI.getOperand(0).getReg();
3933   Register Src = MI.getOperand(1).getReg();
3934   LLT DstTy = MRI.getType(Dst);
3935   LLT SrcTy = MRI.getType(Src);
3936   const LLT S64 = LLT::scalar(64);
3937   const LLT S32 = LLT::scalar(32);
3938 
3939   if (SrcTy != S64 && SrcTy != S32)
3940     return UnableToLegalize;
3941   if (DstTy != S32 && DstTy != S64)
3942     return UnableToLegalize;
3943 
3944   // FPTOSI gives same result as FPTOUI for positive signed integers.
3945   // FPTOUI needs to deal with fp values that convert to unsigned integers
3946   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
3947 
3948   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
3949   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
3950                                                 : APFloat::IEEEdouble(),
3951                     APInt::getNullValue(SrcTy.getSizeInBits()));
3952   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
3953 
3954   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
3955 
3956   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
3957   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
3958   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
3959   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
3960   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
3961   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
3962   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
3963 
3964   MachineInstrBuilder FCMP =
3965       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, DstTy, Src, Threshold);
3966   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
3967 
3968   MI.eraseFromParent();
3969   return Legalized;
3970 }
3971 
3972 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
3973   switch (Opc) {
3974   case TargetOpcode::G_SMIN:
3975     return CmpInst::ICMP_SLT;
3976   case TargetOpcode::G_SMAX:
3977     return CmpInst::ICMP_SGT;
3978   case TargetOpcode::G_UMIN:
3979     return CmpInst::ICMP_ULT;
3980   case TargetOpcode::G_UMAX:
3981     return CmpInst::ICMP_UGT;
3982   default:
3983     llvm_unreachable("not in integer min/max");
3984   }
3985 }
3986 
3987 LegalizerHelper::LegalizeResult
3988 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3989   Register Dst = MI.getOperand(0).getReg();
3990   Register Src0 = MI.getOperand(1).getReg();
3991   Register Src1 = MI.getOperand(2).getReg();
3992 
3993   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
3994   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
3995 
3996   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3997   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
3998 
3999   MI.eraseFromParent();
4000   return Legalized;
4001 }
4002 
4003 LegalizerHelper::LegalizeResult
4004 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4005   Register Dst = MI.getOperand(0).getReg();
4006   Register Src0 = MI.getOperand(1).getReg();
4007   Register Src1 = MI.getOperand(2).getReg();
4008 
4009   const LLT Src0Ty = MRI.getType(Src0);
4010   const LLT Src1Ty = MRI.getType(Src1);
4011 
4012   const int Src0Size = Src0Ty.getScalarSizeInBits();
4013   const int Src1Size = Src1Ty.getScalarSizeInBits();
4014 
4015   auto SignBitMask = MIRBuilder.buildConstant(
4016     Src0Ty, APInt::getSignMask(Src0Size));
4017 
4018   auto NotSignBitMask = MIRBuilder.buildConstant(
4019     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4020 
4021   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4022   MachineInstr *Or;
4023 
4024   if (Src0Ty == Src1Ty) {
4025     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4026     Or = MIRBuilder.buildOr(Dst, And0, And1);
4027   } else if (Src0Size > Src1Size) {
4028     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4029     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4030     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4031     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4032     Or = MIRBuilder.buildOr(Dst, And0, And1);
4033   } else {
4034     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4035     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4036     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4037     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4038     Or = MIRBuilder.buildOr(Dst, And0, And1);
4039   }
4040 
4041   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4042   // constants are a nan and -0.0, but the final result should preserve
4043   // everything.
4044   if (unsigned Flags = MI.getFlags())
4045     Or->setFlags(Flags);
4046 
4047   MI.eraseFromParent();
4048   return Legalized;
4049 }
4050 
4051 LegalizerHelper::LegalizeResult
4052 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4053   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4054     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4055 
4056   Register Dst = MI.getOperand(0).getReg();
4057   Register Src0 = MI.getOperand(1).getReg();
4058   Register Src1 = MI.getOperand(2).getReg();
4059   LLT Ty = MRI.getType(Dst);
4060 
4061   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4062     // Insert canonicalizes if it's possible we need to quiet to get correct
4063     // sNaN behavior.
4064 
4065     // Note this must be done here, and not as an optimization combine in the
4066     // absence of a dedicate quiet-snan instruction as we're using an
4067     // omni-purpose G_FCANONICALIZE.
4068     if (!isKnownNeverSNaN(Src0, MRI))
4069       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4070 
4071     if (!isKnownNeverSNaN(Src1, MRI))
4072       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4073   }
4074 
4075   // If there are no nans, it's safe to simply replace this with the non-IEEE
4076   // version.
4077   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4078   MI.eraseFromParent();
4079   return Legalized;
4080 }
4081 
4082 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4083   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4084   Register DstReg = MI.getOperand(0).getReg();
4085   LLT Ty = MRI.getType(DstReg);
4086   unsigned Flags = MI.getFlags();
4087 
4088   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4089                                   Flags);
4090   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4091   MI.eraseFromParent();
4092   return Legalized;
4093 }
4094 
4095 LegalizerHelper::LegalizeResult
4096 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4097   const unsigned NumDst = MI.getNumOperands() - 1;
4098   const Register SrcReg = MI.getOperand(NumDst).getReg();
4099   LLT SrcTy = MRI.getType(SrcReg);
4100 
4101   Register Dst0Reg = MI.getOperand(0).getReg();
4102   LLT DstTy = MRI.getType(Dst0Reg);
4103 
4104 
4105   // Expand scalarizing unmerge as bitcast to integer and shift.
4106   if (!DstTy.isVector() && SrcTy.isVector() &&
4107       SrcTy.getElementType() == DstTy) {
4108     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4109     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4110 
4111     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4112 
4113     const unsigned DstSize = DstTy.getSizeInBits();
4114     unsigned Offset = DstSize;
4115     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4116       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4117       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4118       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4119     }
4120 
4121     MI.eraseFromParent();
4122     return Legalized;
4123   }
4124 
4125   return UnableToLegalize;
4126 }
4127 
4128 LegalizerHelper::LegalizeResult
4129 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4130   Register DstReg = MI.getOperand(0).getReg();
4131   Register Src0Reg = MI.getOperand(1).getReg();
4132   Register Src1Reg = MI.getOperand(2).getReg();
4133   LLT Src0Ty = MRI.getType(Src0Reg);
4134   LLT DstTy = MRI.getType(DstReg);
4135   LLT IdxTy = LLT::scalar(32);
4136 
4137   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
4138 
4139   SmallVector<int, 32> Mask;
4140   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
4141 
4142   if (DstTy.isScalar()) {
4143     if (Src0Ty.isVector())
4144       return UnableToLegalize;
4145 
4146     // This is just a SELECT.
4147     assert(Mask.size() == 1 && "Expected a single mask element");
4148     Register Val;
4149     if (Mask[0] < 0 || Mask[0] > 1)
4150       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4151     else
4152       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4153     MIRBuilder.buildCopy(DstReg, Val);
4154     MI.eraseFromParent();
4155     return Legalized;
4156   }
4157 
4158   Register Undef;
4159   SmallVector<Register, 32> BuildVec;
4160   LLT EltTy = DstTy.getElementType();
4161 
4162   for (int Idx : Mask) {
4163     if (Idx < 0) {
4164       if (!Undef.isValid())
4165         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4166       BuildVec.push_back(Undef);
4167       continue;
4168     }
4169 
4170     if (Src0Ty.isScalar()) {
4171       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4172     } else {
4173       int NumElts = Src0Ty.getNumElements();
4174       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4175       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4176       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4177       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4178       BuildVec.push_back(Extract.getReg(0));
4179     }
4180   }
4181 
4182   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4183   MI.eraseFromParent();
4184   return Legalized;
4185 }
4186 
4187 LegalizerHelper::LegalizeResult
4188 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4189   Register Dst = MI.getOperand(0).getReg();
4190   Register AllocSize = MI.getOperand(1).getReg();
4191   unsigned Align = MI.getOperand(2).getImm();
4192 
4193   const auto &MF = *MI.getMF();
4194   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4195 
4196   LLT PtrTy = MRI.getType(Dst);
4197   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4198 
4199   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4200   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4201   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4202 
4203   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4204   // have to generate an extra instruction to negate the alloc and then use
4205   // G_PTR_ADD to add the negative offset.
4206   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4207   if (Align) {
4208     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4209     AlignMask.negate();
4210     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4211     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4212   }
4213 
4214   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4215   MIRBuilder.buildCopy(SPReg, SPTmp);
4216   MIRBuilder.buildCopy(Dst, SPTmp);
4217 
4218   MI.eraseFromParent();
4219   return Legalized;
4220 }
4221 
4222 LegalizerHelper::LegalizeResult
4223 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4224   Register Dst = MI.getOperand(0).getReg();
4225   Register Src = MI.getOperand(1).getReg();
4226   unsigned Offset = MI.getOperand(2).getImm();
4227 
4228   LLT DstTy = MRI.getType(Dst);
4229   LLT SrcTy = MRI.getType(Src);
4230 
4231   if (DstTy.isScalar() &&
4232       (SrcTy.isScalar() ||
4233        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4234     LLT SrcIntTy = SrcTy;
4235     if (!SrcTy.isScalar()) {
4236       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4237       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4238     }
4239 
4240     if (Offset == 0)
4241       MIRBuilder.buildTrunc(Dst, Src);
4242     else {
4243       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4244       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4245       MIRBuilder.buildTrunc(Dst, Shr);
4246     }
4247 
4248     MI.eraseFromParent();
4249     return Legalized;
4250   }
4251 
4252   return UnableToLegalize;
4253 }
4254 
4255 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4256   Register Dst = MI.getOperand(0).getReg();
4257   Register Src = MI.getOperand(1).getReg();
4258   Register InsertSrc = MI.getOperand(2).getReg();
4259   uint64_t Offset = MI.getOperand(3).getImm();
4260 
4261   LLT DstTy = MRI.getType(Src);
4262   LLT InsertTy = MRI.getType(InsertSrc);
4263 
4264   if (InsertTy.isScalar() &&
4265       (DstTy.isScalar() ||
4266        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4267     LLT IntDstTy = DstTy;
4268     if (!DstTy.isScalar()) {
4269       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4270       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4271     }
4272 
4273     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4274     if (Offset != 0) {
4275       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4276       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4277     }
4278 
4279     APInt MaskVal = ~APInt::getBitsSet(DstTy.getSizeInBits(), Offset,
4280                                        InsertTy.getSizeInBits());
4281 
4282     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4283     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4284     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4285 
4286     MIRBuilder.buildBitcast(Dst, Or);
4287     MI.eraseFromParent();
4288     return Legalized;
4289   }
4290 
4291   return UnableToLegalize;
4292 }
4293 
4294 LegalizerHelper::LegalizeResult
4295 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4296   Register Dst0 = MI.getOperand(0).getReg();
4297   Register Dst1 = MI.getOperand(1).getReg();
4298   Register LHS = MI.getOperand(2).getReg();
4299   Register RHS = MI.getOperand(3).getReg();
4300   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4301 
4302   LLT Ty = MRI.getType(Dst0);
4303   LLT BoolTy = MRI.getType(Dst1);
4304 
4305   if (IsAdd)
4306     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4307   else
4308     MIRBuilder.buildSub(Dst0, LHS, RHS);
4309 
4310   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4311 
4312   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4313 
4314   // For an addition, the result should be less than one of the operands (LHS)
4315   // if and only if the other operand (RHS) is negative, otherwise there will
4316   // be overflow.
4317   // For a subtraction, the result should be less than one of the operands
4318   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4319   // otherwise there will be overflow.
4320   auto ResultLowerThanLHS =
4321       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4322   auto ConditionRHS = MIRBuilder.buildICmp(
4323       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4324 
4325   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4326   MI.eraseFromParent();
4327   return Legalized;
4328 }
4329