1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
86       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
87     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
88                                                      : UnableToLegalize;
89   auto Step = LI.getAction(MI, MRI);
90   switch (Step.Action) {
91   case Legal:
92     LLVM_DEBUG(dbgs() << ".. Already legal\n");
93     return AlreadyLegal;
94   case Libcall:
95     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
96     return libcall(MI);
97   case NarrowScalar:
98     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
99     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
100   case WidenScalar:
101     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
102     return widenScalar(MI, Step.TypeIdx, Step.NewType);
103   case Lower:
104     LLVM_DEBUG(dbgs() << ".. Lower\n");
105     return lower(MI, Step.TypeIdx, Step.NewType);
106   case FewerElements:
107     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
108     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
109   case MoreElements:
110     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
111     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
112   case Custom:
113     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
114     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
115                                                             : UnableToLegalize;
116   default:
117     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
118     return UnableToLegalize;
119   }
120 }
121 
122 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
123                                    SmallVectorImpl<Register> &VRegs) {
124   for (int i = 0; i < NumParts; ++i)
125     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
126   MIRBuilder.buildUnmerge(VRegs, Reg);
127 }
128 
129 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
130                                    LLT MainTy, LLT &LeftoverTy,
131                                    SmallVectorImpl<Register> &VRegs,
132                                    SmallVectorImpl<Register> &LeftoverRegs) {
133   assert(!LeftoverTy.isValid() && "this is an out argument");
134 
135   unsigned RegSize = RegTy.getSizeInBits();
136   unsigned MainSize = MainTy.getSizeInBits();
137   unsigned NumParts = RegSize / MainSize;
138   unsigned LeftoverSize = RegSize - NumParts * MainSize;
139 
140   // Use an unmerge when possible.
141   if (LeftoverSize == 0) {
142     for (unsigned I = 0; I < NumParts; ++I)
143       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
144     MIRBuilder.buildUnmerge(VRegs, Reg);
145     return true;
146   }
147 
148   if (MainTy.isVector()) {
149     unsigned EltSize = MainTy.getScalarSizeInBits();
150     if (LeftoverSize % EltSize != 0)
151       return false;
152     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
153   } else {
154     LeftoverTy = LLT::scalar(LeftoverSize);
155   }
156 
157   // For irregular sizes, extract the individual parts.
158   for (unsigned I = 0; I != NumParts; ++I) {
159     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
160     VRegs.push_back(NewReg);
161     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
162   }
163 
164   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
165        Offset += LeftoverSize) {
166     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
167     LeftoverRegs.push_back(NewReg);
168     MIRBuilder.buildExtract(NewReg, Reg, Offset);
169   }
170 
171   return true;
172 }
173 
174 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
175   if (OrigTy.isVector() && TargetTy.isVector()) {
176     assert(OrigTy.getElementType() == TargetTy.getElementType());
177     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
178                                     TargetTy.getNumElements());
179     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
180   }
181 
182   if (OrigTy.isVector() && !TargetTy.isVector()) {
183     assert(OrigTy.getElementType() == TargetTy);
184     return TargetTy;
185   }
186 
187   assert(!OrigTy.isVector() && !TargetTy.isVector());
188 
189   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
190                                   TargetTy.getSizeInBits());
191   return LLT::scalar(GCD);
192 }
193 
194 void LegalizerHelper::insertParts(Register DstReg,
195                                   LLT ResultTy, LLT PartTy,
196                                   ArrayRef<Register> PartRegs,
197                                   LLT LeftoverTy,
198                                   ArrayRef<Register> LeftoverRegs) {
199   if (!LeftoverTy.isValid()) {
200     assert(LeftoverRegs.empty());
201 
202     if (!ResultTy.isVector()) {
203       MIRBuilder.buildMerge(DstReg, PartRegs);
204       return;
205     }
206 
207     if (PartTy.isVector())
208       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
209     else
210       MIRBuilder.buildBuildVector(DstReg, PartRegs);
211     return;
212   }
213 
214   unsigned PartSize = PartTy.getSizeInBits();
215   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
216 
217   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
218   MIRBuilder.buildUndef(CurResultReg);
219 
220   unsigned Offset = 0;
221   for (Register PartReg : PartRegs) {
222     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
223     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
224     CurResultReg = NewResultReg;
225     Offset += PartSize;
226   }
227 
228   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
229     // Use the original output register for the final insert to avoid a copy.
230     Register NewResultReg = (I + 1 == E) ?
231       DstReg : MRI.createGenericVirtualRegister(ResultTy);
232 
233     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
234     CurResultReg = NewResultReg;
235     Offset += LeftoverPartSize;
236   }
237 }
238 
239 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
240   switch (Opcode) {
241   case TargetOpcode::G_SDIV:
242     assert((Size == 32 || Size == 64) && "Unsupported size");
243     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
244   case TargetOpcode::G_UDIV:
245     assert((Size == 32 || Size == 64) && "Unsupported size");
246     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
247   case TargetOpcode::G_SREM:
248     assert((Size == 32 || Size == 64) && "Unsupported size");
249     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
250   case TargetOpcode::G_UREM:
251     assert((Size == 32 || Size == 64) && "Unsupported size");
252     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
253   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
254     assert(Size == 32 && "Unsupported size");
255     return RTLIB::CTLZ_I32;
256   case TargetOpcode::G_FADD:
257     assert((Size == 32 || Size == 64) && "Unsupported size");
258     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
259   case TargetOpcode::G_FSUB:
260     assert((Size == 32 || Size == 64) && "Unsupported size");
261     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
262   case TargetOpcode::G_FMUL:
263     assert((Size == 32 || Size == 64) && "Unsupported size");
264     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
265   case TargetOpcode::G_FDIV:
266     assert((Size == 32 || Size == 64) && "Unsupported size");
267     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
268   case TargetOpcode::G_FEXP:
269     assert((Size == 32 || Size == 64) && "Unsupported size");
270     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
271   case TargetOpcode::G_FEXP2:
272     assert((Size == 32 || Size == 64) && "Unsupported size");
273     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
274   case TargetOpcode::G_FREM:
275     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
276   case TargetOpcode::G_FPOW:
277     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
278   case TargetOpcode::G_FMA:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
281   case TargetOpcode::G_FSIN:
282     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
283     return Size == 128 ? RTLIB::SIN_F128
284                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
285   case TargetOpcode::G_FCOS:
286     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
287     return Size == 128 ? RTLIB::COS_F128
288                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
289   case TargetOpcode::G_FLOG10:
290     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
291     return Size == 128 ? RTLIB::LOG10_F128
292                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
293   case TargetOpcode::G_FLOG:
294     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
295     return Size == 128 ? RTLIB::LOG_F128
296                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
297   case TargetOpcode::G_FLOG2:
298     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
299     return Size == 128 ? RTLIB::LOG2_F128
300                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
301   case TargetOpcode::G_FCEIL:
302     assert((Size == 32 || Size == 64) && "Unsupported size");
303     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
304   case TargetOpcode::G_FFLOOR:
305     assert((Size == 32 || Size == 64) && "Unsupported size");
306     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
307   }
308   llvm_unreachable("Unknown libcall function");
309 }
310 
311 LegalizerHelper::LegalizeResult
312 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
313                     const CallLowering::ArgInfo &Result,
314                     ArrayRef<CallLowering::ArgInfo> Args) {
315   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
316   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
317   const char *Name = TLI.getLibcallName(Libcall);
318 
319   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
320 
321   CallLowering::CallLoweringInfo Info;
322   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
323   Info.Callee = MachineOperand::CreateES(Name);
324   Info.OrigRet = Result;
325   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
326   if (!CLI.lowerCall(MIRBuilder, Info))
327     return LegalizerHelper::UnableToLegalize;
328 
329   return LegalizerHelper::Legalized;
330 }
331 
332 // Useful for libcalls where all operands have the same type.
333 static LegalizerHelper::LegalizeResult
334 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
335               Type *OpType) {
336   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
337 
338   SmallVector<CallLowering::ArgInfo, 3> Args;
339   for (unsigned i = 1; i < MI.getNumOperands(); i++)
340     Args.push_back({MI.getOperand(i).getReg(), OpType});
341   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
342                        Args);
343 }
344 
345 LegalizerHelper::LegalizeResult
346 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
347                        MachineInstr &MI) {
348   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
349   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
350 
351   SmallVector<CallLowering::ArgInfo, 3> Args;
352   for (unsigned i = 1; i < MI.getNumOperands(); i++) {
353     Register Reg = MI.getOperand(i).getReg();
354 
355     // Need derive an IR type for call lowering.
356     LLT OpLLT = MRI.getType(Reg);
357     Type *OpTy = nullptr;
358     if (OpLLT.isPointer())
359       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
360     else
361       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
362     Args.push_back({Reg, OpTy});
363   }
364 
365   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
366   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
367   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
368   RTLIB::Libcall RTLibcall;
369   switch (ID) {
370   case Intrinsic::memcpy:
371     RTLibcall = RTLIB::MEMCPY;
372     break;
373   case Intrinsic::memset:
374     RTLibcall = RTLIB::MEMSET;
375     break;
376   case Intrinsic::memmove:
377     RTLibcall = RTLIB::MEMMOVE;
378     break;
379   default:
380     return LegalizerHelper::UnableToLegalize;
381   }
382   const char *Name = TLI.getLibcallName(RTLibcall);
383 
384   MIRBuilder.setInstr(MI);
385   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
386 
387   CallLowering::CallLoweringInfo Info;
388   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
389   Info.Callee = MachineOperand::CreateES(Name);
390   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
391   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
392   if (!CLI.lowerCall(MIRBuilder, Info))
393     return LegalizerHelper::UnableToLegalize;
394 
395   return LegalizerHelper::Legalized;
396 }
397 
398 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
399                                        Type *FromType) {
400   auto ToMVT = MVT::getVT(ToType);
401   auto FromMVT = MVT::getVT(FromType);
402 
403   switch (Opcode) {
404   case TargetOpcode::G_FPEXT:
405     return RTLIB::getFPEXT(FromMVT, ToMVT);
406   case TargetOpcode::G_FPTRUNC:
407     return RTLIB::getFPROUND(FromMVT, ToMVT);
408   case TargetOpcode::G_FPTOSI:
409     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
410   case TargetOpcode::G_FPTOUI:
411     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
412   case TargetOpcode::G_SITOFP:
413     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
414   case TargetOpcode::G_UITOFP:
415     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
416   }
417   llvm_unreachable("Unsupported libcall function");
418 }
419 
420 static LegalizerHelper::LegalizeResult
421 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
422                   Type *FromType) {
423   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
424   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
425                        {{MI.getOperand(1).getReg(), FromType}});
426 }
427 
428 LegalizerHelper::LegalizeResult
429 LegalizerHelper::libcall(MachineInstr &MI) {
430   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
431   unsigned Size = LLTy.getSizeInBits();
432   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
433 
434   MIRBuilder.setInstr(MI);
435 
436   switch (MI.getOpcode()) {
437   default:
438     return UnableToLegalize;
439   case TargetOpcode::G_SDIV:
440   case TargetOpcode::G_UDIV:
441   case TargetOpcode::G_SREM:
442   case TargetOpcode::G_UREM:
443   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
444     Type *HLTy = IntegerType::get(Ctx, Size);
445     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
446     if (Status != Legalized)
447       return Status;
448     break;
449   }
450   case TargetOpcode::G_FADD:
451   case TargetOpcode::G_FSUB:
452   case TargetOpcode::G_FMUL:
453   case TargetOpcode::G_FDIV:
454   case TargetOpcode::G_FMA:
455   case TargetOpcode::G_FPOW:
456   case TargetOpcode::G_FREM:
457   case TargetOpcode::G_FCOS:
458   case TargetOpcode::G_FSIN:
459   case TargetOpcode::G_FLOG10:
460   case TargetOpcode::G_FLOG:
461   case TargetOpcode::G_FLOG2:
462   case TargetOpcode::G_FEXP:
463   case TargetOpcode::G_FEXP2:
464   case TargetOpcode::G_FCEIL:
465   case TargetOpcode::G_FFLOOR: {
466     if (Size > 64) {
467       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
468       return UnableToLegalize;
469     }
470     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
471     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
472     if (Status != Legalized)
473       return Status;
474     break;
475   }
476   case TargetOpcode::G_FPEXT: {
477     // FIXME: Support other floating point types (half, fp128 etc)
478     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
479     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
480     if (ToSize != 64 || FromSize != 32)
481       return UnableToLegalize;
482     LegalizeResult Status = conversionLibcall(
483         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
484     if (Status != Legalized)
485       return Status;
486     break;
487   }
488   case TargetOpcode::G_FPTRUNC: {
489     // FIXME: Support other floating point types (half, fp128 etc)
490     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
491     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
492     if (ToSize != 32 || FromSize != 64)
493       return UnableToLegalize;
494     LegalizeResult Status = conversionLibcall(
495         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
496     if (Status != Legalized)
497       return Status;
498     break;
499   }
500   case TargetOpcode::G_FPTOSI:
501   case TargetOpcode::G_FPTOUI: {
502     // FIXME: Support other types
503     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
504     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
505     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
506       return UnableToLegalize;
507     LegalizeResult Status = conversionLibcall(
508         MI, MIRBuilder,
509         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
510         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
511     if (Status != Legalized)
512       return Status;
513     break;
514   }
515   case TargetOpcode::G_SITOFP:
516   case TargetOpcode::G_UITOFP: {
517     // FIXME: Support other types
518     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
519     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
520     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
521       return UnableToLegalize;
522     LegalizeResult Status = conversionLibcall(
523         MI, MIRBuilder,
524         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
525         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
526     if (Status != Legalized)
527       return Status;
528     break;
529   }
530   }
531 
532   MI.eraseFromParent();
533   return Legalized;
534 }
535 
536 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
537                                                               unsigned TypeIdx,
538                                                               LLT NarrowTy) {
539   MIRBuilder.setInstr(MI);
540 
541   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
542   uint64_t NarrowSize = NarrowTy.getSizeInBits();
543 
544   switch (MI.getOpcode()) {
545   default:
546     return UnableToLegalize;
547   case TargetOpcode::G_IMPLICIT_DEF: {
548     // FIXME: add support for when SizeOp0 isn't an exact multiple of
549     // NarrowSize.
550     if (SizeOp0 % NarrowSize != 0)
551       return UnableToLegalize;
552     int NumParts = SizeOp0 / NarrowSize;
553 
554     SmallVector<Register, 2> DstRegs;
555     for (int i = 0; i < NumParts; ++i)
556       DstRegs.push_back(
557           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
558 
559     Register DstReg = MI.getOperand(0).getReg();
560     if(MRI.getType(DstReg).isVector())
561       MIRBuilder.buildBuildVector(DstReg, DstRegs);
562     else
563       MIRBuilder.buildMerge(DstReg, DstRegs);
564     MI.eraseFromParent();
565     return Legalized;
566   }
567   case TargetOpcode::G_CONSTANT: {
568     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
569     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
570     unsigned TotalSize = Ty.getSizeInBits();
571     unsigned NarrowSize = NarrowTy.getSizeInBits();
572     int NumParts = TotalSize / NarrowSize;
573 
574     SmallVector<Register, 4> PartRegs;
575     for (int I = 0; I != NumParts; ++I) {
576       unsigned Offset = I * NarrowSize;
577       auto K = MIRBuilder.buildConstant(NarrowTy,
578                                         Val.lshr(Offset).trunc(NarrowSize));
579       PartRegs.push_back(K.getReg(0));
580     }
581 
582     LLT LeftoverTy;
583     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
584     SmallVector<Register, 1> LeftoverRegs;
585     if (LeftoverBits != 0) {
586       LeftoverTy = LLT::scalar(LeftoverBits);
587       auto K = MIRBuilder.buildConstant(
588         LeftoverTy,
589         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
590       LeftoverRegs.push_back(K.getReg(0));
591     }
592 
593     insertParts(MI.getOperand(0).getReg(),
594                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
595 
596     MI.eraseFromParent();
597     return Legalized;
598   }
599   case TargetOpcode::G_SEXT: {
600     if (TypeIdx != 0)
601       return UnableToLegalize;
602 
603     if (NarrowTy.getSizeInBits() != SizeOp0 / 2) {
604       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
605       return UnableToLegalize;
606     }
607 
608     Register SrcReg = MI.getOperand(1).getReg();
609 
610     // Shift the sign bit of the low register through the high register.
611     auto ShiftAmt =
612         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
613     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
614     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
615     MI.eraseFromParent();
616     return Legalized;
617   }
618   case TargetOpcode::G_ZEXT: {
619     if (TypeIdx != 0)
620       return UnableToLegalize;
621 
622     if (SizeOp0 % NarrowTy.getSizeInBits() != 0)
623       return UnableToLegalize;
624 
625     // Generate a merge where the bottom bits are taken from the source, and
626     // zero everything else.
627     Register ZeroReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
628     unsigned NumParts = SizeOp0 / NarrowTy.getSizeInBits();
629     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
630     for (unsigned Part = 1; Part < NumParts; ++Part)
631       Srcs.push_back(ZeroReg);
632     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
633     MI.eraseFromParent();
634     return Legalized;
635   }
636 
637   case TargetOpcode::G_ADD: {
638     // FIXME: add support for when SizeOp0 isn't an exact multiple of
639     // NarrowSize.
640     if (SizeOp0 % NarrowSize != 0)
641       return UnableToLegalize;
642     // Expand in terms of carry-setting/consuming G_ADDE instructions.
643     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
644 
645     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
646     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
647     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
648 
649     Register CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
650     MIRBuilder.buildConstant(CarryIn, 0);
651 
652     for (int i = 0; i < NumParts; ++i) {
653       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
654       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
655 
656       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
657                             Src2Regs[i], CarryIn);
658 
659       DstRegs.push_back(DstReg);
660       CarryIn = CarryOut;
661     }
662     Register DstReg = MI.getOperand(0).getReg();
663     if(MRI.getType(DstReg).isVector())
664       MIRBuilder.buildBuildVector(DstReg, DstRegs);
665     else
666       MIRBuilder.buildMerge(DstReg, DstRegs);
667     MI.eraseFromParent();
668     return Legalized;
669   }
670   case TargetOpcode::G_SUB: {
671     // FIXME: add support for when SizeOp0 isn't an exact multiple of
672     // NarrowSize.
673     if (SizeOp0 % NarrowSize != 0)
674       return UnableToLegalize;
675 
676     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
677 
678     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
679     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
680     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
681 
682     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
683     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
684     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
685                           {Src1Regs[0], Src2Regs[0]});
686     DstRegs.push_back(DstReg);
687     Register BorrowIn = BorrowOut;
688     for (int i = 1; i < NumParts; ++i) {
689       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
690       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
691 
692       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
693                             {Src1Regs[i], Src2Regs[i], BorrowIn});
694 
695       DstRegs.push_back(DstReg);
696       BorrowIn = BorrowOut;
697     }
698     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
699     MI.eraseFromParent();
700     return Legalized;
701   }
702   case TargetOpcode::G_MUL:
703   case TargetOpcode::G_UMULH:
704     return narrowScalarMul(MI, NarrowTy);
705   case TargetOpcode::G_EXTRACT:
706     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
707   case TargetOpcode::G_INSERT:
708     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
709   case TargetOpcode::G_LOAD: {
710     const auto &MMO = **MI.memoperands_begin();
711     Register DstReg = MI.getOperand(0).getReg();
712     LLT DstTy = MRI.getType(DstReg);
713     if (DstTy.isVector())
714       return UnableToLegalize;
715 
716     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
717       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
718       auto &MMO = **MI.memoperands_begin();
719       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
720       MIRBuilder.buildAnyExt(DstReg, TmpReg);
721       MI.eraseFromParent();
722       return Legalized;
723     }
724 
725     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
726   }
727   case TargetOpcode::G_ZEXTLOAD:
728   case TargetOpcode::G_SEXTLOAD: {
729     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
730     Register DstReg = MI.getOperand(0).getReg();
731     Register PtrReg = MI.getOperand(1).getReg();
732 
733     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
734     auto &MMO = **MI.memoperands_begin();
735     if (MMO.getSizeInBits() == NarrowSize) {
736       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
737     } else {
738       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
739         : TargetOpcode::G_SEXTLOAD;
740       MIRBuilder.buildInstr(ExtLoad)
741         .addDef(TmpReg)
742         .addUse(PtrReg)
743         .addMemOperand(&MMO);
744     }
745 
746     if (ZExt)
747       MIRBuilder.buildZExt(DstReg, TmpReg);
748     else
749       MIRBuilder.buildSExt(DstReg, TmpReg);
750 
751     MI.eraseFromParent();
752     return Legalized;
753   }
754   case TargetOpcode::G_STORE: {
755     const auto &MMO = **MI.memoperands_begin();
756 
757     Register SrcReg = MI.getOperand(0).getReg();
758     LLT SrcTy = MRI.getType(SrcReg);
759     if (SrcTy.isVector())
760       return UnableToLegalize;
761 
762     int NumParts = SizeOp0 / NarrowSize;
763     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
764     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
765     if (SrcTy.isVector() && LeftoverBits != 0)
766       return UnableToLegalize;
767 
768     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
769       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
770       auto &MMO = **MI.memoperands_begin();
771       MIRBuilder.buildTrunc(TmpReg, SrcReg);
772       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
773       MI.eraseFromParent();
774       return Legalized;
775     }
776 
777     return reduceLoadStoreWidth(MI, 0, NarrowTy);
778   }
779   case TargetOpcode::G_SELECT:
780     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
781   case TargetOpcode::G_AND:
782   case TargetOpcode::G_OR:
783   case TargetOpcode::G_XOR: {
784     // Legalize bitwise operation:
785     // A = BinOp<Ty> B, C
786     // into:
787     // B1, ..., BN = G_UNMERGE_VALUES B
788     // C1, ..., CN = G_UNMERGE_VALUES C
789     // A1 = BinOp<Ty/N> B1, C2
790     // ...
791     // AN = BinOp<Ty/N> BN, CN
792     // A = G_MERGE_VALUES A1, ..., AN
793     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
794   }
795   case TargetOpcode::G_SHL:
796   case TargetOpcode::G_LSHR:
797   case TargetOpcode::G_ASHR:
798     return narrowScalarShift(MI, TypeIdx, NarrowTy);
799   case TargetOpcode::G_CTLZ:
800   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
801   case TargetOpcode::G_CTTZ:
802   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
803   case TargetOpcode::G_CTPOP:
804     if (TypeIdx != 0)
805       return UnableToLegalize; // TODO
806 
807     Observer.changingInstr(MI);
808     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
809     Observer.changedInstr(MI);
810     return Legalized;
811   case TargetOpcode::G_INTTOPTR:
812     if (TypeIdx != 1)
813       return UnableToLegalize;
814 
815     Observer.changingInstr(MI);
816     narrowScalarSrc(MI, NarrowTy, 1);
817     Observer.changedInstr(MI);
818     return Legalized;
819   case TargetOpcode::G_PTRTOINT:
820     if (TypeIdx != 0)
821       return UnableToLegalize;
822 
823     Observer.changingInstr(MI);
824     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
825     Observer.changedInstr(MI);
826     return Legalized;
827   case TargetOpcode::G_PHI: {
828     unsigned NumParts = SizeOp0 / NarrowSize;
829     SmallVector<Register, 2> DstRegs;
830     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
831     DstRegs.resize(NumParts);
832     SrcRegs.resize(MI.getNumOperands() / 2);
833     Observer.changingInstr(MI);
834     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
835       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
836       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
837       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
838                    SrcRegs[i / 2]);
839     }
840     MachineBasicBlock &MBB = *MI.getParent();
841     MIRBuilder.setInsertPt(MBB, MI);
842     for (unsigned i = 0; i < NumParts; ++i) {
843       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
844       MachineInstrBuilder MIB =
845           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
846       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
847         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
848     }
849     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
850     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
851     Observer.changedInstr(MI);
852     MI.eraseFromParent();
853     return Legalized;
854   }
855   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
856   case TargetOpcode::G_INSERT_VECTOR_ELT: {
857     if (TypeIdx != 2)
858       return UnableToLegalize;
859 
860     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
861     Observer.changingInstr(MI);
862     narrowScalarSrc(MI, NarrowTy, OpIdx);
863     Observer.changedInstr(MI);
864     return Legalized;
865   }
866   case TargetOpcode::G_ICMP: {
867     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
868     if (NarrowSize * 2 != SrcSize)
869       return UnableToLegalize;
870 
871     Observer.changingInstr(MI);
872     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
873     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
874     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
875 
876     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
877     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
878     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
879 
880     CmpInst::Predicate Pred =
881         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
882     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
883 
884     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
885       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
886       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
887       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
888       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
889       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
890     } else {
891       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
892       MachineInstrBuilder CmpHEQ =
893           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
894       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
895           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
896       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
897     }
898     Observer.changedInstr(MI);
899     MI.eraseFromParent();
900     return Legalized;
901   }
902   case TargetOpcode::G_SEXT_INREG: {
903     if (TypeIdx != 0)
904       return UnableToLegalize;
905 
906     if (!MI.getOperand(2).isImm())
907       return UnableToLegalize;
908     int64_t SizeInBits = MI.getOperand(2).getImm();
909 
910     // So long as the new type has more bits than the bits we're extending we
911     // don't need to break it apart.
912     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
913       Observer.changingInstr(MI);
914       // We don't lose any non-extension bits by truncating the src and
915       // sign-extending the dst.
916       MachineOperand &MO1 = MI.getOperand(1);
917       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
918       MO1.setReg(TruncMIB->getOperand(0).getReg());
919 
920       MachineOperand &MO2 = MI.getOperand(0);
921       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
922       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
923       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
924       MO2.setReg(DstExt);
925       Observer.changedInstr(MI);
926       return Legalized;
927     }
928 
929     // Break it apart. Components below the extension point are unmodified. The
930     // component containing the extension point becomes a narrower SEXT_INREG.
931     // Components above it are ashr'd from the component containing the
932     // extension point.
933     if (SizeOp0 % NarrowSize != 0)
934       return UnableToLegalize;
935     int NumParts = SizeOp0 / NarrowSize;
936 
937     // List the registers where the destination will be scattered.
938     SmallVector<Register, 2> DstRegs;
939     // List the registers where the source will be split.
940     SmallVector<Register, 2> SrcRegs;
941 
942     // Create all the temporary registers.
943     for (int i = 0; i < NumParts; ++i) {
944       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
945 
946       SrcRegs.push_back(SrcReg);
947     }
948 
949     // Explode the big arguments into smaller chunks.
950     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
951 
952     Register AshrCstReg =
953         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
954             ->getOperand(0)
955             .getReg();
956     Register FullExtensionReg = 0;
957     Register PartialExtensionReg = 0;
958 
959     // Do the operation on each small part.
960     for (int i = 0; i < NumParts; ++i) {
961       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
962         DstRegs.push_back(SrcRegs[i]);
963       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
964         assert(PartialExtensionReg &&
965                "Expected to visit partial extension before full");
966         if (FullExtensionReg) {
967           DstRegs.push_back(FullExtensionReg);
968           continue;
969         }
970         DstRegs.push_back(MIRBuilder
971                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
972                                           {PartialExtensionReg, AshrCstReg})
973                               ->getOperand(0)
974                               .getReg());
975         FullExtensionReg = DstRegs.back();
976       } else {
977         DstRegs.push_back(
978             MIRBuilder
979                 .buildInstr(
980                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
981                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
982                 ->getOperand(0)
983                 .getReg());
984         PartialExtensionReg = DstRegs.back();
985       }
986     }
987 
988     // Gather the destination registers into the final destination.
989     Register DstReg = MI.getOperand(0).getReg();
990     MIRBuilder.buildMerge(DstReg, DstRegs);
991     MI.eraseFromParent();
992     return Legalized;
993   }
994   }
995 }
996 
997 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
998                                      unsigned OpIdx, unsigned ExtOpcode) {
999   MachineOperand &MO = MI.getOperand(OpIdx);
1000   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1001   MO.setReg(ExtB->getOperand(0).getReg());
1002 }
1003 
1004 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1005                                       unsigned OpIdx) {
1006   MachineOperand &MO = MI.getOperand(OpIdx);
1007   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1008                                     {MO.getReg()});
1009   MO.setReg(ExtB->getOperand(0).getReg());
1010 }
1011 
1012 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1013                                      unsigned OpIdx, unsigned TruncOpcode) {
1014   MachineOperand &MO = MI.getOperand(OpIdx);
1015   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1016   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1017   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1018   MO.setReg(DstExt);
1019 }
1020 
1021 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1022                                       unsigned OpIdx, unsigned ExtOpcode) {
1023   MachineOperand &MO = MI.getOperand(OpIdx);
1024   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1025   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1026   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1027   MO.setReg(DstTrunc);
1028 }
1029 
1030 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1031                                             unsigned OpIdx) {
1032   MachineOperand &MO = MI.getOperand(OpIdx);
1033   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1034   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1035   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1036   MO.setReg(DstExt);
1037 }
1038 
1039 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1040                                             unsigned OpIdx) {
1041   MachineOperand &MO = MI.getOperand(OpIdx);
1042 
1043   LLT OldTy = MRI.getType(MO.getReg());
1044   unsigned OldElts = OldTy.getNumElements();
1045   unsigned NewElts = MoreTy.getNumElements();
1046 
1047   unsigned NumParts = NewElts / OldElts;
1048 
1049   // Use concat_vectors if the result is a multiple of the number of elements.
1050   if (NumParts * OldElts == NewElts) {
1051     SmallVector<Register, 8> Parts;
1052     Parts.push_back(MO.getReg());
1053 
1054     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1055     for (unsigned I = 1; I != NumParts; ++I)
1056       Parts.push_back(ImpDef);
1057 
1058     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1059     MO.setReg(Concat.getReg(0));
1060     return;
1061   }
1062 
1063   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1064   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1065   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1066   MO.setReg(MoreReg);
1067 }
1068 
1069 LegalizerHelper::LegalizeResult
1070 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1071                                         LLT WideTy) {
1072   if (TypeIdx != 1)
1073     return UnableToLegalize;
1074 
1075   Register DstReg = MI.getOperand(0).getReg();
1076   LLT DstTy = MRI.getType(DstReg);
1077   if (DstTy.isVector())
1078     return UnableToLegalize;
1079 
1080   Register Src1 = MI.getOperand(1).getReg();
1081   LLT SrcTy = MRI.getType(Src1);
1082   const int DstSize = DstTy.getSizeInBits();
1083   const int SrcSize = SrcTy.getSizeInBits();
1084   const int WideSize = WideTy.getSizeInBits();
1085   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1086 
1087   unsigned NumOps = MI.getNumOperands();
1088   unsigned NumSrc = MI.getNumOperands() - 1;
1089   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1090 
1091   if (WideSize >= DstSize) {
1092     // Directly pack the bits in the target type.
1093     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1094 
1095     for (unsigned I = 2; I != NumOps; ++I) {
1096       const unsigned Offset = (I - 1) * PartSize;
1097 
1098       Register SrcReg = MI.getOperand(I).getReg();
1099       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1100 
1101       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1102 
1103       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1104         MRI.createGenericVirtualRegister(WideTy);
1105 
1106       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1107       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1108       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1109       ResultReg = NextResult;
1110     }
1111 
1112     if (WideSize > DstSize)
1113       MIRBuilder.buildTrunc(DstReg, ResultReg);
1114     else if (DstTy.isPointer())
1115       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1116 
1117     MI.eraseFromParent();
1118     return Legalized;
1119   }
1120 
1121   // Unmerge the original values to the GCD type, and recombine to the next
1122   // multiple greater than the original type.
1123   //
1124   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1125   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1126   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1127   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1128   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1129   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1130   // %12:_(s12) = G_MERGE_VALUES %10, %11
1131   //
1132   // Padding with undef if necessary:
1133   //
1134   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1135   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1136   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1137   // %7:_(s2) = G_IMPLICIT_DEF
1138   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1139   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1140   // %10:_(s12) = G_MERGE_VALUES %8, %9
1141 
1142   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1143   LLT GCDTy = LLT::scalar(GCD);
1144 
1145   SmallVector<Register, 8> Parts;
1146   SmallVector<Register, 8> NewMergeRegs;
1147   SmallVector<Register, 8> Unmerges;
1148   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1149 
1150   // Decompose the original operands if they don't evenly divide.
1151   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1152     Register SrcReg = MI.getOperand(I).getReg();
1153     if (GCD == SrcSize) {
1154       Unmerges.push_back(SrcReg);
1155     } else {
1156       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1157       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1158         Unmerges.push_back(Unmerge.getReg(J));
1159     }
1160   }
1161 
1162   // Pad with undef to the next size that is a multiple of the requested size.
1163   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1164     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1165     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1166       Unmerges.push_back(UndefReg);
1167   }
1168 
1169   const int PartsPerGCD = WideSize / GCD;
1170 
1171   // Build merges of each piece.
1172   ArrayRef<Register> Slicer(Unmerges);
1173   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1174     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1175     NewMergeRegs.push_back(Merge.getReg(0));
1176   }
1177 
1178   // A truncate may be necessary if the requested type doesn't evenly divide the
1179   // original result type.
1180   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1181     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1182   } else {
1183     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1184     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1185   }
1186 
1187   MI.eraseFromParent();
1188   return Legalized;
1189 }
1190 
1191 LegalizerHelper::LegalizeResult
1192 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1193                                           LLT WideTy) {
1194   if (TypeIdx != 0)
1195     return UnableToLegalize;
1196 
1197   unsigned NumDst = MI.getNumOperands() - 1;
1198   Register SrcReg = MI.getOperand(NumDst).getReg();
1199   LLT SrcTy = MRI.getType(SrcReg);
1200   if (!SrcTy.isScalar())
1201     return UnableToLegalize;
1202 
1203   Register Dst0Reg = MI.getOperand(0).getReg();
1204   LLT DstTy = MRI.getType(Dst0Reg);
1205   if (!DstTy.isScalar())
1206     return UnableToLegalize;
1207 
1208   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1209   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1210   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1211 
1212   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1213 
1214   for (unsigned I = 1; I != NumDst; ++I) {
1215     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1216     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1217     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1218   }
1219 
1220   Observer.changingInstr(MI);
1221 
1222   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1223   for (unsigned I = 0; I != NumDst; ++I)
1224     widenScalarDst(MI, WideTy, I);
1225 
1226   Observer.changedInstr(MI);
1227 
1228   return Legalized;
1229 }
1230 
1231 LegalizerHelper::LegalizeResult
1232 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1233                                     LLT WideTy) {
1234   Register DstReg = MI.getOperand(0).getReg();
1235   Register SrcReg = MI.getOperand(1).getReg();
1236   LLT SrcTy = MRI.getType(SrcReg);
1237 
1238   LLT DstTy = MRI.getType(DstReg);
1239   unsigned Offset = MI.getOperand(2).getImm();
1240 
1241   if (TypeIdx == 0) {
1242     if (SrcTy.isVector() || DstTy.isVector())
1243       return UnableToLegalize;
1244 
1245     SrcOp Src(SrcReg);
1246     if (SrcTy.isPointer()) {
1247       // Extracts from pointers can be handled only if they are really just
1248       // simple integers.
1249       const DataLayout &DL = MIRBuilder.getDataLayout();
1250       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1251         return UnableToLegalize;
1252 
1253       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1254       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1255       SrcTy = SrcAsIntTy;
1256     }
1257 
1258     if (DstTy.isPointer())
1259       return UnableToLegalize;
1260 
1261     if (Offset == 0) {
1262       // Avoid a shift in the degenerate case.
1263       MIRBuilder.buildTrunc(DstReg,
1264                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1265       MI.eraseFromParent();
1266       return Legalized;
1267     }
1268 
1269     // Do a shift in the source type.
1270     LLT ShiftTy = SrcTy;
1271     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1272       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1273       ShiftTy = WideTy;
1274     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1275       return UnableToLegalize;
1276 
1277     auto LShr = MIRBuilder.buildLShr(
1278       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1279     MIRBuilder.buildTrunc(DstReg, LShr);
1280     MI.eraseFromParent();
1281     return Legalized;
1282   }
1283 
1284   if (SrcTy.isScalar()) {
1285     Observer.changingInstr(MI);
1286     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1287     Observer.changedInstr(MI);
1288     return Legalized;
1289   }
1290 
1291   if (!SrcTy.isVector())
1292     return UnableToLegalize;
1293 
1294   if (DstTy != SrcTy.getElementType())
1295     return UnableToLegalize;
1296 
1297   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1298     return UnableToLegalize;
1299 
1300   Observer.changingInstr(MI);
1301   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1302 
1303   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1304                           Offset);
1305   widenScalarDst(MI, WideTy.getScalarType(), 0);
1306   Observer.changedInstr(MI);
1307   return Legalized;
1308 }
1309 
1310 LegalizerHelper::LegalizeResult
1311 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1312                                    LLT WideTy) {
1313   if (TypeIdx != 0)
1314     return UnableToLegalize;
1315   Observer.changingInstr(MI);
1316   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1317   widenScalarDst(MI, WideTy);
1318   Observer.changedInstr(MI);
1319   return Legalized;
1320 }
1321 
1322 LegalizerHelper::LegalizeResult
1323 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1324   MIRBuilder.setInstr(MI);
1325 
1326   switch (MI.getOpcode()) {
1327   default:
1328     return UnableToLegalize;
1329   case TargetOpcode::G_EXTRACT:
1330     return widenScalarExtract(MI, TypeIdx, WideTy);
1331   case TargetOpcode::G_INSERT:
1332     return widenScalarInsert(MI, TypeIdx, WideTy);
1333   case TargetOpcode::G_MERGE_VALUES:
1334     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1335   case TargetOpcode::G_UNMERGE_VALUES:
1336     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1337   case TargetOpcode::G_UADDO:
1338   case TargetOpcode::G_USUBO: {
1339     if (TypeIdx == 1)
1340       return UnableToLegalize; // TODO
1341     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1342                                          {MI.getOperand(2).getReg()});
1343     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1344                                          {MI.getOperand(3).getReg()});
1345     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1346                           ? TargetOpcode::G_ADD
1347                           : TargetOpcode::G_SUB;
1348     // Do the arithmetic in the larger type.
1349     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1350     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1351     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1352     auto AndOp = MIRBuilder.buildInstr(
1353         TargetOpcode::G_AND, {WideTy},
1354         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1355     // There is no overflow if the AndOp is the same as NewOp.
1356     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1357                          AndOp);
1358     // Now trunc the NewOp to the original result.
1359     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1360     MI.eraseFromParent();
1361     return Legalized;
1362   }
1363   case TargetOpcode::G_CTTZ:
1364   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1365   case TargetOpcode::G_CTLZ:
1366   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1367   case TargetOpcode::G_CTPOP: {
1368     if (TypeIdx == 0) {
1369       Observer.changingInstr(MI);
1370       widenScalarDst(MI, WideTy, 0);
1371       Observer.changedInstr(MI);
1372       return Legalized;
1373     }
1374 
1375     Register SrcReg = MI.getOperand(1).getReg();
1376 
1377     // First ZEXT the input.
1378     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1379     LLT CurTy = MRI.getType(SrcReg);
1380     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1381       // The count is the same in the larger type except if the original
1382       // value was zero.  This can be handled by setting the bit just off
1383       // the top of the original type.
1384       auto TopBit =
1385           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1386       MIBSrc = MIRBuilder.buildOr(
1387         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1388     }
1389 
1390     // Perform the operation at the larger size.
1391     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1392     // This is already the correct result for CTPOP and CTTZs
1393     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1394         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1395       // The correct result is NewOp - (Difference in widety and current ty).
1396       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1397       MIBNewOp = MIRBuilder.buildInstr(
1398           TargetOpcode::G_SUB, {WideTy},
1399           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1400     }
1401 
1402     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1403     MI.eraseFromParent();
1404     return Legalized;
1405   }
1406   case TargetOpcode::G_BSWAP: {
1407     Observer.changingInstr(MI);
1408     Register DstReg = MI.getOperand(0).getReg();
1409 
1410     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1411     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1412     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1413     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1414 
1415     MI.getOperand(0).setReg(DstExt);
1416 
1417     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1418 
1419     LLT Ty = MRI.getType(DstReg);
1420     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1421     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1422     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1423       .addDef(ShrReg)
1424       .addUse(DstExt)
1425       .addUse(ShiftAmtReg);
1426 
1427     MIRBuilder.buildTrunc(DstReg, ShrReg);
1428     Observer.changedInstr(MI);
1429     return Legalized;
1430   }
1431   case TargetOpcode::G_ADD:
1432   case TargetOpcode::G_AND:
1433   case TargetOpcode::G_MUL:
1434   case TargetOpcode::G_OR:
1435   case TargetOpcode::G_XOR:
1436   case TargetOpcode::G_SUB:
1437     // Perform operation at larger width (any extension is fines here, high bits
1438     // don't affect the result) and then truncate the result back to the
1439     // original type.
1440     Observer.changingInstr(MI);
1441     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1442     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1443     widenScalarDst(MI, WideTy);
1444     Observer.changedInstr(MI);
1445     return Legalized;
1446 
1447   case TargetOpcode::G_SHL:
1448     Observer.changingInstr(MI);
1449 
1450     if (TypeIdx == 0) {
1451       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1452       widenScalarDst(MI, WideTy);
1453     } else {
1454       assert(TypeIdx == 1);
1455       // The "number of bits to shift" operand must preserve its value as an
1456       // unsigned integer:
1457       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1458     }
1459 
1460     Observer.changedInstr(MI);
1461     return Legalized;
1462 
1463   case TargetOpcode::G_SDIV:
1464   case TargetOpcode::G_SREM:
1465   case TargetOpcode::G_SMIN:
1466   case TargetOpcode::G_SMAX:
1467     Observer.changingInstr(MI);
1468     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1469     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1470     widenScalarDst(MI, WideTy);
1471     Observer.changedInstr(MI);
1472     return Legalized;
1473 
1474   case TargetOpcode::G_ASHR:
1475   case TargetOpcode::G_LSHR:
1476     Observer.changingInstr(MI);
1477 
1478     if (TypeIdx == 0) {
1479       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1480         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1481 
1482       widenScalarSrc(MI, WideTy, 1, CvtOp);
1483       widenScalarDst(MI, WideTy);
1484     } else {
1485       assert(TypeIdx == 1);
1486       // The "number of bits to shift" operand must preserve its value as an
1487       // unsigned integer:
1488       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1489     }
1490 
1491     Observer.changedInstr(MI);
1492     return Legalized;
1493   case TargetOpcode::G_UDIV:
1494   case TargetOpcode::G_UREM:
1495   case TargetOpcode::G_UMIN:
1496   case TargetOpcode::G_UMAX:
1497     Observer.changingInstr(MI);
1498     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1499     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1500     widenScalarDst(MI, WideTy);
1501     Observer.changedInstr(MI);
1502     return Legalized;
1503 
1504   case TargetOpcode::G_SELECT:
1505     Observer.changingInstr(MI);
1506     if (TypeIdx == 0) {
1507       // Perform operation at larger width (any extension is fine here, high
1508       // bits don't affect the result) and then truncate the result back to the
1509       // original type.
1510       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1511       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1512       widenScalarDst(MI, WideTy);
1513     } else {
1514       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1515       // Explicit extension is required here since high bits affect the result.
1516       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1517     }
1518     Observer.changedInstr(MI);
1519     return Legalized;
1520 
1521   case TargetOpcode::G_FPTOSI:
1522   case TargetOpcode::G_FPTOUI:
1523     if (TypeIdx != 0)
1524       return UnableToLegalize;
1525     Observer.changingInstr(MI);
1526     widenScalarDst(MI, WideTy);
1527     Observer.changedInstr(MI);
1528     return Legalized;
1529 
1530   case TargetOpcode::G_SITOFP:
1531     if (TypeIdx != 1)
1532       return UnableToLegalize;
1533     Observer.changingInstr(MI);
1534     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1535     Observer.changedInstr(MI);
1536     return Legalized;
1537 
1538   case TargetOpcode::G_UITOFP:
1539     if (TypeIdx != 1)
1540       return UnableToLegalize;
1541     Observer.changingInstr(MI);
1542     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1543     Observer.changedInstr(MI);
1544     return Legalized;
1545 
1546   case TargetOpcode::G_LOAD:
1547   case TargetOpcode::G_SEXTLOAD:
1548   case TargetOpcode::G_ZEXTLOAD:
1549     Observer.changingInstr(MI);
1550     widenScalarDst(MI, WideTy);
1551     Observer.changedInstr(MI);
1552     return Legalized;
1553 
1554   case TargetOpcode::G_STORE: {
1555     if (TypeIdx != 0)
1556       return UnableToLegalize;
1557 
1558     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1559     if (!isPowerOf2_32(Ty.getSizeInBits()))
1560       return UnableToLegalize;
1561 
1562     Observer.changingInstr(MI);
1563 
1564     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1565       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1566     widenScalarSrc(MI, WideTy, 0, ExtType);
1567 
1568     Observer.changedInstr(MI);
1569     return Legalized;
1570   }
1571   case TargetOpcode::G_CONSTANT: {
1572     MachineOperand &SrcMO = MI.getOperand(1);
1573     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1574     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1575     Observer.changingInstr(MI);
1576     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1577 
1578     widenScalarDst(MI, WideTy);
1579     Observer.changedInstr(MI);
1580     return Legalized;
1581   }
1582   case TargetOpcode::G_FCONSTANT: {
1583     MachineOperand &SrcMO = MI.getOperand(1);
1584     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1585     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1586     bool LosesInfo;
1587     switch (WideTy.getSizeInBits()) {
1588     case 32:
1589       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1590                   &LosesInfo);
1591       break;
1592     case 64:
1593       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1594                   &LosesInfo);
1595       break;
1596     default:
1597       return UnableToLegalize;
1598     }
1599 
1600     assert(!LosesInfo && "extend should always be lossless");
1601 
1602     Observer.changingInstr(MI);
1603     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1604 
1605     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1606     Observer.changedInstr(MI);
1607     return Legalized;
1608   }
1609   case TargetOpcode::G_IMPLICIT_DEF: {
1610     Observer.changingInstr(MI);
1611     widenScalarDst(MI, WideTy);
1612     Observer.changedInstr(MI);
1613     return Legalized;
1614   }
1615   case TargetOpcode::G_BRCOND:
1616     Observer.changingInstr(MI);
1617     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1618     Observer.changedInstr(MI);
1619     return Legalized;
1620 
1621   case TargetOpcode::G_FCMP:
1622     Observer.changingInstr(MI);
1623     if (TypeIdx == 0)
1624       widenScalarDst(MI, WideTy);
1625     else {
1626       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1627       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1628     }
1629     Observer.changedInstr(MI);
1630     return Legalized;
1631 
1632   case TargetOpcode::G_ICMP:
1633     Observer.changingInstr(MI);
1634     if (TypeIdx == 0)
1635       widenScalarDst(MI, WideTy);
1636     else {
1637       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1638                                MI.getOperand(1).getPredicate()))
1639                                ? TargetOpcode::G_SEXT
1640                                : TargetOpcode::G_ZEXT;
1641       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1642       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1643     }
1644     Observer.changedInstr(MI);
1645     return Legalized;
1646 
1647   case TargetOpcode::G_GEP:
1648     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1649     Observer.changingInstr(MI);
1650     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1651     Observer.changedInstr(MI);
1652     return Legalized;
1653 
1654   case TargetOpcode::G_PHI: {
1655     assert(TypeIdx == 0 && "Expecting only Idx 0");
1656 
1657     Observer.changingInstr(MI);
1658     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1659       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1660       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1661       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1662     }
1663 
1664     MachineBasicBlock &MBB = *MI.getParent();
1665     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1666     widenScalarDst(MI, WideTy);
1667     Observer.changedInstr(MI);
1668     return Legalized;
1669   }
1670   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1671     if (TypeIdx == 0) {
1672       Register VecReg = MI.getOperand(1).getReg();
1673       LLT VecTy = MRI.getType(VecReg);
1674       Observer.changingInstr(MI);
1675 
1676       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1677                                      WideTy.getSizeInBits()),
1678                      1, TargetOpcode::G_SEXT);
1679 
1680       widenScalarDst(MI, WideTy, 0);
1681       Observer.changedInstr(MI);
1682       return Legalized;
1683     }
1684 
1685     if (TypeIdx != 2)
1686       return UnableToLegalize;
1687     Observer.changingInstr(MI);
1688     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1689     Observer.changedInstr(MI);
1690     return Legalized;
1691   }
1692   case TargetOpcode::G_FADD:
1693   case TargetOpcode::G_FMUL:
1694   case TargetOpcode::G_FSUB:
1695   case TargetOpcode::G_FMA:
1696   case TargetOpcode::G_FNEG:
1697   case TargetOpcode::G_FABS:
1698   case TargetOpcode::G_FCANONICALIZE:
1699   case TargetOpcode::G_FMINNUM:
1700   case TargetOpcode::G_FMAXNUM:
1701   case TargetOpcode::G_FMINNUM_IEEE:
1702   case TargetOpcode::G_FMAXNUM_IEEE:
1703   case TargetOpcode::G_FMINIMUM:
1704   case TargetOpcode::G_FMAXIMUM:
1705   case TargetOpcode::G_FDIV:
1706   case TargetOpcode::G_FREM:
1707   case TargetOpcode::G_FCEIL:
1708   case TargetOpcode::G_FFLOOR:
1709   case TargetOpcode::G_FCOS:
1710   case TargetOpcode::G_FSIN:
1711   case TargetOpcode::G_FLOG10:
1712   case TargetOpcode::G_FLOG:
1713   case TargetOpcode::G_FLOG2:
1714   case TargetOpcode::G_FRINT:
1715   case TargetOpcode::G_FNEARBYINT:
1716   case TargetOpcode::G_FSQRT:
1717   case TargetOpcode::G_FEXP:
1718   case TargetOpcode::G_FEXP2:
1719   case TargetOpcode::G_FPOW:
1720   case TargetOpcode::G_INTRINSIC_TRUNC:
1721   case TargetOpcode::G_INTRINSIC_ROUND:
1722     assert(TypeIdx == 0);
1723     Observer.changingInstr(MI);
1724 
1725     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1726       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1727 
1728     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1729     Observer.changedInstr(MI);
1730     return Legalized;
1731   case TargetOpcode::G_INTTOPTR:
1732     if (TypeIdx != 1)
1733       return UnableToLegalize;
1734 
1735     Observer.changingInstr(MI);
1736     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1737     Observer.changedInstr(MI);
1738     return Legalized;
1739   case TargetOpcode::G_PTRTOINT:
1740     if (TypeIdx != 0)
1741       return UnableToLegalize;
1742 
1743     Observer.changingInstr(MI);
1744     widenScalarDst(MI, WideTy, 0);
1745     Observer.changedInstr(MI);
1746     return Legalized;
1747   case TargetOpcode::G_BUILD_VECTOR: {
1748     Observer.changingInstr(MI);
1749 
1750     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1751     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1752       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1753 
1754     // Avoid changing the result vector type if the source element type was
1755     // requested.
1756     if (TypeIdx == 1) {
1757       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1758       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1759     } else {
1760       widenScalarDst(MI, WideTy, 0);
1761     }
1762 
1763     Observer.changedInstr(MI);
1764     return Legalized;
1765   }
1766   case TargetOpcode::G_SEXT_INREG:
1767     if (TypeIdx != 0)
1768       return UnableToLegalize;
1769 
1770     Observer.changingInstr(MI);
1771     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1772     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1773     Observer.changedInstr(MI);
1774     return Legalized;
1775   }
1776 }
1777 
1778 LegalizerHelper::LegalizeResult
1779 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1780   using namespace TargetOpcode;
1781   MIRBuilder.setInstr(MI);
1782 
1783   switch(MI.getOpcode()) {
1784   default:
1785     return UnableToLegalize;
1786   case TargetOpcode::G_SREM:
1787   case TargetOpcode::G_UREM: {
1788     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1789     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1790         .addDef(QuotReg)
1791         .addUse(MI.getOperand(1).getReg())
1792         .addUse(MI.getOperand(2).getReg());
1793 
1794     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1795     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1796     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1797                         ProdReg);
1798     MI.eraseFromParent();
1799     return Legalized;
1800   }
1801   case TargetOpcode::G_SMULO:
1802   case TargetOpcode::G_UMULO: {
1803     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1804     // result.
1805     Register Res = MI.getOperand(0).getReg();
1806     Register Overflow = MI.getOperand(1).getReg();
1807     Register LHS = MI.getOperand(2).getReg();
1808     Register RHS = MI.getOperand(3).getReg();
1809 
1810     MIRBuilder.buildMul(Res, LHS, RHS);
1811 
1812     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1813                           ? TargetOpcode::G_SMULH
1814                           : TargetOpcode::G_UMULH;
1815 
1816     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1817     MIRBuilder.buildInstr(Opcode)
1818       .addDef(HiPart)
1819       .addUse(LHS)
1820       .addUse(RHS);
1821 
1822     Register Zero = MRI.createGenericVirtualRegister(Ty);
1823     MIRBuilder.buildConstant(Zero, 0);
1824 
1825     // For *signed* multiply, overflow is detected by checking:
1826     // (hi != (lo >> bitwidth-1))
1827     if (Opcode == TargetOpcode::G_SMULH) {
1828       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1829       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1830       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1831       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1832         .addDef(Shifted)
1833         .addUse(Res)
1834         .addUse(ShiftAmt);
1835       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1836     } else {
1837       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1838     }
1839     MI.eraseFromParent();
1840     return Legalized;
1841   }
1842   case TargetOpcode::G_FNEG: {
1843     // TODO: Handle vector types once we are able to
1844     // represent them.
1845     if (Ty.isVector())
1846       return UnableToLegalize;
1847     Register Res = MI.getOperand(0).getReg();
1848     Type *ZeroTy;
1849     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1850     switch (Ty.getSizeInBits()) {
1851     case 16:
1852       ZeroTy = Type::getHalfTy(Ctx);
1853       break;
1854     case 32:
1855       ZeroTy = Type::getFloatTy(Ctx);
1856       break;
1857     case 64:
1858       ZeroTy = Type::getDoubleTy(Ctx);
1859       break;
1860     case 128:
1861       ZeroTy = Type::getFP128Ty(Ctx);
1862       break;
1863     default:
1864       llvm_unreachable("unexpected floating-point type");
1865     }
1866     ConstantFP &ZeroForNegation =
1867         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1868     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1869     Register SubByReg = MI.getOperand(1).getReg();
1870     Register ZeroReg = Zero->getOperand(0).getReg();
1871     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1872                           MI.getFlags());
1873     MI.eraseFromParent();
1874     return Legalized;
1875   }
1876   case TargetOpcode::G_FSUB: {
1877     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1878     // First, check if G_FNEG is marked as Lower. If so, we may
1879     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1880     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1881       return UnableToLegalize;
1882     Register Res = MI.getOperand(0).getReg();
1883     Register LHS = MI.getOperand(1).getReg();
1884     Register RHS = MI.getOperand(2).getReg();
1885     Register Neg = MRI.createGenericVirtualRegister(Ty);
1886     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1887     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1888     MI.eraseFromParent();
1889     return Legalized;
1890   }
1891   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1892     Register OldValRes = MI.getOperand(0).getReg();
1893     Register SuccessRes = MI.getOperand(1).getReg();
1894     Register Addr = MI.getOperand(2).getReg();
1895     Register CmpVal = MI.getOperand(3).getReg();
1896     Register NewVal = MI.getOperand(4).getReg();
1897     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1898                                   **MI.memoperands_begin());
1899     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1900     MI.eraseFromParent();
1901     return Legalized;
1902   }
1903   case TargetOpcode::G_LOAD:
1904   case TargetOpcode::G_SEXTLOAD:
1905   case TargetOpcode::G_ZEXTLOAD: {
1906     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1907     Register DstReg = MI.getOperand(0).getReg();
1908     Register PtrReg = MI.getOperand(1).getReg();
1909     LLT DstTy = MRI.getType(DstReg);
1910     auto &MMO = **MI.memoperands_begin();
1911 
1912     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
1913       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
1914         // This load needs splitting into power of 2 sized loads.
1915         if (DstTy.isVector())
1916           return UnableToLegalize;
1917         if (isPowerOf2_32(DstTy.getSizeInBits()))
1918           return UnableToLegalize; // Don't know what we're being asked to do.
1919 
1920         // Our strategy here is to generate anyextending loads for the smaller
1921         // types up to next power-2 result type, and then combine the two larger
1922         // result values together, before truncating back down to the non-pow-2
1923         // type.
1924         // E.g. v1 = i24 load =>
1925         // v2 = i32 load (2 byte)
1926         // v3 = i32 load (1 byte)
1927         // v4 = i32 shl v3, 16
1928         // v5 = i32 or v4, v2
1929         // v1 = i24 trunc v5
1930         // By doing this we generate the correct truncate which should get
1931         // combined away as an artifact with a matching extend.
1932         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
1933         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
1934 
1935         MachineFunction &MF = MIRBuilder.getMF();
1936         MachineMemOperand *LargeMMO =
1937             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
1938         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
1939             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
1940 
1941         LLT PtrTy = MRI.getType(PtrReg);
1942         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
1943         LLT AnyExtTy = LLT::scalar(AnyExtSize);
1944         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
1945         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
1946         auto LargeLoad =
1947             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
1948 
1949         auto OffsetCst =
1950             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
1951         Register GEPReg = MRI.createGenericVirtualRegister(PtrTy);
1952         auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
1953         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
1954                                               *SmallMMO);
1955 
1956         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
1957         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
1958         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
1959         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
1960         MI.eraseFromParent();
1961         return Legalized;
1962       }
1963       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1964       MI.eraseFromParent();
1965       return Legalized;
1966     }
1967 
1968     if (DstTy.isScalar()) {
1969       Register TmpReg =
1970           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
1971       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1972       switch (MI.getOpcode()) {
1973       default:
1974         llvm_unreachable("Unexpected opcode");
1975       case TargetOpcode::G_LOAD:
1976         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1977         break;
1978       case TargetOpcode::G_SEXTLOAD:
1979         MIRBuilder.buildSExt(DstReg, TmpReg);
1980         break;
1981       case TargetOpcode::G_ZEXTLOAD:
1982         MIRBuilder.buildZExt(DstReg, TmpReg);
1983         break;
1984       }
1985       MI.eraseFromParent();
1986       return Legalized;
1987     }
1988 
1989     return UnableToLegalize;
1990   }
1991   case TargetOpcode::G_STORE: {
1992     // Lower a non-power of 2 store into multiple pow-2 stores.
1993     // E.g. split an i24 store into an i16 store + i8 store.
1994     // We do this by first extending the stored value to the next largest power
1995     // of 2 type, and then using truncating stores to store the components.
1996     // By doing this, likewise with G_LOAD, generate an extend that can be
1997     // artifact-combined away instead of leaving behind extracts.
1998     Register SrcReg = MI.getOperand(0).getReg();
1999     Register PtrReg = MI.getOperand(1).getReg();
2000     LLT SrcTy = MRI.getType(SrcReg);
2001     MachineMemOperand &MMO = **MI.memoperands_begin();
2002     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2003       return UnableToLegalize;
2004     if (SrcTy.isVector())
2005       return UnableToLegalize;
2006     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2007       return UnableToLegalize; // Don't know what we're being asked to do.
2008 
2009     // Extend to the next pow-2.
2010     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2011     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2012 
2013     // Obtain the smaller value by shifting away the larger value.
2014     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2015     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2016     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2017     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2018 
2019     // Generate the GEP and truncating stores.
2020     LLT PtrTy = MRI.getType(PtrReg);
2021     auto OffsetCst =
2022         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2023     Register GEPReg = MRI.createGenericVirtualRegister(PtrTy);
2024     auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2025 
2026     MachineFunction &MF = MIRBuilder.getMF();
2027     MachineMemOperand *LargeMMO =
2028         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2029     MachineMemOperand *SmallMMO =
2030         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2031     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2032     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2033     MI.eraseFromParent();
2034     return Legalized;
2035   }
2036   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2037   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2038   case TargetOpcode::G_CTLZ:
2039   case TargetOpcode::G_CTTZ:
2040   case TargetOpcode::G_CTPOP:
2041     return lowerBitCount(MI, TypeIdx, Ty);
2042   case G_UADDO: {
2043     Register Res = MI.getOperand(0).getReg();
2044     Register CarryOut = MI.getOperand(1).getReg();
2045     Register LHS = MI.getOperand(2).getReg();
2046     Register RHS = MI.getOperand(3).getReg();
2047 
2048     MIRBuilder.buildAdd(Res, LHS, RHS);
2049     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2050 
2051     MI.eraseFromParent();
2052     return Legalized;
2053   }
2054   case G_UADDE: {
2055     Register Res = MI.getOperand(0).getReg();
2056     Register CarryOut = MI.getOperand(1).getReg();
2057     Register LHS = MI.getOperand(2).getReg();
2058     Register RHS = MI.getOperand(3).getReg();
2059     Register CarryIn = MI.getOperand(4).getReg();
2060 
2061     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2062     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2063 
2064     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2065     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2066     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2067     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2068 
2069     MI.eraseFromParent();
2070     return Legalized;
2071   }
2072   case G_USUBO: {
2073     Register Res = MI.getOperand(0).getReg();
2074     Register BorrowOut = MI.getOperand(1).getReg();
2075     Register LHS = MI.getOperand(2).getReg();
2076     Register RHS = MI.getOperand(3).getReg();
2077 
2078     MIRBuilder.buildSub(Res, LHS, RHS);
2079     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2080 
2081     MI.eraseFromParent();
2082     return Legalized;
2083   }
2084   case G_USUBE: {
2085     Register Res = MI.getOperand(0).getReg();
2086     Register BorrowOut = MI.getOperand(1).getReg();
2087     Register LHS = MI.getOperand(2).getReg();
2088     Register RHS = MI.getOperand(3).getReg();
2089     Register BorrowIn = MI.getOperand(4).getReg();
2090 
2091     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2092     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2093     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2094     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2095 
2096     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2097     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2098     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2099     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2100     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2101     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2102 
2103     MI.eraseFromParent();
2104     return Legalized;
2105   }
2106   case G_UITOFP:
2107     return lowerUITOFP(MI, TypeIdx, Ty);
2108   case G_SITOFP:
2109     return lowerSITOFP(MI, TypeIdx, Ty);
2110   case G_SMIN:
2111   case G_SMAX:
2112   case G_UMIN:
2113   case G_UMAX:
2114     return lowerMinMax(MI, TypeIdx, Ty);
2115   case G_FCOPYSIGN:
2116     return lowerFCopySign(MI, TypeIdx, Ty);
2117   case G_FMINNUM:
2118   case G_FMAXNUM:
2119     return lowerFMinNumMaxNum(MI);
2120   case G_UNMERGE_VALUES:
2121     return lowerUnmergeValues(MI);
2122   case TargetOpcode::G_SEXT_INREG: {
2123     assert(MI.getOperand(2).isImm() && "Expected immediate");
2124     int64_t SizeInBits = MI.getOperand(2).getImm();
2125 
2126     Register DstReg = MI.getOperand(0).getReg();
2127     Register SrcReg = MI.getOperand(1).getReg();
2128     LLT DstTy = MRI.getType(DstReg);
2129     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2130 
2131     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2132     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2133     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2134     MI.eraseFromParent();
2135     return Legalized;
2136   }
2137   case G_SHUFFLE_VECTOR:
2138     return lowerShuffleVector(MI);
2139   }
2140 }
2141 
2142 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2143     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2144   SmallVector<Register, 2> DstRegs;
2145 
2146   unsigned NarrowSize = NarrowTy.getSizeInBits();
2147   Register DstReg = MI.getOperand(0).getReg();
2148   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2149   int NumParts = Size / NarrowSize;
2150   // FIXME: Don't know how to handle the situation where the small vectors
2151   // aren't all the same size yet.
2152   if (Size % NarrowSize != 0)
2153     return UnableToLegalize;
2154 
2155   for (int i = 0; i < NumParts; ++i) {
2156     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2157     MIRBuilder.buildUndef(TmpReg);
2158     DstRegs.push_back(TmpReg);
2159   }
2160 
2161   if (NarrowTy.isVector())
2162     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2163   else
2164     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2165 
2166   MI.eraseFromParent();
2167   return Legalized;
2168 }
2169 
2170 LegalizerHelper::LegalizeResult
2171 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2172                                           LLT NarrowTy) {
2173   const unsigned Opc = MI.getOpcode();
2174   const unsigned NumOps = MI.getNumOperands() - 1;
2175   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2176   const Register DstReg = MI.getOperand(0).getReg();
2177   const unsigned Flags = MI.getFlags();
2178   const LLT DstTy = MRI.getType(DstReg);
2179   const unsigned Size = DstTy.getSizeInBits();
2180   const int NumParts = Size / NarrowSize;
2181   const LLT EltTy = DstTy.getElementType();
2182   const unsigned EltSize = EltTy.getSizeInBits();
2183   const unsigned BitsForNumParts = NarrowSize * NumParts;
2184 
2185   // Check if we have any leftovers. If we do, then only handle the case where
2186   // the leftover is one element.
2187   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2188     return UnableToLegalize;
2189 
2190   if (BitsForNumParts != Size) {
2191     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2192     MIRBuilder.buildUndef(AccumDstReg);
2193 
2194     // Handle the pieces which evenly divide into the requested type with
2195     // extract/op/insert sequence.
2196     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2197       SmallVector<SrcOp, 4> SrcOps;
2198       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2199         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2200         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2201         SrcOps.push_back(PartOpReg);
2202       }
2203 
2204       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2205       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2206 
2207       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2208       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2209       AccumDstReg = PartInsertReg;
2210     }
2211 
2212     // Handle the remaining element sized leftover piece.
2213     SmallVector<SrcOp, 4> SrcOps;
2214     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2215       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2216       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2217                               BitsForNumParts);
2218       SrcOps.push_back(PartOpReg);
2219     }
2220 
2221     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2222     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2223     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2224     MI.eraseFromParent();
2225 
2226     return Legalized;
2227   }
2228 
2229   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2230 
2231   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2232 
2233   if (NumOps >= 2)
2234     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2235 
2236   if (NumOps >= 3)
2237     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2238 
2239   for (int i = 0; i < NumParts; ++i) {
2240     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2241 
2242     if (NumOps == 1)
2243       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2244     else if (NumOps == 2) {
2245       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2246     } else if (NumOps == 3) {
2247       MIRBuilder.buildInstr(Opc, {DstReg},
2248                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2249     }
2250 
2251     DstRegs.push_back(DstReg);
2252   }
2253 
2254   if (NarrowTy.isVector())
2255     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2256   else
2257     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2258 
2259   MI.eraseFromParent();
2260   return Legalized;
2261 }
2262 
2263 // Handle splitting vector operations which need to have the same number of
2264 // elements in each type index, but each type index may have a different element
2265 // type.
2266 //
2267 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2268 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2269 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2270 //
2271 // Also handles some irregular breakdown cases, e.g.
2272 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2273 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2274 //             s64 = G_SHL s64, s32
2275 LegalizerHelper::LegalizeResult
2276 LegalizerHelper::fewerElementsVectorMultiEltType(
2277   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2278   if (TypeIdx != 0)
2279     return UnableToLegalize;
2280 
2281   const LLT NarrowTy0 = NarrowTyArg;
2282   const unsigned NewNumElts =
2283       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2284 
2285   const Register DstReg = MI.getOperand(0).getReg();
2286   LLT DstTy = MRI.getType(DstReg);
2287   LLT LeftoverTy0;
2288 
2289   // All of the operands need to have the same number of elements, so if we can
2290   // determine a type breakdown for the result type, we can for all of the
2291   // source types.
2292   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2293   if (NumParts < 0)
2294     return UnableToLegalize;
2295 
2296   SmallVector<MachineInstrBuilder, 4> NewInsts;
2297 
2298   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2299   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2300 
2301   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2302     LLT LeftoverTy;
2303     Register SrcReg = MI.getOperand(I).getReg();
2304     LLT SrcTyI = MRI.getType(SrcReg);
2305     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2306     LLT LeftoverTyI;
2307 
2308     // Split this operand into the requested typed registers, and any leftover
2309     // required to reproduce the original type.
2310     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2311                       LeftoverRegs))
2312       return UnableToLegalize;
2313 
2314     if (I == 1) {
2315       // For the first operand, create an instruction for each part and setup
2316       // the result.
2317       for (Register PartReg : PartRegs) {
2318         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2319         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2320                                .addDef(PartDstReg)
2321                                .addUse(PartReg));
2322         DstRegs.push_back(PartDstReg);
2323       }
2324 
2325       for (Register LeftoverReg : LeftoverRegs) {
2326         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2327         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2328                                .addDef(PartDstReg)
2329                                .addUse(LeftoverReg));
2330         LeftoverDstRegs.push_back(PartDstReg);
2331       }
2332     } else {
2333       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2334 
2335       // Add the newly created operand splits to the existing instructions. The
2336       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2337       // pieces.
2338       unsigned InstCount = 0;
2339       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2340         NewInsts[InstCount++].addUse(PartRegs[J]);
2341       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2342         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2343     }
2344 
2345     PartRegs.clear();
2346     LeftoverRegs.clear();
2347   }
2348 
2349   // Insert the newly built operations and rebuild the result register.
2350   for (auto &MIB : NewInsts)
2351     MIRBuilder.insertInstr(MIB);
2352 
2353   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2354 
2355   MI.eraseFromParent();
2356   return Legalized;
2357 }
2358 
2359 LegalizerHelper::LegalizeResult
2360 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2361                                           LLT NarrowTy) {
2362   if (TypeIdx != 0)
2363     return UnableToLegalize;
2364 
2365   Register DstReg = MI.getOperand(0).getReg();
2366   Register SrcReg = MI.getOperand(1).getReg();
2367   LLT DstTy = MRI.getType(DstReg);
2368   LLT SrcTy = MRI.getType(SrcReg);
2369 
2370   LLT NarrowTy0 = NarrowTy;
2371   LLT NarrowTy1;
2372   unsigned NumParts;
2373 
2374   if (NarrowTy.isVector()) {
2375     // Uneven breakdown not handled.
2376     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2377     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2378       return UnableToLegalize;
2379 
2380     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2381   } else {
2382     NumParts = DstTy.getNumElements();
2383     NarrowTy1 = SrcTy.getElementType();
2384   }
2385 
2386   SmallVector<Register, 4> SrcRegs, DstRegs;
2387   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2388 
2389   for (unsigned I = 0; I < NumParts; ++I) {
2390     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2391     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2392       .addDef(DstReg)
2393       .addUse(SrcRegs[I]);
2394 
2395     NewInst->setFlags(MI.getFlags());
2396     DstRegs.push_back(DstReg);
2397   }
2398 
2399   if (NarrowTy.isVector())
2400     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2401   else
2402     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2403 
2404   MI.eraseFromParent();
2405   return Legalized;
2406 }
2407 
2408 LegalizerHelper::LegalizeResult
2409 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2410                                         LLT NarrowTy) {
2411   Register DstReg = MI.getOperand(0).getReg();
2412   Register Src0Reg = MI.getOperand(2).getReg();
2413   LLT DstTy = MRI.getType(DstReg);
2414   LLT SrcTy = MRI.getType(Src0Reg);
2415 
2416   unsigned NumParts;
2417   LLT NarrowTy0, NarrowTy1;
2418 
2419   if (TypeIdx == 0) {
2420     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2421     unsigned OldElts = DstTy.getNumElements();
2422 
2423     NarrowTy0 = NarrowTy;
2424     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2425     NarrowTy1 = NarrowTy.isVector() ?
2426       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2427       SrcTy.getElementType();
2428 
2429   } else {
2430     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2431     unsigned OldElts = SrcTy.getNumElements();
2432 
2433     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2434       NarrowTy.getNumElements();
2435     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2436                             DstTy.getScalarSizeInBits());
2437     NarrowTy1 = NarrowTy;
2438   }
2439 
2440   // FIXME: Don't know how to handle the situation where the small vectors
2441   // aren't all the same size yet.
2442   if (NarrowTy1.isVector() &&
2443       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2444     return UnableToLegalize;
2445 
2446   CmpInst::Predicate Pred
2447     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2448 
2449   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2450   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2451   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2452 
2453   for (unsigned I = 0; I < NumParts; ++I) {
2454     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2455     DstRegs.push_back(DstReg);
2456 
2457     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2458       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2459     else {
2460       MachineInstr *NewCmp
2461         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2462       NewCmp->setFlags(MI.getFlags());
2463     }
2464   }
2465 
2466   if (NarrowTy1.isVector())
2467     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2468   else
2469     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2470 
2471   MI.eraseFromParent();
2472   return Legalized;
2473 }
2474 
2475 LegalizerHelper::LegalizeResult
2476 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2477                                            LLT NarrowTy) {
2478   Register DstReg = MI.getOperand(0).getReg();
2479   Register CondReg = MI.getOperand(1).getReg();
2480 
2481   unsigned NumParts = 0;
2482   LLT NarrowTy0, NarrowTy1;
2483 
2484   LLT DstTy = MRI.getType(DstReg);
2485   LLT CondTy = MRI.getType(CondReg);
2486   unsigned Size = DstTy.getSizeInBits();
2487 
2488   assert(TypeIdx == 0 || CondTy.isVector());
2489 
2490   if (TypeIdx == 0) {
2491     NarrowTy0 = NarrowTy;
2492     NarrowTy1 = CondTy;
2493 
2494     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2495     // FIXME: Don't know how to handle the situation where the small vectors
2496     // aren't all the same size yet.
2497     if (Size % NarrowSize != 0)
2498       return UnableToLegalize;
2499 
2500     NumParts = Size / NarrowSize;
2501 
2502     // Need to break down the condition type
2503     if (CondTy.isVector()) {
2504       if (CondTy.getNumElements() == NumParts)
2505         NarrowTy1 = CondTy.getElementType();
2506       else
2507         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2508                                 CondTy.getScalarSizeInBits());
2509     }
2510   } else {
2511     NumParts = CondTy.getNumElements();
2512     if (NarrowTy.isVector()) {
2513       // TODO: Handle uneven breakdown.
2514       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2515         return UnableToLegalize;
2516 
2517       return UnableToLegalize;
2518     } else {
2519       NarrowTy0 = DstTy.getElementType();
2520       NarrowTy1 = NarrowTy;
2521     }
2522   }
2523 
2524   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2525   if (CondTy.isVector())
2526     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2527 
2528   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2529   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2530 
2531   for (unsigned i = 0; i < NumParts; ++i) {
2532     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2533     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2534                            Src1Regs[i], Src2Regs[i]);
2535     DstRegs.push_back(DstReg);
2536   }
2537 
2538   if (NarrowTy0.isVector())
2539     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2540   else
2541     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2542 
2543   MI.eraseFromParent();
2544   return Legalized;
2545 }
2546 
2547 LegalizerHelper::LegalizeResult
2548 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2549                                         LLT NarrowTy) {
2550   const Register DstReg = MI.getOperand(0).getReg();
2551   LLT PhiTy = MRI.getType(DstReg);
2552   LLT LeftoverTy;
2553 
2554   // All of the operands need to have the same number of elements, so if we can
2555   // determine a type breakdown for the result type, we can for all of the
2556   // source types.
2557   int NumParts, NumLeftover;
2558   std::tie(NumParts, NumLeftover)
2559     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2560   if (NumParts < 0)
2561     return UnableToLegalize;
2562 
2563   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2564   SmallVector<MachineInstrBuilder, 4> NewInsts;
2565 
2566   const int TotalNumParts = NumParts + NumLeftover;
2567 
2568   // Insert the new phis in the result block first.
2569   for (int I = 0; I != TotalNumParts; ++I) {
2570     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2571     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2572     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2573                        .addDef(PartDstReg));
2574     if (I < NumParts)
2575       DstRegs.push_back(PartDstReg);
2576     else
2577       LeftoverDstRegs.push_back(PartDstReg);
2578   }
2579 
2580   MachineBasicBlock *MBB = MI.getParent();
2581   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2582   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2583 
2584   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2585 
2586   // Insert code to extract the incoming values in each predecessor block.
2587   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2588     PartRegs.clear();
2589     LeftoverRegs.clear();
2590 
2591     Register SrcReg = MI.getOperand(I).getReg();
2592     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2593     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2594 
2595     LLT Unused;
2596     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2597                       LeftoverRegs))
2598       return UnableToLegalize;
2599 
2600     // Add the newly created operand splits to the existing instructions. The
2601     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2602     // pieces.
2603     for (int J = 0; J != TotalNumParts; ++J) {
2604       MachineInstrBuilder MIB = NewInsts[J];
2605       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2606       MIB.addMBB(&OpMBB);
2607     }
2608   }
2609 
2610   MI.eraseFromParent();
2611   return Legalized;
2612 }
2613 
2614 LegalizerHelper::LegalizeResult
2615 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2616                                                   unsigned TypeIdx,
2617                                                   LLT NarrowTy) {
2618   if (TypeIdx != 1)
2619     return UnableToLegalize;
2620 
2621   const int NumDst = MI.getNumOperands() - 1;
2622   const Register SrcReg = MI.getOperand(NumDst).getReg();
2623   LLT SrcTy = MRI.getType(SrcReg);
2624 
2625   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2626 
2627   // TODO: Create sequence of extracts.
2628   if (DstTy == NarrowTy)
2629     return UnableToLegalize;
2630 
2631   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2632   if (DstTy == GCDTy) {
2633     // This would just be a copy of the same unmerge.
2634     // TODO: Create extracts, pad with undef and create intermediate merges.
2635     return UnableToLegalize;
2636   }
2637 
2638   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2639   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2640   const int PartsPerUnmerge = NumDst / NumUnmerge;
2641 
2642   for (int I = 0; I != NumUnmerge; ++I) {
2643     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2644 
2645     for (int J = 0; J != PartsPerUnmerge; ++J)
2646       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2647     MIB.addUse(Unmerge.getReg(I));
2648   }
2649 
2650   MI.eraseFromParent();
2651   return Legalized;
2652 }
2653 
2654 LegalizerHelper::LegalizeResult
2655 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2656                                       LLT NarrowTy) {
2657   // FIXME: Don't know how to handle secondary types yet.
2658   if (TypeIdx != 0)
2659     return UnableToLegalize;
2660 
2661   MachineMemOperand *MMO = *MI.memoperands_begin();
2662 
2663   // This implementation doesn't work for atomics. Give up instead of doing
2664   // something invalid.
2665   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2666       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2667     return UnableToLegalize;
2668 
2669   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2670   Register ValReg = MI.getOperand(0).getReg();
2671   Register AddrReg = MI.getOperand(1).getReg();
2672   LLT ValTy = MRI.getType(ValReg);
2673 
2674   int NumParts = -1;
2675   int NumLeftover = -1;
2676   LLT LeftoverTy;
2677   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2678   if (IsLoad) {
2679     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2680   } else {
2681     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2682                      NarrowLeftoverRegs)) {
2683       NumParts = NarrowRegs.size();
2684       NumLeftover = NarrowLeftoverRegs.size();
2685     }
2686   }
2687 
2688   if (NumParts == -1)
2689     return UnableToLegalize;
2690 
2691   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2692 
2693   unsigned TotalSize = ValTy.getSizeInBits();
2694 
2695   // Split the load/store into PartTy sized pieces starting at Offset. If this
2696   // is a load, return the new registers in ValRegs. For a store, each elements
2697   // of ValRegs should be PartTy. Returns the next offset that needs to be
2698   // handled.
2699   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2700                              unsigned Offset) -> unsigned {
2701     MachineFunction &MF = MIRBuilder.getMF();
2702     unsigned PartSize = PartTy.getSizeInBits();
2703     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2704          Offset += PartSize, ++Idx) {
2705       unsigned ByteSize = PartSize / 8;
2706       unsigned ByteOffset = Offset / 8;
2707       Register NewAddrReg;
2708 
2709       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2710 
2711       MachineMemOperand *NewMMO =
2712         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2713 
2714       if (IsLoad) {
2715         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2716         ValRegs.push_back(Dst);
2717         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2718       } else {
2719         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2720       }
2721     }
2722 
2723     return Offset;
2724   };
2725 
2726   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2727 
2728   // Handle the rest of the register if this isn't an even type breakdown.
2729   if (LeftoverTy.isValid())
2730     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2731 
2732   if (IsLoad) {
2733     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2734                 LeftoverTy, NarrowLeftoverRegs);
2735   }
2736 
2737   MI.eraseFromParent();
2738   return Legalized;
2739 }
2740 
2741 LegalizerHelper::LegalizeResult
2742 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2743                                      LLT NarrowTy) {
2744   using namespace TargetOpcode;
2745 
2746   MIRBuilder.setInstr(MI);
2747   switch (MI.getOpcode()) {
2748   case G_IMPLICIT_DEF:
2749     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2750   case G_AND:
2751   case G_OR:
2752   case G_XOR:
2753   case G_ADD:
2754   case G_SUB:
2755   case G_MUL:
2756   case G_SMULH:
2757   case G_UMULH:
2758   case G_FADD:
2759   case G_FMUL:
2760   case G_FSUB:
2761   case G_FNEG:
2762   case G_FABS:
2763   case G_FCANONICALIZE:
2764   case G_FDIV:
2765   case G_FREM:
2766   case G_FMA:
2767   case G_FPOW:
2768   case G_FEXP:
2769   case G_FEXP2:
2770   case G_FLOG:
2771   case G_FLOG2:
2772   case G_FLOG10:
2773   case G_FNEARBYINT:
2774   case G_FCEIL:
2775   case G_FFLOOR:
2776   case G_FRINT:
2777   case G_INTRINSIC_ROUND:
2778   case G_INTRINSIC_TRUNC:
2779   case G_FCOS:
2780   case G_FSIN:
2781   case G_FSQRT:
2782   case G_BSWAP:
2783   case G_SDIV:
2784   case G_SMIN:
2785   case G_SMAX:
2786   case G_UMIN:
2787   case G_UMAX:
2788   case G_FMINNUM:
2789   case G_FMAXNUM:
2790   case G_FMINNUM_IEEE:
2791   case G_FMAXNUM_IEEE:
2792   case G_FMINIMUM:
2793   case G_FMAXIMUM:
2794     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2795   case G_SHL:
2796   case G_LSHR:
2797   case G_ASHR:
2798   case G_CTLZ:
2799   case G_CTLZ_ZERO_UNDEF:
2800   case G_CTTZ:
2801   case G_CTTZ_ZERO_UNDEF:
2802   case G_CTPOP:
2803   case G_FCOPYSIGN:
2804     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2805   case G_ZEXT:
2806   case G_SEXT:
2807   case G_ANYEXT:
2808   case G_FPEXT:
2809   case G_FPTRUNC:
2810   case G_SITOFP:
2811   case G_UITOFP:
2812   case G_FPTOSI:
2813   case G_FPTOUI:
2814   case G_INTTOPTR:
2815   case G_PTRTOINT:
2816   case G_ADDRSPACE_CAST:
2817     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2818   case G_ICMP:
2819   case G_FCMP:
2820     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2821   case G_SELECT:
2822     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2823   case G_PHI:
2824     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2825   case G_UNMERGE_VALUES:
2826     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
2827   case G_LOAD:
2828   case G_STORE:
2829     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2830   default:
2831     return UnableToLegalize;
2832   }
2833 }
2834 
2835 LegalizerHelper::LegalizeResult
2836 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2837                                              const LLT HalfTy, const LLT AmtTy) {
2838 
2839   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2840   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2841   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2842 
2843   if (Amt.isNullValue()) {
2844     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2845     MI.eraseFromParent();
2846     return Legalized;
2847   }
2848 
2849   LLT NVT = HalfTy;
2850   unsigned NVTBits = HalfTy.getSizeInBits();
2851   unsigned VTBits = 2 * NVTBits;
2852 
2853   SrcOp Lo(Register(0)), Hi(Register(0));
2854   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2855     if (Amt.ugt(VTBits)) {
2856       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2857     } else if (Amt.ugt(NVTBits)) {
2858       Lo = MIRBuilder.buildConstant(NVT, 0);
2859       Hi = MIRBuilder.buildShl(NVT, InL,
2860                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2861     } else if (Amt == NVTBits) {
2862       Lo = MIRBuilder.buildConstant(NVT, 0);
2863       Hi = InL;
2864     } else {
2865       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2866       auto OrLHS =
2867           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2868       auto OrRHS = MIRBuilder.buildLShr(
2869           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2870       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2871     }
2872   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2873     if (Amt.ugt(VTBits)) {
2874       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2875     } else if (Amt.ugt(NVTBits)) {
2876       Lo = MIRBuilder.buildLShr(NVT, InH,
2877                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2878       Hi = MIRBuilder.buildConstant(NVT, 0);
2879     } else if (Amt == NVTBits) {
2880       Lo = InH;
2881       Hi = MIRBuilder.buildConstant(NVT, 0);
2882     } else {
2883       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2884 
2885       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2886       auto OrRHS = MIRBuilder.buildShl(
2887           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2888 
2889       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2890       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2891     }
2892   } else {
2893     if (Amt.ugt(VTBits)) {
2894       Hi = Lo = MIRBuilder.buildAShr(
2895           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2896     } else if (Amt.ugt(NVTBits)) {
2897       Lo = MIRBuilder.buildAShr(NVT, InH,
2898                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2899       Hi = MIRBuilder.buildAShr(NVT, InH,
2900                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2901     } else if (Amt == NVTBits) {
2902       Lo = InH;
2903       Hi = MIRBuilder.buildAShr(NVT, InH,
2904                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2905     } else {
2906       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2907 
2908       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2909       auto OrRHS = MIRBuilder.buildShl(
2910           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2911 
2912       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2913       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2914     }
2915   }
2916 
2917   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2918   MI.eraseFromParent();
2919 
2920   return Legalized;
2921 }
2922 
2923 // TODO: Optimize if constant shift amount.
2924 LegalizerHelper::LegalizeResult
2925 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2926                                    LLT RequestedTy) {
2927   if (TypeIdx == 1) {
2928     Observer.changingInstr(MI);
2929     narrowScalarSrc(MI, RequestedTy, 2);
2930     Observer.changedInstr(MI);
2931     return Legalized;
2932   }
2933 
2934   Register DstReg = MI.getOperand(0).getReg();
2935   LLT DstTy = MRI.getType(DstReg);
2936   if (DstTy.isVector())
2937     return UnableToLegalize;
2938 
2939   Register Amt = MI.getOperand(2).getReg();
2940   LLT ShiftAmtTy = MRI.getType(Amt);
2941   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2942   if (DstEltSize % 2 != 0)
2943     return UnableToLegalize;
2944 
2945   // Ignore the input type. We can only go to exactly half the size of the
2946   // input. If that isn't small enough, the resulting pieces will be further
2947   // legalized.
2948   const unsigned NewBitSize = DstEltSize / 2;
2949   const LLT HalfTy = LLT::scalar(NewBitSize);
2950   const LLT CondTy = LLT::scalar(1);
2951 
2952   if (const MachineInstr *KShiftAmt =
2953           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2954     return narrowScalarShiftByConstant(
2955         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2956   }
2957 
2958   // TODO: Expand with known bits.
2959 
2960   // Handle the fully general expansion by an unknown amount.
2961   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2962 
2963   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2964   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2965   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2966 
2967   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2968   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2969 
2970   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2971   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2972   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2973 
2974   Register ResultRegs[2];
2975   switch (MI.getOpcode()) {
2976   case TargetOpcode::G_SHL: {
2977     // Short: ShAmt < NewBitSize
2978     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2979 
2980     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2981     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2982     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2983 
2984     // Long: ShAmt >= NewBitSize
2985     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2986     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2987 
2988     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2989     auto Hi = MIRBuilder.buildSelect(
2990         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2991 
2992     ResultRegs[0] = Lo.getReg(0);
2993     ResultRegs[1] = Hi.getReg(0);
2994     break;
2995   }
2996   case TargetOpcode::G_LSHR: {
2997     // Short: ShAmt < NewBitSize
2998     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2999 
3000     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3001     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3002     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
3003 
3004     // Long: ShAmt >= NewBitSize
3005     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
3006     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
3007 
3008     auto Lo = MIRBuilder.buildSelect(
3009         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3010     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3011 
3012     ResultRegs[0] = Lo.getReg(0);
3013     ResultRegs[1] = Hi.getReg(0);
3014     break;
3015   }
3016   case TargetOpcode::G_ASHR: {
3017     // Short: ShAmt < NewBitSize
3018     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
3019 
3020     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3021     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
3022     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
3023 
3024     // Long: ShAmt >= NewBitSize
3025 
3026     // Sign of Hi part.
3027     auto HiL = MIRBuilder.buildAShr(
3028         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
3029 
3030     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
3031 
3032     auto Lo = MIRBuilder.buildSelect(
3033         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3034 
3035     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3036 
3037     ResultRegs[0] = Lo.getReg(0);
3038     ResultRegs[1] = Hi.getReg(0);
3039     break;
3040   }
3041   default:
3042     llvm_unreachable("not a shift");
3043   }
3044 
3045   MIRBuilder.buildMerge(DstReg, ResultRegs);
3046   MI.eraseFromParent();
3047   return Legalized;
3048 }
3049 
3050 LegalizerHelper::LegalizeResult
3051 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3052                                        LLT MoreTy) {
3053   assert(TypeIdx == 0 && "Expecting only Idx 0");
3054 
3055   Observer.changingInstr(MI);
3056   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3057     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3058     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3059     moreElementsVectorSrc(MI, MoreTy, I);
3060   }
3061 
3062   MachineBasicBlock &MBB = *MI.getParent();
3063   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3064   moreElementsVectorDst(MI, MoreTy, 0);
3065   Observer.changedInstr(MI);
3066   return Legalized;
3067 }
3068 
3069 LegalizerHelper::LegalizeResult
3070 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3071                                     LLT MoreTy) {
3072   MIRBuilder.setInstr(MI);
3073   unsigned Opc = MI.getOpcode();
3074   switch (Opc) {
3075   case TargetOpcode::G_IMPLICIT_DEF:
3076   case TargetOpcode::G_LOAD: {
3077     if (TypeIdx != 0)
3078       return UnableToLegalize;
3079     Observer.changingInstr(MI);
3080     moreElementsVectorDst(MI, MoreTy, 0);
3081     Observer.changedInstr(MI);
3082     return Legalized;
3083   }
3084   case TargetOpcode::G_STORE:
3085     if (TypeIdx != 0)
3086       return UnableToLegalize;
3087     Observer.changingInstr(MI);
3088     moreElementsVectorSrc(MI, MoreTy, 0);
3089     Observer.changedInstr(MI);
3090     return Legalized;
3091   case TargetOpcode::G_AND:
3092   case TargetOpcode::G_OR:
3093   case TargetOpcode::G_XOR:
3094   case TargetOpcode::G_SMIN:
3095   case TargetOpcode::G_SMAX:
3096   case TargetOpcode::G_UMIN:
3097   case TargetOpcode::G_UMAX: {
3098     Observer.changingInstr(MI);
3099     moreElementsVectorSrc(MI, MoreTy, 1);
3100     moreElementsVectorSrc(MI, MoreTy, 2);
3101     moreElementsVectorDst(MI, MoreTy, 0);
3102     Observer.changedInstr(MI);
3103     return Legalized;
3104   }
3105   case TargetOpcode::G_EXTRACT:
3106     if (TypeIdx != 1)
3107       return UnableToLegalize;
3108     Observer.changingInstr(MI);
3109     moreElementsVectorSrc(MI, MoreTy, 1);
3110     Observer.changedInstr(MI);
3111     return Legalized;
3112   case TargetOpcode::G_INSERT:
3113     if (TypeIdx != 0)
3114       return UnableToLegalize;
3115     Observer.changingInstr(MI);
3116     moreElementsVectorSrc(MI, MoreTy, 1);
3117     moreElementsVectorDst(MI, MoreTy, 0);
3118     Observer.changedInstr(MI);
3119     return Legalized;
3120   case TargetOpcode::G_SELECT:
3121     if (TypeIdx != 0)
3122       return UnableToLegalize;
3123     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3124       return UnableToLegalize;
3125 
3126     Observer.changingInstr(MI);
3127     moreElementsVectorSrc(MI, MoreTy, 2);
3128     moreElementsVectorSrc(MI, MoreTy, 3);
3129     moreElementsVectorDst(MI, MoreTy, 0);
3130     Observer.changedInstr(MI);
3131     return Legalized;
3132   case TargetOpcode::G_PHI:
3133     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3134   default:
3135     return UnableToLegalize;
3136   }
3137 }
3138 
3139 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3140                                         ArrayRef<Register> Src1Regs,
3141                                         ArrayRef<Register> Src2Regs,
3142                                         LLT NarrowTy) {
3143   MachineIRBuilder &B = MIRBuilder;
3144   unsigned SrcParts = Src1Regs.size();
3145   unsigned DstParts = DstRegs.size();
3146 
3147   unsigned DstIdx = 0; // Low bits of the result.
3148   Register FactorSum =
3149       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3150   DstRegs[DstIdx] = FactorSum;
3151 
3152   unsigned CarrySumPrevDstIdx;
3153   SmallVector<Register, 4> Factors;
3154 
3155   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3156     // Collect low parts of muls for DstIdx.
3157     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3158          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3159       MachineInstrBuilder Mul =
3160           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3161       Factors.push_back(Mul.getReg(0));
3162     }
3163     // Collect high parts of muls from previous DstIdx.
3164     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3165          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3166       MachineInstrBuilder Umulh =
3167           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3168       Factors.push_back(Umulh.getReg(0));
3169     }
3170     // Add CarrySum from additons calculated for previous DstIdx.
3171     if (DstIdx != 1) {
3172       Factors.push_back(CarrySumPrevDstIdx);
3173     }
3174 
3175     Register CarrySum;
3176     // Add all factors and accumulate all carries into CarrySum.
3177     if (DstIdx != DstParts - 1) {
3178       MachineInstrBuilder Uaddo =
3179           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3180       FactorSum = Uaddo.getReg(0);
3181       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3182       for (unsigned i = 2; i < Factors.size(); ++i) {
3183         MachineInstrBuilder Uaddo =
3184             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3185         FactorSum = Uaddo.getReg(0);
3186         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3187         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3188       }
3189     } else {
3190       // Since value for the next index is not calculated, neither is CarrySum.
3191       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3192       for (unsigned i = 2; i < Factors.size(); ++i)
3193         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3194     }
3195 
3196     CarrySumPrevDstIdx = CarrySum;
3197     DstRegs[DstIdx] = FactorSum;
3198     Factors.clear();
3199   }
3200 }
3201 
3202 LegalizerHelper::LegalizeResult
3203 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3204   Register DstReg = MI.getOperand(0).getReg();
3205   Register Src1 = MI.getOperand(1).getReg();
3206   Register Src2 = MI.getOperand(2).getReg();
3207 
3208   LLT Ty = MRI.getType(DstReg);
3209   if (Ty.isVector())
3210     return UnableToLegalize;
3211 
3212   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3213   unsigned DstSize = Ty.getSizeInBits();
3214   unsigned NarrowSize = NarrowTy.getSizeInBits();
3215   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3216     return UnableToLegalize;
3217 
3218   unsigned NumDstParts = DstSize / NarrowSize;
3219   unsigned NumSrcParts = SrcSize / NarrowSize;
3220   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3221   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3222 
3223   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3224   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3225   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3226   DstTmpRegs.resize(DstTmpParts);
3227   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3228 
3229   // Take only high half of registers if this is high mul.
3230   ArrayRef<Register> DstRegs(
3231       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3232   MIRBuilder.buildMerge(DstReg, DstRegs);
3233   MI.eraseFromParent();
3234   return Legalized;
3235 }
3236 
3237 LegalizerHelper::LegalizeResult
3238 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3239                                      LLT NarrowTy) {
3240   if (TypeIdx != 1)
3241     return UnableToLegalize;
3242 
3243   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3244 
3245   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3246   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3247   // NarrowSize.
3248   if (SizeOp1 % NarrowSize != 0)
3249     return UnableToLegalize;
3250   int NumParts = SizeOp1 / NarrowSize;
3251 
3252   SmallVector<Register, 2> SrcRegs, DstRegs;
3253   SmallVector<uint64_t, 2> Indexes;
3254   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3255 
3256   Register OpReg = MI.getOperand(0).getReg();
3257   uint64_t OpStart = MI.getOperand(2).getImm();
3258   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3259   for (int i = 0; i < NumParts; ++i) {
3260     unsigned SrcStart = i * NarrowSize;
3261 
3262     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3263       // No part of the extract uses this subregister, ignore it.
3264       continue;
3265     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3266       // The entire subregister is extracted, forward the value.
3267       DstRegs.push_back(SrcRegs[i]);
3268       continue;
3269     }
3270 
3271     // OpSegStart is where this destination segment would start in OpReg if it
3272     // extended infinitely in both directions.
3273     int64_t ExtractOffset;
3274     uint64_t SegSize;
3275     if (OpStart < SrcStart) {
3276       ExtractOffset = 0;
3277       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3278     } else {
3279       ExtractOffset = OpStart - SrcStart;
3280       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3281     }
3282 
3283     Register SegReg = SrcRegs[i];
3284     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3285       // A genuine extract is needed.
3286       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3287       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3288     }
3289 
3290     DstRegs.push_back(SegReg);
3291   }
3292 
3293   Register DstReg = MI.getOperand(0).getReg();
3294   if(MRI.getType(DstReg).isVector())
3295     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3296   else
3297     MIRBuilder.buildMerge(DstReg, DstRegs);
3298   MI.eraseFromParent();
3299   return Legalized;
3300 }
3301 
3302 LegalizerHelper::LegalizeResult
3303 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3304                                     LLT NarrowTy) {
3305   // FIXME: Don't know how to handle secondary types yet.
3306   if (TypeIdx != 0)
3307     return UnableToLegalize;
3308 
3309   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3310   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3311 
3312   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3313   // NarrowSize.
3314   if (SizeOp0 % NarrowSize != 0)
3315     return UnableToLegalize;
3316 
3317   int NumParts = SizeOp0 / NarrowSize;
3318 
3319   SmallVector<Register, 2> SrcRegs, DstRegs;
3320   SmallVector<uint64_t, 2> Indexes;
3321   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3322 
3323   Register OpReg = MI.getOperand(2).getReg();
3324   uint64_t OpStart = MI.getOperand(3).getImm();
3325   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3326   for (int i = 0; i < NumParts; ++i) {
3327     unsigned DstStart = i * NarrowSize;
3328 
3329     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3330       // No part of the insert affects this subregister, forward the original.
3331       DstRegs.push_back(SrcRegs[i]);
3332       continue;
3333     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3334       // The entire subregister is defined by this insert, forward the new
3335       // value.
3336       DstRegs.push_back(OpReg);
3337       continue;
3338     }
3339 
3340     // OpSegStart is where this destination segment would start in OpReg if it
3341     // extended infinitely in both directions.
3342     int64_t ExtractOffset, InsertOffset;
3343     uint64_t SegSize;
3344     if (OpStart < DstStart) {
3345       InsertOffset = 0;
3346       ExtractOffset = DstStart - OpStart;
3347       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3348     } else {
3349       InsertOffset = OpStart - DstStart;
3350       ExtractOffset = 0;
3351       SegSize =
3352         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3353     }
3354 
3355     Register SegReg = OpReg;
3356     if (ExtractOffset != 0 || SegSize != OpSize) {
3357       // A genuine extract is needed.
3358       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3359       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3360     }
3361 
3362     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3363     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3364     DstRegs.push_back(DstReg);
3365   }
3366 
3367   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3368   Register DstReg = MI.getOperand(0).getReg();
3369   if(MRI.getType(DstReg).isVector())
3370     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3371   else
3372     MIRBuilder.buildMerge(DstReg, DstRegs);
3373   MI.eraseFromParent();
3374   return Legalized;
3375 }
3376 
3377 LegalizerHelper::LegalizeResult
3378 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3379                                    LLT NarrowTy) {
3380   Register DstReg = MI.getOperand(0).getReg();
3381   LLT DstTy = MRI.getType(DstReg);
3382 
3383   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3384 
3385   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3386   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3387   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3388   LLT LeftoverTy;
3389   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3390                     Src0Regs, Src0LeftoverRegs))
3391     return UnableToLegalize;
3392 
3393   LLT Unused;
3394   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3395                     Src1Regs, Src1LeftoverRegs))
3396     llvm_unreachable("inconsistent extractParts result");
3397 
3398   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3399     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3400                                         {Src0Regs[I], Src1Regs[I]});
3401     DstRegs.push_back(Inst->getOperand(0).getReg());
3402   }
3403 
3404   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3405     auto Inst = MIRBuilder.buildInstr(
3406       MI.getOpcode(),
3407       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3408     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3409   }
3410 
3411   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3412               LeftoverTy, DstLeftoverRegs);
3413 
3414   MI.eraseFromParent();
3415   return Legalized;
3416 }
3417 
3418 LegalizerHelper::LegalizeResult
3419 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3420                                     LLT NarrowTy) {
3421   if (TypeIdx != 0)
3422     return UnableToLegalize;
3423 
3424   Register CondReg = MI.getOperand(1).getReg();
3425   LLT CondTy = MRI.getType(CondReg);
3426   if (CondTy.isVector()) // TODO: Handle vselect
3427     return UnableToLegalize;
3428 
3429   Register DstReg = MI.getOperand(0).getReg();
3430   LLT DstTy = MRI.getType(DstReg);
3431 
3432   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3433   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3434   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3435   LLT LeftoverTy;
3436   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3437                     Src1Regs, Src1LeftoverRegs))
3438     return UnableToLegalize;
3439 
3440   LLT Unused;
3441   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3442                     Src2Regs, Src2LeftoverRegs))
3443     llvm_unreachable("inconsistent extractParts result");
3444 
3445   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3446     auto Select = MIRBuilder.buildSelect(NarrowTy,
3447                                          CondReg, Src1Regs[I], Src2Regs[I]);
3448     DstRegs.push_back(Select->getOperand(0).getReg());
3449   }
3450 
3451   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3452     auto Select = MIRBuilder.buildSelect(
3453       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3454     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3455   }
3456 
3457   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3458               LeftoverTy, DstLeftoverRegs);
3459 
3460   MI.eraseFromParent();
3461   return Legalized;
3462 }
3463 
3464 LegalizerHelper::LegalizeResult
3465 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3466   unsigned Opc = MI.getOpcode();
3467   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3468   auto isSupported = [this](const LegalityQuery &Q) {
3469     auto QAction = LI.getAction(Q).Action;
3470     return QAction == Legal || QAction == Libcall || QAction == Custom;
3471   };
3472   switch (Opc) {
3473   default:
3474     return UnableToLegalize;
3475   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3476     // This trivially expands to CTLZ.
3477     Observer.changingInstr(MI);
3478     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3479     Observer.changedInstr(MI);
3480     return Legalized;
3481   }
3482   case TargetOpcode::G_CTLZ: {
3483     Register SrcReg = MI.getOperand(1).getReg();
3484     unsigned Len = Ty.getSizeInBits();
3485     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3486       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3487       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3488                                              {Ty}, {SrcReg});
3489       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3490       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3491       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3492                                           SrcReg, MIBZero);
3493       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3494                              MIBCtlzZU);
3495       MI.eraseFromParent();
3496       return Legalized;
3497     }
3498     // for now, we do this:
3499     // NewLen = NextPowerOf2(Len);
3500     // x = x | (x >> 1);
3501     // x = x | (x >> 2);
3502     // ...
3503     // x = x | (x >>16);
3504     // x = x | (x >>32); // for 64-bit input
3505     // Upto NewLen/2
3506     // return Len - popcount(x);
3507     //
3508     // Ref: "Hacker's Delight" by Henry Warren
3509     Register Op = SrcReg;
3510     unsigned NewLen = PowerOf2Ceil(Len);
3511     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3512       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3513       auto MIBOp = MIRBuilder.buildInstr(
3514           TargetOpcode::G_OR, {Ty},
3515           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3516                                      {Op, MIBShiftAmt})});
3517       Op = MIBOp->getOperand(0).getReg();
3518     }
3519     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3520     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3521                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3522     MI.eraseFromParent();
3523     return Legalized;
3524   }
3525   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3526     // This trivially expands to CTTZ.
3527     Observer.changingInstr(MI);
3528     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3529     Observer.changedInstr(MI);
3530     return Legalized;
3531   }
3532   case TargetOpcode::G_CTTZ: {
3533     Register SrcReg = MI.getOperand(1).getReg();
3534     unsigned Len = Ty.getSizeInBits();
3535     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3536       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3537       // zero.
3538       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3539                                              {Ty}, {SrcReg});
3540       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3541       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3542       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3543                                           SrcReg, MIBZero);
3544       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3545                              MIBCttzZU);
3546       MI.eraseFromParent();
3547       return Legalized;
3548     }
3549     // for now, we use: { return popcount(~x & (x - 1)); }
3550     // unless the target has ctlz but not ctpop, in which case we use:
3551     // { return 32 - nlz(~x & (x-1)); }
3552     // Ref: "Hacker's Delight" by Henry Warren
3553     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3554     auto MIBNot =
3555         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3556     auto MIBTmp = MIRBuilder.buildInstr(
3557         TargetOpcode::G_AND, {Ty},
3558         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3559                                        {SrcReg, MIBCstNeg1})});
3560     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3561         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3562       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3563       MIRBuilder.buildInstr(
3564           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3565           {MIBCstLen,
3566            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3567       MI.eraseFromParent();
3568       return Legalized;
3569     }
3570     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3571     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3572     return Legalized;
3573   }
3574   }
3575 }
3576 
3577 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3578 // representation.
3579 LegalizerHelper::LegalizeResult
3580 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3581   Register Dst = MI.getOperand(0).getReg();
3582   Register Src = MI.getOperand(1).getReg();
3583   const LLT S64 = LLT::scalar(64);
3584   const LLT S32 = LLT::scalar(32);
3585   const LLT S1 = LLT::scalar(1);
3586 
3587   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3588 
3589   // unsigned cul2f(ulong u) {
3590   //   uint lz = clz(u);
3591   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3592   //   u = (u << lz) & 0x7fffffffffffffffUL;
3593   //   ulong t = u & 0xffffffffffUL;
3594   //   uint v = (e << 23) | (uint)(u >> 40);
3595   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3596   //   return as_float(v + r);
3597   // }
3598 
3599   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3600   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3601 
3602   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3603 
3604   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3605   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3606 
3607   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3608   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3609 
3610   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3611   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3612 
3613   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3614 
3615   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3616   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3617 
3618   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3619   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3620   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3621 
3622   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3623   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3624   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3625   auto One = MIRBuilder.buildConstant(S32, 1);
3626 
3627   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3628   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3629   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3630   MIRBuilder.buildAdd(Dst, V, R);
3631 
3632   return Legalized;
3633 }
3634 
3635 LegalizerHelper::LegalizeResult
3636 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3637   Register Dst = MI.getOperand(0).getReg();
3638   Register Src = MI.getOperand(1).getReg();
3639   LLT DstTy = MRI.getType(Dst);
3640   LLT SrcTy = MRI.getType(Src);
3641 
3642   if (SrcTy != LLT::scalar(64))
3643     return UnableToLegalize;
3644 
3645   if (DstTy == LLT::scalar(32)) {
3646     // TODO: SelectionDAG has several alternative expansions to port which may
3647     // be more reasonble depending on the available instructions. If a target
3648     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3649     // intermediate type, this is probably worse.
3650     return lowerU64ToF32BitOps(MI);
3651   }
3652 
3653   return UnableToLegalize;
3654 }
3655 
3656 LegalizerHelper::LegalizeResult
3657 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3658   Register Dst = MI.getOperand(0).getReg();
3659   Register Src = MI.getOperand(1).getReg();
3660   LLT DstTy = MRI.getType(Dst);
3661   LLT SrcTy = MRI.getType(Src);
3662 
3663   const LLT S64 = LLT::scalar(64);
3664   const LLT S32 = LLT::scalar(32);
3665   const LLT S1 = LLT::scalar(1);
3666 
3667   if (SrcTy != S64)
3668     return UnableToLegalize;
3669 
3670   if (DstTy == S32) {
3671     // signed cl2f(long l) {
3672     //   long s = l >> 63;
3673     //   float r = cul2f((l + s) ^ s);
3674     //   return s ? -r : r;
3675     // }
3676     Register L = Src;
3677     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3678     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3679 
3680     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3681     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3682     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3683 
3684     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3685     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3686                                             MIRBuilder.buildConstant(S64, 0));
3687     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3688     return Legalized;
3689   }
3690 
3691   return UnableToLegalize;
3692 }
3693 
3694 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
3695   switch (Opc) {
3696   case TargetOpcode::G_SMIN:
3697     return CmpInst::ICMP_SLT;
3698   case TargetOpcode::G_SMAX:
3699     return CmpInst::ICMP_SGT;
3700   case TargetOpcode::G_UMIN:
3701     return CmpInst::ICMP_ULT;
3702   case TargetOpcode::G_UMAX:
3703     return CmpInst::ICMP_UGT;
3704   default:
3705     llvm_unreachable("not in integer min/max");
3706   }
3707 }
3708 
3709 LegalizerHelper::LegalizeResult
3710 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3711   Register Dst = MI.getOperand(0).getReg();
3712   Register Src0 = MI.getOperand(1).getReg();
3713   Register Src1 = MI.getOperand(2).getReg();
3714 
3715   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
3716   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
3717 
3718   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3719   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
3720 
3721   MI.eraseFromParent();
3722   return Legalized;
3723 }
3724 
3725 LegalizerHelper::LegalizeResult
3726 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3727   Register Dst = MI.getOperand(0).getReg();
3728   Register Src0 = MI.getOperand(1).getReg();
3729   Register Src1 = MI.getOperand(2).getReg();
3730 
3731   const LLT Src0Ty = MRI.getType(Src0);
3732   const LLT Src1Ty = MRI.getType(Src1);
3733 
3734   const int Src0Size = Src0Ty.getScalarSizeInBits();
3735   const int Src1Size = Src1Ty.getScalarSizeInBits();
3736 
3737   auto SignBitMask = MIRBuilder.buildConstant(
3738     Src0Ty, APInt::getSignMask(Src0Size));
3739 
3740   auto NotSignBitMask = MIRBuilder.buildConstant(
3741     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
3742 
3743   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
3744   MachineInstr *Or;
3745 
3746   if (Src0Ty == Src1Ty) {
3747     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
3748     Or = MIRBuilder.buildOr(Dst, And0, And1);
3749   } else if (Src0Size > Src1Size) {
3750     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
3751     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
3752     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
3753     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
3754     Or = MIRBuilder.buildOr(Dst, And0, And1);
3755   } else {
3756     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
3757     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
3758     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
3759     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
3760     Or = MIRBuilder.buildOr(Dst, And0, And1);
3761   }
3762 
3763   // Be careful about setting nsz/nnan/ninf on every instruction, since the
3764   // constants are a nan and -0.0, but the final result should preserve
3765   // everything.
3766   if (unsigned Flags = MI.getFlags())
3767     Or->setFlags(Flags);
3768 
3769   MI.eraseFromParent();
3770   return Legalized;
3771 }
3772 
3773 LegalizerHelper::LegalizeResult
3774 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
3775   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
3776     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
3777 
3778   Register Dst = MI.getOperand(0).getReg();
3779   Register Src0 = MI.getOperand(1).getReg();
3780   Register Src1 = MI.getOperand(2).getReg();
3781   LLT Ty = MRI.getType(Dst);
3782 
3783   if (!MI.getFlag(MachineInstr::FmNoNans)) {
3784     // Insert canonicalizes if it's possible we need to quiet to get correct
3785     // sNaN behavior.
3786 
3787     // Note this must be done here, and not as an optimization combine in the
3788     // absence of a dedicate quiet-snan instruction as we're using an
3789     // omni-purpose G_FCANONICALIZE.
3790     if (!isKnownNeverSNaN(Src0, MRI))
3791       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
3792 
3793     if (!isKnownNeverSNaN(Src1, MRI))
3794       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
3795   }
3796 
3797   // If there are no nans, it's safe to simply replace this with the non-IEEE
3798   // version.
3799   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
3800   MI.eraseFromParent();
3801   return Legalized;
3802 }
3803 
3804 LegalizerHelper::LegalizeResult
3805 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
3806   const unsigned NumDst = MI.getNumOperands() - 1;
3807   const Register SrcReg = MI.getOperand(NumDst).getReg();
3808   LLT SrcTy = MRI.getType(SrcReg);
3809 
3810   Register Dst0Reg = MI.getOperand(0).getReg();
3811   LLT DstTy = MRI.getType(Dst0Reg);
3812 
3813 
3814   // Expand scalarizing unmerge as bitcast to integer and shift.
3815   if (!DstTy.isVector() && SrcTy.isVector() &&
3816       SrcTy.getElementType() == DstTy) {
3817     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
3818     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
3819 
3820     MIRBuilder.buildTrunc(Dst0Reg, Cast);
3821 
3822     const unsigned DstSize = DstTy.getSizeInBits();
3823     unsigned Offset = DstSize;
3824     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
3825       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
3826       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
3827       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
3828     }
3829 
3830     MI.eraseFromParent();
3831     return Legalized;
3832   }
3833 
3834   return UnableToLegalize;
3835 }
3836 
3837 LegalizerHelper::LegalizeResult
3838 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
3839   Register DstReg = MI.getOperand(0).getReg();
3840   Register Src0Reg = MI.getOperand(1).getReg();
3841   Register Src1Reg = MI.getOperand(2).getReg();
3842   LLT Src0Ty = MRI.getType(Src0Reg);
3843   LLT DstTy = MRI.getType(DstReg);
3844   LLT IdxTy = LLT::scalar(32);
3845 
3846   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
3847 
3848   SmallVector<int, 32> Mask;
3849   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
3850 
3851   if (DstTy.isScalar()) {
3852     if (Src0Ty.isVector())
3853       return UnableToLegalize;
3854 
3855     // This is just a SELECT.
3856     assert(Mask.size() == 1 && "Expected a single mask element");
3857     Register Val;
3858     if (Mask[0] < 0 || Mask[0] > 1)
3859       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
3860     else
3861       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
3862     MIRBuilder.buildCopy(DstReg, Val);
3863     MI.eraseFromParent();
3864     return Legalized;
3865   }
3866 
3867   Register Undef;
3868   SmallVector<Register, 32> BuildVec;
3869   LLT EltTy = DstTy.getElementType();
3870 
3871   for (int Idx : Mask) {
3872     if (Idx < 0) {
3873       if (!Undef.isValid())
3874         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
3875       BuildVec.push_back(Undef);
3876       continue;
3877     }
3878 
3879     if (Src0Ty.isScalar()) {
3880       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
3881     } else {
3882       int NumElts = Src0Ty.getNumElements();
3883       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
3884       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
3885       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
3886       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
3887       BuildVec.push_back(Extract.getReg(0));
3888     }
3889   }
3890 
3891   MIRBuilder.buildBuildVector(DstReg, BuildVec);
3892   MI.eraseFromParent();
3893   return Legalized;
3894 }
3895