1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 #define DEBUG_TYPE "legalizer" 30 31 using namespace llvm; 32 using namespace LegalizeActions; 33 using namespace MIPatternMatch; 34 35 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 36 /// 37 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 38 /// with any leftover piece as type \p LeftoverTy 39 /// 40 /// Returns -1 in the first element of the pair if the breakdown is not 41 /// satisfiable. 42 static std::pair<int, int> 43 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 44 assert(!LeftoverTy.isValid() && "this is an out argument"); 45 46 unsigned Size = OrigTy.getSizeInBits(); 47 unsigned NarrowSize = NarrowTy.getSizeInBits(); 48 unsigned NumParts = Size / NarrowSize; 49 unsigned LeftoverSize = Size - NumParts * NarrowSize; 50 assert(Size > NarrowSize); 51 52 if (LeftoverSize == 0) 53 return {NumParts, 0}; 54 55 if (NarrowTy.isVector()) { 56 unsigned EltSize = OrigTy.getScalarSizeInBits(); 57 if (LeftoverSize % EltSize != 0) 58 return {-1, -1}; 59 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 60 } else { 61 LeftoverTy = LLT::scalar(LeftoverSize); 62 } 63 64 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 65 return std::make_pair(NumParts, NumLeftover); 66 } 67 68 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 69 70 if (!Ty.isScalar()) 71 return nullptr; 72 73 switch (Ty.getSizeInBits()) { 74 case 16: 75 return Type::getHalfTy(Ctx); 76 case 32: 77 return Type::getFloatTy(Ctx); 78 case 64: 79 return Type::getDoubleTy(Ctx); 80 case 80: 81 return Type::getX86_FP80Ty(Ctx); 82 case 128: 83 return Type::getFP128Ty(Ctx); 84 default: 85 return nullptr; 86 } 87 } 88 89 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 90 GISelChangeObserver &Observer, 91 MachineIRBuilder &Builder) 92 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 93 LI(*MF.getSubtarget().getLegalizerInfo()), 94 TLI(*MF.getSubtarget().getTargetLowering()) { } 95 96 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 97 GISelChangeObserver &Observer, 98 MachineIRBuilder &B) 99 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 100 TLI(*MF.getSubtarget().getTargetLowering()) { } 101 102 LegalizerHelper::LegalizeResult 103 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { 104 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 105 106 MIRBuilder.setInstrAndDebugLoc(MI); 107 108 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 109 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 110 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 111 auto Step = LI.getAction(MI, MRI); 112 switch (Step.Action) { 113 case Legal: 114 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 115 return AlreadyLegal; 116 case Libcall: 117 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 118 return libcall(MI); 119 case NarrowScalar: 120 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 121 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 122 case WidenScalar: 123 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 124 return widenScalar(MI, Step.TypeIdx, Step.NewType); 125 case Bitcast: 126 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 127 return bitcast(MI, Step.TypeIdx, Step.NewType); 128 case Lower: 129 LLVM_DEBUG(dbgs() << ".. Lower\n"); 130 return lower(MI, Step.TypeIdx, Step.NewType); 131 case FewerElements: 132 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 133 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 134 case MoreElements: 135 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 136 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 137 case Custom: 138 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 139 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 140 default: 141 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 142 return UnableToLegalize; 143 } 144 } 145 146 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 147 SmallVectorImpl<Register> &VRegs) { 148 for (int i = 0; i < NumParts; ++i) 149 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 150 MIRBuilder.buildUnmerge(VRegs, Reg); 151 } 152 153 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 154 LLT MainTy, LLT &LeftoverTy, 155 SmallVectorImpl<Register> &VRegs, 156 SmallVectorImpl<Register> &LeftoverRegs) { 157 assert(!LeftoverTy.isValid() && "this is an out argument"); 158 159 unsigned RegSize = RegTy.getSizeInBits(); 160 unsigned MainSize = MainTy.getSizeInBits(); 161 unsigned NumParts = RegSize / MainSize; 162 unsigned LeftoverSize = RegSize - NumParts * MainSize; 163 164 // Use an unmerge when possible. 165 if (LeftoverSize == 0) { 166 for (unsigned I = 0; I < NumParts; ++I) 167 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 168 MIRBuilder.buildUnmerge(VRegs, Reg); 169 return true; 170 } 171 172 if (MainTy.isVector()) { 173 unsigned EltSize = MainTy.getScalarSizeInBits(); 174 if (LeftoverSize % EltSize != 0) 175 return false; 176 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 177 } else { 178 LeftoverTy = LLT::scalar(LeftoverSize); 179 } 180 181 // For irregular sizes, extract the individual parts. 182 for (unsigned I = 0; I != NumParts; ++I) { 183 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 184 VRegs.push_back(NewReg); 185 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 186 } 187 188 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 189 Offset += LeftoverSize) { 190 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 191 LeftoverRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, Offset); 193 } 194 195 return true; 196 } 197 198 void LegalizerHelper::insertParts(Register DstReg, 199 LLT ResultTy, LLT PartTy, 200 ArrayRef<Register> PartRegs, 201 LLT LeftoverTy, 202 ArrayRef<Register> LeftoverRegs) { 203 if (!LeftoverTy.isValid()) { 204 assert(LeftoverRegs.empty()); 205 206 if (!ResultTy.isVector()) { 207 MIRBuilder.buildMerge(DstReg, PartRegs); 208 return; 209 } 210 211 if (PartTy.isVector()) 212 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 213 else 214 MIRBuilder.buildBuildVector(DstReg, PartRegs); 215 return; 216 } 217 218 unsigned PartSize = PartTy.getSizeInBits(); 219 unsigned LeftoverPartSize = LeftoverTy.getSizeInBits(); 220 221 Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy); 222 MIRBuilder.buildUndef(CurResultReg); 223 224 unsigned Offset = 0; 225 for (Register PartReg : PartRegs) { 226 Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy); 227 MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset); 228 CurResultReg = NewResultReg; 229 Offset += PartSize; 230 } 231 232 for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) { 233 // Use the original output register for the final insert to avoid a copy. 234 Register NewResultReg = (I + 1 == E) ? 235 DstReg : MRI.createGenericVirtualRegister(ResultTy); 236 237 MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset); 238 CurResultReg = NewResultReg; 239 Offset += LeftoverPartSize; 240 } 241 } 242 243 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 244 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 245 const MachineInstr &MI) { 246 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 247 248 const int StartIdx = Regs.size(); 249 const int NumResults = MI.getNumOperands() - 1; 250 Regs.resize(Regs.size() + NumResults); 251 for (int I = 0; I != NumResults; ++I) 252 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 253 } 254 255 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 256 LLT GCDTy, Register SrcReg) { 257 LLT SrcTy = MRI.getType(SrcReg); 258 if (SrcTy == GCDTy) { 259 // If the source already evenly divides the result type, we don't need to do 260 // anything. 261 Parts.push_back(SrcReg); 262 } else { 263 // Need to split into common type sized pieces. 264 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 265 getUnmergeResults(Parts, *Unmerge); 266 } 267 } 268 269 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 270 LLT NarrowTy, Register SrcReg) { 271 LLT SrcTy = MRI.getType(SrcReg); 272 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 273 extractGCDType(Parts, GCDTy, SrcReg); 274 return GCDTy; 275 } 276 277 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 278 SmallVectorImpl<Register> &VRegs, 279 unsigned PadStrategy) { 280 LLT LCMTy = getLCMType(DstTy, NarrowTy); 281 282 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 283 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 284 int NumOrigSrc = VRegs.size(); 285 286 Register PadReg; 287 288 // Get a value we can use to pad the source value if the sources won't evenly 289 // cover the result type. 290 if (NumOrigSrc < NumParts * NumSubParts) { 291 if (PadStrategy == TargetOpcode::G_ZEXT) 292 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 293 else if (PadStrategy == TargetOpcode::G_ANYEXT) 294 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 295 else { 296 assert(PadStrategy == TargetOpcode::G_SEXT); 297 298 // Shift the sign bit of the low register through the high register. 299 auto ShiftAmt = 300 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 301 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 302 } 303 } 304 305 // Registers for the final merge to be produced. 306 SmallVector<Register, 4> Remerge(NumParts); 307 308 // Registers needed for intermediate merges, which will be merged into a 309 // source for Remerge. 310 SmallVector<Register, 4> SubMerge(NumSubParts); 311 312 // Once we've fully read off the end of the original source bits, we can reuse 313 // the same high bits for remaining padding elements. 314 Register AllPadReg; 315 316 // Build merges to the LCM type to cover the original result type. 317 for (int I = 0; I != NumParts; ++I) { 318 bool AllMergePartsArePadding = true; 319 320 // Build the requested merges to the requested type. 321 for (int J = 0; J != NumSubParts; ++J) { 322 int Idx = I * NumSubParts + J; 323 if (Idx >= NumOrigSrc) { 324 SubMerge[J] = PadReg; 325 continue; 326 } 327 328 SubMerge[J] = VRegs[Idx]; 329 330 // There are meaningful bits here we can't reuse later. 331 AllMergePartsArePadding = false; 332 } 333 334 // If we've filled up a complete piece with padding bits, we can directly 335 // emit the natural sized constant if applicable, rather than a merge of 336 // smaller constants. 337 if (AllMergePartsArePadding && !AllPadReg) { 338 if (PadStrategy == TargetOpcode::G_ANYEXT) 339 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 340 else if (PadStrategy == TargetOpcode::G_ZEXT) 341 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 342 343 // If this is a sign extension, we can't materialize a trivial constant 344 // with the right type and have to produce a merge. 345 } 346 347 if (AllPadReg) { 348 // Avoid creating additional instructions if we're just adding additional 349 // copies of padding bits. 350 Remerge[I] = AllPadReg; 351 continue; 352 } 353 354 if (NumSubParts == 1) 355 Remerge[I] = SubMerge[0]; 356 else 357 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 358 359 // In the sign extend padding case, re-use the first all-signbit merge. 360 if (AllMergePartsArePadding && !AllPadReg) 361 AllPadReg = Remerge[I]; 362 } 363 364 VRegs = std::move(Remerge); 365 return LCMTy; 366 } 367 368 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 369 ArrayRef<Register> RemergeRegs) { 370 LLT DstTy = MRI.getType(DstReg); 371 372 // Create the merge to the widened source, and extract the relevant bits into 373 // the result. 374 375 if (DstTy == LCMTy) { 376 MIRBuilder.buildMerge(DstReg, RemergeRegs); 377 return; 378 } 379 380 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 381 if (DstTy.isScalar() && LCMTy.isScalar()) { 382 MIRBuilder.buildTrunc(DstReg, Remerge); 383 return; 384 } 385 386 if (LCMTy.isVector()) { 387 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 388 SmallVector<Register, 8> UnmergeDefs(NumDefs); 389 UnmergeDefs[0] = DstReg; 390 for (unsigned I = 1; I != NumDefs; ++I) 391 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 392 393 MIRBuilder.buildUnmerge(UnmergeDefs, 394 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 395 return; 396 } 397 398 llvm_unreachable("unhandled case"); 399 } 400 401 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 402 #define RTLIBCASE_INT(LibcallPrefix) \ 403 do { \ 404 switch (Size) { \ 405 case 32: \ 406 return RTLIB::LibcallPrefix##32; \ 407 case 64: \ 408 return RTLIB::LibcallPrefix##64; \ 409 case 128: \ 410 return RTLIB::LibcallPrefix##128; \ 411 default: \ 412 llvm_unreachable("unexpected size"); \ 413 } \ 414 } while (0) 415 416 #define RTLIBCASE(LibcallPrefix) \ 417 do { \ 418 switch (Size) { \ 419 case 32: \ 420 return RTLIB::LibcallPrefix##32; \ 421 case 64: \ 422 return RTLIB::LibcallPrefix##64; \ 423 case 80: \ 424 return RTLIB::LibcallPrefix##80; \ 425 case 128: \ 426 return RTLIB::LibcallPrefix##128; \ 427 default: \ 428 llvm_unreachable("unexpected size"); \ 429 } \ 430 } while (0) 431 432 switch (Opcode) { 433 case TargetOpcode::G_SDIV: 434 RTLIBCASE_INT(SDIV_I); 435 case TargetOpcode::G_UDIV: 436 RTLIBCASE_INT(UDIV_I); 437 case TargetOpcode::G_SREM: 438 RTLIBCASE_INT(SREM_I); 439 case TargetOpcode::G_UREM: 440 RTLIBCASE_INT(UREM_I); 441 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 442 RTLIBCASE_INT(CTLZ_I); 443 case TargetOpcode::G_FADD: 444 RTLIBCASE(ADD_F); 445 case TargetOpcode::G_FSUB: 446 RTLIBCASE(SUB_F); 447 case TargetOpcode::G_FMUL: 448 RTLIBCASE(MUL_F); 449 case TargetOpcode::G_FDIV: 450 RTLIBCASE(DIV_F); 451 case TargetOpcode::G_FEXP: 452 RTLIBCASE(EXP_F); 453 case TargetOpcode::G_FEXP2: 454 RTLIBCASE(EXP2_F); 455 case TargetOpcode::G_FREM: 456 RTLIBCASE(REM_F); 457 case TargetOpcode::G_FPOW: 458 RTLIBCASE(POW_F); 459 case TargetOpcode::G_FMA: 460 RTLIBCASE(FMA_F); 461 case TargetOpcode::G_FSIN: 462 RTLIBCASE(SIN_F); 463 case TargetOpcode::G_FCOS: 464 RTLIBCASE(COS_F); 465 case TargetOpcode::G_FLOG10: 466 RTLIBCASE(LOG10_F); 467 case TargetOpcode::G_FLOG: 468 RTLIBCASE(LOG_F); 469 case TargetOpcode::G_FLOG2: 470 RTLIBCASE(LOG2_F); 471 case TargetOpcode::G_FCEIL: 472 RTLIBCASE(CEIL_F); 473 case TargetOpcode::G_FFLOOR: 474 RTLIBCASE(FLOOR_F); 475 case TargetOpcode::G_FMINNUM: 476 RTLIBCASE(FMIN_F); 477 case TargetOpcode::G_FMAXNUM: 478 RTLIBCASE(FMAX_F); 479 case TargetOpcode::G_FSQRT: 480 RTLIBCASE(SQRT_F); 481 case TargetOpcode::G_FRINT: 482 RTLIBCASE(RINT_F); 483 case TargetOpcode::G_FNEARBYINT: 484 RTLIBCASE(NEARBYINT_F); 485 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 486 RTLIBCASE(ROUNDEVEN_F); 487 } 488 llvm_unreachable("Unknown libcall function"); 489 } 490 491 /// True if an instruction is in tail position in its caller. Intended for 492 /// legalizing libcalls as tail calls when possible. 493 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 494 MachineInstr &MI) { 495 MachineBasicBlock &MBB = *MI.getParent(); 496 const Function &F = MBB.getParent()->getFunction(); 497 498 // Conservatively require the attributes of the call to match those of 499 // the return. Ignore NoAlias and NonNull because they don't affect the 500 // call sequence. 501 AttributeList CallerAttrs = F.getAttributes(); 502 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 503 .removeAttribute(Attribute::NoAlias) 504 .removeAttribute(Attribute::NonNull) 505 .hasAttributes()) 506 return false; 507 508 // It's not safe to eliminate the sign / zero extension of the return value. 509 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 510 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 511 return false; 512 513 // Only tail call if the following instruction is a standard return. 514 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 515 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 516 return false; 517 518 return true; 519 } 520 521 LegalizerHelper::LegalizeResult 522 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 523 const CallLowering::ArgInfo &Result, 524 ArrayRef<CallLowering::ArgInfo> Args, 525 const CallingConv::ID CC) { 526 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 527 528 CallLowering::CallLoweringInfo Info; 529 Info.CallConv = CC; 530 Info.Callee = MachineOperand::CreateES(Name); 531 Info.OrigRet = Result; 532 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 533 if (!CLI.lowerCall(MIRBuilder, Info)) 534 return LegalizerHelper::UnableToLegalize; 535 536 return LegalizerHelper::Legalized; 537 } 538 539 LegalizerHelper::LegalizeResult 540 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 541 const CallLowering::ArgInfo &Result, 542 ArrayRef<CallLowering::ArgInfo> Args) { 543 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 544 const char *Name = TLI.getLibcallName(Libcall); 545 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 546 return createLibcall(MIRBuilder, Name, Result, Args, CC); 547 } 548 549 // Useful for libcalls where all operands have the same type. 550 static LegalizerHelper::LegalizeResult 551 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 552 Type *OpType) { 553 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 554 555 SmallVector<CallLowering::ArgInfo, 3> Args; 556 for (unsigned i = 1; i < MI.getNumOperands(); i++) 557 Args.push_back({MI.getOperand(i).getReg(), OpType}); 558 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, 559 Args); 560 } 561 562 LegalizerHelper::LegalizeResult 563 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 564 MachineInstr &MI) { 565 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 566 567 SmallVector<CallLowering::ArgInfo, 3> Args; 568 // Add all the args, except for the last which is an imm denoting 'tail'. 569 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 570 Register Reg = MI.getOperand(i).getReg(); 571 572 // Need derive an IR type for call lowering. 573 LLT OpLLT = MRI.getType(Reg); 574 Type *OpTy = nullptr; 575 if (OpLLT.isPointer()) 576 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 577 else 578 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 579 Args.push_back({Reg, OpTy}); 580 } 581 582 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 583 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 584 RTLIB::Libcall RTLibcall; 585 switch (MI.getOpcode()) { 586 case TargetOpcode::G_MEMCPY: 587 RTLibcall = RTLIB::MEMCPY; 588 break; 589 case TargetOpcode::G_MEMMOVE: 590 RTLibcall = RTLIB::MEMMOVE; 591 break; 592 case TargetOpcode::G_MEMSET: 593 RTLibcall = RTLIB::MEMSET; 594 break; 595 default: 596 return LegalizerHelper::UnableToLegalize; 597 } 598 const char *Name = TLI.getLibcallName(RTLibcall); 599 600 CallLowering::CallLoweringInfo Info; 601 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 602 Info.Callee = MachineOperand::CreateES(Name); 603 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); 604 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 605 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 606 607 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 608 if (!CLI.lowerCall(MIRBuilder, Info)) 609 return LegalizerHelper::UnableToLegalize; 610 611 if (Info.LoweredTailCall) { 612 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 613 // We must have a return following the call (or debug insts) to get past 614 // isLibCallInTailPosition. 615 do { 616 MachineInstr *Next = MI.getNextNode(); 617 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 618 "Expected instr following MI to be return or debug inst?"); 619 // We lowered a tail call, so the call is now the return from the block. 620 // Delete the old return. 621 Next->eraseFromParent(); 622 } while (MI.getNextNode()); 623 } 624 625 return LegalizerHelper::Legalized; 626 } 627 628 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 629 Type *FromType) { 630 auto ToMVT = MVT::getVT(ToType); 631 auto FromMVT = MVT::getVT(FromType); 632 633 switch (Opcode) { 634 case TargetOpcode::G_FPEXT: 635 return RTLIB::getFPEXT(FromMVT, ToMVT); 636 case TargetOpcode::G_FPTRUNC: 637 return RTLIB::getFPROUND(FromMVT, ToMVT); 638 case TargetOpcode::G_FPTOSI: 639 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 640 case TargetOpcode::G_FPTOUI: 641 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 642 case TargetOpcode::G_SITOFP: 643 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 644 case TargetOpcode::G_UITOFP: 645 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 646 } 647 llvm_unreachable("Unsupported libcall function"); 648 } 649 650 static LegalizerHelper::LegalizeResult 651 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 652 Type *FromType) { 653 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 654 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, 655 {{MI.getOperand(1).getReg(), FromType}}); 656 } 657 658 LegalizerHelper::LegalizeResult 659 LegalizerHelper::libcall(MachineInstr &MI) { 660 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 661 unsigned Size = LLTy.getSizeInBits(); 662 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 663 664 switch (MI.getOpcode()) { 665 default: 666 return UnableToLegalize; 667 case TargetOpcode::G_SDIV: 668 case TargetOpcode::G_UDIV: 669 case TargetOpcode::G_SREM: 670 case TargetOpcode::G_UREM: 671 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 672 Type *HLTy = IntegerType::get(Ctx, Size); 673 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 674 if (Status != Legalized) 675 return Status; 676 break; 677 } 678 case TargetOpcode::G_FADD: 679 case TargetOpcode::G_FSUB: 680 case TargetOpcode::G_FMUL: 681 case TargetOpcode::G_FDIV: 682 case TargetOpcode::G_FMA: 683 case TargetOpcode::G_FPOW: 684 case TargetOpcode::G_FREM: 685 case TargetOpcode::G_FCOS: 686 case TargetOpcode::G_FSIN: 687 case TargetOpcode::G_FLOG10: 688 case TargetOpcode::G_FLOG: 689 case TargetOpcode::G_FLOG2: 690 case TargetOpcode::G_FEXP: 691 case TargetOpcode::G_FEXP2: 692 case TargetOpcode::G_FCEIL: 693 case TargetOpcode::G_FFLOOR: 694 case TargetOpcode::G_FMINNUM: 695 case TargetOpcode::G_FMAXNUM: 696 case TargetOpcode::G_FSQRT: 697 case TargetOpcode::G_FRINT: 698 case TargetOpcode::G_FNEARBYINT: 699 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 700 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 701 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 702 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 703 return UnableToLegalize; 704 } 705 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 706 if (Status != Legalized) 707 return Status; 708 break; 709 } 710 case TargetOpcode::G_FPEXT: 711 case TargetOpcode::G_FPTRUNC: { 712 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 713 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 714 if (!FromTy || !ToTy) 715 return UnableToLegalize; 716 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPTOSI: 722 case TargetOpcode::G_FPTOUI: { 723 // FIXME: Support other types 724 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 725 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 726 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 727 return UnableToLegalize; 728 LegalizeResult Status = conversionLibcall( 729 MI, MIRBuilder, 730 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 731 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 732 if (Status != Legalized) 733 return Status; 734 break; 735 } 736 case TargetOpcode::G_SITOFP: 737 case TargetOpcode::G_UITOFP: { 738 // FIXME: Support other types 739 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 740 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 741 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 742 return UnableToLegalize; 743 LegalizeResult Status = conversionLibcall( 744 MI, MIRBuilder, 745 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 746 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 747 if (Status != Legalized) 748 return Status; 749 break; 750 } 751 case TargetOpcode::G_MEMCPY: 752 case TargetOpcode::G_MEMMOVE: 753 case TargetOpcode::G_MEMSET: { 754 LegalizeResult Result = createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI); 755 MI.eraseFromParent(); 756 return Result; 757 } 758 } 759 760 MI.eraseFromParent(); 761 return Legalized; 762 } 763 764 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 765 unsigned TypeIdx, 766 LLT NarrowTy) { 767 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 768 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 769 770 switch (MI.getOpcode()) { 771 default: 772 return UnableToLegalize; 773 case TargetOpcode::G_IMPLICIT_DEF: { 774 Register DstReg = MI.getOperand(0).getReg(); 775 LLT DstTy = MRI.getType(DstReg); 776 777 // If SizeOp0 is not an exact multiple of NarrowSize, emit 778 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 779 // FIXME: Although this would also be legal for the general case, it causes 780 // a lot of regressions in the emitted code (superfluous COPYs, artifact 781 // combines not being hit). This seems to be a problem related to the 782 // artifact combiner. 783 if (SizeOp0 % NarrowSize != 0) { 784 LLT ImplicitTy = NarrowTy; 785 if (DstTy.isVector()) 786 ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy); 787 788 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 789 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 790 791 MI.eraseFromParent(); 792 return Legalized; 793 } 794 795 int NumParts = SizeOp0 / NarrowSize; 796 797 SmallVector<Register, 2> DstRegs; 798 for (int i = 0; i < NumParts; ++i) 799 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 800 801 if (DstTy.isVector()) 802 MIRBuilder.buildBuildVector(DstReg, DstRegs); 803 else 804 MIRBuilder.buildMerge(DstReg, DstRegs); 805 MI.eraseFromParent(); 806 return Legalized; 807 } 808 case TargetOpcode::G_CONSTANT: { 809 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 810 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 811 unsigned TotalSize = Ty.getSizeInBits(); 812 unsigned NarrowSize = NarrowTy.getSizeInBits(); 813 int NumParts = TotalSize / NarrowSize; 814 815 SmallVector<Register, 4> PartRegs; 816 for (int I = 0; I != NumParts; ++I) { 817 unsigned Offset = I * NarrowSize; 818 auto K = MIRBuilder.buildConstant(NarrowTy, 819 Val.lshr(Offset).trunc(NarrowSize)); 820 PartRegs.push_back(K.getReg(0)); 821 } 822 823 LLT LeftoverTy; 824 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 825 SmallVector<Register, 1> LeftoverRegs; 826 if (LeftoverBits != 0) { 827 LeftoverTy = LLT::scalar(LeftoverBits); 828 auto K = MIRBuilder.buildConstant( 829 LeftoverTy, 830 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 831 LeftoverRegs.push_back(K.getReg(0)); 832 } 833 834 insertParts(MI.getOperand(0).getReg(), 835 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 836 837 MI.eraseFromParent(); 838 return Legalized; 839 } 840 case TargetOpcode::G_SEXT: 841 case TargetOpcode::G_ZEXT: 842 case TargetOpcode::G_ANYEXT: 843 return narrowScalarExt(MI, TypeIdx, NarrowTy); 844 case TargetOpcode::G_TRUNC: { 845 if (TypeIdx != 1) 846 return UnableToLegalize; 847 848 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 849 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 850 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 851 return UnableToLegalize; 852 } 853 854 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 855 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 856 MI.eraseFromParent(); 857 return Legalized; 858 } 859 860 case TargetOpcode::G_FREEZE: 861 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 862 case TargetOpcode::G_ADD: 863 case TargetOpcode::G_SUB: 864 case TargetOpcode::G_SADDO: 865 case TargetOpcode::G_SSUBO: 866 case TargetOpcode::G_SADDE: 867 case TargetOpcode::G_SSUBE: 868 case TargetOpcode::G_UADDO: 869 case TargetOpcode::G_USUBO: 870 case TargetOpcode::G_UADDE: 871 case TargetOpcode::G_USUBE: 872 return narrowScalarAddSub(MI, TypeIdx, NarrowTy); 873 case TargetOpcode::G_MUL: 874 case TargetOpcode::G_UMULH: 875 return narrowScalarMul(MI, NarrowTy); 876 case TargetOpcode::G_EXTRACT: 877 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 878 case TargetOpcode::G_INSERT: 879 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 880 case TargetOpcode::G_LOAD: { 881 auto &MMO = **MI.memoperands_begin(); 882 Register DstReg = MI.getOperand(0).getReg(); 883 LLT DstTy = MRI.getType(DstReg); 884 if (DstTy.isVector()) 885 return UnableToLegalize; 886 887 if (8 * MMO.getSize() != DstTy.getSizeInBits()) { 888 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 889 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); 890 MIRBuilder.buildAnyExt(DstReg, TmpReg); 891 MI.eraseFromParent(); 892 return Legalized; 893 } 894 895 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 896 } 897 case TargetOpcode::G_ZEXTLOAD: 898 case TargetOpcode::G_SEXTLOAD: { 899 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 900 Register DstReg = MI.getOperand(0).getReg(); 901 Register PtrReg = MI.getOperand(1).getReg(); 902 903 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 904 auto &MMO = **MI.memoperands_begin(); 905 unsigned MemSize = MMO.getSizeInBits(); 906 907 if (MemSize == NarrowSize) { 908 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 909 } else if (MemSize < NarrowSize) { 910 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); 911 } else if (MemSize > NarrowSize) { 912 // FIXME: Need to split the load. 913 return UnableToLegalize; 914 } 915 916 if (ZExt) 917 MIRBuilder.buildZExt(DstReg, TmpReg); 918 else 919 MIRBuilder.buildSExt(DstReg, TmpReg); 920 921 MI.eraseFromParent(); 922 return Legalized; 923 } 924 case TargetOpcode::G_STORE: { 925 const auto &MMO = **MI.memoperands_begin(); 926 927 Register SrcReg = MI.getOperand(0).getReg(); 928 LLT SrcTy = MRI.getType(SrcReg); 929 if (SrcTy.isVector()) 930 return UnableToLegalize; 931 932 int NumParts = SizeOp0 / NarrowSize; 933 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 934 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 935 if (SrcTy.isVector() && LeftoverBits != 0) 936 return UnableToLegalize; 937 938 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) { 939 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 940 auto &MMO = **MI.memoperands_begin(); 941 MIRBuilder.buildTrunc(TmpReg, SrcReg); 942 MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO); 943 MI.eraseFromParent(); 944 return Legalized; 945 } 946 947 return reduceLoadStoreWidth(MI, 0, NarrowTy); 948 } 949 case TargetOpcode::G_SELECT: 950 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 951 case TargetOpcode::G_AND: 952 case TargetOpcode::G_OR: 953 case TargetOpcode::G_XOR: { 954 // Legalize bitwise operation: 955 // A = BinOp<Ty> B, C 956 // into: 957 // B1, ..., BN = G_UNMERGE_VALUES B 958 // C1, ..., CN = G_UNMERGE_VALUES C 959 // A1 = BinOp<Ty/N> B1, C2 960 // ... 961 // AN = BinOp<Ty/N> BN, CN 962 // A = G_MERGE_VALUES A1, ..., AN 963 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 964 } 965 case TargetOpcode::G_SHL: 966 case TargetOpcode::G_LSHR: 967 case TargetOpcode::G_ASHR: 968 return narrowScalarShift(MI, TypeIdx, NarrowTy); 969 case TargetOpcode::G_CTLZ: 970 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 971 case TargetOpcode::G_CTTZ: 972 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 973 case TargetOpcode::G_CTPOP: 974 if (TypeIdx == 1) 975 switch (MI.getOpcode()) { 976 case TargetOpcode::G_CTLZ: 977 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 978 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 979 case TargetOpcode::G_CTTZ: 980 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 981 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 982 case TargetOpcode::G_CTPOP: 983 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 984 default: 985 return UnableToLegalize; 986 } 987 988 Observer.changingInstr(MI); 989 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 990 Observer.changedInstr(MI); 991 return Legalized; 992 case TargetOpcode::G_INTTOPTR: 993 if (TypeIdx != 1) 994 return UnableToLegalize; 995 996 Observer.changingInstr(MI); 997 narrowScalarSrc(MI, NarrowTy, 1); 998 Observer.changedInstr(MI); 999 return Legalized; 1000 case TargetOpcode::G_PTRTOINT: 1001 if (TypeIdx != 0) 1002 return UnableToLegalize; 1003 1004 Observer.changingInstr(MI); 1005 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1006 Observer.changedInstr(MI); 1007 return Legalized; 1008 case TargetOpcode::G_PHI: { 1009 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1010 // NarrowSize. 1011 if (SizeOp0 % NarrowSize != 0) 1012 return UnableToLegalize; 1013 1014 unsigned NumParts = SizeOp0 / NarrowSize; 1015 SmallVector<Register, 2> DstRegs(NumParts); 1016 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1017 Observer.changingInstr(MI); 1018 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1019 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1020 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1021 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1022 SrcRegs[i / 2]); 1023 } 1024 MachineBasicBlock &MBB = *MI.getParent(); 1025 MIRBuilder.setInsertPt(MBB, MI); 1026 for (unsigned i = 0; i < NumParts; ++i) { 1027 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1028 MachineInstrBuilder MIB = 1029 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1030 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1031 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1032 } 1033 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1034 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1035 Observer.changedInstr(MI); 1036 MI.eraseFromParent(); 1037 return Legalized; 1038 } 1039 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1040 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1041 if (TypeIdx != 2) 1042 return UnableToLegalize; 1043 1044 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1045 Observer.changingInstr(MI); 1046 narrowScalarSrc(MI, NarrowTy, OpIdx); 1047 Observer.changedInstr(MI); 1048 return Legalized; 1049 } 1050 case TargetOpcode::G_ICMP: { 1051 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 1052 if (NarrowSize * 2 != SrcSize) 1053 return UnableToLegalize; 1054 1055 Observer.changingInstr(MI); 1056 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); 1057 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); 1058 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2)); 1059 1060 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); 1061 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); 1062 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3)); 1063 1064 CmpInst::Predicate Pred = 1065 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1066 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 1067 1068 if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) { 1069 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL); 1070 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); 1071 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); 1072 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1073 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero); 1074 } else { 1075 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1076 MachineInstrBuilder CmpHEQ = 1077 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1078 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1079 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1080 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); 1081 } 1082 Observer.changedInstr(MI); 1083 MI.eraseFromParent(); 1084 return Legalized; 1085 } 1086 case TargetOpcode::G_SEXT_INREG: { 1087 if (TypeIdx != 0) 1088 return UnableToLegalize; 1089 1090 int64_t SizeInBits = MI.getOperand(2).getImm(); 1091 1092 // So long as the new type has more bits than the bits we're extending we 1093 // don't need to break it apart. 1094 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1095 Observer.changingInstr(MI); 1096 // We don't lose any non-extension bits by truncating the src and 1097 // sign-extending the dst. 1098 MachineOperand &MO1 = MI.getOperand(1); 1099 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1100 MO1.setReg(TruncMIB.getReg(0)); 1101 1102 MachineOperand &MO2 = MI.getOperand(0); 1103 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1104 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1105 MIRBuilder.buildSExt(MO2, DstExt); 1106 MO2.setReg(DstExt); 1107 Observer.changedInstr(MI); 1108 return Legalized; 1109 } 1110 1111 // Break it apart. Components below the extension point are unmodified. The 1112 // component containing the extension point becomes a narrower SEXT_INREG. 1113 // Components above it are ashr'd from the component containing the 1114 // extension point. 1115 if (SizeOp0 % NarrowSize != 0) 1116 return UnableToLegalize; 1117 int NumParts = SizeOp0 / NarrowSize; 1118 1119 // List the registers where the destination will be scattered. 1120 SmallVector<Register, 2> DstRegs; 1121 // List the registers where the source will be split. 1122 SmallVector<Register, 2> SrcRegs; 1123 1124 // Create all the temporary registers. 1125 for (int i = 0; i < NumParts; ++i) { 1126 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1127 1128 SrcRegs.push_back(SrcReg); 1129 } 1130 1131 // Explode the big arguments into smaller chunks. 1132 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1133 1134 Register AshrCstReg = 1135 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1136 .getReg(0); 1137 Register FullExtensionReg = 0; 1138 Register PartialExtensionReg = 0; 1139 1140 // Do the operation on each small part. 1141 for (int i = 0; i < NumParts; ++i) { 1142 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1143 DstRegs.push_back(SrcRegs[i]); 1144 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1145 assert(PartialExtensionReg && 1146 "Expected to visit partial extension before full"); 1147 if (FullExtensionReg) { 1148 DstRegs.push_back(FullExtensionReg); 1149 continue; 1150 } 1151 DstRegs.push_back( 1152 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1153 .getReg(0)); 1154 FullExtensionReg = DstRegs.back(); 1155 } else { 1156 DstRegs.push_back( 1157 MIRBuilder 1158 .buildInstr( 1159 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1160 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1161 .getReg(0)); 1162 PartialExtensionReg = DstRegs.back(); 1163 } 1164 } 1165 1166 // Gather the destination registers into the final destination. 1167 Register DstReg = MI.getOperand(0).getReg(); 1168 MIRBuilder.buildMerge(DstReg, DstRegs); 1169 MI.eraseFromParent(); 1170 return Legalized; 1171 } 1172 case TargetOpcode::G_BSWAP: 1173 case TargetOpcode::G_BITREVERSE: { 1174 if (SizeOp0 % NarrowSize != 0) 1175 return UnableToLegalize; 1176 1177 Observer.changingInstr(MI); 1178 SmallVector<Register, 2> SrcRegs, DstRegs; 1179 unsigned NumParts = SizeOp0 / NarrowSize; 1180 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1181 1182 for (unsigned i = 0; i < NumParts; ++i) { 1183 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1184 {SrcRegs[NumParts - 1 - i]}); 1185 DstRegs.push_back(DstPart.getReg(0)); 1186 } 1187 1188 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1189 1190 Observer.changedInstr(MI); 1191 MI.eraseFromParent(); 1192 return Legalized; 1193 } 1194 case TargetOpcode::G_PTR_ADD: 1195 case TargetOpcode::G_PTRMASK: { 1196 if (TypeIdx != 1) 1197 return UnableToLegalize; 1198 Observer.changingInstr(MI); 1199 narrowScalarSrc(MI, NarrowTy, 2); 1200 Observer.changedInstr(MI); 1201 return Legalized; 1202 } 1203 case TargetOpcode::G_FPTOUI: { 1204 if (TypeIdx != 0) 1205 return UnableToLegalize; 1206 Observer.changingInstr(MI); 1207 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1208 Observer.changedInstr(MI); 1209 return Legalized; 1210 } 1211 case TargetOpcode::G_FPTOSI: { 1212 if (TypeIdx != 0) 1213 return UnableToLegalize; 1214 Observer.changingInstr(MI); 1215 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_SEXT); 1216 Observer.changedInstr(MI); 1217 return Legalized; 1218 } 1219 case TargetOpcode::G_FPEXT: 1220 if (TypeIdx != 0) 1221 return UnableToLegalize; 1222 Observer.changingInstr(MI); 1223 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1224 Observer.changedInstr(MI); 1225 return Legalized; 1226 } 1227 } 1228 1229 Register LegalizerHelper::coerceToScalar(Register Val) { 1230 LLT Ty = MRI.getType(Val); 1231 if (Ty.isScalar()) 1232 return Val; 1233 1234 const DataLayout &DL = MIRBuilder.getDataLayout(); 1235 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1236 if (Ty.isPointer()) { 1237 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1238 return Register(); 1239 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1240 } 1241 1242 Register NewVal = Val; 1243 1244 assert(Ty.isVector()); 1245 LLT EltTy = Ty.getElementType(); 1246 if (EltTy.isPointer()) 1247 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1248 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1249 } 1250 1251 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1252 unsigned OpIdx, unsigned ExtOpcode) { 1253 MachineOperand &MO = MI.getOperand(OpIdx); 1254 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1255 MO.setReg(ExtB.getReg(0)); 1256 } 1257 1258 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1259 unsigned OpIdx) { 1260 MachineOperand &MO = MI.getOperand(OpIdx); 1261 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1262 MO.setReg(ExtB.getReg(0)); 1263 } 1264 1265 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1266 unsigned OpIdx, unsigned TruncOpcode) { 1267 MachineOperand &MO = MI.getOperand(OpIdx); 1268 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1269 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1270 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1271 MO.setReg(DstExt); 1272 } 1273 1274 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1275 unsigned OpIdx, unsigned ExtOpcode) { 1276 MachineOperand &MO = MI.getOperand(OpIdx); 1277 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1278 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1279 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1280 MO.setReg(DstTrunc); 1281 } 1282 1283 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1284 unsigned OpIdx) { 1285 MachineOperand &MO = MI.getOperand(OpIdx); 1286 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1287 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1288 } 1289 1290 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1291 unsigned OpIdx) { 1292 MachineOperand &MO = MI.getOperand(OpIdx); 1293 1294 LLT OldTy = MRI.getType(MO.getReg()); 1295 unsigned OldElts = OldTy.getNumElements(); 1296 unsigned NewElts = MoreTy.getNumElements(); 1297 1298 unsigned NumParts = NewElts / OldElts; 1299 1300 // Use concat_vectors if the result is a multiple of the number of elements. 1301 if (NumParts * OldElts == NewElts) { 1302 SmallVector<Register, 8> Parts; 1303 Parts.push_back(MO.getReg()); 1304 1305 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1306 for (unsigned I = 1; I != NumParts; ++I) 1307 Parts.push_back(ImpDef); 1308 1309 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1310 MO.setReg(Concat.getReg(0)); 1311 return; 1312 } 1313 1314 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1315 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1316 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1317 MO.setReg(MoreReg); 1318 } 1319 1320 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1321 MachineOperand &Op = MI.getOperand(OpIdx); 1322 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1323 } 1324 1325 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1326 MachineOperand &MO = MI.getOperand(OpIdx); 1327 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1328 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1329 MIRBuilder.buildBitcast(MO, CastDst); 1330 MO.setReg(CastDst); 1331 } 1332 1333 LegalizerHelper::LegalizeResult 1334 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1335 LLT WideTy) { 1336 if (TypeIdx != 1) 1337 return UnableToLegalize; 1338 1339 Register DstReg = MI.getOperand(0).getReg(); 1340 LLT DstTy = MRI.getType(DstReg); 1341 if (DstTy.isVector()) 1342 return UnableToLegalize; 1343 1344 Register Src1 = MI.getOperand(1).getReg(); 1345 LLT SrcTy = MRI.getType(Src1); 1346 const int DstSize = DstTy.getSizeInBits(); 1347 const int SrcSize = SrcTy.getSizeInBits(); 1348 const int WideSize = WideTy.getSizeInBits(); 1349 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1350 1351 unsigned NumOps = MI.getNumOperands(); 1352 unsigned NumSrc = MI.getNumOperands() - 1; 1353 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1354 1355 if (WideSize >= DstSize) { 1356 // Directly pack the bits in the target type. 1357 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1358 1359 for (unsigned I = 2; I != NumOps; ++I) { 1360 const unsigned Offset = (I - 1) * PartSize; 1361 1362 Register SrcReg = MI.getOperand(I).getReg(); 1363 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1364 1365 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1366 1367 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1368 MRI.createGenericVirtualRegister(WideTy); 1369 1370 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1371 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1372 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1373 ResultReg = NextResult; 1374 } 1375 1376 if (WideSize > DstSize) 1377 MIRBuilder.buildTrunc(DstReg, ResultReg); 1378 else if (DstTy.isPointer()) 1379 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1380 1381 MI.eraseFromParent(); 1382 return Legalized; 1383 } 1384 1385 // Unmerge the original values to the GCD type, and recombine to the next 1386 // multiple greater than the original type. 1387 // 1388 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1389 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1390 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1391 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1392 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1393 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1394 // %12:_(s12) = G_MERGE_VALUES %10, %11 1395 // 1396 // Padding with undef if necessary: 1397 // 1398 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1399 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1400 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1401 // %7:_(s2) = G_IMPLICIT_DEF 1402 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1403 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1404 // %10:_(s12) = G_MERGE_VALUES %8, %9 1405 1406 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1407 LLT GCDTy = LLT::scalar(GCD); 1408 1409 SmallVector<Register, 8> Parts; 1410 SmallVector<Register, 8> NewMergeRegs; 1411 SmallVector<Register, 8> Unmerges; 1412 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1413 1414 // Decompose the original operands if they don't evenly divide. 1415 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1416 Register SrcReg = MI.getOperand(I).getReg(); 1417 if (GCD == SrcSize) { 1418 Unmerges.push_back(SrcReg); 1419 } else { 1420 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1421 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1422 Unmerges.push_back(Unmerge.getReg(J)); 1423 } 1424 } 1425 1426 // Pad with undef to the next size that is a multiple of the requested size. 1427 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1428 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1429 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1430 Unmerges.push_back(UndefReg); 1431 } 1432 1433 const int PartsPerGCD = WideSize / GCD; 1434 1435 // Build merges of each piece. 1436 ArrayRef<Register> Slicer(Unmerges); 1437 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1438 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1439 NewMergeRegs.push_back(Merge.getReg(0)); 1440 } 1441 1442 // A truncate may be necessary if the requested type doesn't evenly divide the 1443 // original result type. 1444 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1445 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1446 } else { 1447 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1448 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1449 } 1450 1451 MI.eraseFromParent(); 1452 return Legalized; 1453 } 1454 1455 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1456 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1457 LLT OrigTy = MRI.getType(OrigReg); 1458 LLT LCMTy = getLCMType(WideTy, OrigTy); 1459 1460 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1461 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1462 1463 Register UnmergeSrc = WideReg; 1464 1465 // Create a merge to the LCM type, padding with undef 1466 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1467 // => 1468 // %1:_(<4 x s32>) = G_FOO 1469 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1470 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1471 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1472 if (NumMergeParts > 1) { 1473 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1474 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1475 MergeParts[0] = WideReg; 1476 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1477 } 1478 1479 // Unmerge to the original register and pad with dead defs. 1480 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1481 UnmergeResults[0] = OrigReg; 1482 for (int I = 1; I != NumUnmergeParts; ++I) 1483 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1484 1485 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1486 return WideReg; 1487 } 1488 1489 LegalizerHelper::LegalizeResult 1490 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1491 LLT WideTy) { 1492 if (TypeIdx != 0) 1493 return UnableToLegalize; 1494 1495 int NumDst = MI.getNumOperands() - 1; 1496 Register SrcReg = MI.getOperand(NumDst).getReg(); 1497 LLT SrcTy = MRI.getType(SrcReg); 1498 if (SrcTy.isVector()) 1499 return UnableToLegalize; 1500 1501 Register Dst0Reg = MI.getOperand(0).getReg(); 1502 LLT DstTy = MRI.getType(Dst0Reg); 1503 if (!DstTy.isScalar()) 1504 return UnableToLegalize; 1505 1506 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1507 if (SrcTy.isPointer()) { 1508 const DataLayout &DL = MIRBuilder.getDataLayout(); 1509 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1510 LLVM_DEBUG( 1511 dbgs() << "Not casting non-integral address space integer\n"); 1512 return UnableToLegalize; 1513 } 1514 1515 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1516 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1517 } 1518 1519 // Widen SrcTy to WideTy. This does not affect the result, but since the 1520 // user requested this size, it is probably better handled than SrcTy and 1521 // should reduce the total number of legalization artifacts 1522 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1523 SrcTy = WideTy; 1524 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1525 } 1526 1527 // Theres no unmerge type to target. Directly extract the bits from the 1528 // source type 1529 unsigned DstSize = DstTy.getSizeInBits(); 1530 1531 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1532 for (int I = 1; I != NumDst; ++I) { 1533 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1534 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1535 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1536 } 1537 1538 MI.eraseFromParent(); 1539 return Legalized; 1540 } 1541 1542 // Extend the source to a wider type. 1543 LLT LCMTy = getLCMType(SrcTy, WideTy); 1544 1545 Register WideSrc = SrcReg; 1546 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1547 // TODO: If this is an integral address space, cast to integer and anyext. 1548 if (SrcTy.isPointer()) { 1549 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1550 return UnableToLegalize; 1551 } 1552 1553 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1554 } 1555 1556 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1557 1558 // Create a sequence of unmerges and merges to the original results. Since we 1559 // may have widened the source, we will need to pad the results with dead defs 1560 // to cover the source register. 1561 // e.g. widen s48 to s64: 1562 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1563 // 1564 // => 1565 // %4:_(s192) = G_ANYEXT %0:_(s96) 1566 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1567 // ; unpack to GCD type, with extra dead defs 1568 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1569 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1570 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1571 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1572 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1573 const LLT GCDTy = getGCDType(WideTy, DstTy); 1574 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1575 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1576 1577 // Directly unmerge to the destination without going through a GCD type 1578 // if possible 1579 if (PartsPerRemerge == 1) { 1580 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1581 1582 for (int I = 0; I != NumUnmerge; ++I) { 1583 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1584 1585 for (int J = 0; J != PartsPerUnmerge; ++J) { 1586 int Idx = I * PartsPerUnmerge + J; 1587 if (Idx < NumDst) 1588 MIB.addDef(MI.getOperand(Idx).getReg()); 1589 else { 1590 // Create dead def for excess components. 1591 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1592 } 1593 } 1594 1595 MIB.addUse(Unmerge.getReg(I)); 1596 } 1597 } else { 1598 SmallVector<Register, 16> Parts; 1599 for (int J = 0; J != NumUnmerge; ++J) 1600 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1601 1602 SmallVector<Register, 8> RemergeParts; 1603 for (int I = 0; I != NumDst; ++I) { 1604 for (int J = 0; J < PartsPerRemerge; ++J) { 1605 const int Idx = I * PartsPerRemerge + J; 1606 RemergeParts.emplace_back(Parts[Idx]); 1607 } 1608 1609 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1610 RemergeParts.clear(); 1611 } 1612 } 1613 1614 MI.eraseFromParent(); 1615 return Legalized; 1616 } 1617 1618 LegalizerHelper::LegalizeResult 1619 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1620 LLT WideTy) { 1621 Register DstReg = MI.getOperand(0).getReg(); 1622 Register SrcReg = MI.getOperand(1).getReg(); 1623 LLT SrcTy = MRI.getType(SrcReg); 1624 1625 LLT DstTy = MRI.getType(DstReg); 1626 unsigned Offset = MI.getOperand(2).getImm(); 1627 1628 if (TypeIdx == 0) { 1629 if (SrcTy.isVector() || DstTy.isVector()) 1630 return UnableToLegalize; 1631 1632 SrcOp Src(SrcReg); 1633 if (SrcTy.isPointer()) { 1634 // Extracts from pointers can be handled only if they are really just 1635 // simple integers. 1636 const DataLayout &DL = MIRBuilder.getDataLayout(); 1637 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1638 return UnableToLegalize; 1639 1640 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1641 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1642 SrcTy = SrcAsIntTy; 1643 } 1644 1645 if (DstTy.isPointer()) 1646 return UnableToLegalize; 1647 1648 if (Offset == 0) { 1649 // Avoid a shift in the degenerate case. 1650 MIRBuilder.buildTrunc(DstReg, 1651 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1652 MI.eraseFromParent(); 1653 return Legalized; 1654 } 1655 1656 // Do a shift in the source type. 1657 LLT ShiftTy = SrcTy; 1658 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1659 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1660 ShiftTy = WideTy; 1661 } 1662 1663 auto LShr = MIRBuilder.buildLShr( 1664 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1665 MIRBuilder.buildTrunc(DstReg, LShr); 1666 MI.eraseFromParent(); 1667 return Legalized; 1668 } 1669 1670 if (SrcTy.isScalar()) { 1671 Observer.changingInstr(MI); 1672 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1673 Observer.changedInstr(MI); 1674 return Legalized; 1675 } 1676 1677 if (!SrcTy.isVector()) 1678 return UnableToLegalize; 1679 1680 if (DstTy != SrcTy.getElementType()) 1681 return UnableToLegalize; 1682 1683 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1684 return UnableToLegalize; 1685 1686 Observer.changingInstr(MI); 1687 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1688 1689 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1690 Offset); 1691 widenScalarDst(MI, WideTy.getScalarType(), 0); 1692 Observer.changedInstr(MI); 1693 return Legalized; 1694 } 1695 1696 LegalizerHelper::LegalizeResult 1697 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1698 LLT WideTy) { 1699 if (TypeIdx != 0 || WideTy.isVector()) 1700 return UnableToLegalize; 1701 Observer.changingInstr(MI); 1702 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1703 widenScalarDst(MI, WideTy); 1704 Observer.changedInstr(MI); 1705 return Legalized; 1706 } 1707 1708 LegalizerHelper::LegalizeResult 1709 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1710 LLT WideTy) { 1711 if (TypeIdx == 1) 1712 return UnableToLegalize; // TODO 1713 1714 unsigned Opcode; 1715 unsigned ExtOpcode; 1716 Optional<Register> CarryIn = None; 1717 switch (MI.getOpcode()) { 1718 default: 1719 llvm_unreachable("Unexpected opcode!"); 1720 case TargetOpcode::G_SADDO: 1721 Opcode = TargetOpcode::G_ADD; 1722 ExtOpcode = TargetOpcode::G_SEXT; 1723 break; 1724 case TargetOpcode::G_SSUBO: 1725 Opcode = TargetOpcode::G_SUB; 1726 ExtOpcode = TargetOpcode::G_SEXT; 1727 break; 1728 case TargetOpcode::G_UADDO: 1729 Opcode = TargetOpcode::G_ADD; 1730 ExtOpcode = TargetOpcode::G_ZEXT; 1731 break; 1732 case TargetOpcode::G_USUBO: 1733 Opcode = TargetOpcode::G_SUB; 1734 ExtOpcode = TargetOpcode::G_ZEXT; 1735 break; 1736 case TargetOpcode::G_SADDE: 1737 Opcode = TargetOpcode::G_UADDE; 1738 ExtOpcode = TargetOpcode::G_SEXT; 1739 CarryIn = MI.getOperand(4).getReg(); 1740 break; 1741 case TargetOpcode::G_SSUBE: 1742 Opcode = TargetOpcode::G_USUBE; 1743 ExtOpcode = TargetOpcode::G_SEXT; 1744 CarryIn = MI.getOperand(4).getReg(); 1745 break; 1746 case TargetOpcode::G_UADDE: 1747 Opcode = TargetOpcode::G_UADDE; 1748 ExtOpcode = TargetOpcode::G_ZEXT; 1749 CarryIn = MI.getOperand(4).getReg(); 1750 break; 1751 case TargetOpcode::G_USUBE: 1752 Opcode = TargetOpcode::G_USUBE; 1753 ExtOpcode = TargetOpcode::G_ZEXT; 1754 CarryIn = MI.getOperand(4).getReg(); 1755 break; 1756 } 1757 1758 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1759 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1760 // Do the arithmetic in the larger type. 1761 Register NewOp; 1762 if (CarryIn) { 1763 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1764 NewOp = MIRBuilder 1765 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1766 {LHSExt, RHSExt, *CarryIn}) 1767 .getReg(0); 1768 } else { 1769 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1770 } 1771 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1772 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1773 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1774 // There is no overflow if the ExtOp is the same as NewOp. 1775 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1776 // Now trunc the NewOp to the original result. 1777 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1778 MI.eraseFromParent(); 1779 return Legalized; 1780 } 1781 1782 LegalizerHelper::LegalizeResult 1783 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1784 LLT WideTy) { 1785 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1786 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1787 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1788 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1789 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1790 // We can convert this to: 1791 // 1. Any extend iN to iM 1792 // 2. SHL by M-N 1793 // 3. [US][ADD|SUB|SHL]SAT 1794 // 4. L/ASHR by M-N 1795 // 1796 // It may be more efficient to lower this to a min and a max operation in 1797 // the higher precision arithmetic if the promoted operation isn't legal, 1798 // but this decision is up to the target's lowering request. 1799 Register DstReg = MI.getOperand(0).getReg(); 1800 1801 unsigned NewBits = WideTy.getScalarSizeInBits(); 1802 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1803 1804 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1805 // must not left shift the RHS to preserve the shift amount. 1806 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1807 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1808 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1809 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1810 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1811 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1812 1813 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1814 {ShiftL, ShiftR}, MI.getFlags()); 1815 1816 // Use a shift that will preserve the number of sign bits when the trunc is 1817 // folded away. 1818 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1819 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1820 1821 MIRBuilder.buildTrunc(DstReg, Result); 1822 MI.eraseFromParent(); 1823 return Legalized; 1824 } 1825 1826 LegalizerHelper::LegalizeResult 1827 LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, 1828 LLT WideTy) { 1829 if (TypeIdx == 1) 1830 return UnableToLegalize; 1831 1832 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; 1833 Register Result = MI.getOperand(0).getReg(); 1834 Register OriginalOverflow = MI.getOperand(1).getReg(); 1835 Register LHS = MI.getOperand(2).getReg(); 1836 Register RHS = MI.getOperand(3).getReg(); 1837 LLT SrcTy = MRI.getType(LHS); 1838 LLT OverflowTy = MRI.getType(OriginalOverflow); 1839 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); 1840 1841 // To determine if the result overflowed in the larger type, we extend the 1842 // input to the larger type, do the multiply (checking if it overflows), 1843 // then also check the high bits of the result to see if overflow happened 1844 // there. 1845 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 1846 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); 1847 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); 1848 1849 auto Mulo = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy, OverflowTy}, 1850 {LeftOperand, RightOperand}); 1851 auto Mul = Mulo->getOperand(0); 1852 MIRBuilder.buildTrunc(Result, Mul); 1853 1854 MachineInstrBuilder ExtResult; 1855 // Overflow occurred if it occurred in the larger type, or if the high part 1856 // of the result does not zero/sign-extend the low part. Check this second 1857 // possibility first. 1858 if (IsSigned) { 1859 // For signed, overflow occurred when the high part does not sign-extend 1860 // the low part. 1861 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); 1862 } else { 1863 // Unsigned overflow occurred when the high part does not zero-extend the 1864 // low part. 1865 ExtResult = MIRBuilder.buildZExtInReg(WideTy, Mul, SrcBitWidth); 1866 } 1867 1868 // Multiplication cannot overflow if the WideTy is >= 2 * original width, 1869 // so we don't need to check the overflow result of larger type Mulo. 1870 if (WideTy.getScalarSizeInBits() < 2 * SrcBitWidth) { 1871 auto Overflow = 1872 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OverflowTy, Mul, ExtResult); 1873 // Finally check if the multiplication in the larger type itself overflowed. 1874 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow); 1875 } else { 1876 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OriginalOverflow, Mul, ExtResult); 1877 } 1878 MI.eraseFromParent(); 1879 return Legalized; 1880 } 1881 1882 LegalizerHelper::LegalizeResult 1883 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1884 switch (MI.getOpcode()) { 1885 default: 1886 return UnableToLegalize; 1887 case TargetOpcode::G_EXTRACT: 1888 return widenScalarExtract(MI, TypeIdx, WideTy); 1889 case TargetOpcode::G_INSERT: 1890 return widenScalarInsert(MI, TypeIdx, WideTy); 1891 case TargetOpcode::G_MERGE_VALUES: 1892 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1893 case TargetOpcode::G_UNMERGE_VALUES: 1894 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1895 case TargetOpcode::G_SADDO: 1896 case TargetOpcode::G_SSUBO: 1897 case TargetOpcode::G_UADDO: 1898 case TargetOpcode::G_USUBO: 1899 case TargetOpcode::G_SADDE: 1900 case TargetOpcode::G_SSUBE: 1901 case TargetOpcode::G_UADDE: 1902 case TargetOpcode::G_USUBE: 1903 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1904 case TargetOpcode::G_UMULO: 1905 case TargetOpcode::G_SMULO: 1906 return widenScalarMulo(MI, TypeIdx, WideTy); 1907 case TargetOpcode::G_SADDSAT: 1908 case TargetOpcode::G_SSUBSAT: 1909 case TargetOpcode::G_SSHLSAT: 1910 case TargetOpcode::G_UADDSAT: 1911 case TargetOpcode::G_USUBSAT: 1912 case TargetOpcode::G_USHLSAT: 1913 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1914 case TargetOpcode::G_CTTZ: 1915 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1916 case TargetOpcode::G_CTLZ: 1917 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1918 case TargetOpcode::G_CTPOP: { 1919 if (TypeIdx == 0) { 1920 Observer.changingInstr(MI); 1921 widenScalarDst(MI, WideTy, 0); 1922 Observer.changedInstr(MI); 1923 return Legalized; 1924 } 1925 1926 Register SrcReg = MI.getOperand(1).getReg(); 1927 1928 // First ZEXT the input. 1929 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1930 LLT CurTy = MRI.getType(SrcReg); 1931 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1932 // The count is the same in the larger type except if the original 1933 // value was zero. This can be handled by setting the bit just off 1934 // the top of the original type. 1935 auto TopBit = 1936 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1937 MIBSrc = MIRBuilder.buildOr( 1938 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1939 } 1940 1941 // Perform the operation at the larger size. 1942 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1943 // This is already the correct result for CTPOP and CTTZs 1944 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1945 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1946 // The correct result is NewOp - (Difference in widety and current ty). 1947 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1948 MIBNewOp = MIRBuilder.buildSub( 1949 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1950 } 1951 1952 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1953 MI.eraseFromParent(); 1954 return Legalized; 1955 } 1956 case TargetOpcode::G_BSWAP: { 1957 Observer.changingInstr(MI); 1958 Register DstReg = MI.getOperand(0).getReg(); 1959 1960 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 1961 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1962 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 1963 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1964 1965 MI.getOperand(0).setReg(DstExt); 1966 1967 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1968 1969 LLT Ty = MRI.getType(DstReg); 1970 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1971 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 1972 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 1973 1974 MIRBuilder.buildTrunc(DstReg, ShrReg); 1975 Observer.changedInstr(MI); 1976 return Legalized; 1977 } 1978 case TargetOpcode::G_BITREVERSE: { 1979 Observer.changingInstr(MI); 1980 1981 Register DstReg = MI.getOperand(0).getReg(); 1982 LLT Ty = MRI.getType(DstReg); 1983 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1984 1985 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1986 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1987 MI.getOperand(0).setReg(DstExt); 1988 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1989 1990 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 1991 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 1992 MIRBuilder.buildTrunc(DstReg, Shift); 1993 Observer.changedInstr(MI); 1994 return Legalized; 1995 } 1996 case TargetOpcode::G_FREEZE: 1997 Observer.changingInstr(MI); 1998 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1999 widenScalarDst(MI, WideTy); 2000 Observer.changedInstr(MI); 2001 return Legalized; 2002 2003 case TargetOpcode::G_ADD: 2004 case TargetOpcode::G_AND: 2005 case TargetOpcode::G_MUL: 2006 case TargetOpcode::G_OR: 2007 case TargetOpcode::G_XOR: 2008 case TargetOpcode::G_SUB: 2009 // Perform operation at larger width (any extension is fines here, high bits 2010 // don't affect the result) and then truncate the result back to the 2011 // original type. 2012 Observer.changingInstr(MI); 2013 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2014 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2015 widenScalarDst(MI, WideTy); 2016 Observer.changedInstr(MI); 2017 return Legalized; 2018 2019 case TargetOpcode::G_SHL: 2020 Observer.changingInstr(MI); 2021 2022 if (TypeIdx == 0) { 2023 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2024 widenScalarDst(MI, WideTy); 2025 } else { 2026 assert(TypeIdx == 1); 2027 // The "number of bits to shift" operand must preserve its value as an 2028 // unsigned integer: 2029 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2030 } 2031 2032 Observer.changedInstr(MI); 2033 return Legalized; 2034 2035 case TargetOpcode::G_SDIV: 2036 case TargetOpcode::G_SREM: 2037 case TargetOpcode::G_SMIN: 2038 case TargetOpcode::G_SMAX: 2039 Observer.changingInstr(MI); 2040 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2041 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2042 widenScalarDst(MI, WideTy); 2043 Observer.changedInstr(MI); 2044 return Legalized; 2045 2046 case TargetOpcode::G_ASHR: 2047 case TargetOpcode::G_LSHR: 2048 Observer.changingInstr(MI); 2049 2050 if (TypeIdx == 0) { 2051 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2052 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2053 2054 widenScalarSrc(MI, WideTy, 1, CvtOp); 2055 widenScalarDst(MI, WideTy); 2056 } else { 2057 assert(TypeIdx == 1); 2058 // The "number of bits to shift" operand must preserve its value as an 2059 // unsigned integer: 2060 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2061 } 2062 2063 Observer.changedInstr(MI); 2064 return Legalized; 2065 case TargetOpcode::G_UDIV: 2066 case TargetOpcode::G_UREM: 2067 case TargetOpcode::G_UMIN: 2068 case TargetOpcode::G_UMAX: 2069 Observer.changingInstr(MI); 2070 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2071 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2072 widenScalarDst(MI, WideTy); 2073 Observer.changedInstr(MI); 2074 return Legalized; 2075 2076 case TargetOpcode::G_SELECT: 2077 Observer.changingInstr(MI); 2078 if (TypeIdx == 0) { 2079 // Perform operation at larger width (any extension is fine here, high 2080 // bits don't affect the result) and then truncate the result back to the 2081 // original type. 2082 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2083 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2084 widenScalarDst(MI, WideTy); 2085 } else { 2086 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2087 // Explicit extension is required here since high bits affect the result. 2088 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2089 } 2090 Observer.changedInstr(MI); 2091 return Legalized; 2092 2093 case TargetOpcode::G_FPTOSI: 2094 case TargetOpcode::G_FPTOUI: 2095 Observer.changingInstr(MI); 2096 2097 if (TypeIdx == 0) 2098 widenScalarDst(MI, WideTy); 2099 else 2100 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2101 2102 Observer.changedInstr(MI); 2103 return Legalized; 2104 case TargetOpcode::G_SITOFP: 2105 Observer.changingInstr(MI); 2106 2107 if (TypeIdx == 0) 2108 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2109 else 2110 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2111 2112 Observer.changedInstr(MI); 2113 return Legalized; 2114 case TargetOpcode::G_UITOFP: 2115 Observer.changingInstr(MI); 2116 2117 if (TypeIdx == 0) 2118 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2119 else 2120 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2121 2122 Observer.changedInstr(MI); 2123 return Legalized; 2124 case TargetOpcode::G_LOAD: 2125 case TargetOpcode::G_SEXTLOAD: 2126 case TargetOpcode::G_ZEXTLOAD: 2127 Observer.changingInstr(MI); 2128 widenScalarDst(MI, WideTy); 2129 Observer.changedInstr(MI); 2130 return Legalized; 2131 2132 case TargetOpcode::G_STORE: { 2133 if (TypeIdx != 0) 2134 return UnableToLegalize; 2135 2136 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2137 if (!Ty.isScalar()) 2138 return UnableToLegalize; 2139 2140 Observer.changingInstr(MI); 2141 2142 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2143 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2144 widenScalarSrc(MI, WideTy, 0, ExtType); 2145 2146 Observer.changedInstr(MI); 2147 return Legalized; 2148 } 2149 case TargetOpcode::G_CONSTANT: { 2150 MachineOperand &SrcMO = MI.getOperand(1); 2151 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2152 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2153 MRI.getType(MI.getOperand(0).getReg())); 2154 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2155 ExtOpc == TargetOpcode::G_ANYEXT) && 2156 "Illegal Extend"); 2157 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2158 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2159 ? SrcVal.sext(WideTy.getSizeInBits()) 2160 : SrcVal.zext(WideTy.getSizeInBits()); 2161 Observer.changingInstr(MI); 2162 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2163 2164 widenScalarDst(MI, WideTy); 2165 Observer.changedInstr(MI); 2166 return Legalized; 2167 } 2168 case TargetOpcode::G_FCONSTANT: { 2169 MachineOperand &SrcMO = MI.getOperand(1); 2170 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2171 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2172 bool LosesInfo; 2173 switch (WideTy.getSizeInBits()) { 2174 case 32: 2175 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2176 &LosesInfo); 2177 break; 2178 case 64: 2179 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2180 &LosesInfo); 2181 break; 2182 default: 2183 return UnableToLegalize; 2184 } 2185 2186 assert(!LosesInfo && "extend should always be lossless"); 2187 2188 Observer.changingInstr(MI); 2189 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2190 2191 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2192 Observer.changedInstr(MI); 2193 return Legalized; 2194 } 2195 case TargetOpcode::G_IMPLICIT_DEF: { 2196 Observer.changingInstr(MI); 2197 widenScalarDst(MI, WideTy); 2198 Observer.changedInstr(MI); 2199 return Legalized; 2200 } 2201 case TargetOpcode::G_BRCOND: 2202 Observer.changingInstr(MI); 2203 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2204 Observer.changedInstr(MI); 2205 return Legalized; 2206 2207 case TargetOpcode::G_FCMP: 2208 Observer.changingInstr(MI); 2209 if (TypeIdx == 0) 2210 widenScalarDst(MI, WideTy); 2211 else { 2212 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2213 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2214 } 2215 Observer.changedInstr(MI); 2216 return Legalized; 2217 2218 case TargetOpcode::G_ICMP: 2219 Observer.changingInstr(MI); 2220 if (TypeIdx == 0) 2221 widenScalarDst(MI, WideTy); 2222 else { 2223 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2224 MI.getOperand(1).getPredicate())) 2225 ? TargetOpcode::G_SEXT 2226 : TargetOpcode::G_ZEXT; 2227 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2228 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2229 } 2230 Observer.changedInstr(MI); 2231 return Legalized; 2232 2233 case TargetOpcode::G_PTR_ADD: 2234 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2235 Observer.changingInstr(MI); 2236 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2237 Observer.changedInstr(MI); 2238 return Legalized; 2239 2240 case TargetOpcode::G_PHI: { 2241 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2242 2243 Observer.changingInstr(MI); 2244 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2245 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2246 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2247 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2248 } 2249 2250 MachineBasicBlock &MBB = *MI.getParent(); 2251 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2252 widenScalarDst(MI, WideTy); 2253 Observer.changedInstr(MI); 2254 return Legalized; 2255 } 2256 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2257 if (TypeIdx == 0) { 2258 Register VecReg = MI.getOperand(1).getReg(); 2259 LLT VecTy = MRI.getType(VecReg); 2260 Observer.changingInstr(MI); 2261 2262 widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(), 2263 WideTy.getSizeInBits()), 2264 1, TargetOpcode::G_SEXT); 2265 2266 widenScalarDst(MI, WideTy, 0); 2267 Observer.changedInstr(MI); 2268 return Legalized; 2269 } 2270 2271 if (TypeIdx != 2) 2272 return UnableToLegalize; 2273 Observer.changingInstr(MI); 2274 // TODO: Probably should be zext 2275 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2276 Observer.changedInstr(MI); 2277 return Legalized; 2278 } 2279 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2280 if (TypeIdx == 1) { 2281 Observer.changingInstr(MI); 2282 2283 Register VecReg = MI.getOperand(1).getReg(); 2284 LLT VecTy = MRI.getType(VecReg); 2285 LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy); 2286 2287 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2288 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2289 widenScalarDst(MI, WideVecTy, 0); 2290 Observer.changedInstr(MI); 2291 return Legalized; 2292 } 2293 2294 if (TypeIdx == 2) { 2295 Observer.changingInstr(MI); 2296 // TODO: Probably should be zext 2297 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2298 Observer.changedInstr(MI); 2299 return Legalized; 2300 } 2301 2302 return UnableToLegalize; 2303 } 2304 case TargetOpcode::G_FADD: 2305 case TargetOpcode::G_FMUL: 2306 case TargetOpcode::G_FSUB: 2307 case TargetOpcode::G_FMA: 2308 case TargetOpcode::G_FMAD: 2309 case TargetOpcode::G_FNEG: 2310 case TargetOpcode::G_FABS: 2311 case TargetOpcode::G_FCANONICALIZE: 2312 case TargetOpcode::G_FMINNUM: 2313 case TargetOpcode::G_FMAXNUM: 2314 case TargetOpcode::G_FMINNUM_IEEE: 2315 case TargetOpcode::G_FMAXNUM_IEEE: 2316 case TargetOpcode::G_FMINIMUM: 2317 case TargetOpcode::G_FMAXIMUM: 2318 case TargetOpcode::G_FDIV: 2319 case TargetOpcode::G_FREM: 2320 case TargetOpcode::G_FCEIL: 2321 case TargetOpcode::G_FFLOOR: 2322 case TargetOpcode::G_FCOS: 2323 case TargetOpcode::G_FSIN: 2324 case TargetOpcode::G_FLOG10: 2325 case TargetOpcode::G_FLOG: 2326 case TargetOpcode::G_FLOG2: 2327 case TargetOpcode::G_FRINT: 2328 case TargetOpcode::G_FNEARBYINT: 2329 case TargetOpcode::G_FSQRT: 2330 case TargetOpcode::G_FEXP: 2331 case TargetOpcode::G_FEXP2: 2332 case TargetOpcode::G_FPOW: 2333 case TargetOpcode::G_INTRINSIC_TRUNC: 2334 case TargetOpcode::G_INTRINSIC_ROUND: 2335 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2336 assert(TypeIdx == 0); 2337 Observer.changingInstr(MI); 2338 2339 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2340 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2341 2342 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2343 Observer.changedInstr(MI); 2344 return Legalized; 2345 case TargetOpcode::G_FPOWI: { 2346 if (TypeIdx != 0) 2347 return UnableToLegalize; 2348 Observer.changingInstr(MI); 2349 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2350 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2351 Observer.changedInstr(MI); 2352 return Legalized; 2353 } 2354 case TargetOpcode::G_INTTOPTR: 2355 if (TypeIdx != 1) 2356 return UnableToLegalize; 2357 2358 Observer.changingInstr(MI); 2359 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2360 Observer.changedInstr(MI); 2361 return Legalized; 2362 case TargetOpcode::G_PTRTOINT: 2363 if (TypeIdx != 0) 2364 return UnableToLegalize; 2365 2366 Observer.changingInstr(MI); 2367 widenScalarDst(MI, WideTy, 0); 2368 Observer.changedInstr(MI); 2369 return Legalized; 2370 case TargetOpcode::G_BUILD_VECTOR: { 2371 Observer.changingInstr(MI); 2372 2373 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2374 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2375 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2376 2377 // Avoid changing the result vector type if the source element type was 2378 // requested. 2379 if (TypeIdx == 1) { 2380 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2381 } else { 2382 widenScalarDst(MI, WideTy, 0); 2383 } 2384 2385 Observer.changedInstr(MI); 2386 return Legalized; 2387 } 2388 case TargetOpcode::G_SEXT_INREG: 2389 if (TypeIdx != 0) 2390 return UnableToLegalize; 2391 2392 Observer.changingInstr(MI); 2393 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2394 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2395 Observer.changedInstr(MI); 2396 return Legalized; 2397 case TargetOpcode::G_PTRMASK: { 2398 if (TypeIdx != 1) 2399 return UnableToLegalize; 2400 Observer.changingInstr(MI); 2401 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2402 Observer.changedInstr(MI); 2403 return Legalized; 2404 } 2405 } 2406 } 2407 2408 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2409 MachineIRBuilder &B, Register Src, LLT Ty) { 2410 auto Unmerge = B.buildUnmerge(Ty, Src); 2411 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2412 Pieces.push_back(Unmerge.getReg(I)); 2413 } 2414 2415 LegalizerHelper::LegalizeResult 2416 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2417 Register Dst = MI.getOperand(0).getReg(); 2418 Register Src = MI.getOperand(1).getReg(); 2419 LLT DstTy = MRI.getType(Dst); 2420 LLT SrcTy = MRI.getType(Src); 2421 2422 if (SrcTy.isVector()) { 2423 LLT SrcEltTy = SrcTy.getElementType(); 2424 SmallVector<Register, 8> SrcRegs; 2425 2426 if (DstTy.isVector()) { 2427 int NumDstElt = DstTy.getNumElements(); 2428 int NumSrcElt = SrcTy.getNumElements(); 2429 2430 LLT DstEltTy = DstTy.getElementType(); 2431 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2432 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2433 2434 // If there's an element size mismatch, insert intermediate casts to match 2435 // the result element type. 2436 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2437 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2438 // 2439 // => 2440 // 2441 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2442 // %3:_(<2 x s8>) = G_BITCAST %2 2443 // %4:_(<2 x s8>) = G_BITCAST %3 2444 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2445 DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy); 2446 SrcPartTy = SrcEltTy; 2447 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2448 // 2449 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2450 // 2451 // => 2452 // 2453 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2454 // %3:_(s16) = G_BITCAST %2 2455 // %4:_(s16) = G_BITCAST %3 2456 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2457 SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy); 2458 DstCastTy = DstEltTy; 2459 } 2460 2461 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2462 for (Register &SrcReg : SrcRegs) 2463 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2464 } else 2465 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2466 2467 MIRBuilder.buildMerge(Dst, SrcRegs); 2468 MI.eraseFromParent(); 2469 return Legalized; 2470 } 2471 2472 if (DstTy.isVector()) { 2473 SmallVector<Register, 8> SrcRegs; 2474 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2475 MIRBuilder.buildMerge(Dst, SrcRegs); 2476 MI.eraseFromParent(); 2477 return Legalized; 2478 } 2479 2480 return UnableToLegalize; 2481 } 2482 2483 /// Figure out the bit offset into a register when coercing a vector index for 2484 /// the wide element type. This is only for the case when promoting vector to 2485 /// one with larger elements. 2486 // 2487 /// 2488 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2489 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2490 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2491 Register Idx, 2492 unsigned NewEltSize, 2493 unsigned OldEltSize) { 2494 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2495 LLT IdxTy = B.getMRI()->getType(Idx); 2496 2497 // Now figure out the amount we need to shift to get the target bits. 2498 auto OffsetMask = B.buildConstant( 2499 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2500 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2501 return B.buildShl(IdxTy, OffsetIdx, 2502 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2503 } 2504 2505 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2506 /// is casting to a vector with a smaller element size, perform multiple element 2507 /// extracts and merge the results. If this is coercing to a vector with larger 2508 /// elements, index the bitcasted vector and extract the target element with bit 2509 /// operations. This is intended to force the indexing in the native register 2510 /// size for architectures that can dynamically index the register file. 2511 LegalizerHelper::LegalizeResult 2512 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2513 LLT CastTy) { 2514 if (TypeIdx != 1) 2515 return UnableToLegalize; 2516 2517 Register Dst = MI.getOperand(0).getReg(); 2518 Register SrcVec = MI.getOperand(1).getReg(); 2519 Register Idx = MI.getOperand(2).getReg(); 2520 LLT SrcVecTy = MRI.getType(SrcVec); 2521 LLT IdxTy = MRI.getType(Idx); 2522 2523 LLT SrcEltTy = SrcVecTy.getElementType(); 2524 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2525 unsigned OldNumElts = SrcVecTy.getNumElements(); 2526 2527 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2528 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2529 2530 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2531 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2532 if (NewNumElts > OldNumElts) { 2533 // Decreasing the vector element size 2534 // 2535 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2536 // => 2537 // v4i32:castx = bitcast x:v2i64 2538 // 2539 // i64 = bitcast 2540 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2541 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2542 // 2543 if (NewNumElts % OldNumElts != 0) 2544 return UnableToLegalize; 2545 2546 // Type of the intermediate result vector. 2547 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2548 LLT MidTy = LLT::scalarOrVector(NewEltsPerOldElt, NewEltTy); 2549 2550 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2551 2552 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2553 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2554 2555 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2556 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2557 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2558 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2559 NewOps[I] = Elt.getReg(0); 2560 } 2561 2562 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2563 MIRBuilder.buildBitcast(Dst, NewVec); 2564 MI.eraseFromParent(); 2565 return Legalized; 2566 } 2567 2568 if (NewNumElts < OldNumElts) { 2569 if (NewEltSize % OldEltSize != 0) 2570 return UnableToLegalize; 2571 2572 // This only depends on powers of 2 because we use bit tricks to figure out 2573 // the bit offset we need to shift to get the target element. A general 2574 // expansion could emit division/multiply. 2575 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2576 return UnableToLegalize; 2577 2578 // Increasing the vector element size. 2579 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2580 // 2581 // => 2582 // 2583 // %cast = G_BITCAST %vec 2584 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2585 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2586 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2587 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2588 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2589 // %elt = G_TRUNC %elt_bits 2590 2591 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2592 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2593 2594 // Divide to get the index in the wider element type. 2595 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2596 2597 Register WideElt = CastVec; 2598 if (CastTy.isVector()) { 2599 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2600 ScaledIdx).getReg(0); 2601 } 2602 2603 // Compute the bit offset into the register of the target element. 2604 Register OffsetBits = getBitcastWiderVectorElementOffset( 2605 MIRBuilder, Idx, NewEltSize, OldEltSize); 2606 2607 // Shift the wide element to get the target element. 2608 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2609 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2610 MI.eraseFromParent(); 2611 return Legalized; 2612 } 2613 2614 return UnableToLegalize; 2615 } 2616 2617 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2618 /// TargetReg, while preserving other bits in \p TargetReg. 2619 /// 2620 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2621 static Register buildBitFieldInsert(MachineIRBuilder &B, 2622 Register TargetReg, Register InsertReg, 2623 Register OffsetBits) { 2624 LLT TargetTy = B.getMRI()->getType(TargetReg); 2625 LLT InsertTy = B.getMRI()->getType(InsertReg); 2626 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2627 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2628 2629 // Produce a bitmask of the value to insert 2630 auto EltMask = B.buildConstant( 2631 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2632 InsertTy.getSizeInBits())); 2633 // Shift it into position 2634 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2635 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2636 2637 // Clear out the bits in the wide element 2638 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2639 2640 // The value to insert has all zeros already, so stick it into the masked 2641 // wide element. 2642 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2643 } 2644 2645 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2646 /// is increasing the element size, perform the indexing in the target element 2647 /// type, and use bit operations to insert at the element position. This is 2648 /// intended for architectures that can dynamically index the register file and 2649 /// want to force indexing in the native register size. 2650 LegalizerHelper::LegalizeResult 2651 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2652 LLT CastTy) { 2653 if (TypeIdx != 0) 2654 return UnableToLegalize; 2655 2656 Register Dst = MI.getOperand(0).getReg(); 2657 Register SrcVec = MI.getOperand(1).getReg(); 2658 Register Val = MI.getOperand(2).getReg(); 2659 Register Idx = MI.getOperand(3).getReg(); 2660 2661 LLT VecTy = MRI.getType(Dst); 2662 LLT IdxTy = MRI.getType(Idx); 2663 2664 LLT VecEltTy = VecTy.getElementType(); 2665 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2666 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2667 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2668 2669 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2670 unsigned OldNumElts = VecTy.getNumElements(); 2671 2672 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2673 if (NewNumElts < OldNumElts) { 2674 if (NewEltSize % OldEltSize != 0) 2675 return UnableToLegalize; 2676 2677 // This only depends on powers of 2 because we use bit tricks to figure out 2678 // the bit offset we need to shift to get the target element. A general 2679 // expansion could emit division/multiply. 2680 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2681 return UnableToLegalize; 2682 2683 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2684 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2685 2686 // Divide to get the index in the wider element type. 2687 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2688 2689 Register ExtractedElt = CastVec; 2690 if (CastTy.isVector()) { 2691 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2692 ScaledIdx).getReg(0); 2693 } 2694 2695 // Compute the bit offset into the register of the target element. 2696 Register OffsetBits = getBitcastWiderVectorElementOffset( 2697 MIRBuilder, Idx, NewEltSize, OldEltSize); 2698 2699 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2700 Val, OffsetBits); 2701 if (CastTy.isVector()) { 2702 InsertedElt = MIRBuilder.buildInsertVectorElement( 2703 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2704 } 2705 2706 MIRBuilder.buildBitcast(Dst, InsertedElt); 2707 MI.eraseFromParent(); 2708 return Legalized; 2709 } 2710 2711 return UnableToLegalize; 2712 } 2713 2714 LegalizerHelper::LegalizeResult 2715 LegalizerHelper::lowerLoad(MachineInstr &MI) { 2716 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2717 Register DstReg = MI.getOperand(0).getReg(); 2718 Register PtrReg = MI.getOperand(1).getReg(); 2719 LLT DstTy = MRI.getType(DstReg); 2720 auto &MMO = **MI.memoperands_begin(); 2721 2722 if (DstTy.getSizeInBits() == MMO.getSizeInBits()) { 2723 if (MI.getOpcode() == TargetOpcode::G_LOAD) { 2724 // This load needs splitting into power of 2 sized loads. 2725 if (DstTy.isVector()) 2726 return UnableToLegalize; 2727 if (isPowerOf2_32(DstTy.getSizeInBits())) 2728 return UnableToLegalize; // Don't know what we're being asked to do. 2729 2730 // Our strategy here is to generate anyextending loads for the smaller 2731 // types up to next power-2 result type, and then combine the two larger 2732 // result values together, before truncating back down to the non-pow-2 2733 // type. 2734 // E.g. v1 = i24 load => 2735 // v2 = i32 zextload (2 byte) 2736 // v3 = i32 load (1 byte) 2737 // v4 = i32 shl v3, 16 2738 // v5 = i32 or v4, v2 2739 // v1 = i24 trunc v5 2740 // By doing this we generate the correct truncate which should get 2741 // combined away as an artifact with a matching extend. 2742 uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits()); 2743 uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize; 2744 2745 MachineFunction &MF = MIRBuilder.getMF(); 2746 MachineMemOperand *LargeMMO = 2747 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2748 MachineMemOperand *SmallMMO = MF.getMachineMemOperand( 2749 &MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2750 2751 LLT PtrTy = MRI.getType(PtrReg); 2752 unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits()); 2753 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2754 Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2755 Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2756 auto LargeLoad = MIRBuilder.buildLoadInstr( 2757 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO); 2758 2759 auto OffsetCst = MIRBuilder.buildConstant( 2760 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2761 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2762 auto SmallPtr = 2763 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2764 auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0), 2765 *SmallMMO); 2766 2767 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2768 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2769 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2770 MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)}); 2771 MI.eraseFromParent(); 2772 return Legalized; 2773 } 2774 2775 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); 2776 MI.eraseFromParent(); 2777 return Legalized; 2778 } 2779 2780 if (DstTy.isScalar()) { 2781 Register TmpReg = 2782 MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits())); 2783 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 2784 switch (MI.getOpcode()) { 2785 default: 2786 llvm_unreachable("Unexpected opcode"); 2787 case TargetOpcode::G_LOAD: 2788 MIRBuilder.buildAnyExtOrTrunc(DstReg, TmpReg); 2789 break; 2790 case TargetOpcode::G_SEXTLOAD: 2791 MIRBuilder.buildSExt(DstReg, TmpReg); 2792 break; 2793 case TargetOpcode::G_ZEXTLOAD: 2794 MIRBuilder.buildZExt(DstReg, TmpReg); 2795 break; 2796 } 2797 2798 MI.eraseFromParent(); 2799 return Legalized; 2800 } 2801 2802 return UnableToLegalize; 2803 } 2804 2805 LegalizerHelper::LegalizeResult 2806 LegalizerHelper::lowerStore(MachineInstr &MI) { 2807 // Lower a non-power of 2 store into multiple pow-2 stores. 2808 // E.g. split an i24 store into an i16 store + i8 store. 2809 // We do this by first extending the stored value to the next largest power 2810 // of 2 type, and then using truncating stores to store the components. 2811 // By doing this, likewise with G_LOAD, generate an extend that can be 2812 // artifact-combined away instead of leaving behind extracts. 2813 Register SrcReg = MI.getOperand(0).getReg(); 2814 Register PtrReg = MI.getOperand(1).getReg(); 2815 LLT SrcTy = MRI.getType(SrcReg); 2816 MachineMemOperand &MMO = **MI.memoperands_begin(); 2817 if (SrcTy.getSizeInBits() != MMO.getSizeInBits()) 2818 return UnableToLegalize; 2819 if (SrcTy.isVector()) 2820 return UnableToLegalize; 2821 if (isPowerOf2_32(SrcTy.getSizeInBits())) 2822 return UnableToLegalize; // Don't know what we're being asked to do. 2823 2824 // Extend to the next pow-2. 2825 const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits())); 2826 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2827 2828 // Obtain the smaller value by shifting away the larger value. 2829 uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits()); 2830 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2831 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2832 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2833 2834 // Generate the PtrAdd and truncating stores. 2835 LLT PtrTy = MRI.getType(PtrReg); 2836 auto OffsetCst = MIRBuilder.buildConstant( 2837 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2838 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2839 auto SmallPtr = 2840 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2841 2842 MachineFunction &MF = MIRBuilder.getMF(); 2843 MachineMemOperand *LargeMMO = 2844 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2845 MachineMemOperand *SmallMMO = 2846 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2847 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO); 2848 MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO); 2849 MI.eraseFromParent(); 2850 return Legalized; 2851 } 2852 2853 LegalizerHelper::LegalizeResult 2854 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2855 switch (MI.getOpcode()) { 2856 case TargetOpcode::G_LOAD: { 2857 if (TypeIdx != 0) 2858 return UnableToLegalize; 2859 2860 Observer.changingInstr(MI); 2861 bitcastDst(MI, CastTy, 0); 2862 Observer.changedInstr(MI); 2863 return Legalized; 2864 } 2865 case TargetOpcode::G_STORE: { 2866 if (TypeIdx != 0) 2867 return UnableToLegalize; 2868 2869 Observer.changingInstr(MI); 2870 bitcastSrc(MI, CastTy, 0); 2871 Observer.changedInstr(MI); 2872 return Legalized; 2873 } 2874 case TargetOpcode::G_SELECT: { 2875 if (TypeIdx != 0) 2876 return UnableToLegalize; 2877 2878 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 2879 LLVM_DEBUG( 2880 dbgs() << "bitcast action not implemented for vector select\n"); 2881 return UnableToLegalize; 2882 } 2883 2884 Observer.changingInstr(MI); 2885 bitcastSrc(MI, CastTy, 2); 2886 bitcastSrc(MI, CastTy, 3); 2887 bitcastDst(MI, CastTy, 0); 2888 Observer.changedInstr(MI); 2889 return Legalized; 2890 } 2891 case TargetOpcode::G_AND: 2892 case TargetOpcode::G_OR: 2893 case TargetOpcode::G_XOR: { 2894 Observer.changingInstr(MI); 2895 bitcastSrc(MI, CastTy, 1); 2896 bitcastSrc(MI, CastTy, 2); 2897 bitcastDst(MI, CastTy, 0); 2898 Observer.changedInstr(MI); 2899 return Legalized; 2900 } 2901 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 2902 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 2903 case TargetOpcode::G_INSERT_VECTOR_ELT: 2904 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 2905 default: 2906 return UnableToLegalize; 2907 } 2908 } 2909 2910 // Legalize an instruction by changing the opcode in place. 2911 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 2912 Observer.changingInstr(MI); 2913 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 2914 Observer.changedInstr(MI); 2915 } 2916 2917 LegalizerHelper::LegalizeResult 2918 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 2919 using namespace TargetOpcode; 2920 2921 switch(MI.getOpcode()) { 2922 default: 2923 return UnableToLegalize; 2924 case TargetOpcode::G_BITCAST: 2925 return lowerBitcast(MI); 2926 case TargetOpcode::G_SREM: 2927 case TargetOpcode::G_UREM: { 2928 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2929 auto Quot = 2930 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 2931 {MI.getOperand(1), MI.getOperand(2)}); 2932 2933 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 2934 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 2935 MI.eraseFromParent(); 2936 return Legalized; 2937 } 2938 case TargetOpcode::G_SADDO: 2939 case TargetOpcode::G_SSUBO: 2940 return lowerSADDO_SSUBO(MI); 2941 case TargetOpcode::G_UMULH: 2942 case TargetOpcode::G_SMULH: 2943 return lowerSMULH_UMULH(MI); 2944 case TargetOpcode::G_SMULO: 2945 case TargetOpcode::G_UMULO: { 2946 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 2947 // result. 2948 Register Res = MI.getOperand(0).getReg(); 2949 Register Overflow = MI.getOperand(1).getReg(); 2950 Register LHS = MI.getOperand(2).getReg(); 2951 Register RHS = MI.getOperand(3).getReg(); 2952 LLT Ty = MRI.getType(Res); 2953 2954 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 2955 ? TargetOpcode::G_SMULH 2956 : TargetOpcode::G_UMULH; 2957 2958 Observer.changingInstr(MI); 2959 const auto &TII = MIRBuilder.getTII(); 2960 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 2961 MI.RemoveOperand(1); 2962 Observer.changedInstr(MI); 2963 2964 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 2965 auto Zero = MIRBuilder.buildConstant(Ty, 0); 2966 2967 // Move insert point forward so we can use the Res register if needed. 2968 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2969 2970 // For *signed* multiply, overflow is detected by checking: 2971 // (hi != (lo >> bitwidth-1)) 2972 if (Opcode == TargetOpcode::G_SMULH) { 2973 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 2974 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 2975 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 2976 } else { 2977 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 2978 } 2979 return Legalized; 2980 } 2981 case TargetOpcode::G_FNEG: { 2982 Register Res = MI.getOperand(0).getReg(); 2983 LLT Ty = MRI.getType(Res); 2984 2985 // TODO: Handle vector types once we are able to 2986 // represent them. 2987 if (Ty.isVector()) 2988 return UnableToLegalize; 2989 auto SignMask = 2990 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 2991 Register SubByReg = MI.getOperand(1).getReg(); 2992 MIRBuilder.buildXor(Res, SubByReg, SignMask); 2993 MI.eraseFromParent(); 2994 return Legalized; 2995 } 2996 case TargetOpcode::G_FSUB: { 2997 Register Res = MI.getOperand(0).getReg(); 2998 LLT Ty = MRI.getType(Res); 2999 3000 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 3001 // First, check if G_FNEG is marked as Lower. If so, we may 3002 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 3003 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 3004 return UnableToLegalize; 3005 Register LHS = MI.getOperand(1).getReg(); 3006 Register RHS = MI.getOperand(2).getReg(); 3007 Register Neg = MRI.createGenericVirtualRegister(Ty); 3008 MIRBuilder.buildFNeg(Neg, RHS); 3009 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3010 MI.eraseFromParent(); 3011 return Legalized; 3012 } 3013 case TargetOpcode::G_FMAD: 3014 return lowerFMad(MI); 3015 case TargetOpcode::G_FFLOOR: 3016 return lowerFFloor(MI); 3017 case TargetOpcode::G_INTRINSIC_ROUND: 3018 return lowerIntrinsicRound(MI); 3019 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3020 // Since round even is the assumed rounding mode for unconstrained FP 3021 // operations, rint and roundeven are the same operation. 3022 changeOpcode(MI, TargetOpcode::G_FRINT); 3023 return Legalized; 3024 } 3025 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3026 Register OldValRes = MI.getOperand(0).getReg(); 3027 Register SuccessRes = MI.getOperand(1).getReg(); 3028 Register Addr = MI.getOperand(2).getReg(); 3029 Register CmpVal = MI.getOperand(3).getReg(); 3030 Register NewVal = MI.getOperand(4).getReg(); 3031 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3032 **MI.memoperands_begin()); 3033 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3034 MI.eraseFromParent(); 3035 return Legalized; 3036 } 3037 case TargetOpcode::G_LOAD: 3038 case TargetOpcode::G_SEXTLOAD: 3039 case TargetOpcode::G_ZEXTLOAD: 3040 return lowerLoad(MI); 3041 case TargetOpcode::G_STORE: 3042 return lowerStore(MI); 3043 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3044 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3045 case TargetOpcode::G_CTLZ: 3046 case TargetOpcode::G_CTTZ: 3047 case TargetOpcode::G_CTPOP: 3048 return lowerBitCount(MI); 3049 case G_UADDO: { 3050 Register Res = MI.getOperand(0).getReg(); 3051 Register CarryOut = MI.getOperand(1).getReg(); 3052 Register LHS = MI.getOperand(2).getReg(); 3053 Register RHS = MI.getOperand(3).getReg(); 3054 3055 MIRBuilder.buildAdd(Res, LHS, RHS); 3056 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3057 3058 MI.eraseFromParent(); 3059 return Legalized; 3060 } 3061 case G_UADDE: { 3062 Register Res = MI.getOperand(0).getReg(); 3063 Register CarryOut = MI.getOperand(1).getReg(); 3064 Register LHS = MI.getOperand(2).getReg(); 3065 Register RHS = MI.getOperand(3).getReg(); 3066 Register CarryIn = MI.getOperand(4).getReg(); 3067 LLT Ty = MRI.getType(Res); 3068 3069 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3070 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3071 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3072 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3073 3074 MI.eraseFromParent(); 3075 return Legalized; 3076 } 3077 case G_USUBO: { 3078 Register Res = MI.getOperand(0).getReg(); 3079 Register BorrowOut = MI.getOperand(1).getReg(); 3080 Register LHS = MI.getOperand(2).getReg(); 3081 Register RHS = MI.getOperand(3).getReg(); 3082 3083 MIRBuilder.buildSub(Res, LHS, RHS); 3084 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3085 3086 MI.eraseFromParent(); 3087 return Legalized; 3088 } 3089 case G_USUBE: { 3090 Register Res = MI.getOperand(0).getReg(); 3091 Register BorrowOut = MI.getOperand(1).getReg(); 3092 Register LHS = MI.getOperand(2).getReg(); 3093 Register RHS = MI.getOperand(3).getReg(); 3094 Register BorrowIn = MI.getOperand(4).getReg(); 3095 const LLT CondTy = MRI.getType(BorrowOut); 3096 const LLT Ty = MRI.getType(Res); 3097 3098 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3099 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3100 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3101 3102 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3103 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3104 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3105 3106 MI.eraseFromParent(); 3107 return Legalized; 3108 } 3109 case G_UITOFP: 3110 return lowerUITOFP(MI); 3111 case G_SITOFP: 3112 return lowerSITOFP(MI); 3113 case G_FPTOUI: 3114 return lowerFPTOUI(MI); 3115 case G_FPTOSI: 3116 return lowerFPTOSI(MI); 3117 case G_FPTRUNC: 3118 return lowerFPTRUNC(MI); 3119 case G_FPOWI: 3120 return lowerFPOWI(MI); 3121 case G_SMIN: 3122 case G_SMAX: 3123 case G_UMIN: 3124 case G_UMAX: 3125 return lowerMinMax(MI); 3126 case G_FCOPYSIGN: 3127 return lowerFCopySign(MI); 3128 case G_FMINNUM: 3129 case G_FMAXNUM: 3130 return lowerFMinNumMaxNum(MI); 3131 case G_MERGE_VALUES: 3132 return lowerMergeValues(MI); 3133 case G_UNMERGE_VALUES: 3134 return lowerUnmergeValues(MI); 3135 case TargetOpcode::G_SEXT_INREG: { 3136 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3137 int64_t SizeInBits = MI.getOperand(2).getImm(); 3138 3139 Register DstReg = MI.getOperand(0).getReg(); 3140 Register SrcReg = MI.getOperand(1).getReg(); 3141 LLT DstTy = MRI.getType(DstReg); 3142 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3143 3144 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3145 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3146 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3147 MI.eraseFromParent(); 3148 return Legalized; 3149 } 3150 case G_EXTRACT_VECTOR_ELT: 3151 case G_INSERT_VECTOR_ELT: 3152 return lowerExtractInsertVectorElt(MI); 3153 case G_SHUFFLE_VECTOR: 3154 return lowerShuffleVector(MI); 3155 case G_DYN_STACKALLOC: 3156 return lowerDynStackAlloc(MI); 3157 case G_EXTRACT: 3158 return lowerExtract(MI); 3159 case G_INSERT: 3160 return lowerInsert(MI); 3161 case G_BSWAP: 3162 return lowerBswap(MI); 3163 case G_BITREVERSE: 3164 return lowerBitreverse(MI); 3165 case G_READ_REGISTER: 3166 case G_WRITE_REGISTER: 3167 return lowerReadWriteRegister(MI); 3168 case G_UADDSAT: 3169 case G_USUBSAT: { 3170 // Try to make a reasonable guess about which lowering strategy to use. The 3171 // target can override this with custom lowering and calling the 3172 // implementation functions. 3173 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3174 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3175 return lowerAddSubSatToMinMax(MI); 3176 return lowerAddSubSatToAddoSubo(MI); 3177 } 3178 case G_SADDSAT: 3179 case G_SSUBSAT: { 3180 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3181 3182 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3183 // since it's a shorter expansion. However, we would need to figure out the 3184 // preferred boolean type for the carry out for the query. 3185 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3186 return lowerAddSubSatToMinMax(MI); 3187 return lowerAddSubSatToAddoSubo(MI); 3188 } 3189 case G_SSHLSAT: 3190 case G_USHLSAT: 3191 return lowerShlSat(MI); 3192 case G_ABS: { 3193 // Expand %res = G_ABS %a into: 3194 // %v1 = G_ASHR %a, scalar_size-1 3195 // %v2 = G_ADD %a, %v1 3196 // %res = G_XOR %v2, %v1 3197 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3198 Register OpReg = MI.getOperand(1).getReg(); 3199 auto ShiftAmt = 3200 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 3201 auto Shift = 3202 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 3203 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 3204 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 3205 MI.eraseFromParent(); 3206 return Legalized; 3207 } 3208 case G_SELECT: 3209 return lowerSelect(MI); 3210 case G_SDIVREM: 3211 case G_UDIVREM: 3212 return lowerDIVREM(MI); 3213 case G_FSHL: 3214 case G_FSHR: 3215 return lowerFunnelShift(MI); 3216 } 3217 } 3218 3219 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3220 Align MinAlign) const { 3221 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3222 // datalayout for the preferred alignment. Also there should be a target hook 3223 // for this to allow targets to reduce the alignment and ignore the 3224 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3225 // the type. 3226 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3227 } 3228 3229 MachineInstrBuilder 3230 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3231 MachinePointerInfo &PtrInfo) { 3232 MachineFunction &MF = MIRBuilder.getMF(); 3233 const DataLayout &DL = MIRBuilder.getDataLayout(); 3234 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3235 3236 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3237 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3238 3239 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3240 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3241 } 3242 3243 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3244 LLT VecTy) { 3245 int64_t IdxVal; 3246 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3247 return IdxReg; 3248 3249 LLT IdxTy = B.getMRI()->getType(IdxReg); 3250 unsigned NElts = VecTy.getNumElements(); 3251 if (isPowerOf2_32(NElts)) { 3252 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3253 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3254 } 3255 3256 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3257 .getReg(0); 3258 } 3259 3260 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3261 Register Index) { 3262 LLT EltTy = VecTy.getElementType(); 3263 3264 // Calculate the element offset and add it to the pointer. 3265 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3266 assert(EltSize * 8 == EltTy.getSizeInBits() && 3267 "Converting bits to bytes lost precision"); 3268 3269 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3270 3271 LLT IdxTy = MRI.getType(Index); 3272 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3273 MIRBuilder.buildConstant(IdxTy, EltSize)); 3274 3275 LLT PtrTy = MRI.getType(VecPtr); 3276 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3277 } 3278 3279 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3280 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3281 Register DstReg = MI.getOperand(0).getReg(); 3282 LLT DstTy = MRI.getType(DstReg); 3283 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3284 3285 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3286 3287 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3288 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3289 3290 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3291 MI.eraseFromParent(); 3292 return Legalized; 3293 } 3294 3295 // Handle splitting vector operations which need to have the same number of 3296 // elements in each type index, but each type index may have a different element 3297 // type. 3298 // 3299 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3300 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3301 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3302 // 3303 // Also handles some irregular breakdown cases, e.g. 3304 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3305 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3306 // s64 = G_SHL s64, s32 3307 LegalizerHelper::LegalizeResult 3308 LegalizerHelper::fewerElementsVectorMultiEltType( 3309 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3310 if (TypeIdx != 0) 3311 return UnableToLegalize; 3312 3313 const LLT NarrowTy0 = NarrowTyArg; 3314 const unsigned NewNumElts = 3315 NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1; 3316 3317 const Register DstReg = MI.getOperand(0).getReg(); 3318 LLT DstTy = MRI.getType(DstReg); 3319 LLT LeftoverTy0; 3320 3321 // All of the operands need to have the same number of elements, so if we can 3322 // determine a type breakdown for the result type, we can for all of the 3323 // source types. 3324 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3325 if (NumParts < 0) 3326 return UnableToLegalize; 3327 3328 SmallVector<MachineInstrBuilder, 4> NewInsts; 3329 3330 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3331 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3332 3333 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3334 Register SrcReg = MI.getOperand(I).getReg(); 3335 LLT SrcTyI = MRI.getType(SrcReg); 3336 LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType()); 3337 LLT LeftoverTyI; 3338 3339 // Split this operand into the requested typed registers, and any leftover 3340 // required to reproduce the original type. 3341 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3342 LeftoverRegs)) 3343 return UnableToLegalize; 3344 3345 if (I == 1) { 3346 // For the first operand, create an instruction for each part and setup 3347 // the result. 3348 for (Register PartReg : PartRegs) { 3349 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3350 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3351 .addDef(PartDstReg) 3352 .addUse(PartReg)); 3353 DstRegs.push_back(PartDstReg); 3354 } 3355 3356 for (Register LeftoverReg : LeftoverRegs) { 3357 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3358 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3359 .addDef(PartDstReg) 3360 .addUse(LeftoverReg)); 3361 LeftoverDstRegs.push_back(PartDstReg); 3362 } 3363 } else { 3364 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3365 3366 // Add the newly created operand splits to the existing instructions. The 3367 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3368 // pieces. 3369 unsigned InstCount = 0; 3370 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3371 NewInsts[InstCount++].addUse(PartRegs[J]); 3372 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3373 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3374 } 3375 3376 PartRegs.clear(); 3377 LeftoverRegs.clear(); 3378 } 3379 3380 // Insert the newly built operations and rebuild the result register. 3381 for (auto &MIB : NewInsts) 3382 MIRBuilder.insertInstr(MIB); 3383 3384 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3385 3386 MI.eraseFromParent(); 3387 return Legalized; 3388 } 3389 3390 LegalizerHelper::LegalizeResult 3391 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3392 LLT NarrowTy) { 3393 if (TypeIdx != 0) 3394 return UnableToLegalize; 3395 3396 Register DstReg = MI.getOperand(0).getReg(); 3397 Register SrcReg = MI.getOperand(1).getReg(); 3398 LLT DstTy = MRI.getType(DstReg); 3399 LLT SrcTy = MRI.getType(SrcReg); 3400 3401 LLT NarrowTy0 = NarrowTy; 3402 LLT NarrowTy1; 3403 unsigned NumParts; 3404 3405 if (NarrowTy.isVector()) { 3406 // Uneven breakdown not handled. 3407 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3408 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3409 return UnableToLegalize; 3410 3411 NarrowTy1 = LLT::vector(NarrowTy.getNumElements(), SrcTy.getElementType()); 3412 } else { 3413 NumParts = DstTy.getNumElements(); 3414 NarrowTy1 = SrcTy.getElementType(); 3415 } 3416 3417 SmallVector<Register, 4> SrcRegs, DstRegs; 3418 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3419 3420 for (unsigned I = 0; I < NumParts; ++I) { 3421 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3422 MachineInstr *NewInst = 3423 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3424 3425 NewInst->setFlags(MI.getFlags()); 3426 DstRegs.push_back(DstReg); 3427 } 3428 3429 if (NarrowTy.isVector()) 3430 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3431 else 3432 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3433 3434 MI.eraseFromParent(); 3435 return Legalized; 3436 } 3437 3438 LegalizerHelper::LegalizeResult 3439 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3440 LLT NarrowTy) { 3441 Register DstReg = MI.getOperand(0).getReg(); 3442 Register Src0Reg = MI.getOperand(2).getReg(); 3443 LLT DstTy = MRI.getType(DstReg); 3444 LLT SrcTy = MRI.getType(Src0Reg); 3445 3446 unsigned NumParts; 3447 LLT NarrowTy0, NarrowTy1; 3448 3449 if (TypeIdx == 0) { 3450 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3451 unsigned OldElts = DstTy.getNumElements(); 3452 3453 NarrowTy0 = NarrowTy; 3454 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3455 NarrowTy1 = NarrowTy.isVector() ? 3456 LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) : 3457 SrcTy.getElementType(); 3458 3459 } else { 3460 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3461 unsigned OldElts = SrcTy.getNumElements(); 3462 3463 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3464 NarrowTy.getNumElements(); 3465 NarrowTy0 = LLT::vector(NarrowTy.getNumElements(), 3466 DstTy.getScalarSizeInBits()); 3467 NarrowTy1 = NarrowTy; 3468 } 3469 3470 // FIXME: Don't know how to handle the situation where the small vectors 3471 // aren't all the same size yet. 3472 if (NarrowTy1.isVector() && 3473 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3474 return UnableToLegalize; 3475 3476 CmpInst::Predicate Pred 3477 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3478 3479 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3480 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3481 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3482 3483 for (unsigned I = 0; I < NumParts; ++I) { 3484 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3485 DstRegs.push_back(DstReg); 3486 3487 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3488 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3489 else { 3490 MachineInstr *NewCmp 3491 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3492 NewCmp->setFlags(MI.getFlags()); 3493 } 3494 } 3495 3496 if (NarrowTy1.isVector()) 3497 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3498 else 3499 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3500 3501 MI.eraseFromParent(); 3502 return Legalized; 3503 } 3504 3505 LegalizerHelper::LegalizeResult 3506 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3507 LLT NarrowTy) { 3508 Register DstReg = MI.getOperand(0).getReg(); 3509 Register CondReg = MI.getOperand(1).getReg(); 3510 3511 unsigned NumParts = 0; 3512 LLT NarrowTy0, NarrowTy1; 3513 3514 LLT DstTy = MRI.getType(DstReg); 3515 LLT CondTy = MRI.getType(CondReg); 3516 unsigned Size = DstTy.getSizeInBits(); 3517 3518 assert(TypeIdx == 0 || CondTy.isVector()); 3519 3520 if (TypeIdx == 0) { 3521 NarrowTy0 = NarrowTy; 3522 NarrowTy1 = CondTy; 3523 3524 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3525 // FIXME: Don't know how to handle the situation where the small vectors 3526 // aren't all the same size yet. 3527 if (Size % NarrowSize != 0) 3528 return UnableToLegalize; 3529 3530 NumParts = Size / NarrowSize; 3531 3532 // Need to break down the condition type 3533 if (CondTy.isVector()) { 3534 if (CondTy.getNumElements() == NumParts) 3535 NarrowTy1 = CondTy.getElementType(); 3536 else 3537 NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts, 3538 CondTy.getScalarSizeInBits()); 3539 } 3540 } else { 3541 NumParts = CondTy.getNumElements(); 3542 if (NarrowTy.isVector()) { 3543 // TODO: Handle uneven breakdown. 3544 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3545 return UnableToLegalize; 3546 3547 return UnableToLegalize; 3548 } else { 3549 NarrowTy0 = DstTy.getElementType(); 3550 NarrowTy1 = NarrowTy; 3551 } 3552 } 3553 3554 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3555 if (CondTy.isVector()) 3556 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3557 3558 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3559 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3560 3561 for (unsigned i = 0; i < NumParts; ++i) { 3562 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3563 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3564 Src1Regs[i], Src2Regs[i]); 3565 DstRegs.push_back(DstReg); 3566 } 3567 3568 if (NarrowTy0.isVector()) 3569 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3570 else 3571 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3572 3573 MI.eraseFromParent(); 3574 return Legalized; 3575 } 3576 3577 LegalizerHelper::LegalizeResult 3578 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3579 LLT NarrowTy) { 3580 const Register DstReg = MI.getOperand(0).getReg(); 3581 LLT PhiTy = MRI.getType(DstReg); 3582 LLT LeftoverTy; 3583 3584 // All of the operands need to have the same number of elements, so if we can 3585 // determine a type breakdown for the result type, we can for all of the 3586 // source types. 3587 int NumParts, NumLeftover; 3588 std::tie(NumParts, NumLeftover) 3589 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3590 if (NumParts < 0) 3591 return UnableToLegalize; 3592 3593 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3594 SmallVector<MachineInstrBuilder, 4> NewInsts; 3595 3596 const int TotalNumParts = NumParts + NumLeftover; 3597 3598 // Insert the new phis in the result block first. 3599 for (int I = 0; I != TotalNumParts; ++I) { 3600 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3601 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3602 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3603 .addDef(PartDstReg)); 3604 if (I < NumParts) 3605 DstRegs.push_back(PartDstReg); 3606 else 3607 LeftoverDstRegs.push_back(PartDstReg); 3608 } 3609 3610 MachineBasicBlock *MBB = MI.getParent(); 3611 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3612 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3613 3614 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3615 3616 // Insert code to extract the incoming values in each predecessor block. 3617 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3618 PartRegs.clear(); 3619 LeftoverRegs.clear(); 3620 3621 Register SrcReg = MI.getOperand(I).getReg(); 3622 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3623 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3624 3625 LLT Unused; 3626 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3627 LeftoverRegs)) 3628 return UnableToLegalize; 3629 3630 // Add the newly created operand splits to the existing instructions. The 3631 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3632 // pieces. 3633 for (int J = 0; J != TotalNumParts; ++J) { 3634 MachineInstrBuilder MIB = NewInsts[J]; 3635 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3636 MIB.addMBB(&OpMBB); 3637 } 3638 } 3639 3640 MI.eraseFromParent(); 3641 return Legalized; 3642 } 3643 3644 LegalizerHelper::LegalizeResult 3645 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3646 unsigned TypeIdx, 3647 LLT NarrowTy) { 3648 if (TypeIdx != 1) 3649 return UnableToLegalize; 3650 3651 const int NumDst = MI.getNumOperands() - 1; 3652 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3653 LLT SrcTy = MRI.getType(SrcReg); 3654 3655 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3656 3657 // TODO: Create sequence of extracts. 3658 if (DstTy == NarrowTy) 3659 return UnableToLegalize; 3660 3661 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3662 if (DstTy == GCDTy) { 3663 // This would just be a copy of the same unmerge. 3664 // TODO: Create extracts, pad with undef and create intermediate merges. 3665 return UnableToLegalize; 3666 } 3667 3668 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3669 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3670 const int PartsPerUnmerge = NumDst / NumUnmerge; 3671 3672 for (int I = 0; I != NumUnmerge; ++I) { 3673 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3674 3675 for (int J = 0; J != PartsPerUnmerge; ++J) 3676 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3677 MIB.addUse(Unmerge.getReg(I)); 3678 } 3679 3680 MI.eraseFromParent(); 3681 return Legalized; 3682 } 3683 3684 LegalizerHelper::LegalizeResult 3685 LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx, 3686 LLT NarrowTy) { 3687 Register Result = MI.getOperand(0).getReg(); 3688 Register Overflow = MI.getOperand(1).getReg(); 3689 Register LHS = MI.getOperand(2).getReg(); 3690 Register RHS = MI.getOperand(3).getReg(); 3691 3692 LLT SrcTy = MRI.getType(LHS); 3693 if (!SrcTy.isVector()) 3694 return UnableToLegalize; 3695 3696 LLT ElementType = SrcTy.getElementType(); 3697 LLT OverflowElementTy = MRI.getType(Overflow).getElementType(); 3698 const int NumResult = SrcTy.getNumElements(); 3699 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3700 3701 // Unmerge the operands to smaller parts of GCD type. 3702 auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS); 3703 auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS); 3704 3705 const int NumOps = UnmergeLHS->getNumOperands() - 1; 3706 const int PartsPerUnmerge = NumResult / NumOps; 3707 LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy); 3708 LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType); 3709 3710 // Perform the operation over unmerged parts. 3711 SmallVector<Register, 8> ResultParts; 3712 SmallVector<Register, 8> OverflowParts; 3713 for (int I = 0; I != NumOps; ++I) { 3714 Register Operand1 = UnmergeLHS->getOperand(I).getReg(); 3715 Register Operand2 = UnmergeRHS->getOperand(I).getReg(); 3716 auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy}, 3717 {Operand1, Operand2}); 3718 ResultParts.push_back(PartMul->getOperand(0).getReg()); 3719 OverflowParts.push_back(PartMul->getOperand(1).getReg()); 3720 } 3721 3722 LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts); 3723 LLT OverflowLCMTy = 3724 LLT::scalarOrVector(ResultLCMTy.getNumElements(), OverflowElementTy); 3725 3726 // Recombine the pieces to the original result and overflow registers. 3727 buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts); 3728 buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts); 3729 MI.eraseFromParent(); 3730 return Legalized; 3731 } 3732 3733 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3734 // a vector 3735 // 3736 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3737 // undef as necessary. 3738 // 3739 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3740 // -> <2 x s16> 3741 // 3742 // %4:_(s16) = G_IMPLICIT_DEF 3743 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3744 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3745 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3746 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3747 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3748 LegalizerHelper::LegalizeResult 3749 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3750 LLT NarrowTy) { 3751 Register DstReg = MI.getOperand(0).getReg(); 3752 LLT DstTy = MRI.getType(DstReg); 3753 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3754 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3755 3756 // Break into a common type 3757 SmallVector<Register, 16> Parts; 3758 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3759 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3760 3761 // Build the requested new merge, padding with undef. 3762 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3763 TargetOpcode::G_ANYEXT); 3764 3765 // Pack into the original result register. 3766 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3767 3768 MI.eraseFromParent(); 3769 return Legalized; 3770 } 3771 3772 LegalizerHelper::LegalizeResult 3773 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3774 unsigned TypeIdx, 3775 LLT NarrowVecTy) { 3776 Register DstReg = MI.getOperand(0).getReg(); 3777 Register SrcVec = MI.getOperand(1).getReg(); 3778 Register InsertVal; 3779 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3780 3781 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3782 if (IsInsert) 3783 InsertVal = MI.getOperand(2).getReg(); 3784 3785 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3786 3787 // TODO: Handle total scalarization case. 3788 if (!NarrowVecTy.isVector()) 3789 return UnableToLegalize; 3790 3791 LLT VecTy = MRI.getType(SrcVec); 3792 3793 // If the index is a constant, we can really break this down as you would 3794 // expect, and index into the target size pieces. 3795 int64_t IdxVal; 3796 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 3797 // Avoid out of bounds indexing the pieces. 3798 if (IdxVal >= VecTy.getNumElements()) { 3799 MIRBuilder.buildUndef(DstReg); 3800 MI.eraseFromParent(); 3801 return Legalized; 3802 } 3803 3804 SmallVector<Register, 8> VecParts; 3805 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3806 3807 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3808 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3809 TargetOpcode::G_ANYEXT); 3810 3811 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3812 3813 LLT IdxTy = MRI.getType(Idx); 3814 int64_t PartIdx = IdxVal / NewNumElts; 3815 auto NewIdx = 3816 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3817 3818 if (IsInsert) { 3819 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3820 3821 // Use the adjusted index to insert into one of the subvectors. 3822 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3823 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3824 VecParts[PartIdx] = InsertPart.getReg(0); 3825 3826 // Recombine the inserted subvector with the others to reform the result 3827 // vector. 3828 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3829 } else { 3830 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3831 } 3832 3833 MI.eraseFromParent(); 3834 return Legalized; 3835 } 3836 3837 // With a variable index, we can't perform the operation in a smaller type, so 3838 // we're forced to expand this. 3839 // 3840 // TODO: We could emit a chain of compare/select to figure out which piece to 3841 // index. 3842 return lowerExtractInsertVectorElt(MI); 3843 } 3844 3845 LegalizerHelper::LegalizeResult 3846 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, 3847 LLT NarrowTy) { 3848 // FIXME: Don't know how to handle secondary types yet. 3849 if (TypeIdx != 0) 3850 return UnableToLegalize; 3851 3852 MachineMemOperand *MMO = *MI.memoperands_begin(); 3853 3854 // This implementation doesn't work for atomics. Give up instead of doing 3855 // something invalid. 3856 if (MMO->getOrdering() != AtomicOrdering::NotAtomic || 3857 MMO->getFailureOrdering() != AtomicOrdering::NotAtomic) 3858 return UnableToLegalize; 3859 3860 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; 3861 Register ValReg = MI.getOperand(0).getReg(); 3862 Register AddrReg = MI.getOperand(1).getReg(); 3863 LLT ValTy = MRI.getType(ValReg); 3864 3865 // FIXME: Do we need a distinct NarrowMemory legalize action? 3866 if (ValTy.getSizeInBits() != 8 * MMO->getSize()) { 3867 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3868 return UnableToLegalize; 3869 } 3870 3871 int NumParts = -1; 3872 int NumLeftover = -1; 3873 LLT LeftoverTy; 3874 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3875 if (IsLoad) { 3876 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3877 } else { 3878 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3879 NarrowLeftoverRegs)) { 3880 NumParts = NarrowRegs.size(); 3881 NumLeftover = NarrowLeftoverRegs.size(); 3882 } 3883 } 3884 3885 if (NumParts == -1) 3886 return UnableToLegalize; 3887 3888 LLT PtrTy = MRI.getType(AddrReg); 3889 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 3890 3891 unsigned TotalSize = ValTy.getSizeInBits(); 3892 3893 // Split the load/store into PartTy sized pieces starting at Offset. If this 3894 // is a load, return the new registers in ValRegs. For a store, each elements 3895 // of ValRegs should be PartTy. Returns the next offset that needs to be 3896 // handled. 3897 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3898 unsigned Offset) -> unsigned { 3899 MachineFunction &MF = MIRBuilder.getMF(); 3900 unsigned PartSize = PartTy.getSizeInBits(); 3901 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 3902 Offset += PartSize, ++Idx) { 3903 unsigned ByteSize = PartSize / 8; 3904 unsigned ByteOffset = Offset / 8; 3905 Register NewAddrReg; 3906 3907 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 3908 3909 MachineMemOperand *NewMMO = 3910 MF.getMachineMemOperand(MMO, ByteOffset, ByteSize); 3911 3912 if (IsLoad) { 3913 Register Dst = MRI.createGenericVirtualRegister(PartTy); 3914 ValRegs.push_back(Dst); 3915 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 3916 } else { 3917 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 3918 } 3919 } 3920 3921 return Offset; 3922 }; 3923 3924 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 3925 3926 // Handle the rest of the register if this isn't an even type breakdown. 3927 if (LeftoverTy.isValid()) 3928 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 3929 3930 if (IsLoad) { 3931 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 3932 LeftoverTy, NarrowLeftoverRegs); 3933 } 3934 3935 MI.eraseFromParent(); 3936 return Legalized; 3937 } 3938 3939 LegalizerHelper::LegalizeResult 3940 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 3941 LLT NarrowTy) { 3942 assert(TypeIdx == 0 && "only one type index expected"); 3943 3944 const unsigned Opc = MI.getOpcode(); 3945 const int NumOps = MI.getNumOperands() - 1; 3946 const Register DstReg = MI.getOperand(0).getReg(); 3947 const unsigned Flags = MI.getFlags(); 3948 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 3949 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 3950 3951 assert(NumOps <= 3 && "expected instruction with 1 result and 1-3 sources"); 3952 3953 // First of all check whether we are narrowing (changing the element type) 3954 // or reducing the vector elements 3955 const LLT DstTy = MRI.getType(DstReg); 3956 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 3957 3958 SmallVector<Register, 8> ExtractedRegs[3]; 3959 SmallVector<Register, 8> Parts; 3960 3961 unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3962 3963 // Break down all the sources into NarrowTy pieces we can operate on. This may 3964 // involve creating merges to a wider type, padded with undef. 3965 for (int I = 0; I != NumOps; ++I) { 3966 Register SrcReg = MI.getOperand(I + 1).getReg(); 3967 LLT SrcTy = MRI.getType(SrcReg); 3968 3969 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 3970 // For fewerElements, this is a smaller vector with the same element type. 3971 LLT OpNarrowTy; 3972 if (IsNarrow) { 3973 OpNarrowTy = NarrowScalarTy; 3974 3975 // In case of narrowing, we need to cast vectors to scalars for this to 3976 // work properly 3977 // FIXME: Can we do without the bitcast here if we're narrowing? 3978 if (SrcTy.isVector()) { 3979 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 3980 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 3981 } 3982 } else { 3983 OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType()); 3984 } 3985 3986 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 3987 3988 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 3989 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 3990 TargetOpcode::G_ANYEXT); 3991 } 3992 3993 SmallVector<Register, 8> ResultRegs; 3994 3995 // Input operands for each sub-instruction. 3996 SmallVector<SrcOp, 4> InputRegs(NumOps, Register()); 3997 3998 int NumParts = ExtractedRegs[0].size(); 3999 const unsigned DstSize = DstTy.getSizeInBits(); 4000 const LLT DstScalarTy = LLT::scalar(DstSize); 4001 4002 // Narrowing needs to use scalar types 4003 LLT DstLCMTy, NarrowDstTy; 4004 if (IsNarrow) { 4005 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 4006 NarrowDstTy = NarrowScalarTy; 4007 } else { 4008 DstLCMTy = getLCMType(DstTy, NarrowTy); 4009 NarrowDstTy = NarrowTy; 4010 } 4011 4012 // We widened the source registers to satisfy merge/unmerge size 4013 // constraints. We'll have some extra fully undef parts. 4014 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 4015 4016 for (int I = 0; I != NumRealParts; ++I) { 4017 // Emit this instruction on each of the split pieces. 4018 for (int J = 0; J != NumOps; ++J) 4019 InputRegs[J] = ExtractedRegs[J][I]; 4020 4021 auto Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 4022 ResultRegs.push_back(Inst.getReg(0)); 4023 } 4024 4025 // Fill out the widened result with undef instead of creating instructions 4026 // with undef inputs. 4027 int NumUndefParts = NumParts - NumRealParts; 4028 if (NumUndefParts != 0) 4029 ResultRegs.append(NumUndefParts, 4030 MIRBuilder.buildUndef(NarrowDstTy).getReg(0)); 4031 4032 // Extract the possibly padded result. Use a scratch register if we need to do 4033 // a final bitcast, otherwise use the original result register. 4034 Register MergeDstReg; 4035 if (IsNarrow && DstTy.isVector()) 4036 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 4037 else 4038 MergeDstReg = DstReg; 4039 4040 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs); 4041 4042 // Recast to vector if we narrowed a vector 4043 if (IsNarrow && DstTy.isVector()) 4044 MIRBuilder.buildBitcast(DstReg, MergeDstReg); 4045 4046 MI.eraseFromParent(); 4047 return Legalized; 4048 } 4049 4050 LegalizerHelper::LegalizeResult 4051 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 4052 LLT NarrowTy) { 4053 Register DstReg = MI.getOperand(0).getReg(); 4054 Register SrcReg = MI.getOperand(1).getReg(); 4055 int64_t Imm = MI.getOperand(2).getImm(); 4056 4057 LLT DstTy = MRI.getType(DstReg); 4058 4059 SmallVector<Register, 8> Parts; 4060 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4061 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4062 4063 for (Register &R : Parts) 4064 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4065 4066 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4067 4068 MI.eraseFromParent(); 4069 return Legalized; 4070 } 4071 4072 LegalizerHelper::LegalizeResult 4073 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4074 LLT NarrowTy) { 4075 using namespace TargetOpcode; 4076 4077 switch (MI.getOpcode()) { 4078 case G_IMPLICIT_DEF: 4079 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4080 case G_TRUNC: 4081 case G_AND: 4082 case G_OR: 4083 case G_XOR: 4084 case G_ADD: 4085 case G_SUB: 4086 case G_MUL: 4087 case G_PTR_ADD: 4088 case G_SMULH: 4089 case G_UMULH: 4090 case G_FADD: 4091 case G_FMUL: 4092 case G_FSUB: 4093 case G_FNEG: 4094 case G_FABS: 4095 case G_FCANONICALIZE: 4096 case G_FDIV: 4097 case G_FREM: 4098 case G_FMA: 4099 case G_FMAD: 4100 case G_FPOW: 4101 case G_FEXP: 4102 case G_FEXP2: 4103 case G_FLOG: 4104 case G_FLOG2: 4105 case G_FLOG10: 4106 case G_FNEARBYINT: 4107 case G_FCEIL: 4108 case G_FFLOOR: 4109 case G_FRINT: 4110 case G_INTRINSIC_ROUND: 4111 case G_INTRINSIC_ROUNDEVEN: 4112 case G_INTRINSIC_TRUNC: 4113 case G_FCOS: 4114 case G_FSIN: 4115 case G_FSQRT: 4116 case G_BSWAP: 4117 case G_BITREVERSE: 4118 case G_SDIV: 4119 case G_UDIV: 4120 case G_SREM: 4121 case G_UREM: 4122 case G_SMIN: 4123 case G_SMAX: 4124 case G_UMIN: 4125 case G_UMAX: 4126 case G_FMINNUM: 4127 case G_FMAXNUM: 4128 case G_FMINNUM_IEEE: 4129 case G_FMAXNUM_IEEE: 4130 case G_FMINIMUM: 4131 case G_FMAXIMUM: 4132 case G_FSHL: 4133 case G_FSHR: 4134 case G_FREEZE: 4135 case G_SADDSAT: 4136 case G_SSUBSAT: 4137 case G_UADDSAT: 4138 case G_USUBSAT: 4139 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4140 case G_UMULO: 4141 case G_SMULO: 4142 return fewerElementsVectorMulo(MI, TypeIdx, NarrowTy); 4143 case G_SHL: 4144 case G_LSHR: 4145 case G_ASHR: 4146 case G_SSHLSAT: 4147 case G_USHLSAT: 4148 case G_CTLZ: 4149 case G_CTLZ_ZERO_UNDEF: 4150 case G_CTTZ: 4151 case G_CTTZ_ZERO_UNDEF: 4152 case G_CTPOP: 4153 case G_FCOPYSIGN: 4154 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4155 case G_ZEXT: 4156 case G_SEXT: 4157 case G_ANYEXT: 4158 case G_FPEXT: 4159 case G_FPTRUNC: 4160 case G_SITOFP: 4161 case G_UITOFP: 4162 case G_FPTOSI: 4163 case G_FPTOUI: 4164 case G_INTTOPTR: 4165 case G_PTRTOINT: 4166 case G_ADDRSPACE_CAST: 4167 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4168 case G_ICMP: 4169 case G_FCMP: 4170 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4171 case G_SELECT: 4172 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4173 case G_PHI: 4174 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4175 case G_UNMERGE_VALUES: 4176 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4177 case G_BUILD_VECTOR: 4178 assert(TypeIdx == 0 && "not a vector type index"); 4179 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4180 case G_CONCAT_VECTORS: 4181 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4182 return UnableToLegalize; 4183 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4184 case G_EXTRACT_VECTOR_ELT: 4185 case G_INSERT_VECTOR_ELT: 4186 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4187 case G_LOAD: 4188 case G_STORE: 4189 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 4190 case G_SEXT_INREG: 4191 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4192 default: 4193 return UnableToLegalize; 4194 } 4195 } 4196 4197 LegalizerHelper::LegalizeResult 4198 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4199 const LLT HalfTy, const LLT AmtTy) { 4200 4201 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4202 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4203 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4204 4205 if (Amt.isNullValue()) { 4206 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4207 MI.eraseFromParent(); 4208 return Legalized; 4209 } 4210 4211 LLT NVT = HalfTy; 4212 unsigned NVTBits = HalfTy.getSizeInBits(); 4213 unsigned VTBits = 2 * NVTBits; 4214 4215 SrcOp Lo(Register(0)), Hi(Register(0)); 4216 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4217 if (Amt.ugt(VTBits)) { 4218 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4219 } else if (Amt.ugt(NVTBits)) { 4220 Lo = MIRBuilder.buildConstant(NVT, 0); 4221 Hi = MIRBuilder.buildShl(NVT, InL, 4222 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4223 } else if (Amt == NVTBits) { 4224 Lo = MIRBuilder.buildConstant(NVT, 0); 4225 Hi = InL; 4226 } else { 4227 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4228 auto OrLHS = 4229 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4230 auto OrRHS = MIRBuilder.buildLShr( 4231 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4232 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4233 } 4234 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4235 if (Amt.ugt(VTBits)) { 4236 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4237 } else if (Amt.ugt(NVTBits)) { 4238 Lo = MIRBuilder.buildLShr(NVT, InH, 4239 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4240 Hi = MIRBuilder.buildConstant(NVT, 0); 4241 } else if (Amt == NVTBits) { 4242 Lo = InH; 4243 Hi = MIRBuilder.buildConstant(NVT, 0); 4244 } else { 4245 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4246 4247 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4248 auto OrRHS = MIRBuilder.buildShl( 4249 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4250 4251 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4252 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4253 } 4254 } else { 4255 if (Amt.ugt(VTBits)) { 4256 Hi = Lo = MIRBuilder.buildAShr( 4257 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4258 } else if (Amt.ugt(NVTBits)) { 4259 Lo = MIRBuilder.buildAShr(NVT, InH, 4260 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4261 Hi = MIRBuilder.buildAShr(NVT, InH, 4262 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4263 } else if (Amt == NVTBits) { 4264 Lo = InH; 4265 Hi = MIRBuilder.buildAShr(NVT, InH, 4266 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4267 } else { 4268 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4269 4270 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4271 auto OrRHS = MIRBuilder.buildShl( 4272 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4273 4274 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4275 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4276 } 4277 } 4278 4279 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4280 MI.eraseFromParent(); 4281 4282 return Legalized; 4283 } 4284 4285 // TODO: Optimize if constant shift amount. 4286 LegalizerHelper::LegalizeResult 4287 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4288 LLT RequestedTy) { 4289 if (TypeIdx == 1) { 4290 Observer.changingInstr(MI); 4291 narrowScalarSrc(MI, RequestedTy, 2); 4292 Observer.changedInstr(MI); 4293 return Legalized; 4294 } 4295 4296 Register DstReg = MI.getOperand(0).getReg(); 4297 LLT DstTy = MRI.getType(DstReg); 4298 if (DstTy.isVector()) 4299 return UnableToLegalize; 4300 4301 Register Amt = MI.getOperand(2).getReg(); 4302 LLT ShiftAmtTy = MRI.getType(Amt); 4303 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4304 if (DstEltSize % 2 != 0) 4305 return UnableToLegalize; 4306 4307 // Ignore the input type. We can only go to exactly half the size of the 4308 // input. If that isn't small enough, the resulting pieces will be further 4309 // legalized. 4310 const unsigned NewBitSize = DstEltSize / 2; 4311 const LLT HalfTy = LLT::scalar(NewBitSize); 4312 const LLT CondTy = LLT::scalar(1); 4313 4314 if (const MachineInstr *KShiftAmt = 4315 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4316 return narrowScalarShiftByConstant( 4317 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4318 } 4319 4320 // TODO: Expand with known bits. 4321 4322 // Handle the fully general expansion by an unknown amount. 4323 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4324 4325 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4326 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4327 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4328 4329 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4330 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4331 4332 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4333 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4334 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4335 4336 Register ResultRegs[2]; 4337 switch (MI.getOpcode()) { 4338 case TargetOpcode::G_SHL: { 4339 // Short: ShAmt < NewBitSize 4340 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4341 4342 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4343 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4344 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4345 4346 // Long: ShAmt >= NewBitSize 4347 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4348 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4349 4350 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4351 auto Hi = MIRBuilder.buildSelect( 4352 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4353 4354 ResultRegs[0] = Lo.getReg(0); 4355 ResultRegs[1] = Hi.getReg(0); 4356 break; 4357 } 4358 case TargetOpcode::G_LSHR: 4359 case TargetOpcode::G_ASHR: { 4360 // Short: ShAmt < NewBitSize 4361 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4362 4363 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4364 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4365 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4366 4367 // Long: ShAmt >= NewBitSize 4368 MachineInstrBuilder HiL; 4369 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4370 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4371 } else { 4372 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4373 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4374 } 4375 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4376 {InH, AmtExcess}); // Lo from Hi part. 4377 4378 auto Lo = MIRBuilder.buildSelect( 4379 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4380 4381 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4382 4383 ResultRegs[0] = Lo.getReg(0); 4384 ResultRegs[1] = Hi.getReg(0); 4385 break; 4386 } 4387 default: 4388 llvm_unreachable("not a shift"); 4389 } 4390 4391 MIRBuilder.buildMerge(DstReg, ResultRegs); 4392 MI.eraseFromParent(); 4393 return Legalized; 4394 } 4395 4396 LegalizerHelper::LegalizeResult 4397 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4398 LLT MoreTy) { 4399 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4400 4401 Observer.changingInstr(MI); 4402 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4403 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4404 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4405 moreElementsVectorSrc(MI, MoreTy, I); 4406 } 4407 4408 MachineBasicBlock &MBB = *MI.getParent(); 4409 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4410 moreElementsVectorDst(MI, MoreTy, 0); 4411 Observer.changedInstr(MI); 4412 return Legalized; 4413 } 4414 4415 LegalizerHelper::LegalizeResult 4416 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4417 LLT MoreTy) { 4418 unsigned Opc = MI.getOpcode(); 4419 switch (Opc) { 4420 case TargetOpcode::G_IMPLICIT_DEF: 4421 case TargetOpcode::G_LOAD: { 4422 if (TypeIdx != 0) 4423 return UnableToLegalize; 4424 Observer.changingInstr(MI); 4425 moreElementsVectorDst(MI, MoreTy, 0); 4426 Observer.changedInstr(MI); 4427 return Legalized; 4428 } 4429 case TargetOpcode::G_STORE: 4430 if (TypeIdx != 0) 4431 return UnableToLegalize; 4432 Observer.changingInstr(MI); 4433 moreElementsVectorSrc(MI, MoreTy, 0); 4434 Observer.changedInstr(MI); 4435 return Legalized; 4436 case TargetOpcode::G_AND: 4437 case TargetOpcode::G_OR: 4438 case TargetOpcode::G_XOR: 4439 case TargetOpcode::G_SMIN: 4440 case TargetOpcode::G_SMAX: 4441 case TargetOpcode::G_UMIN: 4442 case TargetOpcode::G_UMAX: 4443 case TargetOpcode::G_FMINNUM: 4444 case TargetOpcode::G_FMAXNUM: 4445 case TargetOpcode::G_FMINNUM_IEEE: 4446 case TargetOpcode::G_FMAXNUM_IEEE: 4447 case TargetOpcode::G_FMINIMUM: 4448 case TargetOpcode::G_FMAXIMUM: { 4449 Observer.changingInstr(MI); 4450 moreElementsVectorSrc(MI, MoreTy, 1); 4451 moreElementsVectorSrc(MI, MoreTy, 2); 4452 moreElementsVectorDst(MI, MoreTy, 0); 4453 Observer.changedInstr(MI); 4454 return Legalized; 4455 } 4456 case TargetOpcode::G_EXTRACT: 4457 if (TypeIdx != 1) 4458 return UnableToLegalize; 4459 Observer.changingInstr(MI); 4460 moreElementsVectorSrc(MI, MoreTy, 1); 4461 Observer.changedInstr(MI); 4462 return Legalized; 4463 case TargetOpcode::G_INSERT: 4464 case TargetOpcode::G_FREEZE: 4465 if (TypeIdx != 0) 4466 return UnableToLegalize; 4467 Observer.changingInstr(MI); 4468 moreElementsVectorSrc(MI, MoreTy, 1); 4469 moreElementsVectorDst(MI, MoreTy, 0); 4470 Observer.changedInstr(MI); 4471 return Legalized; 4472 case TargetOpcode::G_SELECT: 4473 if (TypeIdx != 0) 4474 return UnableToLegalize; 4475 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4476 return UnableToLegalize; 4477 4478 Observer.changingInstr(MI); 4479 moreElementsVectorSrc(MI, MoreTy, 2); 4480 moreElementsVectorSrc(MI, MoreTy, 3); 4481 moreElementsVectorDst(MI, MoreTy, 0); 4482 Observer.changedInstr(MI); 4483 return Legalized; 4484 case TargetOpcode::G_UNMERGE_VALUES: { 4485 if (TypeIdx != 1) 4486 return UnableToLegalize; 4487 4488 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4489 int NumDst = MI.getNumOperands() - 1; 4490 moreElementsVectorSrc(MI, MoreTy, NumDst); 4491 4492 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4493 for (int I = 0; I != NumDst; ++I) 4494 MIB.addDef(MI.getOperand(I).getReg()); 4495 4496 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4497 for (int I = NumDst; I != NewNumDst; ++I) 4498 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4499 4500 MIB.addUse(MI.getOperand(NumDst).getReg()); 4501 MI.eraseFromParent(); 4502 return Legalized; 4503 } 4504 case TargetOpcode::G_PHI: 4505 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4506 default: 4507 return UnableToLegalize; 4508 } 4509 } 4510 4511 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4512 ArrayRef<Register> Src1Regs, 4513 ArrayRef<Register> Src2Regs, 4514 LLT NarrowTy) { 4515 MachineIRBuilder &B = MIRBuilder; 4516 unsigned SrcParts = Src1Regs.size(); 4517 unsigned DstParts = DstRegs.size(); 4518 4519 unsigned DstIdx = 0; // Low bits of the result. 4520 Register FactorSum = 4521 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4522 DstRegs[DstIdx] = FactorSum; 4523 4524 unsigned CarrySumPrevDstIdx; 4525 SmallVector<Register, 4> Factors; 4526 4527 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4528 // Collect low parts of muls for DstIdx. 4529 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4530 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4531 MachineInstrBuilder Mul = 4532 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4533 Factors.push_back(Mul.getReg(0)); 4534 } 4535 // Collect high parts of muls from previous DstIdx. 4536 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4537 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4538 MachineInstrBuilder Umulh = 4539 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4540 Factors.push_back(Umulh.getReg(0)); 4541 } 4542 // Add CarrySum from additions calculated for previous DstIdx. 4543 if (DstIdx != 1) { 4544 Factors.push_back(CarrySumPrevDstIdx); 4545 } 4546 4547 Register CarrySum; 4548 // Add all factors and accumulate all carries into CarrySum. 4549 if (DstIdx != DstParts - 1) { 4550 MachineInstrBuilder Uaddo = 4551 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 4552 FactorSum = Uaddo.getReg(0); 4553 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 4554 for (unsigned i = 2; i < Factors.size(); ++i) { 4555 MachineInstrBuilder Uaddo = 4556 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 4557 FactorSum = Uaddo.getReg(0); 4558 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 4559 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 4560 } 4561 } else { 4562 // Since value for the next index is not calculated, neither is CarrySum. 4563 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 4564 for (unsigned i = 2; i < Factors.size(); ++i) 4565 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 4566 } 4567 4568 CarrySumPrevDstIdx = CarrySum; 4569 DstRegs[DstIdx] = FactorSum; 4570 Factors.clear(); 4571 } 4572 } 4573 4574 LegalizerHelper::LegalizeResult 4575 LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, 4576 LLT NarrowTy) { 4577 if (TypeIdx != 0) 4578 return UnableToLegalize; 4579 4580 Register DstReg = MI.getOperand(0).getReg(); 4581 LLT DstType = MRI.getType(DstReg); 4582 // FIXME: add support for vector types 4583 if (DstType.isVector()) 4584 return UnableToLegalize; 4585 4586 uint64_t SizeOp0 = DstType.getSizeInBits(); 4587 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4588 4589 // FIXME: add support for when SizeOp0 isn't an exact multiple of 4590 // NarrowSize. 4591 if (SizeOp0 % NarrowSize != 0) 4592 return UnableToLegalize; 4593 4594 // Expand in terms of carry-setting/consuming G_<Op>E instructions. 4595 int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); 4596 4597 unsigned Opcode = MI.getOpcode(); 4598 unsigned OpO, OpE, OpF; 4599 switch (Opcode) { 4600 case TargetOpcode::G_SADDO: 4601 case TargetOpcode::G_SADDE: 4602 case TargetOpcode::G_UADDO: 4603 case TargetOpcode::G_UADDE: 4604 case TargetOpcode::G_ADD: 4605 OpO = TargetOpcode::G_UADDO; 4606 OpE = TargetOpcode::G_UADDE; 4607 OpF = TargetOpcode::G_UADDE; 4608 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE) 4609 OpF = TargetOpcode::G_SADDE; 4610 break; 4611 case TargetOpcode::G_SSUBO: 4612 case TargetOpcode::G_SSUBE: 4613 case TargetOpcode::G_USUBO: 4614 case TargetOpcode::G_USUBE: 4615 case TargetOpcode::G_SUB: 4616 OpO = TargetOpcode::G_USUBO; 4617 OpE = TargetOpcode::G_USUBE; 4618 OpF = TargetOpcode::G_USUBE; 4619 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE) 4620 OpF = TargetOpcode::G_SSUBE; 4621 break; 4622 default: 4623 llvm_unreachable("Unexpected add/sub opcode!"); 4624 } 4625 4626 // 1 for a plain add/sub, 2 if this is an operation with a carry-out. 4627 unsigned NumDefs = MI.getNumExplicitDefs(); 4628 Register Src1 = MI.getOperand(NumDefs).getReg(); 4629 Register Src2 = MI.getOperand(NumDefs + 1).getReg(); 4630 Register CarryDst; 4631 if (NumDefs == 2) 4632 CarryDst = MI.getOperand(1).getReg(); 4633 Register CarryIn; 4634 if (MI.getNumOperands() == NumDefs + 3) 4635 CarryIn = MI.getOperand(NumDefs + 2).getReg(); 4636 4637 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 4638 extractParts(Src1, NarrowTy, NumParts, Src1Regs); 4639 extractParts(Src2, NarrowTy, NumParts, Src2Regs); 4640 4641 for (int i = 0; i < NumParts; ++i) { 4642 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 4643 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 4644 // Forward the final carry-out to the destination register 4645 if (i == NumParts - 1 && CarryDst) 4646 CarryOut = CarryDst; 4647 4648 if (!CarryIn) { 4649 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, 4650 {Src1Regs[i], Src2Regs[i]}); 4651 } else if (i == NumParts - 1) { 4652 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, 4653 {Src1Regs[i], Src2Regs[i], CarryIn}); 4654 } else { 4655 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, 4656 {Src1Regs[i], Src2Regs[i], CarryIn}); 4657 } 4658 4659 DstRegs.push_back(DstReg); 4660 CarryIn = CarryOut; 4661 } 4662 MIRBuilder.buildMerge(DstReg, DstRegs); 4663 MI.eraseFromParent(); 4664 return Legalized; 4665 } 4666 4667 LegalizerHelper::LegalizeResult 4668 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 4669 Register DstReg = MI.getOperand(0).getReg(); 4670 Register Src1 = MI.getOperand(1).getReg(); 4671 Register Src2 = MI.getOperand(2).getReg(); 4672 4673 LLT Ty = MRI.getType(DstReg); 4674 if (Ty.isVector()) 4675 return UnableToLegalize; 4676 4677 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 4678 unsigned DstSize = Ty.getSizeInBits(); 4679 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4680 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 4681 return UnableToLegalize; 4682 4683 unsigned NumDstParts = DstSize / NarrowSize; 4684 unsigned NumSrcParts = SrcSize / NarrowSize; 4685 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 4686 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 4687 4688 SmallVector<Register, 2> Src1Parts, Src2Parts; 4689 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 4690 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 4691 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 4692 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 4693 4694 // Take only high half of registers if this is high mul. 4695 ArrayRef<Register> DstRegs( 4696 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 4697 MIRBuilder.buildMerge(DstReg, DstRegs); 4698 MI.eraseFromParent(); 4699 return Legalized; 4700 } 4701 4702 LegalizerHelper::LegalizeResult 4703 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 4704 LLT NarrowTy) { 4705 if (TypeIdx != 1) 4706 return UnableToLegalize; 4707 4708 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4709 4710 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 4711 // FIXME: add support for when SizeOp1 isn't an exact multiple of 4712 // NarrowSize. 4713 if (SizeOp1 % NarrowSize != 0) 4714 return UnableToLegalize; 4715 int NumParts = SizeOp1 / NarrowSize; 4716 4717 SmallVector<Register, 2> SrcRegs, DstRegs; 4718 SmallVector<uint64_t, 2> Indexes; 4719 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4720 4721 Register OpReg = MI.getOperand(0).getReg(); 4722 uint64_t OpStart = MI.getOperand(2).getImm(); 4723 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4724 for (int i = 0; i < NumParts; ++i) { 4725 unsigned SrcStart = i * NarrowSize; 4726 4727 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 4728 // No part of the extract uses this subregister, ignore it. 4729 continue; 4730 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4731 // The entire subregister is extracted, forward the value. 4732 DstRegs.push_back(SrcRegs[i]); 4733 continue; 4734 } 4735 4736 // OpSegStart is where this destination segment would start in OpReg if it 4737 // extended infinitely in both directions. 4738 int64_t ExtractOffset; 4739 uint64_t SegSize; 4740 if (OpStart < SrcStart) { 4741 ExtractOffset = 0; 4742 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 4743 } else { 4744 ExtractOffset = OpStart - SrcStart; 4745 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 4746 } 4747 4748 Register SegReg = SrcRegs[i]; 4749 if (ExtractOffset != 0 || SegSize != NarrowSize) { 4750 // A genuine extract is needed. 4751 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4752 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 4753 } 4754 4755 DstRegs.push_back(SegReg); 4756 } 4757 4758 Register DstReg = MI.getOperand(0).getReg(); 4759 if (MRI.getType(DstReg).isVector()) 4760 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4761 else if (DstRegs.size() > 1) 4762 MIRBuilder.buildMerge(DstReg, DstRegs); 4763 else 4764 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 4765 MI.eraseFromParent(); 4766 return Legalized; 4767 } 4768 4769 LegalizerHelper::LegalizeResult 4770 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 4771 LLT NarrowTy) { 4772 // FIXME: Don't know how to handle secondary types yet. 4773 if (TypeIdx != 0) 4774 return UnableToLegalize; 4775 4776 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 4777 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4778 4779 // FIXME: add support for when SizeOp0 isn't an exact multiple of 4780 // NarrowSize. 4781 if (SizeOp0 % NarrowSize != 0) 4782 return UnableToLegalize; 4783 4784 int NumParts = SizeOp0 / NarrowSize; 4785 4786 SmallVector<Register, 2> SrcRegs, DstRegs; 4787 SmallVector<uint64_t, 2> Indexes; 4788 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4789 4790 Register OpReg = MI.getOperand(2).getReg(); 4791 uint64_t OpStart = MI.getOperand(3).getImm(); 4792 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4793 for (int i = 0; i < NumParts; ++i) { 4794 unsigned DstStart = i * NarrowSize; 4795 4796 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 4797 // No part of the insert affects this subregister, forward the original. 4798 DstRegs.push_back(SrcRegs[i]); 4799 continue; 4800 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4801 // The entire subregister is defined by this insert, forward the new 4802 // value. 4803 DstRegs.push_back(OpReg); 4804 continue; 4805 } 4806 4807 // OpSegStart is where this destination segment would start in OpReg if it 4808 // extended infinitely in both directions. 4809 int64_t ExtractOffset, InsertOffset; 4810 uint64_t SegSize; 4811 if (OpStart < DstStart) { 4812 InsertOffset = 0; 4813 ExtractOffset = DstStart - OpStart; 4814 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 4815 } else { 4816 InsertOffset = OpStart - DstStart; 4817 ExtractOffset = 0; 4818 SegSize = 4819 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 4820 } 4821 4822 Register SegReg = OpReg; 4823 if (ExtractOffset != 0 || SegSize != OpSize) { 4824 // A genuine extract is needed. 4825 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4826 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 4827 } 4828 4829 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 4830 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset); 4831 DstRegs.push_back(DstReg); 4832 } 4833 4834 assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered"); 4835 Register DstReg = MI.getOperand(0).getReg(); 4836 if(MRI.getType(DstReg).isVector()) 4837 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4838 else 4839 MIRBuilder.buildMerge(DstReg, DstRegs); 4840 MI.eraseFromParent(); 4841 return Legalized; 4842 } 4843 4844 LegalizerHelper::LegalizeResult 4845 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 4846 LLT NarrowTy) { 4847 Register DstReg = MI.getOperand(0).getReg(); 4848 LLT DstTy = MRI.getType(DstReg); 4849 4850 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 4851 4852 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4853 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 4854 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4855 LLT LeftoverTy; 4856 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 4857 Src0Regs, Src0LeftoverRegs)) 4858 return UnableToLegalize; 4859 4860 LLT Unused; 4861 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 4862 Src1Regs, Src1LeftoverRegs)) 4863 llvm_unreachable("inconsistent extractParts result"); 4864 4865 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4866 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 4867 {Src0Regs[I], Src1Regs[I]}); 4868 DstRegs.push_back(Inst.getReg(0)); 4869 } 4870 4871 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4872 auto Inst = MIRBuilder.buildInstr( 4873 MI.getOpcode(), 4874 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 4875 DstLeftoverRegs.push_back(Inst.getReg(0)); 4876 } 4877 4878 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4879 LeftoverTy, DstLeftoverRegs); 4880 4881 MI.eraseFromParent(); 4882 return Legalized; 4883 } 4884 4885 LegalizerHelper::LegalizeResult 4886 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 4887 LLT NarrowTy) { 4888 if (TypeIdx != 0) 4889 return UnableToLegalize; 4890 4891 Register DstReg = MI.getOperand(0).getReg(); 4892 Register SrcReg = MI.getOperand(1).getReg(); 4893 4894 LLT DstTy = MRI.getType(DstReg); 4895 if (DstTy.isVector()) 4896 return UnableToLegalize; 4897 4898 SmallVector<Register, 8> Parts; 4899 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4900 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 4901 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4902 4903 MI.eraseFromParent(); 4904 return Legalized; 4905 } 4906 4907 LegalizerHelper::LegalizeResult 4908 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 4909 LLT NarrowTy) { 4910 if (TypeIdx != 0) 4911 return UnableToLegalize; 4912 4913 Register CondReg = MI.getOperand(1).getReg(); 4914 LLT CondTy = MRI.getType(CondReg); 4915 if (CondTy.isVector()) // TODO: Handle vselect 4916 return UnableToLegalize; 4917 4918 Register DstReg = MI.getOperand(0).getReg(); 4919 LLT DstTy = MRI.getType(DstReg); 4920 4921 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4922 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4923 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 4924 LLT LeftoverTy; 4925 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 4926 Src1Regs, Src1LeftoverRegs)) 4927 return UnableToLegalize; 4928 4929 LLT Unused; 4930 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 4931 Src2Regs, Src2LeftoverRegs)) 4932 llvm_unreachable("inconsistent extractParts result"); 4933 4934 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4935 auto Select = MIRBuilder.buildSelect(NarrowTy, 4936 CondReg, Src1Regs[I], Src2Regs[I]); 4937 DstRegs.push_back(Select.getReg(0)); 4938 } 4939 4940 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4941 auto Select = MIRBuilder.buildSelect( 4942 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 4943 DstLeftoverRegs.push_back(Select.getReg(0)); 4944 } 4945 4946 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4947 LeftoverTy, DstLeftoverRegs); 4948 4949 MI.eraseFromParent(); 4950 return Legalized; 4951 } 4952 4953 LegalizerHelper::LegalizeResult 4954 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 4955 LLT NarrowTy) { 4956 if (TypeIdx != 1) 4957 return UnableToLegalize; 4958 4959 Register DstReg = MI.getOperand(0).getReg(); 4960 Register SrcReg = MI.getOperand(1).getReg(); 4961 LLT DstTy = MRI.getType(DstReg); 4962 LLT SrcTy = MRI.getType(SrcReg); 4963 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4964 4965 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4966 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 4967 4968 MachineIRBuilder &B = MIRBuilder; 4969 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 4970 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 4971 auto C_0 = B.buildConstant(NarrowTy, 0); 4972 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 4973 UnmergeSrc.getReg(1), C_0); 4974 auto LoCTLZ = IsUndef ? 4975 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 4976 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 4977 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 4978 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 4979 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 4980 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 4981 4982 MI.eraseFromParent(); 4983 return Legalized; 4984 } 4985 4986 return UnableToLegalize; 4987 } 4988 4989 LegalizerHelper::LegalizeResult 4990 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 4991 LLT NarrowTy) { 4992 if (TypeIdx != 1) 4993 return UnableToLegalize; 4994 4995 Register DstReg = MI.getOperand(0).getReg(); 4996 Register SrcReg = MI.getOperand(1).getReg(); 4997 LLT DstTy = MRI.getType(DstReg); 4998 LLT SrcTy = MRI.getType(SrcReg); 4999 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5000 5001 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5002 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 5003 5004 MachineIRBuilder &B = MIRBuilder; 5005 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5006 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 5007 auto C_0 = B.buildConstant(NarrowTy, 0); 5008 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5009 UnmergeSrc.getReg(0), C_0); 5010 auto HiCTTZ = IsUndef ? 5011 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 5012 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 5013 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5014 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 5015 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 5016 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 5017 5018 MI.eraseFromParent(); 5019 return Legalized; 5020 } 5021 5022 return UnableToLegalize; 5023 } 5024 5025 LegalizerHelper::LegalizeResult 5026 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 5027 LLT NarrowTy) { 5028 if (TypeIdx != 1) 5029 return UnableToLegalize; 5030 5031 Register DstReg = MI.getOperand(0).getReg(); 5032 LLT DstTy = MRI.getType(DstReg); 5033 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 5034 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5035 5036 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5037 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 5038 5039 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 5040 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 5041 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 5042 5043 MI.eraseFromParent(); 5044 return Legalized; 5045 } 5046 5047 return UnableToLegalize; 5048 } 5049 5050 LegalizerHelper::LegalizeResult 5051 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 5052 unsigned Opc = MI.getOpcode(); 5053 const auto &TII = MIRBuilder.getTII(); 5054 auto isSupported = [this](const LegalityQuery &Q) { 5055 auto QAction = LI.getAction(Q).Action; 5056 return QAction == Legal || QAction == Libcall || QAction == Custom; 5057 }; 5058 switch (Opc) { 5059 default: 5060 return UnableToLegalize; 5061 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 5062 // This trivially expands to CTLZ. 5063 Observer.changingInstr(MI); 5064 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 5065 Observer.changedInstr(MI); 5066 return Legalized; 5067 } 5068 case TargetOpcode::G_CTLZ: { 5069 Register DstReg = MI.getOperand(0).getReg(); 5070 Register SrcReg = MI.getOperand(1).getReg(); 5071 LLT DstTy = MRI.getType(DstReg); 5072 LLT SrcTy = MRI.getType(SrcReg); 5073 unsigned Len = SrcTy.getSizeInBits(); 5074 5075 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5076 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 5077 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 5078 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 5079 auto ICmp = MIRBuilder.buildICmp( 5080 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 5081 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5082 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 5083 MI.eraseFromParent(); 5084 return Legalized; 5085 } 5086 // for now, we do this: 5087 // NewLen = NextPowerOf2(Len); 5088 // x = x | (x >> 1); 5089 // x = x | (x >> 2); 5090 // ... 5091 // x = x | (x >>16); 5092 // x = x | (x >>32); // for 64-bit input 5093 // Upto NewLen/2 5094 // return Len - popcount(x); 5095 // 5096 // Ref: "Hacker's Delight" by Henry Warren 5097 Register Op = SrcReg; 5098 unsigned NewLen = PowerOf2Ceil(Len); 5099 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 5100 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 5101 auto MIBOp = MIRBuilder.buildOr( 5102 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 5103 Op = MIBOp.getReg(0); 5104 } 5105 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 5106 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 5107 MIBPop); 5108 MI.eraseFromParent(); 5109 return Legalized; 5110 } 5111 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 5112 // This trivially expands to CTTZ. 5113 Observer.changingInstr(MI); 5114 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 5115 Observer.changedInstr(MI); 5116 return Legalized; 5117 } 5118 case TargetOpcode::G_CTTZ: { 5119 Register DstReg = MI.getOperand(0).getReg(); 5120 Register SrcReg = MI.getOperand(1).getReg(); 5121 LLT DstTy = MRI.getType(DstReg); 5122 LLT SrcTy = MRI.getType(SrcReg); 5123 5124 unsigned Len = SrcTy.getSizeInBits(); 5125 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5126 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 5127 // zero. 5128 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 5129 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 5130 auto ICmp = MIRBuilder.buildICmp( 5131 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 5132 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5133 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 5134 MI.eraseFromParent(); 5135 return Legalized; 5136 } 5137 // for now, we use: { return popcount(~x & (x - 1)); } 5138 // unless the target has ctlz but not ctpop, in which case we use: 5139 // { return 32 - nlz(~x & (x-1)); } 5140 // Ref: "Hacker's Delight" by Henry Warren 5141 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 5142 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 5143 auto MIBTmp = MIRBuilder.buildAnd( 5144 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 5145 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 5146 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 5147 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 5148 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 5149 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 5150 MI.eraseFromParent(); 5151 return Legalized; 5152 } 5153 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 5154 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 5155 return Legalized; 5156 } 5157 case TargetOpcode::G_CTPOP: { 5158 Register SrcReg = MI.getOperand(1).getReg(); 5159 LLT Ty = MRI.getType(SrcReg); 5160 unsigned Size = Ty.getSizeInBits(); 5161 MachineIRBuilder &B = MIRBuilder; 5162 5163 // Count set bits in blocks of 2 bits. Default approach would be 5164 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5165 // We use following formula instead: 5166 // B2Count = val - { (val >> 1) & 0x55555555 } 5167 // since it gives same result in blocks of 2 with one instruction less. 5168 auto C_1 = B.buildConstant(Ty, 1); 5169 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5170 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5171 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5172 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5173 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5174 5175 // In order to get count in blocks of 4 add values from adjacent block of 2. 5176 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5177 auto C_2 = B.buildConstant(Ty, 2); 5178 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5179 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5180 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5181 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5182 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5183 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5184 5185 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5186 // addition since count value sits in range {0,...,8} and 4 bits are enough 5187 // to hold such binary values. After addition high 4 bits still hold count 5188 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5189 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5190 auto C_4 = B.buildConstant(Ty, 4); 5191 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5192 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5193 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5194 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5195 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5196 5197 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5198 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5199 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5200 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5201 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5202 5203 // Shift count result from 8 high bits to low bits. 5204 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5205 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5206 5207 MI.eraseFromParent(); 5208 return Legalized; 5209 } 5210 } 5211 } 5212 5213 // Check that (every element of) Reg is undef or not an exact multiple of BW. 5214 static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI, 5215 Register Reg, unsigned BW) { 5216 return matchUnaryPredicate( 5217 MRI, Reg, 5218 [=](const Constant *C) { 5219 // Null constant here means an undef. 5220 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C); 5221 return !CI || CI->getValue().urem(BW) != 0; 5222 }, 5223 /*AllowUndefs*/ true); 5224 } 5225 5226 LegalizerHelper::LegalizeResult 5227 LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { 5228 Register Dst = MI.getOperand(0).getReg(); 5229 Register X = MI.getOperand(1).getReg(); 5230 Register Y = MI.getOperand(2).getReg(); 5231 Register Z = MI.getOperand(3).getReg(); 5232 LLT Ty = MRI.getType(Dst); 5233 LLT ShTy = MRI.getType(Z); 5234 5235 unsigned BW = Ty.getScalarSizeInBits(); 5236 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5237 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5238 5239 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5240 // fshl X, Y, Z -> fshr X, Y, -Z 5241 // fshr X, Y, Z -> fshl X, Y, -Z 5242 auto Zero = MIRBuilder.buildConstant(ShTy, 0); 5243 Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0); 5244 } else { 5245 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z 5246 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z 5247 auto One = MIRBuilder.buildConstant(ShTy, 1); 5248 if (IsFSHL) { 5249 Y = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5250 X = MIRBuilder.buildLShr(Ty, X, One).getReg(0); 5251 } else { 5252 X = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5253 Y = MIRBuilder.buildShl(Ty, Y, One).getReg(0); 5254 } 5255 5256 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); 5257 } 5258 5259 MIRBuilder.buildInstr(RevOpcode, {Dst}, {X, Y, Z}); 5260 MI.eraseFromParent(); 5261 return Legalized; 5262 } 5263 5264 LegalizerHelper::LegalizeResult 5265 LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { 5266 Register Dst = MI.getOperand(0).getReg(); 5267 Register X = MI.getOperand(1).getReg(); 5268 Register Y = MI.getOperand(2).getReg(); 5269 Register Z = MI.getOperand(3).getReg(); 5270 LLT Ty = MRI.getType(Dst); 5271 LLT ShTy = MRI.getType(Z); 5272 5273 const unsigned BW = Ty.getScalarSizeInBits(); 5274 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5275 5276 Register ShX, ShY; 5277 Register ShAmt, InvShAmt; 5278 5279 // FIXME: Emit optimized urem by constant instead of letting it expand later. 5280 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5281 // fshl: X << C | Y >> (BW - C) 5282 // fshr: X << (BW - C) | Y >> C 5283 // where C = Z % BW is not zero 5284 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5285 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5286 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); 5287 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); 5288 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); 5289 } else { 5290 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) 5291 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) 5292 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); 5293 if (isPowerOf2_32(BW)) { 5294 // Z % BW -> Z & (BW - 1) 5295 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); 5296 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) 5297 auto NotZ = MIRBuilder.buildNot(ShTy, Z); 5298 InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0); 5299 } else { 5300 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5301 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5302 InvShAmt = MIRBuilder.buildSub(ShTy, Mask, ShAmt).getReg(0); 5303 } 5304 5305 auto One = MIRBuilder.buildConstant(ShTy, 1); 5306 if (IsFSHL) { 5307 ShX = MIRBuilder.buildShl(Ty, X, ShAmt).getReg(0); 5308 auto ShY1 = MIRBuilder.buildLShr(Ty, Y, One); 5309 ShY = MIRBuilder.buildLShr(Ty, ShY1, InvShAmt).getReg(0); 5310 } else { 5311 auto ShX1 = MIRBuilder.buildShl(Ty, X, One); 5312 ShX = MIRBuilder.buildShl(Ty, ShX1, InvShAmt).getReg(0); 5313 ShY = MIRBuilder.buildLShr(Ty, Y, ShAmt).getReg(0); 5314 } 5315 } 5316 5317 MIRBuilder.buildOr(Dst, ShX, ShY); 5318 MI.eraseFromParent(); 5319 return Legalized; 5320 } 5321 5322 LegalizerHelper::LegalizeResult 5323 LegalizerHelper::lowerFunnelShift(MachineInstr &MI) { 5324 // These operations approximately do the following (while avoiding undefined 5325 // shifts by BW): 5326 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 5327 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 5328 Register Dst = MI.getOperand(0).getReg(); 5329 LLT Ty = MRI.getType(Dst); 5330 LLT ShTy = MRI.getType(MI.getOperand(3).getReg()); 5331 5332 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5333 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5334 if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) 5335 return lowerFunnelShiftAsShifts(MI); 5336 return lowerFunnelShiftWithInverse(MI); 5337 } 5338 5339 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5340 // representation. 5341 LegalizerHelper::LegalizeResult 5342 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5343 Register Dst = MI.getOperand(0).getReg(); 5344 Register Src = MI.getOperand(1).getReg(); 5345 const LLT S64 = LLT::scalar(64); 5346 const LLT S32 = LLT::scalar(32); 5347 const LLT S1 = LLT::scalar(1); 5348 5349 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5350 5351 // unsigned cul2f(ulong u) { 5352 // uint lz = clz(u); 5353 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5354 // u = (u << lz) & 0x7fffffffffffffffUL; 5355 // ulong t = u & 0xffffffffffUL; 5356 // uint v = (e << 23) | (uint)(u >> 40); 5357 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5358 // return as_float(v + r); 5359 // } 5360 5361 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5362 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5363 5364 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5365 5366 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5367 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5368 5369 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5370 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5371 5372 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5373 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5374 5375 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5376 5377 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5378 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5379 5380 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5381 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5382 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5383 5384 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5385 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5386 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5387 auto One = MIRBuilder.buildConstant(S32, 1); 5388 5389 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5390 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5391 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5392 MIRBuilder.buildAdd(Dst, V, R); 5393 5394 MI.eraseFromParent(); 5395 return Legalized; 5396 } 5397 5398 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5399 Register Dst = MI.getOperand(0).getReg(); 5400 Register Src = MI.getOperand(1).getReg(); 5401 LLT DstTy = MRI.getType(Dst); 5402 LLT SrcTy = MRI.getType(Src); 5403 5404 if (SrcTy == LLT::scalar(1)) { 5405 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5406 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5407 MIRBuilder.buildSelect(Dst, Src, True, False); 5408 MI.eraseFromParent(); 5409 return Legalized; 5410 } 5411 5412 if (SrcTy != LLT::scalar(64)) 5413 return UnableToLegalize; 5414 5415 if (DstTy == LLT::scalar(32)) { 5416 // TODO: SelectionDAG has several alternative expansions to port which may 5417 // be more reasonble depending on the available instructions. If a target 5418 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5419 // intermediate type, this is probably worse. 5420 return lowerU64ToF32BitOps(MI); 5421 } 5422 5423 return UnableToLegalize; 5424 } 5425 5426 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5427 Register Dst = MI.getOperand(0).getReg(); 5428 Register Src = MI.getOperand(1).getReg(); 5429 LLT DstTy = MRI.getType(Dst); 5430 LLT SrcTy = MRI.getType(Src); 5431 5432 const LLT S64 = LLT::scalar(64); 5433 const LLT S32 = LLT::scalar(32); 5434 const LLT S1 = LLT::scalar(1); 5435 5436 if (SrcTy == S1) { 5437 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 5438 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5439 MIRBuilder.buildSelect(Dst, Src, True, False); 5440 MI.eraseFromParent(); 5441 return Legalized; 5442 } 5443 5444 if (SrcTy != S64) 5445 return UnableToLegalize; 5446 5447 if (DstTy == S32) { 5448 // signed cl2f(long l) { 5449 // long s = l >> 63; 5450 // float r = cul2f((l + s) ^ s); 5451 // return s ? -r : r; 5452 // } 5453 Register L = Src; 5454 auto SignBit = MIRBuilder.buildConstant(S64, 63); 5455 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 5456 5457 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 5458 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 5459 auto R = MIRBuilder.buildUITOFP(S32, Xor); 5460 5461 auto RNeg = MIRBuilder.buildFNeg(S32, R); 5462 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 5463 MIRBuilder.buildConstant(S64, 0)); 5464 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 5465 MI.eraseFromParent(); 5466 return Legalized; 5467 } 5468 5469 return UnableToLegalize; 5470 } 5471 5472 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 5473 Register Dst = MI.getOperand(0).getReg(); 5474 Register Src = MI.getOperand(1).getReg(); 5475 LLT DstTy = MRI.getType(Dst); 5476 LLT SrcTy = MRI.getType(Src); 5477 const LLT S64 = LLT::scalar(64); 5478 const LLT S32 = LLT::scalar(32); 5479 5480 if (SrcTy != S64 && SrcTy != S32) 5481 return UnableToLegalize; 5482 if (DstTy != S32 && DstTy != S64) 5483 return UnableToLegalize; 5484 5485 // FPTOSI gives same result as FPTOUI for positive signed integers. 5486 // FPTOUI needs to deal with fp values that convert to unsigned integers 5487 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 5488 5489 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 5490 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 5491 : APFloat::IEEEdouble(), 5492 APInt::getNullValue(SrcTy.getSizeInBits())); 5493 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 5494 5495 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 5496 5497 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 5498 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 5499 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 5500 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 5501 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 5502 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 5503 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 5504 5505 const LLT S1 = LLT::scalar(1); 5506 5507 MachineInstrBuilder FCMP = 5508 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 5509 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 5510 5511 MI.eraseFromParent(); 5512 return Legalized; 5513 } 5514 5515 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 5516 Register Dst = MI.getOperand(0).getReg(); 5517 Register Src = MI.getOperand(1).getReg(); 5518 LLT DstTy = MRI.getType(Dst); 5519 LLT SrcTy = MRI.getType(Src); 5520 const LLT S64 = LLT::scalar(64); 5521 const LLT S32 = LLT::scalar(32); 5522 5523 // FIXME: Only f32 to i64 conversions are supported. 5524 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 5525 return UnableToLegalize; 5526 5527 // Expand f32 -> i64 conversion 5528 // This algorithm comes from compiler-rt's implementation of fixsfdi: 5529 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c 5530 5531 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 5532 5533 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 5534 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 5535 5536 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 5537 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 5538 5539 auto SignMask = MIRBuilder.buildConstant(SrcTy, 5540 APInt::getSignMask(SrcEltBits)); 5541 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 5542 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 5543 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 5544 Sign = MIRBuilder.buildSExt(DstTy, Sign); 5545 5546 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 5547 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 5548 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 5549 5550 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 5551 R = MIRBuilder.buildZExt(DstTy, R); 5552 5553 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 5554 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 5555 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 5556 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 5557 5558 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 5559 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 5560 5561 const LLT S1 = LLT::scalar(1); 5562 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 5563 S1, Exponent, ExponentLoBit); 5564 5565 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 5566 5567 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 5568 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 5569 5570 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 5571 5572 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 5573 S1, Exponent, ZeroSrcTy); 5574 5575 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 5576 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 5577 5578 MI.eraseFromParent(); 5579 return Legalized; 5580 } 5581 5582 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 5583 LegalizerHelper::LegalizeResult 5584 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 5585 Register Dst = MI.getOperand(0).getReg(); 5586 Register Src = MI.getOperand(1).getReg(); 5587 5588 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 5589 return UnableToLegalize; 5590 5591 const unsigned ExpMask = 0x7ff; 5592 const unsigned ExpBiasf64 = 1023; 5593 const unsigned ExpBiasf16 = 15; 5594 const LLT S32 = LLT::scalar(32); 5595 const LLT S1 = LLT::scalar(1); 5596 5597 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 5598 Register U = Unmerge.getReg(0); 5599 Register UH = Unmerge.getReg(1); 5600 5601 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 5602 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 5603 5604 // Subtract the fp64 exponent bias (1023) to get the real exponent and 5605 // add the f16 bias (15) to get the biased exponent for the f16 format. 5606 E = MIRBuilder.buildAdd( 5607 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 5608 5609 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 5610 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 5611 5612 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 5613 MIRBuilder.buildConstant(S32, 0x1ff)); 5614 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 5615 5616 auto Zero = MIRBuilder.buildConstant(S32, 0); 5617 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 5618 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 5619 M = MIRBuilder.buildOr(S32, M, Lo40Set); 5620 5621 // (M != 0 ? 0x0200 : 0) | 0x7c00; 5622 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 5623 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 5624 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 5625 5626 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 5627 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 5628 5629 // N = M | (E << 12); 5630 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 5631 auto N = MIRBuilder.buildOr(S32, M, EShl12); 5632 5633 // B = clamp(1-E, 0, 13); 5634 auto One = MIRBuilder.buildConstant(S32, 1); 5635 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 5636 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 5637 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 5638 5639 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 5640 MIRBuilder.buildConstant(S32, 0x1000)); 5641 5642 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 5643 auto D0 = MIRBuilder.buildShl(S32, D, B); 5644 5645 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 5646 D0, SigSetHigh); 5647 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 5648 D = MIRBuilder.buildOr(S32, D, D1); 5649 5650 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 5651 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 5652 5653 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 5654 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 5655 5656 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 5657 MIRBuilder.buildConstant(S32, 3)); 5658 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 5659 5660 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 5661 MIRBuilder.buildConstant(S32, 5)); 5662 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 5663 5664 V1 = MIRBuilder.buildOr(S32, V0, V1); 5665 V = MIRBuilder.buildAdd(S32, V, V1); 5666 5667 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 5668 E, MIRBuilder.buildConstant(S32, 30)); 5669 V = MIRBuilder.buildSelect(S32, CmpEGt30, 5670 MIRBuilder.buildConstant(S32, 0x7c00), V); 5671 5672 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 5673 E, MIRBuilder.buildConstant(S32, 1039)); 5674 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 5675 5676 // Extract the sign bit. 5677 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 5678 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 5679 5680 // Insert the sign bit 5681 V = MIRBuilder.buildOr(S32, Sign, V); 5682 5683 MIRBuilder.buildTrunc(Dst, V); 5684 MI.eraseFromParent(); 5685 return Legalized; 5686 } 5687 5688 LegalizerHelper::LegalizeResult 5689 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 5690 Register Dst = MI.getOperand(0).getReg(); 5691 Register Src = MI.getOperand(1).getReg(); 5692 5693 LLT DstTy = MRI.getType(Dst); 5694 LLT SrcTy = MRI.getType(Src); 5695 const LLT S64 = LLT::scalar(64); 5696 const LLT S16 = LLT::scalar(16); 5697 5698 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 5699 return lowerFPTRUNC_F64_TO_F16(MI); 5700 5701 return UnableToLegalize; 5702 } 5703 5704 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 5705 // multiplication tree. 5706 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 5707 Register Dst = MI.getOperand(0).getReg(); 5708 Register Src0 = MI.getOperand(1).getReg(); 5709 Register Src1 = MI.getOperand(2).getReg(); 5710 LLT Ty = MRI.getType(Dst); 5711 5712 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 5713 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 5714 MI.eraseFromParent(); 5715 return Legalized; 5716 } 5717 5718 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 5719 switch (Opc) { 5720 case TargetOpcode::G_SMIN: 5721 return CmpInst::ICMP_SLT; 5722 case TargetOpcode::G_SMAX: 5723 return CmpInst::ICMP_SGT; 5724 case TargetOpcode::G_UMIN: 5725 return CmpInst::ICMP_ULT; 5726 case TargetOpcode::G_UMAX: 5727 return CmpInst::ICMP_UGT; 5728 default: 5729 llvm_unreachable("not in integer min/max"); 5730 } 5731 } 5732 5733 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 5734 Register Dst = MI.getOperand(0).getReg(); 5735 Register Src0 = MI.getOperand(1).getReg(); 5736 Register Src1 = MI.getOperand(2).getReg(); 5737 5738 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 5739 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 5740 5741 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 5742 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 5743 5744 MI.eraseFromParent(); 5745 return Legalized; 5746 } 5747 5748 LegalizerHelper::LegalizeResult 5749 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 5750 Register Dst = MI.getOperand(0).getReg(); 5751 Register Src0 = MI.getOperand(1).getReg(); 5752 Register Src1 = MI.getOperand(2).getReg(); 5753 5754 const LLT Src0Ty = MRI.getType(Src0); 5755 const LLT Src1Ty = MRI.getType(Src1); 5756 5757 const int Src0Size = Src0Ty.getScalarSizeInBits(); 5758 const int Src1Size = Src1Ty.getScalarSizeInBits(); 5759 5760 auto SignBitMask = MIRBuilder.buildConstant( 5761 Src0Ty, APInt::getSignMask(Src0Size)); 5762 5763 auto NotSignBitMask = MIRBuilder.buildConstant( 5764 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 5765 5766 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); 5767 Register And1; 5768 if (Src0Ty == Src1Ty) { 5769 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); 5770 } else if (Src0Size > Src1Size) { 5771 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 5772 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 5773 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 5774 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); 5775 } else { 5776 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 5777 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 5778 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 5779 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); 5780 } 5781 5782 // Be careful about setting nsz/nnan/ninf on every instruction, since the 5783 // constants are a nan and -0.0, but the final result should preserve 5784 // everything. 5785 unsigned Flags = MI.getFlags(); 5786 MIRBuilder.buildOr(Dst, And0, And1, Flags); 5787 5788 MI.eraseFromParent(); 5789 return Legalized; 5790 } 5791 5792 LegalizerHelper::LegalizeResult 5793 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 5794 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 5795 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 5796 5797 Register Dst = MI.getOperand(0).getReg(); 5798 Register Src0 = MI.getOperand(1).getReg(); 5799 Register Src1 = MI.getOperand(2).getReg(); 5800 LLT Ty = MRI.getType(Dst); 5801 5802 if (!MI.getFlag(MachineInstr::FmNoNans)) { 5803 // Insert canonicalizes if it's possible we need to quiet to get correct 5804 // sNaN behavior. 5805 5806 // Note this must be done here, and not as an optimization combine in the 5807 // absence of a dedicate quiet-snan instruction as we're using an 5808 // omni-purpose G_FCANONICALIZE. 5809 if (!isKnownNeverSNaN(Src0, MRI)) 5810 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 5811 5812 if (!isKnownNeverSNaN(Src1, MRI)) 5813 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 5814 } 5815 5816 // If there are no nans, it's safe to simply replace this with the non-IEEE 5817 // version. 5818 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 5819 MI.eraseFromParent(); 5820 return Legalized; 5821 } 5822 5823 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 5824 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 5825 Register DstReg = MI.getOperand(0).getReg(); 5826 LLT Ty = MRI.getType(DstReg); 5827 unsigned Flags = MI.getFlags(); 5828 5829 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 5830 Flags); 5831 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 5832 MI.eraseFromParent(); 5833 return Legalized; 5834 } 5835 5836 LegalizerHelper::LegalizeResult 5837 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 5838 Register DstReg = MI.getOperand(0).getReg(); 5839 Register X = MI.getOperand(1).getReg(); 5840 const unsigned Flags = MI.getFlags(); 5841 const LLT Ty = MRI.getType(DstReg); 5842 const LLT CondTy = Ty.changeElementSize(1); 5843 5844 // round(x) => 5845 // t = trunc(x); 5846 // d = fabs(x - t); 5847 // o = copysign(1.0f, x); 5848 // return t + (d >= 0.5 ? o : 0.0); 5849 5850 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 5851 5852 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 5853 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 5854 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5855 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 5856 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 5857 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 5858 5859 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 5860 Flags); 5861 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 5862 5863 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 5864 5865 MI.eraseFromParent(); 5866 return Legalized; 5867 } 5868 5869 LegalizerHelper::LegalizeResult 5870 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 5871 Register DstReg = MI.getOperand(0).getReg(); 5872 Register SrcReg = MI.getOperand(1).getReg(); 5873 unsigned Flags = MI.getFlags(); 5874 LLT Ty = MRI.getType(DstReg); 5875 const LLT CondTy = Ty.changeElementSize(1); 5876 5877 // result = trunc(src); 5878 // if (src < 0.0 && src != result) 5879 // result += -1.0. 5880 5881 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 5882 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5883 5884 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 5885 SrcReg, Zero, Flags); 5886 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 5887 SrcReg, Trunc, Flags); 5888 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 5889 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 5890 5891 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 5892 MI.eraseFromParent(); 5893 return Legalized; 5894 } 5895 5896 LegalizerHelper::LegalizeResult 5897 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 5898 const unsigned NumOps = MI.getNumOperands(); 5899 Register DstReg = MI.getOperand(0).getReg(); 5900 Register Src0Reg = MI.getOperand(1).getReg(); 5901 LLT DstTy = MRI.getType(DstReg); 5902 LLT SrcTy = MRI.getType(Src0Reg); 5903 unsigned PartSize = SrcTy.getSizeInBits(); 5904 5905 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 5906 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 5907 5908 for (unsigned I = 2; I != NumOps; ++I) { 5909 const unsigned Offset = (I - 1) * PartSize; 5910 5911 Register SrcReg = MI.getOperand(I).getReg(); 5912 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 5913 5914 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 5915 MRI.createGenericVirtualRegister(WideTy); 5916 5917 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 5918 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 5919 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 5920 ResultReg = NextResult; 5921 } 5922 5923 if (DstTy.isPointer()) { 5924 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 5925 DstTy.getAddressSpace())) { 5926 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 5927 return UnableToLegalize; 5928 } 5929 5930 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 5931 } 5932 5933 MI.eraseFromParent(); 5934 return Legalized; 5935 } 5936 5937 LegalizerHelper::LegalizeResult 5938 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 5939 const unsigned NumDst = MI.getNumOperands() - 1; 5940 Register SrcReg = MI.getOperand(NumDst).getReg(); 5941 Register Dst0Reg = MI.getOperand(0).getReg(); 5942 LLT DstTy = MRI.getType(Dst0Reg); 5943 if (DstTy.isPointer()) 5944 return UnableToLegalize; // TODO 5945 5946 SrcReg = coerceToScalar(SrcReg); 5947 if (!SrcReg) 5948 return UnableToLegalize; 5949 5950 // Expand scalarizing unmerge as bitcast to integer and shift. 5951 LLT IntTy = MRI.getType(SrcReg); 5952 5953 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 5954 5955 const unsigned DstSize = DstTy.getSizeInBits(); 5956 unsigned Offset = DstSize; 5957 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 5958 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 5959 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 5960 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 5961 } 5962 5963 MI.eraseFromParent(); 5964 return Legalized; 5965 } 5966 5967 /// Lower a vector extract or insert by writing the vector to a stack temporary 5968 /// and reloading the element or vector. 5969 /// 5970 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 5971 /// => 5972 /// %stack_temp = G_FRAME_INDEX 5973 /// G_STORE %vec, %stack_temp 5974 /// %idx = clamp(%idx, %vec.getNumElements()) 5975 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 5976 /// %dst = G_LOAD %element_ptr 5977 LegalizerHelper::LegalizeResult 5978 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 5979 Register DstReg = MI.getOperand(0).getReg(); 5980 Register SrcVec = MI.getOperand(1).getReg(); 5981 Register InsertVal; 5982 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 5983 InsertVal = MI.getOperand(2).getReg(); 5984 5985 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 5986 5987 LLT VecTy = MRI.getType(SrcVec); 5988 LLT EltTy = VecTy.getElementType(); 5989 if (!EltTy.isByteSized()) { // Not implemented. 5990 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 5991 return UnableToLegalize; 5992 } 5993 5994 unsigned EltBytes = EltTy.getSizeInBytes(); 5995 Align VecAlign = getStackTemporaryAlignment(VecTy); 5996 Align EltAlign; 5997 5998 MachinePointerInfo PtrInfo; 5999 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 6000 VecAlign, PtrInfo); 6001 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 6002 6003 // Get the pointer to the element, and be sure not to hit undefined behavior 6004 // if the index is out of bounds. 6005 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 6006 6007 int64_t IdxVal; 6008 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 6009 int64_t Offset = IdxVal * EltBytes; 6010 PtrInfo = PtrInfo.getWithOffset(Offset); 6011 EltAlign = commonAlignment(VecAlign, Offset); 6012 } else { 6013 // We lose information with a variable offset. 6014 EltAlign = getStackTemporaryAlignment(EltTy); 6015 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 6016 } 6017 6018 if (InsertVal) { 6019 // Write the inserted element 6020 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 6021 6022 // Reload the whole vector. 6023 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 6024 } else { 6025 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 6026 } 6027 6028 MI.eraseFromParent(); 6029 return Legalized; 6030 } 6031 6032 LegalizerHelper::LegalizeResult 6033 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 6034 Register DstReg = MI.getOperand(0).getReg(); 6035 Register Src0Reg = MI.getOperand(1).getReg(); 6036 Register Src1Reg = MI.getOperand(2).getReg(); 6037 LLT Src0Ty = MRI.getType(Src0Reg); 6038 LLT DstTy = MRI.getType(DstReg); 6039 LLT IdxTy = LLT::scalar(32); 6040 6041 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 6042 6043 if (DstTy.isScalar()) { 6044 if (Src0Ty.isVector()) 6045 return UnableToLegalize; 6046 6047 // This is just a SELECT. 6048 assert(Mask.size() == 1 && "Expected a single mask element"); 6049 Register Val; 6050 if (Mask[0] < 0 || Mask[0] > 1) 6051 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 6052 else 6053 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6054 MIRBuilder.buildCopy(DstReg, Val); 6055 MI.eraseFromParent(); 6056 return Legalized; 6057 } 6058 6059 Register Undef; 6060 SmallVector<Register, 32> BuildVec; 6061 LLT EltTy = DstTy.getElementType(); 6062 6063 for (int Idx : Mask) { 6064 if (Idx < 0) { 6065 if (!Undef.isValid()) 6066 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 6067 BuildVec.push_back(Undef); 6068 continue; 6069 } 6070 6071 if (Src0Ty.isScalar()) { 6072 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6073 } else { 6074 int NumElts = Src0Ty.getNumElements(); 6075 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 6076 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 6077 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 6078 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 6079 BuildVec.push_back(Extract.getReg(0)); 6080 } 6081 } 6082 6083 MIRBuilder.buildBuildVector(DstReg, BuildVec); 6084 MI.eraseFromParent(); 6085 return Legalized; 6086 } 6087 6088 LegalizerHelper::LegalizeResult 6089 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 6090 const auto &MF = *MI.getMF(); 6091 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 6092 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 6093 return UnableToLegalize; 6094 6095 Register Dst = MI.getOperand(0).getReg(); 6096 Register AllocSize = MI.getOperand(1).getReg(); 6097 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 6098 6099 LLT PtrTy = MRI.getType(Dst); 6100 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 6101 6102 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 6103 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 6104 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 6105 6106 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 6107 // have to generate an extra instruction to negate the alloc and then use 6108 // G_PTR_ADD to add the negative offset. 6109 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 6110 if (Alignment > Align(1)) { 6111 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 6112 AlignMask.negate(); 6113 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 6114 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 6115 } 6116 6117 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 6118 MIRBuilder.buildCopy(SPReg, SPTmp); 6119 MIRBuilder.buildCopy(Dst, SPTmp); 6120 6121 MI.eraseFromParent(); 6122 return Legalized; 6123 } 6124 6125 LegalizerHelper::LegalizeResult 6126 LegalizerHelper::lowerExtract(MachineInstr &MI) { 6127 Register Dst = MI.getOperand(0).getReg(); 6128 Register Src = MI.getOperand(1).getReg(); 6129 unsigned Offset = MI.getOperand(2).getImm(); 6130 6131 LLT DstTy = MRI.getType(Dst); 6132 LLT SrcTy = MRI.getType(Src); 6133 6134 if (DstTy.isScalar() && 6135 (SrcTy.isScalar() || 6136 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 6137 LLT SrcIntTy = SrcTy; 6138 if (!SrcTy.isScalar()) { 6139 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 6140 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 6141 } 6142 6143 if (Offset == 0) 6144 MIRBuilder.buildTrunc(Dst, Src); 6145 else { 6146 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 6147 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 6148 MIRBuilder.buildTrunc(Dst, Shr); 6149 } 6150 6151 MI.eraseFromParent(); 6152 return Legalized; 6153 } 6154 6155 return UnableToLegalize; 6156 } 6157 6158 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 6159 Register Dst = MI.getOperand(0).getReg(); 6160 Register Src = MI.getOperand(1).getReg(); 6161 Register InsertSrc = MI.getOperand(2).getReg(); 6162 uint64_t Offset = MI.getOperand(3).getImm(); 6163 6164 LLT DstTy = MRI.getType(Src); 6165 LLT InsertTy = MRI.getType(InsertSrc); 6166 6167 if (InsertTy.isVector() || 6168 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 6169 return UnableToLegalize; 6170 6171 const DataLayout &DL = MIRBuilder.getDataLayout(); 6172 if ((DstTy.isPointer() && 6173 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 6174 (InsertTy.isPointer() && 6175 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 6176 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 6177 return UnableToLegalize; 6178 } 6179 6180 LLT IntDstTy = DstTy; 6181 6182 if (!DstTy.isScalar()) { 6183 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 6184 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 6185 } 6186 6187 if (!InsertTy.isScalar()) { 6188 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 6189 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 6190 } 6191 6192 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 6193 if (Offset != 0) { 6194 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 6195 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 6196 } 6197 6198 APInt MaskVal = APInt::getBitsSetWithWrap( 6199 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 6200 6201 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 6202 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 6203 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 6204 6205 MIRBuilder.buildCast(Dst, Or); 6206 MI.eraseFromParent(); 6207 return Legalized; 6208 } 6209 6210 LegalizerHelper::LegalizeResult 6211 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 6212 Register Dst0 = MI.getOperand(0).getReg(); 6213 Register Dst1 = MI.getOperand(1).getReg(); 6214 Register LHS = MI.getOperand(2).getReg(); 6215 Register RHS = MI.getOperand(3).getReg(); 6216 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 6217 6218 LLT Ty = MRI.getType(Dst0); 6219 LLT BoolTy = MRI.getType(Dst1); 6220 6221 if (IsAdd) 6222 MIRBuilder.buildAdd(Dst0, LHS, RHS); 6223 else 6224 MIRBuilder.buildSub(Dst0, LHS, RHS); 6225 6226 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 6227 6228 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6229 6230 // For an addition, the result should be less than one of the operands (LHS) 6231 // if and only if the other operand (RHS) is negative, otherwise there will 6232 // be overflow. 6233 // For a subtraction, the result should be less than one of the operands 6234 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 6235 // otherwise there will be overflow. 6236 auto ResultLowerThanLHS = 6237 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 6238 auto ConditionRHS = MIRBuilder.buildICmp( 6239 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 6240 6241 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 6242 MI.eraseFromParent(); 6243 return Legalized; 6244 } 6245 6246 LegalizerHelper::LegalizeResult 6247 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 6248 Register Res = MI.getOperand(0).getReg(); 6249 Register LHS = MI.getOperand(1).getReg(); 6250 Register RHS = MI.getOperand(2).getReg(); 6251 LLT Ty = MRI.getType(Res); 6252 bool IsSigned; 6253 bool IsAdd; 6254 unsigned BaseOp; 6255 switch (MI.getOpcode()) { 6256 default: 6257 llvm_unreachable("unexpected addsat/subsat opcode"); 6258 case TargetOpcode::G_UADDSAT: 6259 IsSigned = false; 6260 IsAdd = true; 6261 BaseOp = TargetOpcode::G_ADD; 6262 break; 6263 case TargetOpcode::G_SADDSAT: 6264 IsSigned = true; 6265 IsAdd = true; 6266 BaseOp = TargetOpcode::G_ADD; 6267 break; 6268 case TargetOpcode::G_USUBSAT: 6269 IsSigned = false; 6270 IsAdd = false; 6271 BaseOp = TargetOpcode::G_SUB; 6272 break; 6273 case TargetOpcode::G_SSUBSAT: 6274 IsSigned = true; 6275 IsAdd = false; 6276 BaseOp = TargetOpcode::G_SUB; 6277 break; 6278 } 6279 6280 if (IsSigned) { 6281 // sadd.sat(a, b) -> 6282 // hi = 0x7fffffff - smax(a, 0) 6283 // lo = 0x80000000 - smin(a, 0) 6284 // a + smin(smax(lo, b), hi) 6285 // ssub.sat(a, b) -> 6286 // lo = smax(a, -1) - 0x7fffffff 6287 // hi = smin(a, -1) - 0x80000000 6288 // a - smin(smax(lo, b), hi) 6289 // TODO: AMDGPU can use a "median of 3" instruction here: 6290 // a +/- med3(lo, b, hi) 6291 uint64_t NumBits = Ty.getScalarSizeInBits(); 6292 auto MaxVal = 6293 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6294 auto MinVal = 6295 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6296 MachineInstrBuilder Hi, Lo; 6297 if (IsAdd) { 6298 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6299 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6300 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6301 } else { 6302 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6303 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6304 MaxVal); 6305 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6306 MinVal); 6307 } 6308 auto RHSClamped = 6309 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6310 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6311 } else { 6312 // uadd.sat(a, b) -> a + umin(~a, b) 6313 // usub.sat(a, b) -> a - umin(a, b) 6314 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6315 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6316 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6317 } 6318 6319 MI.eraseFromParent(); 6320 return Legalized; 6321 } 6322 6323 LegalizerHelper::LegalizeResult 6324 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6325 Register Res = MI.getOperand(0).getReg(); 6326 Register LHS = MI.getOperand(1).getReg(); 6327 Register RHS = MI.getOperand(2).getReg(); 6328 LLT Ty = MRI.getType(Res); 6329 LLT BoolTy = Ty.changeElementSize(1); 6330 bool IsSigned; 6331 bool IsAdd; 6332 unsigned OverflowOp; 6333 switch (MI.getOpcode()) { 6334 default: 6335 llvm_unreachable("unexpected addsat/subsat opcode"); 6336 case TargetOpcode::G_UADDSAT: 6337 IsSigned = false; 6338 IsAdd = true; 6339 OverflowOp = TargetOpcode::G_UADDO; 6340 break; 6341 case TargetOpcode::G_SADDSAT: 6342 IsSigned = true; 6343 IsAdd = true; 6344 OverflowOp = TargetOpcode::G_SADDO; 6345 break; 6346 case TargetOpcode::G_USUBSAT: 6347 IsSigned = false; 6348 IsAdd = false; 6349 OverflowOp = TargetOpcode::G_USUBO; 6350 break; 6351 case TargetOpcode::G_SSUBSAT: 6352 IsSigned = true; 6353 IsAdd = false; 6354 OverflowOp = TargetOpcode::G_SSUBO; 6355 break; 6356 } 6357 6358 auto OverflowRes = 6359 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6360 Register Tmp = OverflowRes.getReg(0); 6361 Register Ov = OverflowRes.getReg(1); 6362 MachineInstrBuilder Clamp; 6363 if (IsSigned) { 6364 // sadd.sat(a, b) -> 6365 // {tmp, ov} = saddo(a, b) 6366 // ov ? (tmp >>s 31) + 0x80000000 : r 6367 // ssub.sat(a, b) -> 6368 // {tmp, ov} = ssubo(a, b) 6369 // ov ? (tmp >>s 31) + 0x80000000 : r 6370 uint64_t NumBits = Ty.getScalarSizeInBits(); 6371 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6372 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6373 auto MinVal = 6374 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6375 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6376 } else { 6377 // uadd.sat(a, b) -> 6378 // {tmp, ov} = uaddo(a, b) 6379 // ov ? 0xffffffff : tmp 6380 // usub.sat(a, b) -> 6381 // {tmp, ov} = usubo(a, b) 6382 // ov ? 0 : tmp 6383 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6384 } 6385 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6386 6387 MI.eraseFromParent(); 6388 return Legalized; 6389 } 6390 6391 LegalizerHelper::LegalizeResult 6392 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6393 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6394 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6395 "Expected shlsat opcode!"); 6396 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6397 Register Res = MI.getOperand(0).getReg(); 6398 Register LHS = MI.getOperand(1).getReg(); 6399 Register RHS = MI.getOperand(2).getReg(); 6400 LLT Ty = MRI.getType(Res); 6401 LLT BoolTy = Ty.changeElementSize(1); 6402 6403 unsigned BW = Ty.getScalarSizeInBits(); 6404 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6405 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6406 : MIRBuilder.buildLShr(Ty, Result, RHS); 6407 6408 MachineInstrBuilder SatVal; 6409 if (IsSigned) { 6410 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6411 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6412 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6413 MIRBuilder.buildConstant(Ty, 0)); 6414 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6415 } else { 6416 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6417 } 6418 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6419 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6420 6421 MI.eraseFromParent(); 6422 return Legalized; 6423 } 6424 6425 LegalizerHelper::LegalizeResult 6426 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6427 Register Dst = MI.getOperand(0).getReg(); 6428 Register Src = MI.getOperand(1).getReg(); 6429 const LLT Ty = MRI.getType(Src); 6430 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6431 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6432 6433 // Swap most and least significant byte, set remaining bytes in Res to zero. 6434 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6435 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 6436 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6437 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 6438 6439 // Set i-th high/low byte in Res to i-th low/high byte from Src. 6440 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 6441 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 6442 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 6443 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 6444 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 6445 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 6446 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 6447 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 6448 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 6449 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 6450 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6451 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 6452 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 6453 } 6454 Res.getInstr()->getOperand(0).setReg(Dst); 6455 6456 MI.eraseFromParent(); 6457 return Legalized; 6458 } 6459 6460 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 6461 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 6462 MachineInstrBuilder Src, APInt Mask) { 6463 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 6464 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 6465 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 6466 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 6467 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 6468 return B.buildOr(Dst, LHS, RHS); 6469 } 6470 6471 LegalizerHelper::LegalizeResult 6472 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 6473 Register Dst = MI.getOperand(0).getReg(); 6474 Register Src = MI.getOperand(1).getReg(); 6475 const LLT Ty = MRI.getType(Src); 6476 unsigned Size = Ty.getSizeInBits(); 6477 6478 MachineInstrBuilder BSWAP = 6479 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 6480 6481 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 6482 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 6483 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 6484 MachineInstrBuilder Swap4 = 6485 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 6486 6487 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 6488 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 6489 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 6490 MachineInstrBuilder Swap2 = 6491 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 6492 6493 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 6494 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 6495 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 6496 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 6497 6498 MI.eraseFromParent(); 6499 return Legalized; 6500 } 6501 6502 LegalizerHelper::LegalizeResult 6503 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 6504 MachineFunction &MF = MIRBuilder.getMF(); 6505 6506 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 6507 int NameOpIdx = IsRead ? 1 : 0; 6508 int ValRegIndex = IsRead ? 0 : 1; 6509 6510 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 6511 const LLT Ty = MRI.getType(ValReg); 6512 const MDString *RegStr = cast<MDString>( 6513 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 6514 6515 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 6516 if (!PhysReg.isValid()) 6517 return UnableToLegalize; 6518 6519 if (IsRead) 6520 MIRBuilder.buildCopy(ValReg, PhysReg); 6521 else 6522 MIRBuilder.buildCopy(PhysReg, ValReg); 6523 6524 MI.eraseFromParent(); 6525 return Legalized; 6526 } 6527 6528 LegalizerHelper::LegalizeResult 6529 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 6530 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 6531 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 6532 Register Result = MI.getOperand(0).getReg(); 6533 LLT OrigTy = MRI.getType(Result); 6534 auto SizeInBits = OrigTy.getScalarSizeInBits(); 6535 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 6536 6537 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 6538 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 6539 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 6540 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 6541 6542 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 6543 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 6544 MIRBuilder.buildTrunc(Result, Shifted); 6545 6546 MI.eraseFromParent(); 6547 return Legalized; 6548 } 6549 6550 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 6551 // Implement vector G_SELECT in terms of XOR, AND, OR. 6552 Register DstReg = MI.getOperand(0).getReg(); 6553 Register MaskReg = MI.getOperand(1).getReg(); 6554 Register Op1Reg = MI.getOperand(2).getReg(); 6555 Register Op2Reg = MI.getOperand(3).getReg(); 6556 LLT DstTy = MRI.getType(DstReg); 6557 LLT MaskTy = MRI.getType(MaskReg); 6558 LLT Op1Ty = MRI.getType(Op1Reg); 6559 if (!DstTy.isVector()) 6560 return UnableToLegalize; 6561 6562 // Vector selects can have a scalar predicate. If so, splat into a vector and 6563 // finish for later legalization attempts to try again. 6564 if (MaskTy.isScalar()) { 6565 Register MaskElt = MaskReg; 6566 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 6567 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 6568 // Generate a vector splat idiom to be pattern matched later. 6569 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 6570 Observer.changingInstr(MI); 6571 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 6572 Observer.changedInstr(MI); 6573 return Legalized; 6574 } 6575 6576 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 6577 return UnableToLegalize; 6578 } 6579 6580 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 6581 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 6582 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 6583 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 6584 MI.eraseFromParent(); 6585 return Legalized; 6586 } 6587 6588 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) { 6589 // Split DIVREM into individual instructions. 6590 unsigned Opcode = MI.getOpcode(); 6591 6592 MIRBuilder.buildInstr( 6593 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV 6594 : TargetOpcode::G_UDIV, 6595 {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 6596 MIRBuilder.buildInstr( 6597 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM 6598 : TargetOpcode::G_UREM, 6599 {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 6600 MI.eraseFromParent(); 6601 return Legalized; 6602 } 6603