1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 
25 #include <sstream>
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 
31 LegalizerHelper::LegalizerHelper(MachineFunction &MF)
32     : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
33   MIRBuilder.setMF(MF);
34 }
35 
36 LegalizerHelper::LegalizeResult
37 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
38   DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
39 
40   auto Action = LI.getAction(MI, MRI);
41   switch (std::get<0>(Action)) {
42   case LegalizerInfo::Legal:
43     DEBUG(dbgs() << ".. Already legal\n");
44     return AlreadyLegal;
45   case LegalizerInfo::Libcall:
46     DEBUG(dbgs() << ".. Convert to libcall\n");
47     return libcall(MI);
48   case LegalizerInfo::NarrowScalar:
49     DEBUG(dbgs() << ".. Narrow scalar\n");
50     return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
51   case LegalizerInfo::WidenScalar:
52     DEBUG(dbgs() << ".. Widen scalar\n");
53     return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
54   case LegalizerInfo::Lower:
55     DEBUG(dbgs() << ".. Lower\n");
56     return lower(MI, std::get<1>(Action), std::get<2>(Action));
57   case LegalizerInfo::FewerElements:
58     DEBUG(dbgs() << ".. Reduce number of elements\n");
59     return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
60   case LegalizerInfo::Custom:
61     DEBUG(dbgs() << ".. Custom legalization\n");
62     return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
63                                                   : UnableToLegalize;
64   default:
65     DEBUG(dbgs() << ".. Unable to legalize\n");
66     return UnableToLegalize;
67   }
68 }
69 
70 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
71                                    SmallVectorImpl<unsigned> &VRegs) {
72   for (int i = 0; i < NumParts; ++i)
73     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
74   MIRBuilder.buildUnmerge(VRegs, Reg);
75 }
76 
77 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
78   switch (Opcode) {
79   case TargetOpcode::G_SDIV:
80     assert(Size == 32 && "Unsupported size");
81     return RTLIB::SDIV_I32;
82   case TargetOpcode::G_UDIV:
83     assert(Size == 32 && "Unsupported size");
84     return RTLIB::UDIV_I32;
85   case TargetOpcode::G_SREM:
86     assert(Size == 32 && "Unsupported size");
87     return RTLIB::SREM_I32;
88   case TargetOpcode::G_UREM:
89     assert(Size == 32 && "Unsupported size");
90     return RTLIB::UREM_I32;
91   case TargetOpcode::G_FADD:
92     assert((Size == 32 || Size == 64) && "Unsupported size");
93     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
94   case TargetOpcode::G_FREM:
95     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
96   case TargetOpcode::G_FPOW:
97     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
98   }
99   llvm_unreachable("Unknown libcall function");
100 }
101 
102 LegalizerHelper::LegalizeResult
103 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
104                     const CallLowering::ArgInfo &Result,
105                     ArrayRef<CallLowering::ArgInfo> Args) {
106   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
107   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
108   const char *Name = TLI.getLibcallName(Libcall);
109 
110   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
111   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
112                      MachineOperand::CreateES(Name), Result, Args))
113     return LegalizerHelper::UnableToLegalize;
114 
115   return LegalizerHelper::Legalized;
116 }
117 
118 static LegalizerHelper::LegalizeResult
119 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
120               Type *OpType) {
121   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
122   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
123                        {{MI.getOperand(1).getReg(), OpType},
124                         {MI.getOperand(2).getReg(), OpType}});
125 }
126 
127 LegalizerHelper::LegalizeResult
128 LegalizerHelper::libcall(MachineInstr &MI) {
129   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
130   unsigned Size = LLTy.getSizeInBits();
131   auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
132 
133   MIRBuilder.setInstr(MI);
134 
135   switch (MI.getOpcode()) {
136   default:
137     return UnableToLegalize;
138   case TargetOpcode::G_SDIV:
139   case TargetOpcode::G_UDIV:
140   case TargetOpcode::G_SREM:
141   case TargetOpcode::G_UREM: {
142     Type *HLTy = Type::getInt32Ty(Ctx);
143     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
144     if (Status != Legalized)
145       return Status;
146     break;
147   }
148   case TargetOpcode::G_FADD:
149   case TargetOpcode::G_FPOW:
150   case TargetOpcode::G_FREM: {
151     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
152     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
153     if (Status != Legalized)
154       return Status;
155     break;
156   }
157   }
158 
159   MI.eraseFromParent();
160   return Legalized;
161 }
162 
163 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
164                                                               unsigned TypeIdx,
165                                                               LLT NarrowTy) {
166   // FIXME: Don't know how to handle secondary types yet.
167   if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
168     return UnableToLegalize;
169 
170   MIRBuilder.setInstr(MI);
171 
172   switch (MI.getOpcode()) {
173   default:
174     return UnableToLegalize;
175   case TargetOpcode::G_IMPLICIT_DEF: {
176     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
177                    NarrowTy.getSizeInBits();
178 
179     SmallVector<unsigned, 2> DstRegs;
180     for (int i = 0; i < NumParts; ++i) {
181       unsigned Dst = MRI.createGenericVirtualRegister(NarrowTy);
182       MIRBuilder.buildUndef(Dst);
183       DstRegs.push_back(Dst);
184     }
185     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
186     MI.eraseFromParent();
187     return Legalized;
188   }
189   case TargetOpcode::G_ADD: {
190     // Expand in terms of carry-setting/consuming G_ADDE instructions.
191     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
192                    NarrowTy.getSizeInBits();
193 
194     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
195     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
196     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
197 
198     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
199     MIRBuilder.buildConstant(CarryIn, 0);
200 
201     for (int i = 0; i < NumParts; ++i) {
202       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
203       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
204 
205       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
206                             Src2Regs[i], CarryIn);
207 
208       DstRegs.push_back(DstReg);
209       CarryIn = CarryOut;
210     }
211     unsigned DstReg = MI.getOperand(0).getReg();
212     MIRBuilder.buildMerge(DstReg, DstRegs);
213     MI.eraseFromParent();
214     return Legalized;
215   }
216   case TargetOpcode::G_EXTRACT: {
217     if (TypeIdx != 1)
218       return UnableToLegalize;
219 
220     int64_t NarrowSize = NarrowTy.getSizeInBits();
221     int NumParts =
222         MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() / NarrowSize;
223 
224     SmallVector<unsigned, 2> SrcRegs, DstRegs;
225     SmallVector<uint64_t, 2> Indexes;
226     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
227 
228     unsigned OpReg = MI.getOperand(0).getReg();
229     int64_t OpStart = MI.getOperand(2).getImm();
230     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
231     for (int i = 0; i < NumParts; ++i) {
232       unsigned SrcStart = i * NarrowSize;
233 
234       if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
235         // No part of the extract uses this subregister, ignore it.
236         continue;
237       } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
238         // The entire subregister is extracted, forward the value.
239         DstRegs.push_back(SrcRegs[i]);
240         continue;
241       }
242 
243       // OpSegStart is where this destination segment would start in OpReg if it
244       // extended infinitely in both directions.
245       int64_t ExtractOffset, SegSize;
246       if (OpStart < SrcStart) {
247         ExtractOffset = 0;
248         SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
249       } else {
250         ExtractOffset = OpStart - SrcStart;
251         SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
252       }
253 
254       unsigned SegReg = SrcRegs[i];
255       if (ExtractOffset != 0 || SegSize != NarrowSize) {
256         // A genuine extract is needed.
257         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
258         MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
259       }
260 
261       DstRegs.push_back(SegReg);
262     }
263 
264     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
265     MI.eraseFromParent();
266     return Legalized;
267   }
268   case TargetOpcode::G_INSERT: {
269     if (TypeIdx != 0)
270       return UnableToLegalize;
271 
272     int64_t NarrowSize = NarrowTy.getSizeInBits();
273     int NumParts =
274         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
275 
276     SmallVector<unsigned, 2> SrcRegs, DstRegs;
277     SmallVector<uint64_t, 2> Indexes;
278     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
279 
280     unsigned OpReg = MI.getOperand(2).getReg();
281     int64_t OpStart = MI.getOperand(3).getImm();
282     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
283     for (int i = 0; i < NumParts; ++i) {
284       unsigned DstStart = i * NarrowSize;
285 
286       if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
287         // No part of the insert affects this subregister, forward the original.
288         DstRegs.push_back(SrcRegs[i]);
289         continue;
290       } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
291         // The entire subregister is defined by this insert, forward the new
292         // value.
293         DstRegs.push_back(OpReg);
294         continue;
295       }
296 
297       // OpSegStart is where this destination segment would start in OpReg if it
298       // extended infinitely in both directions.
299       int64_t ExtractOffset, InsertOffset, SegSize;
300       if (OpStart < DstStart) {
301         InsertOffset = 0;
302         ExtractOffset = DstStart - OpStart;
303         SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
304       } else {
305         InsertOffset = OpStart - DstStart;
306         ExtractOffset = 0;
307         SegSize =
308             std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
309       }
310 
311       unsigned SegReg = OpReg;
312       if (ExtractOffset != 0 || SegSize != OpSize) {
313         // A genuine extract is needed.
314         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
315         MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
316       }
317 
318       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
319       MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
320       DstRegs.push_back(DstReg);
321     }
322 
323     assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
324     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
325     MI.eraseFromParent();
326     return Legalized;
327   }
328   case TargetOpcode::G_LOAD: {
329     unsigned NarrowSize = NarrowTy.getSizeInBits();
330     int NumParts =
331         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
332     LLT OffsetTy = LLT::scalar(
333         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
334 
335     SmallVector<unsigned, 2> DstRegs;
336     for (int i = 0; i < NumParts; ++i) {
337       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
338       unsigned SrcReg = 0;
339       unsigned Adjustment = i * NarrowSize / 8;
340 
341       MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
342                                 Adjustment);
343 
344       // TODO: This is conservatively correct, but we probably want to split the
345       // memory operands in the future.
346       MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
347 
348       DstRegs.push_back(DstReg);
349     }
350     unsigned DstReg = MI.getOperand(0).getReg();
351     MIRBuilder.buildMerge(DstReg, DstRegs);
352     MI.eraseFromParent();
353     return Legalized;
354   }
355   case TargetOpcode::G_STORE: {
356     unsigned NarrowSize = NarrowTy.getSizeInBits();
357     int NumParts =
358         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
359     LLT OffsetTy = LLT::scalar(
360         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
361 
362     SmallVector<unsigned, 2> SrcRegs;
363     extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
364 
365     for (int i = 0; i < NumParts; ++i) {
366       unsigned DstReg = 0;
367       unsigned Adjustment = i * NarrowSize / 8;
368 
369       MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
370                                 Adjustment);
371 
372       // TODO: This is conservatively correct, but we probably want to split the
373       // memory operands in the future.
374       MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
375     }
376     MI.eraseFromParent();
377     return Legalized;
378   }
379   case TargetOpcode::G_CONSTANT: {
380     unsigned NarrowSize = NarrowTy.getSizeInBits();
381     int NumParts =
382         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
383     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
384     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
385 
386     SmallVector<unsigned, 2> DstRegs;
387     for (int i = 0; i < NumParts; ++i) {
388       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
389       ConstantInt *CI =
390           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
391       MIRBuilder.buildConstant(DstReg, *CI);
392       DstRegs.push_back(DstReg);
393     }
394     unsigned DstReg = MI.getOperand(0).getReg();
395     MIRBuilder.buildMerge(DstReg, DstRegs);
396     MI.eraseFromParent();
397     return Legalized;
398   }
399   case TargetOpcode::G_OR: {
400     // Legalize bitwise operation:
401     // A = BinOp<Ty> B, C
402     // into:
403     // B1, ..., BN = G_UNMERGE_VALUES B
404     // C1, ..., CN = G_UNMERGE_VALUES C
405     // A1 = BinOp<Ty/N> B1, C2
406     // ...
407     // AN = BinOp<Ty/N> BN, CN
408     // A = G_MERGE_VALUES A1, ..., AN
409     unsigned NarrowSize = NarrowTy.getSizeInBits();
410     int NumParts =
411         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
412 
413     // List the registers where the destination will be scattered.
414     SmallVector<unsigned, 2> DstRegs;
415     // List the registers where the first argument will be split.
416     SmallVector<unsigned, 2> SrcsReg1;
417     // List the registers where the second argument will be split.
418     SmallVector<unsigned, 2> SrcsReg2;
419     // Create all the temporary registers.
420     for (int i = 0; i < NumParts; ++i) {
421       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
422       unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
423       unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
424 
425       DstRegs.push_back(DstReg);
426       SrcsReg1.push_back(SrcReg1);
427       SrcsReg2.push_back(SrcReg2);
428     }
429     // Explode the big arguments into smaller chunks.
430     MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
431     MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
432 
433     // Do the operation on each small part.
434     for (int i = 0; i < NumParts; ++i)
435       MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]);
436 
437     // Gather the destination registers into the final destination.
438     unsigned DstReg = MI.getOperand(0).getReg();
439     MIRBuilder.buildMerge(DstReg, DstRegs);
440     MI.eraseFromParent();
441     return Legalized;
442   }
443   }
444 }
445 
446 LegalizerHelper::LegalizeResult
447 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
448   MIRBuilder.setInstr(MI);
449 
450   switch (MI.getOpcode()) {
451   default:
452     return UnableToLegalize;
453   case TargetOpcode::G_ADD:
454   case TargetOpcode::G_AND:
455   case TargetOpcode::G_MUL:
456   case TargetOpcode::G_OR:
457   case TargetOpcode::G_XOR:
458   case TargetOpcode::G_SUB:
459   case TargetOpcode::G_SHL: {
460     // Perform operation at larger width (any extension is fine here, high bits
461     // don't affect the result) and then truncate the result back to the
462     // original type.
463     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
464     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
465     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
466     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
467 
468     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
469     MIRBuilder.buildInstr(MI.getOpcode())
470         .addDef(DstExt)
471         .addUse(Src1Ext)
472         .addUse(Src2Ext);
473 
474     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
475     MI.eraseFromParent();
476     return Legalized;
477   }
478   case TargetOpcode::G_SDIV:
479   case TargetOpcode::G_UDIV:
480   case TargetOpcode::G_SREM:
481   case TargetOpcode::G_UREM:
482   case TargetOpcode::G_ASHR:
483   case TargetOpcode::G_LSHR: {
484     unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
485                              MI.getOpcode() == TargetOpcode::G_SREM ||
486                              MI.getOpcode() == TargetOpcode::G_ASHR
487                          ? TargetOpcode::G_SEXT
488                          : TargetOpcode::G_ZEXT;
489 
490     unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
491     MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
492         MI.getOperand(1).getReg());
493 
494     unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
495     MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
496         MI.getOperand(2).getReg());
497 
498     unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
499     MIRBuilder.buildInstr(MI.getOpcode())
500         .addDef(ResExt)
501         .addUse(LHSExt)
502         .addUse(RHSExt);
503 
504     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
505     MI.eraseFromParent();
506     return Legalized;
507   }
508   case TargetOpcode::G_SELECT: {
509     if (TypeIdx != 0)
510       return UnableToLegalize;
511 
512     // Perform operation at larger width (any extension is fine here, high bits
513     // don't affect the result) and then truncate the result back to the
514     // original type.
515     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
516     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
517     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
518     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
519 
520     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
521     MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
522         .addDef(DstExt)
523         .addReg(MI.getOperand(1).getReg())
524         .addUse(Src1Ext)
525         .addUse(Src2Ext);
526 
527     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
528     MI.eraseFromParent();
529     return Legalized;
530   }
531   case TargetOpcode::G_FPTOSI:
532   case TargetOpcode::G_FPTOUI: {
533     if (TypeIdx != 0)
534       return UnableToLegalize;
535 
536     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
537     MIRBuilder.buildInstr(MI.getOpcode())
538         .addDef(DstExt)
539         .addUse(MI.getOperand(1).getReg());
540 
541     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
542     MI.eraseFromParent();
543     return Legalized;
544   }
545   case TargetOpcode::G_SITOFP:
546   case TargetOpcode::G_UITOFP: {
547     if (TypeIdx != 1)
548       return UnableToLegalize;
549 
550     unsigned Src = MI.getOperand(1).getReg();
551     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
552 
553     if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
554       MIRBuilder.buildSExt(SrcExt, Src);
555     } else {
556       assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
557       MIRBuilder.buildZExt(SrcExt, Src);
558     }
559 
560     MIRBuilder.buildInstr(MI.getOpcode())
561         .addDef(MI.getOperand(0).getReg())
562         .addUse(SrcExt);
563 
564     MI.eraseFromParent();
565     return Legalized;
566   }
567   case TargetOpcode::G_INSERT: {
568     if (TypeIdx != 0)
569       return UnableToLegalize;
570 
571     unsigned Src = MI.getOperand(1).getReg();
572     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
573     MIRBuilder.buildAnyExt(SrcExt, Src);
574 
575     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
576     auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
577                                       MI.getOperand(3).getImm());
578     for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
579       MIB.addReg(MI.getOperand(OpNum).getReg());
580       MIB.addImm(MI.getOperand(OpNum + 1).getImm());
581     }
582 
583     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
584     MI.eraseFromParent();
585     return Legalized;
586   }
587   case TargetOpcode::G_LOAD: {
588     assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
589                WideTy.getSizeInBits() &&
590            "illegal to increase number of bytes loaded");
591 
592     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
593     MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
594                          **MI.memoperands_begin());
595     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
596     MI.eraseFromParent();
597     return Legalized;
598   }
599   case TargetOpcode::G_STORE: {
600     if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
601         WideTy != LLT::scalar(8))
602       return UnableToLegalize;
603 
604     auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
605     auto Content = TLI.getBooleanContents(false, false);
606 
607     unsigned ExtOp = TargetOpcode::G_ANYEXT;
608     if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
609       ExtOp = TargetOpcode::G_ZEXT;
610     else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
611       ExtOp = TargetOpcode::G_SEXT;
612     else
613       ExtOp = TargetOpcode::G_ANYEXT;
614 
615     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
616     MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
617         MI.getOperand(0).getReg());
618     MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
619                           **MI.memoperands_begin());
620     MI.eraseFromParent();
621     return Legalized;
622   }
623   case TargetOpcode::G_CONSTANT: {
624     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
625     MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
626     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
627     MI.eraseFromParent();
628     return Legalized;
629   }
630   case TargetOpcode::G_FCONSTANT: {
631     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
632     MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
633     MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
634     MI.eraseFromParent();
635     return Legalized;
636   }
637   case TargetOpcode::G_BRCOND: {
638     unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
639     MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
640     MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
641     MI.eraseFromParent();
642     return Legalized;
643   }
644   case TargetOpcode::G_FCMP: {
645     unsigned Op0Ext, Op1Ext, DstReg;
646     unsigned Cmp1 = MI.getOperand(2).getReg();
647     unsigned Cmp2 = MI.getOperand(3).getReg();
648     if (TypeIdx == 0) {
649       Op0Ext = Cmp1;
650       Op1Ext = Cmp2;
651       DstReg = MRI.createGenericVirtualRegister(WideTy);
652     } else {
653       Op0Ext = MRI.createGenericVirtualRegister(WideTy);
654       Op1Ext = MRI.createGenericVirtualRegister(WideTy);
655       DstReg = MI.getOperand(0).getReg();
656       MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op0Ext, Cmp1);
657       MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op1Ext, Cmp2);
658     }
659     MIRBuilder.buildFCmp(
660         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
661         DstReg, Op0Ext, Op1Ext);
662     if (TypeIdx == 0)
663       MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
664                             DstReg);
665     MI.eraseFromParent();
666     return Legalized;
667   }
668   case TargetOpcode::G_ICMP: {
669     bool IsSigned = CmpInst::isSigned(
670         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
671     unsigned Cmp1 = MI.getOperand(2).getReg();
672     unsigned Cmp2 = MI.getOperand(3).getReg();
673     unsigned Op0Ext, Op1Ext, DstReg;
674     if (TypeIdx == 0) {
675       Op0Ext = Cmp1;
676       Op1Ext = Cmp2;
677       DstReg = MRI.createGenericVirtualRegister(WideTy);
678     } else {
679       Op0Ext = MRI.createGenericVirtualRegister(WideTy);
680       Op1Ext = MRI.createGenericVirtualRegister(WideTy);
681       DstReg = MI.getOperand(0).getReg();
682       if (IsSigned) {
683         MIRBuilder.buildSExt(Op0Ext, Cmp1);
684         MIRBuilder.buildSExt(Op1Ext, Cmp2);
685       } else {
686         MIRBuilder.buildZExt(Op0Ext, Cmp1);
687         MIRBuilder.buildZExt(Op1Ext, Cmp2);
688       }
689     }
690     MIRBuilder.buildICmp(
691         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
692         DstReg, Op0Ext, Op1Ext);
693     if (TypeIdx == 0)
694       MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
695                             DstReg);
696     MI.eraseFromParent();
697     return Legalized;
698   }
699   case TargetOpcode::G_GEP: {
700     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
701     unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
702     MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
703     MI.getOperand(2).setReg(OffsetExt);
704     return Legalized;
705   }
706   case TargetOpcode::G_PHI: {
707     assert(TypeIdx == 0 && "Expecting only Idx 0");
708     auto getExtendedReg = [&](unsigned Reg, MachineBasicBlock &MBB) {
709       auto FirstTermIt = MBB.getFirstTerminator();
710       MIRBuilder.setInsertPt(MBB, FirstTermIt);
711       MachineInstr *DefMI = MRI.getVRegDef(Reg);
712       MachineInstrBuilder MIB;
713       if (DefMI->getOpcode() == TargetOpcode::G_TRUNC)
714         MIB = MIRBuilder.buildAnyExtOrTrunc(WideTy,
715                                             DefMI->getOperand(1).getReg());
716       else
717         MIB = MIRBuilder.buildAnyExt(WideTy, Reg);
718       return MIB->getOperand(0).getReg();
719     };
720     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, WideTy);
721     for (auto OpIt = MI.operands_begin() + 1, OpE = MI.operands_end();
722          OpIt != OpE;) {
723       unsigned Reg = OpIt++->getReg();
724       MachineBasicBlock *OpMBB = OpIt++->getMBB();
725       MIB.addReg(getExtendedReg(Reg, *OpMBB));
726       MIB.addMBB(OpMBB);
727     }
728     auto *MBB = MI.getParent();
729     MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
730     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(),
731                           MIB->getOperand(0).getReg());
732     MI.eraseFromParent();
733     return Legalized;
734   }
735   }
736 }
737 
738 LegalizerHelper::LegalizeResult
739 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
740   using namespace TargetOpcode;
741   MIRBuilder.setInstr(MI);
742 
743   switch(MI.getOpcode()) {
744   default:
745     return UnableToLegalize;
746   case TargetOpcode::G_SREM:
747   case TargetOpcode::G_UREM: {
748     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
749     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
750         .addDef(QuotReg)
751         .addUse(MI.getOperand(1).getReg())
752         .addUse(MI.getOperand(2).getReg());
753 
754     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
755     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
756     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
757                         ProdReg);
758     MI.eraseFromParent();
759     return Legalized;
760   }
761   case TargetOpcode::G_SMULO:
762   case TargetOpcode::G_UMULO: {
763     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
764     // result.
765     unsigned Res = MI.getOperand(0).getReg();
766     unsigned Overflow = MI.getOperand(1).getReg();
767     unsigned LHS = MI.getOperand(2).getReg();
768     unsigned RHS = MI.getOperand(3).getReg();
769 
770     MIRBuilder.buildMul(Res, LHS, RHS);
771 
772     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
773                           ? TargetOpcode::G_SMULH
774                           : TargetOpcode::G_UMULH;
775 
776     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
777     MIRBuilder.buildInstr(Opcode)
778       .addDef(HiPart)
779       .addUse(LHS)
780       .addUse(RHS);
781 
782     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
783     MIRBuilder.buildConstant(Zero, 0);
784     MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
785     MI.eraseFromParent();
786     return Legalized;
787   }
788   case TargetOpcode::G_FNEG: {
789     // TODO: Handle vector types once we are able to
790     // represent them.
791     if (Ty.isVector())
792       return UnableToLegalize;
793     unsigned Res = MI.getOperand(0).getReg();
794     Type *ZeroTy;
795     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
796     switch (Ty.getSizeInBits()) {
797     case 16:
798       ZeroTy = Type::getHalfTy(Ctx);
799       break;
800     case 32:
801       ZeroTy = Type::getFloatTy(Ctx);
802       break;
803     case 64:
804       ZeroTy = Type::getDoubleTy(Ctx);
805       break;
806     default:
807       llvm_unreachable("unexpected floating-point type");
808     }
809     ConstantFP &ZeroForNegation =
810         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
811     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
812     MIRBuilder.buildFConstant(Zero, ZeroForNegation);
813     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
814         .addDef(Res)
815         .addUse(Zero)
816         .addUse(MI.getOperand(1).getReg());
817     MI.eraseFromParent();
818     return Legalized;
819   }
820   case TargetOpcode::G_FSUB: {
821     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
822     // First, check if G_FNEG is marked as Lower. If so, we may
823     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
824     if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
825       return UnableToLegalize;
826     unsigned Res = MI.getOperand(0).getReg();
827     unsigned LHS = MI.getOperand(1).getReg();
828     unsigned RHS = MI.getOperand(2).getReg();
829     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
830     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
831     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
832         .addDef(Res)
833         .addUse(LHS)
834         .addUse(Neg);
835     MI.eraseFromParent();
836     return Legalized;
837   }
838   }
839 }
840 
841 LegalizerHelper::LegalizeResult
842 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
843                                      LLT NarrowTy) {
844   // FIXME: Don't know how to handle secondary types yet.
845   if (TypeIdx != 0)
846     return UnableToLegalize;
847   switch (MI.getOpcode()) {
848   default:
849     return UnableToLegalize;
850   case TargetOpcode::G_ADD: {
851     unsigned NarrowSize = NarrowTy.getSizeInBits();
852     unsigned DstReg = MI.getOperand(0).getReg();
853     int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
854 
855     MIRBuilder.setInstr(MI);
856 
857     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
858     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
859     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
860 
861     for (int i = 0; i < NumParts; ++i) {
862       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
863       MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
864       DstRegs.push_back(DstReg);
865     }
866 
867     MIRBuilder.buildMerge(DstReg, DstRegs);
868     MI.eraseFromParent();
869     return Legalized;
870   }
871   }
872 }
873