1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   auto Step = LI.getAction(MI, MRI);
86   switch (Step.Action) {
87   case Legal:
88     LLVM_DEBUG(dbgs() << ".. Already legal\n");
89     return AlreadyLegal;
90   case Libcall:
91     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
92     return libcall(MI);
93   case NarrowScalar:
94     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
95     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
96   case WidenScalar:
97     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
98     return widenScalar(MI, Step.TypeIdx, Step.NewType);
99   case Lower:
100     LLVM_DEBUG(dbgs() << ".. Lower\n");
101     return lower(MI, Step.TypeIdx, Step.NewType);
102   case FewerElements:
103     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
104     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
105   case MoreElements:
106     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
107     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
108   case Custom:
109     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
110     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
111                                                             : UnableToLegalize;
112   default:
113     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
114     return UnableToLegalize;
115   }
116 }
117 
118 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
119                                    SmallVectorImpl<unsigned> &VRegs) {
120   for (int i = 0; i < NumParts; ++i)
121     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
122   MIRBuilder.buildUnmerge(VRegs, Reg);
123 }
124 
125 bool LegalizerHelper::extractParts(unsigned Reg, LLT RegTy,
126                                    LLT MainTy, LLT &LeftoverTy,
127                                    SmallVectorImpl<unsigned> &VRegs,
128                                    SmallVectorImpl<unsigned> &LeftoverRegs) {
129   assert(!LeftoverTy.isValid() && "this is an out argument");
130 
131   unsigned RegSize = RegTy.getSizeInBits();
132   unsigned MainSize = MainTy.getSizeInBits();
133   unsigned NumParts = RegSize / MainSize;
134   unsigned LeftoverSize = RegSize - NumParts * MainSize;
135 
136   // Use an unmerge when possible.
137   if (LeftoverSize == 0) {
138     for (unsigned I = 0; I < NumParts; ++I)
139       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
140     MIRBuilder.buildUnmerge(VRegs, Reg);
141     return true;
142   }
143 
144   if (MainTy.isVector()) {
145     unsigned EltSize = MainTy.getScalarSizeInBits();
146     if (LeftoverSize % EltSize != 0)
147       return false;
148     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
149   } else {
150     LeftoverTy = LLT::scalar(LeftoverSize);
151   }
152 
153   // For irregular sizes, extract the individual parts.
154   for (unsigned I = 0; I != NumParts; ++I) {
155     unsigned NewReg = MRI.createGenericVirtualRegister(MainTy);
156     VRegs.push_back(NewReg);
157     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
158   }
159 
160   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
161        Offset += LeftoverSize) {
162     unsigned NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
163     LeftoverRegs.push_back(NewReg);
164     MIRBuilder.buildExtract(NewReg, Reg, Offset);
165   }
166 
167   return true;
168 }
169 
170 void LegalizerHelper::insertParts(unsigned DstReg,
171                                   LLT ResultTy, LLT PartTy,
172                                   ArrayRef<unsigned> PartRegs,
173                                   LLT LeftoverTy,
174                                   ArrayRef<unsigned> LeftoverRegs) {
175   if (!LeftoverTy.isValid()) {
176     assert(LeftoverRegs.empty());
177 
178     if (!ResultTy.isVector()) {
179       MIRBuilder.buildMerge(DstReg, PartRegs);
180       return;
181     }
182 
183     if (PartTy.isVector())
184       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
185     else
186       MIRBuilder.buildBuildVector(DstReg, PartRegs);
187     return;
188   }
189 
190   unsigned PartSize = PartTy.getSizeInBits();
191   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
192 
193   unsigned CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
194   MIRBuilder.buildUndef(CurResultReg);
195 
196   unsigned Offset = 0;
197   for (unsigned PartReg : PartRegs) {
198     unsigned NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
199     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
200     CurResultReg = NewResultReg;
201     Offset += PartSize;
202   }
203 
204   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
205     // Use the original output register for the final insert to avoid a copy.
206     unsigned NewResultReg = (I + 1 == E) ?
207       DstReg : MRI.createGenericVirtualRegister(ResultTy);
208 
209     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
210     CurResultReg = NewResultReg;
211     Offset += LeftoverPartSize;
212   }
213 }
214 
215 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
216   switch (Opcode) {
217   case TargetOpcode::G_SDIV:
218     assert((Size == 32 || Size == 64) && "Unsupported size");
219     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
220   case TargetOpcode::G_UDIV:
221     assert((Size == 32 || Size == 64) && "Unsupported size");
222     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
223   case TargetOpcode::G_SREM:
224     assert((Size == 32 || Size == 64) && "Unsupported size");
225     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
226   case TargetOpcode::G_UREM:
227     assert((Size == 32 || Size == 64) && "Unsupported size");
228     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
229   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
230     assert(Size == 32 && "Unsupported size");
231     return RTLIB::CTLZ_I32;
232   case TargetOpcode::G_FADD:
233     assert((Size == 32 || Size == 64) && "Unsupported size");
234     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
235   case TargetOpcode::G_FSUB:
236     assert((Size == 32 || Size == 64) && "Unsupported size");
237     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
238   case TargetOpcode::G_FMUL:
239     assert((Size == 32 || Size == 64) && "Unsupported size");
240     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
241   case TargetOpcode::G_FDIV:
242     assert((Size == 32 || Size == 64) && "Unsupported size");
243     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
244   case TargetOpcode::G_FEXP:
245     assert((Size == 32 || Size == 64) && "Unsupported size");
246     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
247   case TargetOpcode::G_FEXP2:
248     assert((Size == 32 || Size == 64) && "Unsupported size");
249     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
250   case TargetOpcode::G_FREM:
251     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
252   case TargetOpcode::G_FPOW:
253     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
254   case TargetOpcode::G_FMA:
255     assert((Size == 32 || Size == 64) && "Unsupported size");
256     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
257   case TargetOpcode::G_FSIN:
258     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
259     return Size == 128 ? RTLIB::SIN_F128
260                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
261   case TargetOpcode::G_FCOS:
262     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
263     return Size == 128 ? RTLIB::COS_F128
264                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
265   case TargetOpcode::G_FLOG10:
266     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
267     return Size == 128 ? RTLIB::LOG10_F128
268                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
269   case TargetOpcode::G_FLOG:
270     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
271     return Size == 128 ? RTLIB::LOG_F128
272                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
273   case TargetOpcode::G_FLOG2:
274     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
275     return Size == 128 ? RTLIB::LOG2_F128
276                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
277   }
278   llvm_unreachable("Unknown libcall function");
279 }
280 
281 LegalizerHelper::LegalizeResult
282 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
283                     const CallLowering::ArgInfo &Result,
284                     ArrayRef<CallLowering::ArgInfo> Args) {
285   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
286   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
287   const char *Name = TLI.getLibcallName(Libcall);
288 
289   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
290   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
291                      MachineOperand::CreateES(Name), Result, Args))
292     return LegalizerHelper::UnableToLegalize;
293 
294   return LegalizerHelper::Legalized;
295 }
296 
297 // Useful for libcalls where all operands have the same type.
298 static LegalizerHelper::LegalizeResult
299 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
300               Type *OpType) {
301   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
302 
303   SmallVector<CallLowering::ArgInfo, 3> Args;
304   for (unsigned i = 1; i < MI.getNumOperands(); i++)
305     Args.push_back({MI.getOperand(i).getReg(), OpType});
306   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
307                        Args);
308 }
309 
310 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
311                                        Type *FromType) {
312   auto ToMVT = MVT::getVT(ToType);
313   auto FromMVT = MVT::getVT(FromType);
314 
315   switch (Opcode) {
316   case TargetOpcode::G_FPEXT:
317     return RTLIB::getFPEXT(FromMVT, ToMVT);
318   case TargetOpcode::G_FPTRUNC:
319     return RTLIB::getFPROUND(FromMVT, ToMVT);
320   case TargetOpcode::G_FPTOSI:
321     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
322   case TargetOpcode::G_FPTOUI:
323     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
324   case TargetOpcode::G_SITOFP:
325     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
326   case TargetOpcode::G_UITOFP:
327     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
328   }
329   llvm_unreachable("Unsupported libcall function");
330 }
331 
332 static LegalizerHelper::LegalizeResult
333 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
334                   Type *FromType) {
335   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
336   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
337                        {{MI.getOperand(1).getReg(), FromType}});
338 }
339 
340 LegalizerHelper::LegalizeResult
341 LegalizerHelper::libcall(MachineInstr &MI) {
342   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
343   unsigned Size = LLTy.getSizeInBits();
344   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
345 
346   MIRBuilder.setInstr(MI);
347 
348   switch (MI.getOpcode()) {
349   default:
350     return UnableToLegalize;
351   case TargetOpcode::G_SDIV:
352   case TargetOpcode::G_UDIV:
353   case TargetOpcode::G_SREM:
354   case TargetOpcode::G_UREM:
355   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
356     Type *HLTy = IntegerType::get(Ctx, Size);
357     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
358     if (Status != Legalized)
359       return Status;
360     break;
361   }
362   case TargetOpcode::G_FADD:
363   case TargetOpcode::G_FSUB:
364   case TargetOpcode::G_FMUL:
365   case TargetOpcode::G_FDIV:
366   case TargetOpcode::G_FMA:
367   case TargetOpcode::G_FPOW:
368   case TargetOpcode::G_FREM:
369   case TargetOpcode::G_FCOS:
370   case TargetOpcode::G_FSIN:
371   case TargetOpcode::G_FLOG10:
372   case TargetOpcode::G_FLOG:
373   case TargetOpcode::G_FLOG2:
374   case TargetOpcode::G_FEXP:
375   case TargetOpcode::G_FEXP2: {
376     if (Size > 64) {
377       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
378       return UnableToLegalize;
379     }
380     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
381     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
382     if (Status != Legalized)
383       return Status;
384     break;
385   }
386   case TargetOpcode::G_FPEXT: {
387     // FIXME: Support other floating point types (half, fp128 etc)
388     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
389     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
390     if (ToSize != 64 || FromSize != 32)
391       return UnableToLegalize;
392     LegalizeResult Status = conversionLibcall(
393         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
394     if (Status != Legalized)
395       return Status;
396     break;
397   }
398   case TargetOpcode::G_FPTRUNC: {
399     // FIXME: Support other floating point types (half, fp128 etc)
400     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
401     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
402     if (ToSize != 32 || FromSize != 64)
403       return UnableToLegalize;
404     LegalizeResult Status = conversionLibcall(
405         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
406     if (Status != Legalized)
407       return Status;
408     break;
409   }
410   case TargetOpcode::G_FPTOSI:
411   case TargetOpcode::G_FPTOUI: {
412     // FIXME: Support other types
413     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
414     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
415     if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
416       return UnableToLegalize;
417     LegalizeResult Status = conversionLibcall(
418         MI, MIRBuilder, Type::getInt32Ty(Ctx),
419         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
420     if (Status != Legalized)
421       return Status;
422     break;
423   }
424   case TargetOpcode::G_SITOFP:
425   case TargetOpcode::G_UITOFP: {
426     // FIXME: Support other types
427     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
428     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
429     if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
430       return UnableToLegalize;
431     LegalizeResult Status = conversionLibcall(
432         MI, MIRBuilder,
433         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
434         Type::getInt32Ty(Ctx));
435     if (Status != Legalized)
436       return Status;
437     break;
438   }
439   }
440 
441   MI.eraseFromParent();
442   return Legalized;
443 }
444 
445 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
446                                                               unsigned TypeIdx,
447                                                               LLT NarrowTy) {
448   MIRBuilder.setInstr(MI);
449 
450   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
451   uint64_t NarrowSize = NarrowTy.getSizeInBits();
452 
453   switch (MI.getOpcode()) {
454   default:
455     return UnableToLegalize;
456   case TargetOpcode::G_IMPLICIT_DEF: {
457     // FIXME: add support for when SizeOp0 isn't an exact multiple of
458     // NarrowSize.
459     if (SizeOp0 % NarrowSize != 0)
460       return UnableToLegalize;
461     int NumParts = SizeOp0 / NarrowSize;
462 
463     SmallVector<unsigned, 2> DstRegs;
464     for (int i = 0; i < NumParts; ++i)
465       DstRegs.push_back(
466           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
467 
468     unsigned DstReg = MI.getOperand(0).getReg();
469     if(MRI.getType(DstReg).isVector())
470       MIRBuilder.buildBuildVector(DstReg, DstRegs);
471     else
472       MIRBuilder.buildMerge(DstReg, DstRegs);
473     MI.eraseFromParent();
474     return Legalized;
475   }
476   case TargetOpcode::G_CONSTANT: {
477     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
478     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
479     unsigned TotalSize = Ty.getSizeInBits();
480     unsigned NarrowSize = NarrowTy.getSizeInBits();
481     int NumParts = TotalSize / NarrowSize;
482 
483     SmallVector<unsigned, 4> PartRegs;
484     for (int I = 0; I != NumParts; ++I) {
485       unsigned Offset = I * NarrowSize;
486       auto K = MIRBuilder.buildConstant(NarrowTy,
487                                         Val.lshr(Offset).trunc(NarrowSize));
488       PartRegs.push_back(K.getReg(0));
489     }
490 
491     LLT LeftoverTy;
492     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
493     SmallVector<unsigned, 1> LeftoverRegs;
494     if (LeftoverBits != 0) {
495       LeftoverTy = LLT::scalar(LeftoverBits);
496       auto K = MIRBuilder.buildConstant(
497         LeftoverTy,
498         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
499       LeftoverRegs.push_back(K.getReg(0));
500     }
501 
502     insertParts(MI.getOperand(0).getReg(),
503                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
504 
505     MI.eraseFromParent();
506     return Legalized;
507   }
508   case TargetOpcode::G_ADD: {
509     // FIXME: add support for when SizeOp0 isn't an exact multiple of
510     // NarrowSize.
511     if (SizeOp0 % NarrowSize != 0)
512       return UnableToLegalize;
513     // Expand in terms of carry-setting/consuming G_ADDE instructions.
514     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
515 
516     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
517     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
518     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
519 
520     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
521     MIRBuilder.buildConstant(CarryIn, 0);
522 
523     for (int i = 0; i < NumParts; ++i) {
524       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
525       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
526 
527       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
528                             Src2Regs[i], CarryIn);
529 
530       DstRegs.push_back(DstReg);
531       CarryIn = CarryOut;
532     }
533     unsigned DstReg = MI.getOperand(0).getReg();
534     if(MRI.getType(DstReg).isVector())
535       MIRBuilder.buildBuildVector(DstReg, DstRegs);
536     else
537       MIRBuilder.buildMerge(DstReg, DstRegs);
538     MI.eraseFromParent();
539     return Legalized;
540   }
541   case TargetOpcode::G_SUB: {
542     // FIXME: add support for when SizeOp0 isn't an exact multiple of
543     // NarrowSize.
544     if (SizeOp0 % NarrowSize != 0)
545       return UnableToLegalize;
546 
547     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
548 
549     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
550     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
551     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
552 
553     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
554     unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
555     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
556                           {Src1Regs[0], Src2Regs[0]});
557     DstRegs.push_back(DstReg);
558     unsigned BorrowIn = BorrowOut;
559     for (int i = 1; i < NumParts; ++i) {
560       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
561       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
562 
563       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
564                             {Src1Regs[i], Src2Regs[i], BorrowIn});
565 
566       DstRegs.push_back(DstReg);
567       BorrowIn = BorrowOut;
568     }
569     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
570     MI.eraseFromParent();
571     return Legalized;
572   }
573   case TargetOpcode::G_MUL:
574   case TargetOpcode::G_UMULH:
575     return narrowScalarMul(MI, NarrowTy);
576   case TargetOpcode::G_EXTRACT:
577     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
578   case TargetOpcode::G_INSERT:
579     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
580   case TargetOpcode::G_LOAD: {
581     const auto &MMO = **MI.memoperands_begin();
582     unsigned DstReg = MI.getOperand(0).getReg();
583     LLT DstTy = MRI.getType(DstReg);
584     if (DstTy.isVector())
585       return UnableToLegalize;
586 
587     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
588       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
589       auto &MMO = **MI.memoperands_begin();
590       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
591       MIRBuilder.buildAnyExt(DstReg, TmpReg);
592       MI.eraseFromParent();
593       return Legalized;
594     }
595 
596     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
597   }
598   case TargetOpcode::G_ZEXTLOAD:
599   case TargetOpcode::G_SEXTLOAD: {
600     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
601     unsigned DstReg = MI.getOperand(0).getReg();
602     unsigned PtrReg = MI.getOperand(1).getReg();
603 
604     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
605     auto &MMO = **MI.memoperands_begin();
606     if (MMO.getSizeInBits() == NarrowSize) {
607       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
608     } else {
609       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
610         : TargetOpcode::G_SEXTLOAD;
611       MIRBuilder.buildInstr(ExtLoad)
612         .addDef(TmpReg)
613         .addUse(PtrReg)
614         .addMemOperand(&MMO);
615     }
616 
617     if (ZExt)
618       MIRBuilder.buildZExt(DstReg, TmpReg);
619     else
620       MIRBuilder.buildSExt(DstReg, TmpReg);
621 
622     MI.eraseFromParent();
623     return Legalized;
624   }
625   case TargetOpcode::G_STORE: {
626     const auto &MMO = **MI.memoperands_begin();
627 
628     unsigned SrcReg = MI.getOperand(0).getReg();
629     LLT SrcTy = MRI.getType(SrcReg);
630     if (SrcTy.isVector())
631       return UnableToLegalize;
632 
633     int NumParts = SizeOp0 / NarrowSize;
634     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
635     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
636     if (SrcTy.isVector() && LeftoverBits != 0)
637       return UnableToLegalize;
638 
639     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
640       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
641       auto &MMO = **MI.memoperands_begin();
642       MIRBuilder.buildTrunc(TmpReg, SrcReg);
643       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
644       MI.eraseFromParent();
645       return Legalized;
646     }
647 
648     return reduceLoadStoreWidth(MI, 0, NarrowTy);
649   }
650   case TargetOpcode::G_SELECT:
651     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
652   case TargetOpcode::G_AND:
653   case TargetOpcode::G_OR:
654   case TargetOpcode::G_XOR: {
655     // Legalize bitwise operation:
656     // A = BinOp<Ty> B, C
657     // into:
658     // B1, ..., BN = G_UNMERGE_VALUES B
659     // C1, ..., CN = G_UNMERGE_VALUES C
660     // A1 = BinOp<Ty/N> B1, C2
661     // ...
662     // AN = BinOp<Ty/N> BN, CN
663     // A = G_MERGE_VALUES A1, ..., AN
664     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
665   }
666   case TargetOpcode::G_SHL:
667   case TargetOpcode::G_LSHR:
668   case TargetOpcode::G_ASHR:
669     return narrowScalarShift(MI, TypeIdx, NarrowTy);
670   case TargetOpcode::G_CTLZ:
671   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
672   case TargetOpcode::G_CTTZ:
673   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
674   case TargetOpcode::G_CTPOP:
675     if (TypeIdx != 0)
676       return UnableToLegalize; // TODO
677 
678     Observer.changingInstr(MI);
679     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
680     Observer.changedInstr(MI);
681     return Legalized;
682   case TargetOpcode::G_INTTOPTR:
683     if (TypeIdx != 1)
684       return UnableToLegalize;
685 
686     Observer.changingInstr(MI);
687     narrowScalarSrc(MI, NarrowTy, 1);
688     Observer.changedInstr(MI);
689     return Legalized;
690   case TargetOpcode::G_PTRTOINT:
691     if (TypeIdx != 0)
692       return UnableToLegalize;
693 
694     Observer.changingInstr(MI);
695     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
696     Observer.changedInstr(MI);
697     return Legalized;
698   }
699 }
700 
701 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
702                                      unsigned OpIdx, unsigned ExtOpcode) {
703   MachineOperand &MO = MI.getOperand(OpIdx);
704   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
705   MO.setReg(ExtB->getOperand(0).getReg());
706 }
707 
708 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
709                                       unsigned OpIdx) {
710   MachineOperand &MO = MI.getOperand(OpIdx);
711   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
712                                     {MO.getReg()});
713   MO.setReg(ExtB->getOperand(0).getReg());
714 }
715 
716 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
717                                      unsigned OpIdx, unsigned TruncOpcode) {
718   MachineOperand &MO = MI.getOperand(OpIdx);
719   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
720   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
721   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
722   MO.setReg(DstExt);
723 }
724 
725 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
726                                       unsigned OpIdx, unsigned ExtOpcode) {
727   MachineOperand &MO = MI.getOperand(OpIdx);
728   unsigned DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
729   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
730   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
731   MO.setReg(DstTrunc);
732 }
733 
734 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
735                                             unsigned OpIdx) {
736   MachineOperand &MO = MI.getOperand(OpIdx);
737   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
738   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
739   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
740   MO.setReg(DstExt);
741 }
742 
743 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
744                                             unsigned OpIdx) {
745   MachineOperand &MO = MI.getOperand(OpIdx);
746 
747   LLT OldTy = MRI.getType(MO.getReg());
748   unsigned OldElts = OldTy.getNumElements();
749   unsigned NewElts = MoreTy.getNumElements();
750 
751   unsigned NumParts = NewElts / OldElts;
752 
753   // Use concat_vectors if the result is a multiple of the number of elements.
754   if (NumParts * OldElts == NewElts) {
755     SmallVector<unsigned, 8> Parts;
756     Parts.push_back(MO.getReg());
757 
758     unsigned ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
759     for (unsigned I = 1; I != NumParts; ++I)
760       Parts.push_back(ImpDef);
761 
762     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
763     MO.setReg(Concat.getReg(0));
764     return;
765   }
766 
767   unsigned MoreReg = MRI.createGenericVirtualRegister(MoreTy);
768   unsigned ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
769   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
770   MO.setReg(MoreReg);
771 }
772 
773 LegalizerHelper::LegalizeResult
774 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
775                                         LLT WideTy) {
776   if (TypeIdx != 1)
777     return UnableToLegalize;
778 
779   unsigned DstReg = MI.getOperand(0).getReg();
780   LLT DstTy = MRI.getType(DstReg);
781   if (!DstTy.isScalar())
782     return UnableToLegalize;
783 
784   unsigned NumOps = MI.getNumOperands();
785   unsigned NumSrc = MI.getNumOperands() - 1;
786   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
787 
788   unsigned Src1 = MI.getOperand(1).getReg();
789   unsigned ResultReg = MIRBuilder.buildZExt(DstTy, Src1)->getOperand(0).getReg();
790 
791   for (unsigned I = 2; I != NumOps; ++I) {
792     const unsigned Offset = (I - 1) * PartSize;
793 
794     unsigned SrcReg = MI.getOperand(I).getReg();
795     assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
796 
797     auto ZextInput = MIRBuilder.buildZExt(DstTy, SrcReg);
798 
799     unsigned NextResult = I + 1 == NumOps ? DstReg :
800       MRI.createGenericVirtualRegister(DstTy);
801 
802     auto ShiftAmt = MIRBuilder.buildConstant(DstTy, Offset);
803     auto Shl = MIRBuilder.buildShl(DstTy, ZextInput, ShiftAmt);
804     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
805     ResultReg = NextResult;
806   }
807 
808   MI.eraseFromParent();
809   return Legalized;
810 }
811 
812 LegalizerHelper::LegalizeResult
813 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
814                                           LLT WideTy) {
815   if (TypeIdx != 0)
816     return UnableToLegalize;
817 
818   unsigned NumDst = MI.getNumOperands() - 1;
819   unsigned SrcReg = MI.getOperand(NumDst).getReg();
820   LLT SrcTy = MRI.getType(SrcReg);
821   if (!SrcTy.isScalar())
822     return UnableToLegalize;
823 
824   unsigned Dst0Reg = MI.getOperand(0).getReg();
825   LLT DstTy = MRI.getType(Dst0Reg);
826   if (!DstTy.isScalar())
827     return UnableToLegalize;
828 
829   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
830   LLT NewSrcTy = LLT::scalar(NewSrcSize);
831   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
832 
833   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
834 
835   for (unsigned I = 1; I != NumDst; ++I) {
836     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
837     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
838     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
839   }
840 
841   Observer.changingInstr(MI);
842 
843   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
844   for (unsigned I = 0; I != NumDst; ++I)
845     widenScalarDst(MI, WideTy, I);
846 
847   Observer.changedInstr(MI);
848 
849   return Legalized;
850 }
851 
852 LegalizerHelper::LegalizeResult
853 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
854                                     LLT WideTy) {
855   unsigned DstReg = MI.getOperand(0).getReg();
856   unsigned SrcReg = MI.getOperand(1).getReg();
857   LLT SrcTy = MRI.getType(SrcReg);
858 
859   LLT DstTy = MRI.getType(DstReg);
860   unsigned Offset = MI.getOperand(2).getImm();
861 
862   if (TypeIdx == 0) {
863     if (SrcTy.isVector() || DstTy.isVector())
864       return UnableToLegalize;
865 
866     SrcOp Src(SrcReg);
867     if (SrcTy.isPointer()) {
868       // Extracts from pointers can be handled only if they are really just
869       // simple integers.
870       const DataLayout &DL = MIRBuilder.getDataLayout();
871       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
872         return UnableToLegalize;
873 
874       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
875       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
876       SrcTy = SrcAsIntTy;
877     }
878 
879     if (DstTy.isPointer())
880       return UnableToLegalize;
881 
882     if (Offset == 0) {
883       // Avoid a shift in the degenerate case.
884       MIRBuilder.buildTrunc(DstReg,
885                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
886       MI.eraseFromParent();
887       return Legalized;
888     }
889 
890     // Do a shift in the source type.
891     LLT ShiftTy = SrcTy;
892     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
893       Src = MIRBuilder.buildAnyExt(WideTy, Src);
894       ShiftTy = WideTy;
895     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
896       return UnableToLegalize;
897 
898     auto LShr = MIRBuilder.buildLShr(
899       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
900     MIRBuilder.buildTrunc(DstReg, LShr);
901     MI.eraseFromParent();
902     return Legalized;
903   }
904 
905   if (SrcTy.isScalar()) {
906     Observer.changingInstr(MI);
907     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
908     Observer.changedInstr(MI);
909     return Legalized;
910   }
911 
912   if (!SrcTy.isVector())
913     return UnableToLegalize;
914 
915   if (DstTy != SrcTy.getElementType())
916     return UnableToLegalize;
917 
918   if (Offset % SrcTy.getScalarSizeInBits() != 0)
919     return UnableToLegalize;
920 
921   Observer.changingInstr(MI);
922   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
923 
924   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
925                           Offset);
926   widenScalarDst(MI, WideTy.getScalarType(), 0);
927   Observer.changedInstr(MI);
928   return Legalized;
929 }
930 
931 LegalizerHelper::LegalizeResult
932 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
933                                    LLT WideTy) {
934   if (TypeIdx != 0)
935     return UnableToLegalize;
936   Observer.changingInstr(MI);
937   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
938   widenScalarDst(MI, WideTy);
939   Observer.changedInstr(MI);
940   return Legalized;
941 }
942 
943 LegalizerHelper::LegalizeResult
944 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
945   MIRBuilder.setInstr(MI);
946 
947   switch (MI.getOpcode()) {
948   default:
949     return UnableToLegalize;
950   case TargetOpcode::G_EXTRACT:
951     return widenScalarExtract(MI, TypeIdx, WideTy);
952   case TargetOpcode::G_INSERT:
953     return widenScalarInsert(MI, TypeIdx, WideTy);
954   case TargetOpcode::G_MERGE_VALUES:
955     return widenScalarMergeValues(MI, TypeIdx, WideTy);
956   case TargetOpcode::G_UNMERGE_VALUES:
957     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
958   case TargetOpcode::G_UADDO:
959   case TargetOpcode::G_USUBO: {
960     if (TypeIdx == 1)
961       return UnableToLegalize; // TODO
962     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
963                                          {MI.getOperand(2).getReg()});
964     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
965                                          {MI.getOperand(3).getReg()});
966     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
967                           ? TargetOpcode::G_ADD
968                           : TargetOpcode::G_SUB;
969     // Do the arithmetic in the larger type.
970     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
971     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
972     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
973     auto AndOp = MIRBuilder.buildInstr(
974         TargetOpcode::G_AND, {WideTy},
975         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
976     // There is no overflow if the AndOp is the same as NewOp.
977     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
978                          AndOp);
979     // Now trunc the NewOp to the original result.
980     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
981     MI.eraseFromParent();
982     return Legalized;
983   }
984   case TargetOpcode::G_CTTZ:
985   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
986   case TargetOpcode::G_CTLZ:
987   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
988   case TargetOpcode::G_CTPOP: {
989     if (TypeIdx == 0) {
990       Observer.changingInstr(MI);
991       widenScalarDst(MI, WideTy, 0);
992       Observer.changedInstr(MI);
993       return Legalized;
994     }
995 
996     unsigned SrcReg = MI.getOperand(1).getReg();
997 
998     // First ZEXT the input.
999     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1000     LLT CurTy = MRI.getType(SrcReg);
1001     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1002       // The count is the same in the larger type except if the original
1003       // value was zero.  This can be handled by setting the bit just off
1004       // the top of the original type.
1005       auto TopBit =
1006           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1007       MIBSrc = MIRBuilder.buildOr(
1008         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1009     }
1010 
1011     // Perform the operation at the larger size.
1012     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1013     // This is already the correct result for CTPOP and CTTZs
1014     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1015         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1016       // The correct result is NewOp - (Difference in widety and current ty).
1017       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1018       MIBNewOp = MIRBuilder.buildInstr(
1019           TargetOpcode::G_SUB, {WideTy},
1020           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1021     }
1022 
1023     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1024     MI.eraseFromParent();
1025     return Legalized;
1026   }
1027   case TargetOpcode::G_BSWAP: {
1028     Observer.changingInstr(MI);
1029     unsigned DstReg = MI.getOperand(0).getReg();
1030 
1031     unsigned ShrReg = MRI.createGenericVirtualRegister(WideTy);
1032     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
1033     unsigned ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1034     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1035 
1036     MI.getOperand(0).setReg(DstExt);
1037 
1038     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1039 
1040     LLT Ty = MRI.getType(DstReg);
1041     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1042     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1043     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1044       .addDef(ShrReg)
1045       .addUse(DstExt)
1046       .addUse(ShiftAmtReg);
1047 
1048     MIRBuilder.buildTrunc(DstReg, ShrReg);
1049     Observer.changedInstr(MI);
1050     return Legalized;
1051   }
1052   case TargetOpcode::G_ADD:
1053   case TargetOpcode::G_AND:
1054   case TargetOpcode::G_MUL:
1055   case TargetOpcode::G_OR:
1056   case TargetOpcode::G_XOR:
1057   case TargetOpcode::G_SUB:
1058     // Perform operation at larger width (any extension is fines here, high bits
1059     // don't affect the result) and then truncate the result back to the
1060     // original type.
1061     Observer.changingInstr(MI);
1062     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1063     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1064     widenScalarDst(MI, WideTy);
1065     Observer.changedInstr(MI);
1066     return Legalized;
1067 
1068   case TargetOpcode::G_SHL:
1069     Observer.changingInstr(MI);
1070 
1071     if (TypeIdx == 0) {
1072       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1073       widenScalarDst(MI, WideTy);
1074     } else {
1075       assert(TypeIdx == 1);
1076       // The "number of bits to shift" operand must preserve its value as an
1077       // unsigned integer:
1078       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1079     }
1080 
1081     Observer.changedInstr(MI);
1082     return Legalized;
1083 
1084   case TargetOpcode::G_SDIV:
1085   case TargetOpcode::G_SREM:
1086     Observer.changingInstr(MI);
1087     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1088     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1089     widenScalarDst(MI, WideTy);
1090     Observer.changedInstr(MI);
1091     return Legalized;
1092 
1093   case TargetOpcode::G_ASHR:
1094   case TargetOpcode::G_LSHR:
1095     Observer.changingInstr(MI);
1096 
1097     if (TypeIdx == 0) {
1098       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1099         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1100 
1101       widenScalarSrc(MI, WideTy, 1, CvtOp);
1102       widenScalarDst(MI, WideTy);
1103     } else {
1104       assert(TypeIdx == 1);
1105       // The "number of bits to shift" operand must preserve its value as an
1106       // unsigned integer:
1107       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1108     }
1109 
1110     Observer.changedInstr(MI);
1111     return Legalized;
1112   case TargetOpcode::G_UDIV:
1113   case TargetOpcode::G_UREM:
1114     Observer.changingInstr(MI);
1115     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1116     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1117     widenScalarDst(MI, WideTy);
1118     Observer.changedInstr(MI);
1119     return Legalized;
1120 
1121   case TargetOpcode::G_SELECT:
1122     Observer.changingInstr(MI);
1123     if (TypeIdx == 0) {
1124       // Perform operation at larger width (any extension is fine here, high
1125       // bits don't affect the result) and then truncate the result back to the
1126       // original type.
1127       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1128       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1129       widenScalarDst(MI, WideTy);
1130     } else {
1131       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1132       // Explicit extension is required here since high bits affect the result.
1133       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1134     }
1135     Observer.changedInstr(MI);
1136     return Legalized;
1137 
1138   case TargetOpcode::G_FPTOSI:
1139   case TargetOpcode::G_FPTOUI:
1140     if (TypeIdx != 0)
1141       return UnableToLegalize;
1142     Observer.changingInstr(MI);
1143     widenScalarDst(MI, WideTy);
1144     Observer.changedInstr(MI);
1145     return Legalized;
1146 
1147   case TargetOpcode::G_SITOFP:
1148     if (TypeIdx != 1)
1149       return UnableToLegalize;
1150     Observer.changingInstr(MI);
1151     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1152     Observer.changedInstr(MI);
1153     return Legalized;
1154 
1155   case TargetOpcode::G_UITOFP:
1156     if (TypeIdx != 1)
1157       return UnableToLegalize;
1158     Observer.changingInstr(MI);
1159     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1160     Observer.changedInstr(MI);
1161     return Legalized;
1162 
1163   case TargetOpcode::G_LOAD:
1164   case TargetOpcode::G_SEXTLOAD:
1165   case TargetOpcode::G_ZEXTLOAD:
1166     Observer.changingInstr(MI);
1167     widenScalarDst(MI, WideTy);
1168     Observer.changedInstr(MI);
1169     return Legalized;
1170 
1171   case TargetOpcode::G_STORE: {
1172     if (TypeIdx != 0)
1173       return UnableToLegalize;
1174 
1175     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1176     if (!isPowerOf2_32(Ty.getSizeInBits()))
1177       return UnableToLegalize;
1178 
1179     Observer.changingInstr(MI);
1180 
1181     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1182       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1183     widenScalarSrc(MI, WideTy, 0, ExtType);
1184 
1185     Observer.changedInstr(MI);
1186     return Legalized;
1187   }
1188   case TargetOpcode::G_CONSTANT: {
1189     MachineOperand &SrcMO = MI.getOperand(1);
1190     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1191     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1192     Observer.changingInstr(MI);
1193     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1194 
1195     widenScalarDst(MI, WideTy);
1196     Observer.changedInstr(MI);
1197     return Legalized;
1198   }
1199   case TargetOpcode::G_FCONSTANT: {
1200     MachineOperand &SrcMO = MI.getOperand(1);
1201     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1202     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1203     bool LosesInfo;
1204     switch (WideTy.getSizeInBits()) {
1205     case 32:
1206       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1207                   &LosesInfo);
1208       break;
1209     case 64:
1210       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1211                   &LosesInfo);
1212       break;
1213     default:
1214       return UnableToLegalize;
1215     }
1216 
1217     assert(!LosesInfo && "extend should always be lossless");
1218 
1219     Observer.changingInstr(MI);
1220     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1221 
1222     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1223     Observer.changedInstr(MI);
1224     return Legalized;
1225   }
1226   case TargetOpcode::G_IMPLICIT_DEF: {
1227     Observer.changingInstr(MI);
1228     widenScalarDst(MI, WideTy);
1229     Observer.changedInstr(MI);
1230     return Legalized;
1231   }
1232   case TargetOpcode::G_BRCOND:
1233     Observer.changingInstr(MI);
1234     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1235     Observer.changedInstr(MI);
1236     return Legalized;
1237 
1238   case TargetOpcode::G_FCMP:
1239     Observer.changingInstr(MI);
1240     if (TypeIdx == 0)
1241       widenScalarDst(MI, WideTy);
1242     else {
1243       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1244       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1245     }
1246     Observer.changedInstr(MI);
1247     return Legalized;
1248 
1249   case TargetOpcode::G_ICMP:
1250     Observer.changingInstr(MI);
1251     if (TypeIdx == 0)
1252       widenScalarDst(MI, WideTy);
1253     else {
1254       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1255                                MI.getOperand(1).getPredicate()))
1256                                ? TargetOpcode::G_SEXT
1257                                : TargetOpcode::G_ZEXT;
1258       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1259       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1260     }
1261     Observer.changedInstr(MI);
1262     return Legalized;
1263 
1264   case TargetOpcode::G_GEP:
1265     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1266     Observer.changingInstr(MI);
1267     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1268     Observer.changedInstr(MI);
1269     return Legalized;
1270 
1271   case TargetOpcode::G_PHI: {
1272     assert(TypeIdx == 0 && "Expecting only Idx 0");
1273 
1274     Observer.changingInstr(MI);
1275     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1276       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1277       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1278       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1279     }
1280 
1281     MachineBasicBlock &MBB = *MI.getParent();
1282     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1283     widenScalarDst(MI, WideTy);
1284     Observer.changedInstr(MI);
1285     return Legalized;
1286   }
1287   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1288     if (TypeIdx == 0) {
1289       unsigned VecReg = MI.getOperand(1).getReg();
1290       LLT VecTy = MRI.getType(VecReg);
1291       Observer.changingInstr(MI);
1292 
1293       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1294                                      WideTy.getSizeInBits()),
1295                      1, TargetOpcode::G_SEXT);
1296 
1297       widenScalarDst(MI, WideTy, 0);
1298       Observer.changedInstr(MI);
1299       return Legalized;
1300     }
1301 
1302     if (TypeIdx != 2)
1303       return UnableToLegalize;
1304     Observer.changingInstr(MI);
1305     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1306     Observer.changedInstr(MI);
1307     return Legalized;
1308   }
1309   case TargetOpcode::G_FADD:
1310   case TargetOpcode::G_FMUL:
1311   case TargetOpcode::G_FSUB:
1312   case TargetOpcode::G_FMA:
1313   case TargetOpcode::G_FNEG:
1314   case TargetOpcode::G_FABS:
1315   case TargetOpcode::G_FCANONICALIZE:
1316   case TargetOpcode::G_FDIV:
1317   case TargetOpcode::G_FREM:
1318   case TargetOpcode::G_FCEIL:
1319   case TargetOpcode::G_FFLOOR:
1320   case TargetOpcode::G_FCOS:
1321   case TargetOpcode::G_FSIN:
1322   case TargetOpcode::G_FLOG10:
1323   case TargetOpcode::G_FLOG:
1324   case TargetOpcode::G_FLOG2:
1325   case TargetOpcode::G_FRINT:
1326   case TargetOpcode::G_FNEARBYINT:
1327   case TargetOpcode::G_FSQRT:
1328   case TargetOpcode::G_FEXP:
1329   case TargetOpcode::G_FEXP2:
1330   case TargetOpcode::G_FPOW:
1331   case TargetOpcode::G_INTRINSIC_TRUNC:
1332   case TargetOpcode::G_INTRINSIC_ROUND:
1333     assert(TypeIdx == 0);
1334     Observer.changingInstr(MI);
1335 
1336     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1337       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1338 
1339     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1340     Observer.changedInstr(MI);
1341     return Legalized;
1342   case TargetOpcode::G_INTTOPTR:
1343     if (TypeIdx != 1)
1344       return UnableToLegalize;
1345 
1346     Observer.changingInstr(MI);
1347     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1348     Observer.changedInstr(MI);
1349     return Legalized;
1350   case TargetOpcode::G_PTRTOINT:
1351     if (TypeIdx != 0)
1352       return UnableToLegalize;
1353 
1354     Observer.changingInstr(MI);
1355     widenScalarDst(MI, WideTy, 0);
1356     Observer.changedInstr(MI);
1357     return Legalized;
1358   }
1359 }
1360 
1361 LegalizerHelper::LegalizeResult
1362 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1363   using namespace TargetOpcode;
1364   MIRBuilder.setInstr(MI);
1365 
1366   switch(MI.getOpcode()) {
1367   default:
1368     return UnableToLegalize;
1369   case TargetOpcode::G_SREM:
1370   case TargetOpcode::G_UREM: {
1371     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
1372     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1373         .addDef(QuotReg)
1374         .addUse(MI.getOperand(1).getReg())
1375         .addUse(MI.getOperand(2).getReg());
1376 
1377     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
1378     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1379     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1380                         ProdReg);
1381     MI.eraseFromParent();
1382     return Legalized;
1383   }
1384   case TargetOpcode::G_SMULO:
1385   case TargetOpcode::G_UMULO: {
1386     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1387     // result.
1388     unsigned Res = MI.getOperand(0).getReg();
1389     unsigned Overflow = MI.getOperand(1).getReg();
1390     unsigned LHS = MI.getOperand(2).getReg();
1391     unsigned RHS = MI.getOperand(3).getReg();
1392 
1393     MIRBuilder.buildMul(Res, LHS, RHS);
1394 
1395     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1396                           ? TargetOpcode::G_SMULH
1397                           : TargetOpcode::G_UMULH;
1398 
1399     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
1400     MIRBuilder.buildInstr(Opcode)
1401       .addDef(HiPart)
1402       .addUse(LHS)
1403       .addUse(RHS);
1404 
1405     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
1406     MIRBuilder.buildConstant(Zero, 0);
1407 
1408     // For *signed* multiply, overflow is detected by checking:
1409     // (hi != (lo >> bitwidth-1))
1410     if (Opcode == TargetOpcode::G_SMULH) {
1411       unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
1412       unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1413       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1414       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1415         .addDef(Shifted)
1416         .addUse(Res)
1417         .addUse(ShiftAmt);
1418       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1419     } else {
1420       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1421     }
1422     MI.eraseFromParent();
1423     return Legalized;
1424   }
1425   case TargetOpcode::G_FNEG: {
1426     // TODO: Handle vector types once we are able to
1427     // represent them.
1428     if (Ty.isVector())
1429       return UnableToLegalize;
1430     unsigned Res = MI.getOperand(0).getReg();
1431     Type *ZeroTy;
1432     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1433     switch (Ty.getSizeInBits()) {
1434     case 16:
1435       ZeroTy = Type::getHalfTy(Ctx);
1436       break;
1437     case 32:
1438       ZeroTy = Type::getFloatTy(Ctx);
1439       break;
1440     case 64:
1441       ZeroTy = Type::getDoubleTy(Ctx);
1442       break;
1443     case 128:
1444       ZeroTy = Type::getFP128Ty(Ctx);
1445       break;
1446     default:
1447       llvm_unreachable("unexpected floating-point type");
1448     }
1449     ConstantFP &ZeroForNegation =
1450         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1451     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1452     unsigned SubByReg = MI.getOperand(1).getReg();
1453     unsigned ZeroReg = Zero->getOperand(0).getReg();
1454     MachineInstr *SrcMI = MRI.getVRegDef(SubByReg);
1455     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1456                           SrcMI->getFlags());
1457     MI.eraseFromParent();
1458     return Legalized;
1459   }
1460   case TargetOpcode::G_FSUB: {
1461     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1462     // First, check if G_FNEG is marked as Lower. If so, we may
1463     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1464     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1465       return UnableToLegalize;
1466     unsigned Res = MI.getOperand(0).getReg();
1467     unsigned LHS = MI.getOperand(1).getReg();
1468     unsigned RHS = MI.getOperand(2).getReg();
1469     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1470     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1471     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1472     MI.eraseFromParent();
1473     return Legalized;
1474   }
1475   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1476     unsigned OldValRes = MI.getOperand(0).getReg();
1477     unsigned SuccessRes = MI.getOperand(1).getReg();
1478     unsigned Addr = MI.getOperand(2).getReg();
1479     unsigned CmpVal = MI.getOperand(3).getReg();
1480     unsigned NewVal = MI.getOperand(4).getReg();
1481     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1482                                   **MI.memoperands_begin());
1483     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1484     MI.eraseFromParent();
1485     return Legalized;
1486   }
1487   case TargetOpcode::G_LOAD:
1488   case TargetOpcode::G_SEXTLOAD:
1489   case TargetOpcode::G_ZEXTLOAD: {
1490     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1491     unsigned DstReg = MI.getOperand(0).getReg();
1492     unsigned PtrReg = MI.getOperand(1).getReg();
1493     LLT DstTy = MRI.getType(DstReg);
1494     auto &MMO = **MI.memoperands_begin();
1495 
1496     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1497       // In the case of G_LOAD, this was a non-extending load already and we're
1498       // about to lower to the same instruction.
1499       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1500           return UnableToLegalize;
1501       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1502       MI.eraseFromParent();
1503       return Legalized;
1504     }
1505 
1506     if (DstTy.isScalar()) {
1507       unsigned TmpReg =
1508           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
1509       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1510       switch (MI.getOpcode()) {
1511       default:
1512         llvm_unreachable("Unexpected opcode");
1513       case TargetOpcode::G_LOAD:
1514         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1515         break;
1516       case TargetOpcode::G_SEXTLOAD:
1517         MIRBuilder.buildSExt(DstReg, TmpReg);
1518         break;
1519       case TargetOpcode::G_ZEXTLOAD:
1520         MIRBuilder.buildZExt(DstReg, TmpReg);
1521         break;
1522       }
1523       MI.eraseFromParent();
1524       return Legalized;
1525     }
1526 
1527     return UnableToLegalize;
1528   }
1529   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1530   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1531   case TargetOpcode::G_CTLZ:
1532   case TargetOpcode::G_CTTZ:
1533   case TargetOpcode::G_CTPOP:
1534     return lowerBitCount(MI, TypeIdx, Ty);
1535   case G_UADDO: {
1536     unsigned Res = MI.getOperand(0).getReg();
1537     unsigned CarryOut = MI.getOperand(1).getReg();
1538     unsigned LHS = MI.getOperand(2).getReg();
1539     unsigned RHS = MI.getOperand(3).getReg();
1540 
1541     MIRBuilder.buildAdd(Res, LHS, RHS);
1542     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1543 
1544     MI.eraseFromParent();
1545     return Legalized;
1546   }
1547   case G_UADDE: {
1548     unsigned Res = MI.getOperand(0).getReg();
1549     unsigned CarryOut = MI.getOperand(1).getReg();
1550     unsigned LHS = MI.getOperand(2).getReg();
1551     unsigned RHS = MI.getOperand(3).getReg();
1552     unsigned CarryIn = MI.getOperand(4).getReg();
1553 
1554     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1555     unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1556 
1557     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1558     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1559     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1560     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1561 
1562     MI.eraseFromParent();
1563     return Legalized;
1564   }
1565   case G_USUBO: {
1566     unsigned Res = MI.getOperand(0).getReg();
1567     unsigned BorrowOut = MI.getOperand(1).getReg();
1568     unsigned LHS = MI.getOperand(2).getReg();
1569     unsigned RHS = MI.getOperand(3).getReg();
1570 
1571     MIRBuilder.buildSub(Res, LHS, RHS);
1572     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1573 
1574     MI.eraseFromParent();
1575     return Legalized;
1576   }
1577   case G_USUBE: {
1578     unsigned Res = MI.getOperand(0).getReg();
1579     unsigned BorrowOut = MI.getOperand(1).getReg();
1580     unsigned LHS = MI.getOperand(2).getReg();
1581     unsigned RHS = MI.getOperand(3).getReg();
1582     unsigned BorrowIn = MI.getOperand(4).getReg();
1583 
1584     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1585     unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1586     unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1587     unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1588 
1589     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1590     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1591     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1592     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1593     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1594     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1595 
1596     MI.eraseFromParent();
1597     return Legalized;
1598   }
1599   }
1600 }
1601 
1602 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1603     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1604   SmallVector<unsigned, 2> DstRegs;
1605 
1606   unsigned NarrowSize = NarrowTy.getSizeInBits();
1607   unsigned DstReg = MI.getOperand(0).getReg();
1608   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1609   int NumParts = Size / NarrowSize;
1610   // FIXME: Don't know how to handle the situation where the small vectors
1611   // aren't all the same size yet.
1612   if (Size % NarrowSize != 0)
1613     return UnableToLegalize;
1614 
1615   for (int i = 0; i < NumParts; ++i) {
1616     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1617     MIRBuilder.buildUndef(TmpReg);
1618     DstRegs.push_back(TmpReg);
1619   }
1620 
1621   if (NarrowTy.isVector())
1622     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1623   else
1624     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1625 
1626   MI.eraseFromParent();
1627   return Legalized;
1628 }
1629 
1630 LegalizerHelper::LegalizeResult
1631 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1632                                           LLT NarrowTy) {
1633   const unsigned Opc = MI.getOpcode();
1634   const unsigned NumOps = MI.getNumOperands() - 1;
1635   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1636   const unsigned DstReg = MI.getOperand(0).getReg();
1637   const unsigned Flags = MI.getFlags();
1638   const LLT DstTy = MRI.getType(DstReg);
1639   const unsigned Size = DstTy.getSizeInBits();
1640   const int NumParts = Size / NarrowSize;
1641   const LLT EltTy = DstTy.getElementType();
1642   const unsigned EltSize = EltTy.getSizeInBits();
1643   const unsigned BitsForNumParts = NarrowSize * NumParts;
1644 
1645   // Check if we have any leftovers. If we do, then only handle the case where
1646   // the leftover is one element.
1647   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1648     return UnableToLegalize;
1649 
1650   if (BitsForNumParts != Size) {
1651     unsigned AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1652     MIRBuilder.buildUndef(AccumDstReg);
1653 
1654     // Handle the pieces which evenly divide into the requested type with
1655     // extract/op/insert sequence.
1656     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1657       SmallVector<SrcOp, 4> SrcOps;
1658       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1659         unsigned PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1660         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1661         SrcOps.push_back(PartOpReg);
1662       }
1663 
1664       unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1665       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1666 
1667       unsigned PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1668       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1669       AccumDstReg = PartInsertReg;
1670     }
1671 
1672     // Handle the remaining element sized leftover piece.
1673     SmallVector<SrcOp, 4> SrcOps;
1674     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1675       unsigned PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1676       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1677                               BitsForNumParts);
1678       SrcOps.push_back(PartOpReg);
1679     }
1680 
1681     unsigned PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1682     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1683     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1684     MI.eraseFromParent();
1685 
1686     return Legalized;
1687   }
1688 
1689   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1690 
1691   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1692 
1693   if (NumOps >= 2)
1694     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1695 
1696   if (NumOps >= 3)
1697     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1698 
1699   for (int i = 0; i < NumParts; ++i) {
1700     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1701 
1702     if (NumOps == 1)
1703       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1704     else if (NumOps == 2) {
1705       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1706     } else if (NumOps == 3) {
1707       MIRBuilder.buildInstr(Opc, {DstReg},
1708                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1709     }
1710 
1711     DstRegs.push_back(DstReg);
1712   }
1713 
1714   if (NarrowTy.isVector())
1715     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1716   else
1717     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1718 
1719   MI.eraseFromParent();
1720   return Legalized;
1721 }
1722 
1723 // Handle splitting vector operations which need to have the same number of
1724 // elements in each type index, but each type index may have a different element
1725 // type.
1726 //
1727 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
1728 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1729 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1730 //
1731 // Also handles some irregular breakdown cases, e.g.
1732 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
1733 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1734 //             s64 = G_SHL s64, s32
1735 LegalizerHelper::LegalizeResult
1736 LegalizerHelper::fewerElementsVectorMultiEltType(
1737   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
1738   if (TypeIdx != 0)
1739     return UnableToLegalize;
1740 
1741   const LLT NarrowTy0 = NarrowTyArg;
1742   const unsigned NewNumElts =
1743       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
1744 
1745   const unsigned DstReg = MI.getOperand(0).getReg();
1746   LLT DstTy = MRI.getType(DstReg);
1747   LLT LeftoverTy0;
1748 
1749   int NumParts, NumLeftover;
1750   // All of the operands need to have the same number of elements, so if we can
1751   // determine a type breakdown for the result type, we can for all of the
1752   // source types.
1753   std::tie(NumParts, NumLeftover)
1754     = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1755   if (NumParts < 0)
1756     return UnableToLegalize;
1757 
1758   SmallVector<MachineInstrBuilder, 4> NewInsts;
1759 
1760   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
1761   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
1762 
1763   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1764     LLT LeftoverTy;
1765     unsigned SrcReg = MI.getOperand(I).getReg();
1766     LLT SrcTyI = MRI.getType(SrcReg);
1767     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
1768     LLT LeftoverTyI;
1769 
1770     // Split this operand into the requested typed registers, and any leftover
1771     // required to reproduce the original type.
1772     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
1773                       LeftoverRegs))
1774       return UnableToLegalize;
1775 
1776     if (I == 1) {
1777       // For the first operand, create an instruction for each part and setup
1778       // the result.
1779       for (unsigned PartReg : PartRegs) {
1780         unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1781         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1782                                .addDef(PartDstReg)
1783                                .addUse(PartReg));
1784         DstRegs.push_back(PartDstReg);
1785       }
1786 
1787       for (unsigned LeftoverReg : LeftoverRegs) {
1788         unsigned PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1789         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1790                                .addDef(PartDstReg)
1791                                .addUse(LeftoverReg));
1792         LeftoverDstRegs.push_back(PartDstReg);
1793       }
1794     } else {
1795       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
1796 
1797       // Add the newly created operand splits to the existing instructions. The
1798       // odd-sized pieces are ordered after the requested NarrowTyArg sized
1799       // pieces.
1800       unsigned InstCount = 0;
1801       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
1802         NewInsts[InstCount++].addUse(PartRegs[J]);
1803       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
1804         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
1805     }
1806 
1807     PartRegs.clear();
1808     LeftoverRegs.clear();
1809   }
1810 
1811   // Insert the newly built operations and rebuild the result register.
1812   for (auto &MIB : NewInsts)
1813     MIRBuilder.insertInstr(MIB);
1814 
1815   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
1816 
1817   MI.eraseFromParent();
1818   return Legalized;
1819 }
1820 
1821 LegalizerHelper::LegalizeResult
1822 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
1823                                           LLT NarrowTy) {
1824   if (TypeIdx != 0)
1825     return UnableToLegalize;
1826 
1827   unsigned DstReg = MI.getOperand(0).getReg();
1828   unsigned SrcReg = MI.getOperand(1).getReg();
1829   LLT DstTy = MRI.getType(DstReg);
1830   LLT SrcTy = MRI.getType(SrcReg);
1831 
1832   LLT NarrowTy0 = NarrowTy;
1833   LLT NarrowTy1;
1834   unsigned NumParts;
1835 
1836   if (NarrowTy.isVector()) {
1837     // Uneven breakdown not handled.
1838     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
1839     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
1840       return UnableToLegalize;
1841 
1842     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
1843   } else {
1844     NumParts = DstTy.getNumElements();
1845     NarrowTy1 = SrcTy.getElementType();
1846   }
1847 
1848   SmallVector<unsigned, 4> SrcRegs, DstRegs;
1849   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
1850 
1851   for (unsigned I = 0; I < NumParts; ++I) {
1852     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1853     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
1854       .addDef(DstReg)
1855       .addUse(SrcRegs[I]);
1856 
1857     NewInst->setFlags(MI.getFlags());
1858     DstRegs.push_back(DstReg);
1859   }
1860 
1861   if (NarrowTy.isVector())
1862     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1863   else
1864     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1865 
1866   MI.eraseFromParent();
1867   return Legalized;
1868 }
1869 
1870 LegalizerHelper::LegalizeResult
1871 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
1872                                         LLT NarrowTy) {
1873   unsigned DstReg = MI.getOperand(0).getReg();
1874   unsigned Src0Reg = MI.getOperand(2).getReg();
1875   LLT DstTy = MRI.getType(DstReg);
1876   LLT SrcTy = MRI.getType(Src0Reg);
1877 
1878   unsigned NumParts;
1879   LLT NarrowTy0, NarrowTy1;
1880 
1881   if (TypeIdx == 0) {
1882     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1883     unsigned OldElts = DstTy.getNumElements();
1884 
1885     NarrowTy0 = NarrowTy;
1886     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
1887     NarrowTy1 = NarrowTy.isVector() ?
1888       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
1889       SrcTy.getElementType();
1890 
1891   } else {
1892     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1893     unsigned OldElts = SrcTy.getNumElements();
1894 
1895     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
1896       NarrowTy.getNumElements();
1897     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
1898                             DstTy.getScalarSizeInBits());
1899     NarrowTy1 = NarrowTy;
1900   }
1901 
1902   // FIXME: Don't know how to handle the situation where the small vectors
1903   // aren't all the same size yet.
1904   if (NarrowTy1.isVector() &&
1905       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
1906     return UnableToLegalize;
1907 
1908   CmpInst::Predicate Pred
1909     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1910 
1911   SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
1912   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
1913   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
1914 
1915   for (unsigned I = 0; I < NumParts; ++I) {
1916     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1917     DstRegs.push_back(DstReg);
1918 
1919     if (MI.getOpcode() == TargetOpcode::G_ICMP)
1920       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1921     else {
1922       MachineInstr *NewCmp
1923         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1924       NewCmp->setFlags(MI.getFlags());
1925     }
1926   }
1927 
1928   if (NarrowTy1.isVector())
1929     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1930   else
1931     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1932 
1933   MI.eraseFromParent();
1934   return Legalized;
1935 }
1936 
1937 LegalizerHelper::LegalizeResult
1938 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
1939                                            LLT NarrowTy) {
1940   unsigned DstReg = MI.getOperand(0).getReg();
1941   unsigned CondReg = MI.getOperand(1).getReg();
1942 
1943   unsigned NumParts = 0;
1944   LLT NarrowTy0, NarrowTy1;
1945 
1946   LLT DstTy = MRI.getType(DstReg);
1947   LLT CondTy = MRI.getType(CondReg);
1948   unsigned Size = DstTy.getSizeInBits();
1949 
1950   assert(TypeIdx == 0 || CondTy.isVector());
1951 
1952   if (TypeIdx == 0) {
1953     NarrowTy0 = NarrowTy;
1954     NarrowTy1 = CondTy;
1955 
1956     unsigned NarrowSize = NarrowTy0.getSizeInBits();
1957     // FIXME: Don't know how to handle the situation where the small vectors
1958     // aren't all the same size yet.
1959     if (Size % NarrowSize != 0)
1960       return UnableToLegalize;
1961 
1962     NumParts = Size / NarrowSize;
1963 
1964     // Need to break down the condition type
1965     if (CondTy.isVector()) {
1966       if (CondTy.getNumElements() == NumParts)
1967         NarrowTy1 = CondTy.getElementType();
1968       else
1969         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
1970                                 CondTy.getScalarSizeInBits());
1971     }
1972   } else {
1973     NumParts = CondTy.getNumElements();
1974     if (NarrowTy.isVector()) {
1975       // TODO: Handle uneven breakdown.
1976       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
1977         return UnableToLegalize;
1978 
1979       return UnableToLegalize;
1980     } else {
1981       NarrowTy0 = DstTy.getElementType();
1982       NarrowTy1 = NarrowTy;
1983     }
1984   }
1985 
1986   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1987   if (CondTy.isVector())
1988     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
1989 
1990   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
1991   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
1992 
1993   for (unsigned i = 0; i < NumParts; ++i) {
1994     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1995     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
1996                            Src1Regs[i], Src2Regs[i]);
1997     DstRegs.push_back(DstReg);
1998   }
1999 
2000   if (NarrowTy0.isVector())
2001     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2002   else
2003     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2004 
2005   MI.eraseFromParent();
2006   return Legalized;
2007 }
2008 
2009 LegalizerHelper::LegalizeResult
2010 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2011                                         LLT NarrowTy) {
2012   const unsigned DstReg = MI.getOperand(0).getReg();
2013   LLT PhiTy = MRI.getType(DstReg);
2014   LLT LeftoverTy;
2015 
2016   // All of the operands need to have the same number of elements, so if we can
2017   // determine a type breakdown for the result type, we can for all of the
2018   // source types.
2019   int NumParts, NumLeftover;
2020   std::tie(NumParts, NumLeftover)
2021     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2022   if (NumParts < 0)
2023     return UnableToLegalize;
2024 
2025   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
2026   SmallVector<MachineInstrBuilder, 4> NewInsts;
2027 
2028   const int TotalNumParts = NumParts + NumLeftover;
2029 
2030   // Insert the new phis in the result block first.
2031   for (int I = 0; I != TotalNumParts; ++I) {
2032     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2033     unsigned PartDstReg = MRI.createGenericVirtualRegister(Ty);
2034     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2035                        .addDef(PartDstReg));
2036     if (I < NumParts)
2037       DstRegs.push_back(PartDstReg);
2038     else
2039       LeftoverDstRegs.push_back(PartDstReg);
2040   }
2041 
2042   MachineBasicBlock *MBB = MI.getParent();
2043   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2044   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2045 
2046   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
2047 
2048   // Insert code to extract the incoming values in each predecessor block.
2049   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2050     PartRegs.clear();
2051     LeftoverRegs.clear();
2052 
2053     unsigned SrcReg = MI.getOperand(I).getReg();
2054     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2055     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2056 
2057     LLT Unused;
2058     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2059                       LeftoverRegs))
2060       return UnableToLegalize;
2061 
2062     // Add the newly created operand splits to the existing instructions. The
2063     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2064     // pieces.
2065     for (int J = 0; J != TotalNumParts; ++J) {
2066       MachineInstrBuilder MIB = NewInsts[J];
2067       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2068       MIB.addMBB(&OpMBB);
2069     }
2070   }
2071 
2072   MI.eraseFromParent();
2073   return Legalized;
2074 }
2075 
2076 LegalizerHelper::LegalizeResult
2077 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2078                                       LLT NarrowTy) {
2079   // FIXME: Don't know how to handle secondary types yet.
2080   if (TypeIdx != 0)
2081     return UnableToLegalize;
2082 
2083   MachineMemOperand *MMO = *MI.memoperands_begin();
2084 
2085   // This implementation doesn't work for atomics. Give up instead of doing
2086   // something invalid.
2087   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2088       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2089     return UnableToLegalize;
2090 
2091   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2092   unsigned ValReg = MI.getOperand(0).getReg();
2093   unsigned AddrReg = MI.getOperand(1).getReg();
2094   LLT ValTy = MRI.getType(ValReg);
2095 
2096   int NumParts = -1;
2097   int NumLeftover = -1;
2098   LLT LeftoverTy;
2099   SmallVector<unsigned, 8> NarrowRegs, NarrowLeftoverRegs;
2100   if (IsLoad) {
2101     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2102   } else {
2103     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2104                      NarrowLeftoverRegs)) {
2105       NumParts = NarrowRegs.size();
2106       NumLeftover = NarrowLeftoverRegs.size();
2107     }
2108   }
2109 
2110   if (NumParts == -1)
2111     return UnableToLegalize;
2112 
2113   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2114 
2115   unsigned TotalSize = ValTy.getSizeInBits();
2116 
2117   // Split the load/store into PartTy sized pieces starting at Offset. If this
2118   // is a load, return the new registers in ValRegs. For a store, each elements
2119   // of ValRegs should be PartTy. Returns the next offset that needs to be
2120   // handled.
2121   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<unsigned> &ValRegs,
2122                              unsigned Offset) -> unsigned {
2123     MachineFunction &MF = MIRBuilder.getMF();
2124     unsigned PartSize = PartTy.getSizeInBits();
2125     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2126          Offset += PartSize, ++Idx) {
2127       unsigned ByteSize = PartSize / 8;
2128       unsigned ByteOffset = Offset / 8;
2129       unsigned NewAddrReg = 0;
2130 
2131       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2132 
2133       MachineMemOperand *NewMMO =
2134         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2135 
2136       if (IsLoad) {
2137         unsigned Dst = MRI.createGenericVirtualRegister(PartTy);
2138         ValRegs.push_back(Dst);
2139         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2140       } else {
2141         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2142       }
2143     }
2144 
2145     return Offset;
2146   };
2147 
2148   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2149 
2150   // Handle the rest of the register if this isn't an even type breakdown.
2151   if (LeftoverTy.isValid())
2152     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2153 
2154   if (IsLoad) {
2155     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2156                 LeftoverTy, NarrowLeftoverRegs);
2157   }
2158 
2159   MI.eraseFromParent();
2160   return Legalized;
2161 }
2162 
2163 LegalizerHelper::LegalizeResult
2164 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2165                                      LLT NarrowTy) {
2166   using namespace TargetOpcode;
2167 
2168   MIRBuilder.setInstr(MI);
2169   switch (MI.getOpcode()) {
2170   case G_IMPLICIT_DEF:
2171     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2172   case G_AND:
2173   case G_OR:
2174   case G_XOR:
2175   case G_ADD:
2176   case G_SUB:
2177   case G_MUL:
2178   case G_SMULH:
2179   case G_UMULH:
2180   case G_FADD:
2181   case G_FMUL:
2182   case G_FSUB:
2183   case G_FNEG:
2184   case G_FABS:
2185   case G_FCANONICALIZE:
2186   case G_FDIV:
2187   case G_FREM:
2188   case G_FMA:
2189   case G_FPOW:
2190   case G_FEXP:
2191   case G_FEXP2:
2192   case G_FLOG:
2193   case G_FLOG2:
2194   case G_FLOG10:
2195   case G_FNEARBYINT:
2196   case G_FCEIL:
2197   case G_FFLOOR:
2198   case G_FRINT:
2199   case G_INTRINSIC_ROUND:
2200   case G_INTRINSIC_TRUNC:
2201   case G_FCOS:
2202   case G_FSIN:
2203   case G_FSQRT:
2204   case G_BSWAP:
2205   case G_SDIV:
2206     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2207   case G_SHL:
2208   case G_LSHR:
2209   case G_ASHR:
2210   case G_CTLZ:
2211   case G_CTLZ_ZERO_UNDEF:
2212   case G_CTTZ:
2213   case G_CTTZ_ZERO_UNDEF:
2214   case G_CTPOP:
2215     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2216   case G_ZEXT:
2217   case G_SEXT:
2218   case G_ANYEXT:
2219   case G_FPEXT:
2220   case G_FPTRUNC:
2221   case G_SITOFP:
2222   case G_UITOFP:
2223   case G_FPTOSI:
2224   case G_FPTOUI:
2225   case G_INTTOPTR:
2226   case G_PTRTOINT:
2227   case G_ADDRSPACE_CAST:
2228     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2229   case G_ICMP:
2230   case G_FCMP:
2231     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2232   case G_SELECT:
2233     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2234   case G_PHI:
2235     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2236   case G_LOAD:
2237   case G_STORE:
2238     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2239   default:
2240     return UnableToLegalize;
2241   }
2242 }
2243 
2244 LegalizerHelper::LegalizeResult
2245 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2246                                              const LLT HalfTy, const LLT AmtTy) {
2247 
2248   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2249   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2250   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2251 
2252   if (Amt.isNullValue()) {
2253     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2254     MI.eraseFromParent();
2255     return Legalized;
2256   }
2257 
2258   LLT NVT = HalfTy;
2259   unsigned NVTBits = HalfTy.getSizeInBits();
2260   unsigned VTBits = 2 * NVTBits;
2261 
2262   SrcOp Lo(0), Hi(0);
2263   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2264     if (Amt.ugt(VTBits)) {
2265       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2266     } else if (Amt.ugt(NVTBits)) {
2267       Lo = MIRBuilder.buildConstant(NVT, 0);
2268       Hi = MIRBuilder.buildShl(NVT, InL,
2269                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2270     } else if (Amt == NVTBits) {
2271       Lo = MIRBuilder.buildConstant(NVT, 0);
2272       Hi = InL;
2273     } else {
2274       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2275       auto OrLHS =
2276           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2277       auto OrRHS = MIRBuilder.buildLShr(
2278           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2279       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2280     }
2281   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2282     if (Amt.ugt(VTBits)) {
2283       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2284     } else if (Amt.ugt(NVTBits)) {
2285       Lo = MIRBuilder.buildLShr(NVT, InH,
2286                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2287       Hi = MIRBuilder.buildConstant(NVT, 0);
2288     } else if (Amt == NVTBits) {
2289       Lo = InH;
2290       Hi = MIRBuilder.buildConstant(NVT, 0);
2291     } else {
2292       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2293 
2294       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2295       auto OrRHS = MIRBuilder.buildShl(
2296           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2297 
2298       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2299       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2300     }
2301   } else {
2302     if (Amt.ugt(VTBits)) {
2303       Hi = Lo = MIRBuilder.buildAShr(
2304           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2305     } else if (Amt.ugt(NVTBits)) {
2306       Lo = MIRBuilder.buildAShr(NVT, InH,
2307                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2308       Hi = MIRBuilder.buildAShr(NVT, InH,
2309                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2310     } else if (Amt == NVTBits) {
2311       Lo = InH;
2312       Hi = MIRBuilder.buildAShr(NVT, InH,
2313                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2314     } else {
2315       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2316 
2317       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2318       auto OrRHS = MIRBuilder.buildShl(
2319           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2320 
2321       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2322       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2323     }
2324   }
2325 
2326   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2327   MI.eraseFromParent();
2328 
2329   return Legalized;
2330 }
2331 
2332 // TODO: Optimize if constant shift amount.
2333 LegalizerHelper::LegalizeResult
2334 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2335                                    LLT RequestedTy) {
2336   if (TypeIdx == 1) {
2337     Observer.changingInstr(MI);
2338     narrowScalarSrc(MI, RequestedTy, 2);
2339     Observer.changedInstr(MI);
2340     return Legalized;
2341   }
2342 
2343   unsigned DstReg = MI.getOperand(0).getReg();
2344   LLT DstTy = MRI.getType(DstReg);
2345   if (DstTy.isVector())
2346     return UnableToLegalize;
2347 
2348   unsigned Amt = MI.getOperand(2).getReg();
2349   LLT ShiftAmtTy = MRI.getType(Amt);
2350   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2351   if (DstEltSize % 2 != 0)
2352     return UnableToLegalize;
2353 
2354   // Ignore the input type. We can only go to exactly half the size of the
2355   // input. If that isn't small enough, the resulting pieces will be further
2356   // legalized.
2357   const unsigned NewBitSize = DstEltSize / 2;
2358   const LLT HalfTy = LLT::scalar(NewBitSize);
2359   const LLT CondTy = LLT::scalar(1);
2360 
2361   if (const MachineInstr *KShiftAmt =
2362           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2363     return narrowScalarShiftByConstant(
2364         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2365   }
2366 
2367   // TODO: Expand with known bits.
2368 
2369   // Handle the fully general expansion by an unknown amount.
2370   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2371 
2372   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2373   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2374   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2375 
2376   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2377   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2378 
2379   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2380   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2381   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2382 
2383   unsigned ResultRegs[2];
2384   switch (MI.getOpcode()) {
2385   case TargetOpcode::G_SHL: {
2386     // Short: ShAmt < NewBitSize
2387     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2388 
2389     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2390     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2391     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2392 
2393     // Long: ShAmt >= NewBitSize
2394     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2395     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2396 
2397     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2398     auto Hi = MIRBuilder.buildSelect(
2399         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2400 
2401     ResultRegs[0] = Lo.getReg(0);
2402     ResultRegs[1] = Hi.getReg(0);
2403     break;
2404   }
2405   case TargetOpcode::G_LSHR: {
2406     // Short: ShAmt < NewBitSize
2407     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2408 
2409     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2410     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2411     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2412 
2413     // Long: ShAmt >= NewBitSize
2414     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2415     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2416 
2417     auto Lo = MIRBuilder.buildSelect(
2418         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2419     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2420 
2421     ResultRegs[0] = Lo.getReg(0);
2422     ResultRegs[1] = Hi.getReg(0);
2423     break;
2424   }
2425   case TargetOpcode::G_ASHR: {
2426     // Short: ShAmt < NewBitSize
2427     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2428 
2429     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2430     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2431     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2432 
2433     // Long: ShAmt >= NewBitSize
2434 
2435     // Sign of Hi part.
2436     auto HiL = MIRBuilder.buildAShr(
2437         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2438 
2439     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2440 
2441     auto Lo = MIRBuilder.buildSelect(
2442         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2443 
2444     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2445 
2446     ResultRegs[0] = Lo.getReg(0);
2447     ResultRegs[1] = Hi.getReg(0);
2448     break;
2449   }
2450   default:
2451     llvm_unreachable("not a shift");
2452   }
2453 
2454   MIRBuilder.buildMerge(DstReg, ResultRegs);
2455   MI.eraseFromParent();
2456   return Legalized;
2457 }
2458 
2459 LegalizerHelper::LegalizeResult
2460 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2461                                        LLT MoreTy) {
2462   assert(TypeIdx == 0 && "Expecting only Idx 0");
2463 
2464   Observer.changingInstr(MI);
2465   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2466     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2467     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2468     moreElementsVectorSrc(MI, MoreTy, I);
2469   }
2470 
2471   MachineBasicBlock &MBB = *MI.getParent();
2472   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2473   moreElementsVectorDst(MI, MoreTy, 0);
2474   Observer.changedInstr(MI);
2475   return Legalized;
2476 }
2477 
2478 LegalizerHelper::LegalizeResult
2479 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2480                                     LLT MoreTy) {
2481   MIRBuilder.setInstr(MI);
2482   unsigned Opc = MI.getOpcode();
2483   switch (Opc) {
2484   case TargetOpcode::G_IMPLICIT_DEF: {
2485     Observer.changingInstr(MI);
2486     moreElementsVectorDst(MI, MoreTy, 0);
2487     Observer.changedInstr(MI);
2488     return Legalized;
2489   }
2490   case TargetOpcode::G_AND:
2491   case TargetOpcode::G_OR:
2492   case TargetOpcode::G_XOR: {
2493     Observer.changingInstr(MI);
2494     moreElementsVectorSrc(MI, MoreTy, 1);
2495     moreElementsVectorSrc(MI, MoreTy, 2);
2496     moreElementsVectorDst(MI, MoreTy, 0);
2497     Observer.changedInstr(MI);
2498     return Legalized;
2499   }
2500   case TargetOpcode::G_EXTRACT:
2501     if (TypeIdx != 1)
2502       return UnableToLegalize;
2503     Observer.changingInstr(MI);
2504     moreElementsVectorSrc(MI, MoreTy, 1);
2505     Observer.changedInstr(MI);
2506     return Legalized;
2507   case TargetOpcode::G_INSERT:
2508     if (TypeIdx != 0)
2509       return UnableToLegalize;
2510     Observer.changingInstr(MI);
2511     moreElementsVectorSrc(MI, MoreTy, 1);
2512     moreElementsVectorDst(MI, MoreTy, 0);
2513     Observer.changedInstr(MI);
2514     return Legalized;
2515   case TargetOpcode::G_SELECT:
2516     if (TypeIdx != 0)
2517       return UnableToLegalize;
2518     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2519       return UnableToLegalize;
2520 
2521     Observer.changingInstr(MI);
2522     moreElementsVectorSrc(MI, MoreTy, 2);
2523     moreElementsVectorSrc(MI, MoreTy, 3);
2524     moreElementsVectorDst(MI, MoreTy, 0);
2525     Observer.changedInstr(MI);
2526     return Legalized;
2527   case TargetOpcode::G_PHI:
2528     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2529   default:
2530     return UnableToLegalize;
2531   }
2532 }
2533 
2534 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<unsigned> &DstRegs,
2535                                         ArrayRef<unsigned> Src1Regs,
2536                                         ArrayRef<unsigned> Src2Regs,
2537                                         LLT NarrowTy) {
2538   MachineIRBuilder &B = MIRBuilder;
2539   unsigned SrcParts = Src1Regs.size();
2540   unsigned DstParts = DstRegs.size();
2541 
2542   unsigned DstIdx = 0; // Low bits of the result.
2543   unsigned FactorSum =
2544       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
2545   DstRegs[DstIdx] = FactorSum;
2546 
2547   unsigned CarrySumPrevDstIdx;
2548   SmallVector<unsigned, 4> Factors;
2549 
2550   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
2551     // Collect low parts of muls for DstIdx.
2552     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
2553          i <= std::min(DstIdx, SrcParts - 1); ++i) {
2554       MachineInstrBuilder Mul =
2555           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
2556       Factors.push_back(Mul.getReg(0));
2557     }
2558     // Collect high parts of muls from previous DstIdx.
2559     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
2560          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
2561       MachineInstrBuilder Umulh =
2562           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
2563       Factors.push_back(Umulh.getReg(0));
2564     }
2565     // Add CarrySum from additons calculated for previous DstIdx.
2566     if (DstIdx != 1) {
2567       Factors.push_back(CarrySumPrevDstIdx);
2568     }
2569 
2570     unsigned CarrySum = 0;
2571     // Add all factors and accumulate all carries into CarrySum.
2572     if (DstIdx != DstParts - 1) {
2573       MachineInstrBuilder Uaddo =
2574           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
2575       FactorSum = Uaddo.getReg(0);
2576       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
2577       for (unsigned i = 2; i < Factors.size(); ++i) {
2578         MachineInstrBuilder Uaddo =
2579             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
2580         FactorSum = Uaddo.getReg(0);
2581         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
2582         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
2583       }
2584     } else {
2585       // Since value for the next index is not calculated, neither is CarrySum.
2586       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
2587       for (unsigned i = 2; i < Factors.size(); ++i)
2588         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
2589     }
2590 
2591     CarrySumPrevDstIdx = CarrySum;
2592     DstRegs[DstIdx] = FactorSum;
2593     Factors.clear();
2594   }
2595 }
2596 
2597 LegalizerHelper::LegalizeResult
2598 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
2599   unsigned DstReg = MI.getOperand(0).getReg();
2600   unsigned Src1 = MI.getOperand(1).getReg();
2601   unsigned Src2 = MI.getOperand(2).getReg();
2602 
2603   LLT Ty = MRI.getType(DstReg);
2604   if (Ty.isVector())
2605     return UnableToLegalize;
2606 
2607   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
2608   unsigned DstSize = Ty.getSizeInBits();
2609   unsigned NarrowSize = NarrowTy.getSizeInBits();
2610   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
2611     return UnableToLegalize;
2612 
2613   unsigned NumDstParts = DstSize / NarrowSize;
2614   unsigned NumSrcParts = SrcSize / NarrowSize;
2615   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
2616   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
2617 
2618   SmallVector<unsigned, 2> Src1Parts, Src2Parts, DstTmpRegs;
2619   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
2620   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
2621   DstTmpRegs.resize(DstTmpParts);
2622   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
2623 
2624   // Take only high half of registers if this is high mul.
2625   ArrayRef<unsigned> DstRegs(
2626       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
2627   MIRBuilder.buildMerge(DstReg, DstRegs);
2628   MI.eraseFromParent();
2629   return Legalized;
2630 }
2631 
2632 LegalizerHelper::LegalizeResult
2633 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2634                                      LLT NarrowTy) {
2635   if (TypeIdx != 1)
2636     return UnableToLegalize;
2637 
2638   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2639 
2640   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2641   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2642   // NarrowSize.
2643   if (SizeOp1 % NarrowSize != 0)
2644     return UnableToLegalize;
2645   int NumParts = SizeOp1 / NarrowSize;
2646 
2647   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2648   SmallVector<uint64_t, 2> Indexes;
2649   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2650 
2651   unsigned OpReg = MI.getOperand(0).getReg();
2652   uint64_t OpStart = MI.getOperand(2).getImm();
2653   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2654   for (int i = 0; i < NumParts; ++i) {
2655     unsigned SrcStart = i * NarrowSize;
2656 
2657     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2658       // No part of the extract uses this subregister, ignore it.
2659       continue;
2660     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2661       // The entire subregister is extracted, forward the value.
2662       DstRegs.push_back(SrcRegs[i]);
2663       continue;
2664     }
2665 
2666     // OpSegStart is where this destination segment would start in OpReg if it
2667     // extended infinitely in both directions.
2668     int64_t ExtractOffset;
2669     uint64_t SegSize;
2670     if (OpStart < SrcStart) {
2671       ExtractOffset = 0;
2672       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2673     } else {
2674       ExtractOffset = OpStart - SrcStart;
2675       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2676     }
2677 
2678     unsigned SegReg = SrcRegs[i];
2679     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2680       // A genuine extract is needed.
2681       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2682       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2683     }
2684 
2685     DstRegs.push_back(SegReg);
2686   }
2687 
2688   unsigned DstReg = MI.getOperand(0).getReg();
2689   if(MRI.getType(DstReg).isVector())
2690     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2691   else
2692     MIRBuilder.buildMerge(DstReg, DstRegs);
2693   MI.eraseFromParent();
2694   return Legalized;
2695 }
2696 
2697 LegalizerHelper::LegalizeResult
2698 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2699                                     LLT NarrowTy) {
2700   // FIXME: Don't know how to handle secondary types yet.
2701   if (TypeIdx != 0)
2702     return UnableToLegalize;
2703 
2704   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2705   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2706 
2707   // FIXME: add support for when SizeOp0 isn't an exact multiple of
2708   // NarrowSize.
2709   if (SizeOp0 % NarrowSize != 0)
2710     return UnableToLegalize;
2711 
2712   int NumParts = SizeOp0 / NarrowSize;
2713 
2714   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2715   SmallVector<uint64_t, 2> Indexes;
2716   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2717 
2718   unsigned OpReg = MI.getOperand(2).getReg();
2719   uint64_t OpStart = MI.getOperand(3).getImm();
2720   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2721   for (int i = 0; i < NumParts; ++i) {
2722     unsigned DstStart = i * NarrowSize;
2723 
2724     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
2725       // No part of the insert affects this subregister, forward the original.
2726       DstRegs.push_back(SrcRegs[i]);
2727       continue;
2728     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2729       // The entire subregister is defined by this insert, forward the new
2730       // value.
2731       DstRegs.push_back(OpReg);
2732       continue;
2733     }
2734 
2735     // OpSegStart is where this destination segment would start in OpReg if it
2736     // extended infinitely in both directions.
2737     int64_t ExtractOffset, InsertOffset;
2738     uint64_t SegSize;
2739     if (OpStart < DstStart) {
2740       InsertOffset = 0;
2741       ExtractOffset = DstStart - OpStart;
2742       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
2743     } else {
2744       InsertOffset = OpStart - DstStart;
2745       ExtractOffset = 0;
2746       SegSize =
2747         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
2748     }
2749 
2750     unsigned SegReg = OpReg;
2751     if (ExtractOffset != 0 || SegSize != OpSize) {
2752       // A genuine extract is needed.
2753       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2754       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
2755     }
2756 
2757     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2758     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
2759     DstRegs.push_back(DstReg);
2760   }
2761 
2762   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2763   unsigned DstReg = MI.getOperand(0).getReg();
2764   if(MRI.getType(DstReg).isVector())
2765     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2766   else
2767     MIRBuilder.buildMerge(DstReg, DstRegs);
2768   MI.eraseFromParent();
2769   return Legalized;
2770 }
2771 
2772 LegalizerHelper::LegalizeResult
2773 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
2774                                    LLT NarrowTy) {
2775   unsigned DstReg = MI.getOperand(0).getReg();
2776   LLT DstTy = MRI.getType(DstReg);
2777 
2778   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
2779 
2780   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2781   SmallVector<unsigned, 4> Src0Regs, Src0LeftoverRegs;
2782   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2783   LLT LeftoverTy;
2784   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
2785                     Src0Regs, Src0LeftoverRegs))
2786     return UnableToLegalize;
2787 
2788   LLT Unused;
2789   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
2790                     Src1Regs, Src1LeftoverRegs))
2791     llvm_unreachable("inconsistent extractParts result");
2792 
2793   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2794     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
2795                                         {Src0Regs[I], Src1Regs[I]});
2796     DstRegs.push_back(Inst->getOperand(0).getReg());
2797   }
2798 
2799   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2800     auto Inst = MIRBuilder.buildInstr(
2801       MI.getOpcode(),
2802       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
2803     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
2804   }
2805 
2806   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2807               LeftoverTy, DstLeftoverRegs);
2808 
2809   MI.eraseFromParent();
2810   return Legalized;
2811 }
2812 
2813 LegalizerHelper::LegalizeResult
2814 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
2815                                     LLT NarrowTy) {
2816   if (TypeIdx != 0)
2817     return UnableToLegalize;
2818 
2819   unsigned CondReg = MI.getOperand(1).getReg();
2820   LLT CondTy = MRI.getType(CondReg);
2821   if (CondTy.isVector()) // TODO: Handle vselect
2822     return UnableToLegalize;
2823 
2824   unsigned DstReg = MI.getOperand(0).getReg();
2825   LLT DstTy = MRI.getType(DstReg);
2826 
2827   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2828   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2829   SmallVector<unsigned, 4> Src2Regs, Src2LeftoverRegs;
2830   LLT LeftoverTy;
2831   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
2832                     Src1Regs, Src1LeftoverRegs))
2833     return UnableToLegalize;
2834 
2835   LLT Unused;
2836   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
2837                     Src2Regs, Src2LeftoverRegs))
2838     llvm_unreachable("inconsistent extractParts result");
2839 
2840   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2841     auto Select = MIRBuilder.buildSelect(NarrowTy,
2842                                          CondReg, Src1Regs[I], Src2Regs[I]);
2843     DstRegs.push_back(Select->getOperand(0).getReg());
2844   }
2845 
2846   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2847     auto Select = MIRBuilder.buildSelect(
2848       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
2849     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
2850   }
2851 
2852   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2853               LeftoverTy, DstLeftoverRegs);
2854 
2855   MI.eraseFromParent();
2856   return Legalized;
2857 }
2858 
2859 LegalizerHelper::LegalizeResult
2860 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2861   unsigned Opc = MI.getOpcode();
2862   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2863   auto isSupported = [this](const LegalityQuery &Q) {
2864     auto QAction = LI.getAction(Q).Action;
2865     return QAction == Legal || QAction == Libcall || QAction == Custom;
2866   };
2867   switch (Opc) {
2868   default:
2869     return UnableToLegalize;
2870   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
2871     // This trivially expands to CTLZ.
2872     Observer.changingInstr(MI);
2873     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
2874     Observer.changedInstr(MI);
2875     return Legalized;
2876   }
2877   case TargetOpcode::G_CTLZ: {
2878     unsigned SrcReg = MI.getOperand(1).getReg();
2879     unsigned Len = Ty.getSizeInBits();
2880     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
2881       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
2882       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
2883                                              {Ty}, {SrcReg});
2884       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2885       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2886       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2887                                           SrcReg, MIBZero);
2888       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2889                              MIBCtlzZU);
2890       MI.eraseFromParent();
2891       return Legalized;
2892     }
2893     // for now, we do this:
2894     // NewLen = NextPowerOf2(Len);
2895     // x = x | (x >> 1);
2896     // x = x | (x >> 2);
2897     // ...
2898     // x = x | (x >>16);
2899     // x = x | (x >>32); // for 64-bit input
2900     // Upto NewLen/2
2901     // return Len - popcount(x);
2902     //
2903     // Ref: "Hacker's Delight" by Henry Warren
2904     unsigned Op = SrcReg;
2905     unsigned NewLen = PowerOf2Ceil(Len);
2906     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
2907       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
2908       auto MIBOp = MIRBuilder.buildInstr(
2909           TargetOpcode::G_OR, {Ty},
2910           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
2911                                      {Op, MIBShiftAmt})});
2912       Op = MIBOp->getOperand(0).getReg();
2913     }
2914     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
2915     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2916                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
2917     MI.eraseFromParent();
2918     return Legalized;
2919   }
2920   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
2921     // This trivially expands to CTTZ.
2922     Observer.changingInstr(MI);
2923     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
2924     Observer.changedInstr(MI);
2925     return Legalized;
2926   }
2927   case TargetOpcode::G_CTTZ: {
2928     unsigned SrcReg = MI.getOperand(1).getReg();
2929     unsigned Len = Ty.getSizeInBits();
2930     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
2931       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
2932       // zero.
2933       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
2934                                              {Ty}, {SrcReg});
2935       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2936       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2937       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2938                                           SrcReg, MIBZero);
2939       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2940                              MIBCttzZU);
2941       MI.eraseFromParent();
2942       return Legalized;
2943     }
2944     // for now, we use: { return popcount(~x & (x - 1)); }
2945     // unless the target has ctlz but not ctpop, in which case we use:
2946     // { return 32 - nlz(~x & (x-1)); }
2947     // Ref: "Hacker's Delight" by Henry Warren
2948     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
2949     auto MIBNot =
2950         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
2951     auto MIBTmp = MIRBuilder.buildInstr(
2952         TargetOpcode::G_AND, {Ty},
2953         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
2954                                        {SrcReg, MIBCstNeg1})});
2955     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
2956         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
2957       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
2958       MIRBuilder.buildInstr(
2959           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2960           {MIBCstLen,
2961            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
2962       MI.eraseFromParent();
2963       return Legalized;
2964     }
2965     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
2966     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
2967     return Legalized;
2968   }
2969   }
2970 }
2971