1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   auto Step = LI.getAction(MI, MRI);
86   switch (Step.Action) {
87   case Legal:
88     LLVM_DEBUG(dbgs() << ".. Already legal\n");
89     return AlreadyLegal;
90   case Libcall:
91     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
92     return libcall(MI);
93   case NarrowScalar:
94     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
95     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
96   case WidenScalar:
97     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
98     return widenScalar(MI, Step.TypeIdx, Step.NewType);
99   case Lower:
100     LLVM_DEBUG(dbgs() << ".. Lower\n");
101     return lower(MI, Step.TypeIdx, Step.NewType);
102   case FewerElements:
103     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
104     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
105   case MoreElements:
106     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
107     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
108   case Custom:
109     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
110     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
111                                                             : UnableToLegalize;
112   default:
113     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
114     return UnableToLegalize;
115   }
116 }
117 
118 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
119                                    SmallVectorImpl<unsigned> &VRegs) {
120   for (int i = 0; i < NumParts; ++i)
121     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
122   MIRBuilder.buildUnmerge(VRegs, Reg);
123 }
124 
125 bool LegalizerHelper::extractParts(unsigned Reg, LLT RegTy,
126                                    LLT MainTy, LLT &LeftoverTy,
127                                    SmallVectorImpl<unsigned> &VRegs,
128                                    SmallVectorImpl<unsigned> &LeftoverRegs) {
129   assert(!LeftoverTy.isValid() && "this is an out argument");
130 
131   unsigned RegSize = RegTy.getSizeInBits();
132   unsigned MainSize = MainTy.getSizeInBits();
133   unsigned NumParts = RegSize / MainSize;
134   unsigned LeftoverSize = RegSize - NumParts * MainSize;
135 
136   // Use an unmerge when possible.
137   if (LeftoverSize == 0) {
138     for (unsigned I = 0; I < NumParts; ++I)
139       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
140     MIRBuilder.buildUnmerge(VRegs, Reg);
141     return true;
142   }
143 
144   if (MainTy.isVector()) {
145     unsigned EltSize = MainTy.getScalarSizeInBits();
146     if (LeftoverSize % EltSize != 0)
147       return false;
148     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
149   } else {
150     LeftoverTy = LLT::scalar(LeftoverSize);
151   }
152 
153   // For irregular sizes, extract the individual parts.
154   for (unsigned I = 0; I != NumParts; ++I) {
155     unsigned NewReg = MRI.createGenericVirtualRegister(MainTy);
156     VRegs.push_back(NewReg);
157     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
158   }
159 
160   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
161        Offset += LeftoverSize) {
162     unsigned NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
163     LeftoverRegs.push_back(NewReg);
164     MIRBuilder.buildExtract(NewReg, Reg, Offset);
165   }
166 
167   return true;
168 }
169 
170 void LegalizerHelper::insertParts(unsigned DstReg,
171                                   LLT ResultTy, LLT PartTy,
172                                   ArrayRef<unsigned> PartRegs,
173                                   LLT LeftoverTy,
174                                   ArrayRef<unsigned> LeftoverRegs) {
175   if (!LeftoverTy.isValid()) {
176     assert(LeftoverRegs.empty());
177 
178     if (!ResultTy.isVector()) {
179       MIRBuilder.buildMerge(DstReg, PartRegs);
180       return;
181     }
182 
183     if (PartTy.isVector())
184       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
185     else
186       MIRBuilder.buildBuildVector(DstReg, PartRegs);
187     return;
188   }
189 
190   unsigned PartSize = PartTy.getSizeInBits();
191   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
192 
193   unsigned CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
194   MIRBuilder.buildUndef(CurResultReg);
195 
196   unsigned Offset = 0;
197   for (unsigned PartReg : PartRegs) {
198     unsigned NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
199     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
200     CurResultReg = NewResultReg;
201     Offset += PartSize;
202   }
203 
204   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
205     // Use the original output register for the final insert to avoid a copy.
206     unsigned NewResultReg = (I + 1 == E) ?
207       DstReg : MRI.createGenericVirtualRegister(ResultTy);
208 
209     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
210     CurResultReg = NewResultReg;
211     Offset += LeftoverPartSize;
212   }
213 }
214 
215 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
216   switch (Opcode) {
217   case TargetOpcode::G_SDIV:
218     assert((Size == 32 || Size == 64) && "Unsupported size");
219     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
220   case TargetOpcode::G_UDIV:
221     assert((Size == 32 || Size == 64) && "Unsupported size");
222     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
223   case TargetOpcode::G_SREM:
224     assert((Size == 32 || Size == 64) && "Unsupported size");
225     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
226   case TargetOpcode::G_UREM:
227     assert((Size == 32 || Size == 64) && "Unsupported size");
228     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
229   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
230     assert(Size == 32 && "Unsupported size");
231     return RTLIB::CTLZ_I32;
232   case TargetOpcode::G_FADD:
233     assert((Size == 32 || Size == 64) && "Unsupported size");
234     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
235   case TargetOpcode::G_FSUB:
236     assert((Size == 32 || Size == 64) && "Unsupported size");
237     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
238   case TargetOpcode::G_FMUL:
239     assert((Size == 32 || Size == 64) && "Unsupported size");
240     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
241   case TargetOpcode::G_FDIV:
242     assert((Size == 32 || Size == 64) && "Unsupported size");
243     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
244   case TargetOpcode::G_FEXP:
245     assert((Size == 32 || Size == 64) && "Unsupported size");
246     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
247   case TargetOpcode::G_FREM:
248     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
249   case TargetOpcode::G_FPOW:
250     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
251   case TargetOpcode::G_FMA:
252     assert((Size == 32 || Size == 64) && "Unsupported size");
253     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
254   case TargetOpcode::G_FSIN:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     return Size == 128 ? RTLIB::SIN_F128
257                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
258   case TargetOpcode::G_FCOS:
259     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
260     return Size == 128 ? RTLIB::COS_F128
261                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
262   case TargetOpcode::G_FLOG10:
263     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
264     return Size == 128 ? RTLIB::LOG10_F128
265                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
266   case TargetOpcode::G_FLOG:
267     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
268     return Size == 128 ? RTLIB::LOG_F128
269                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
270   case TargetOpcode::G_FLOG2:
271     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
272     return Size == 128 ? RTLIB::LOG2_F128
273                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
274   }
275   llvm_unreachable("Unknown libcall function");
276 }
277 
278 LegalizerHelper::LegalizeResult
279 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
280                     const CallLowering::ArgInfo &Result,
281                     ArrayRef<CallLowering::ArgInfo> Args) {
282   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
283   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
284   const char *Name = TLI.getLibcallName(Libcall);
285 
286   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
287   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
288                      MachineOperand::CreateES(Name), Result, Args))
289     return LegalizerHelper::UnableToLegalize;
290 
291   return LegalizerHelper::Legalized;
292 }
293 
294 // Useful for libcalls where all operands have the same type.
295 static LegalizerHelper::LegalizeResult
296 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
297               Type *OpType) {
298   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
299 
300   SmallVector<CallLowering::ArgInfo, 3> Args;
301   for (unsigned i = 1; i < MI.getNumOperands(); i++)
302     Args.push_back({MI.getOperand(i).getReg(), OpType});
303   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
304                        Args);
305 }
306 
307 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
308                                        Type *FromType) {
309   auto ToMVT = MVT::getVT(ToType);
310   auto FromMVT = MVT::getVT(FromType);
311 
312   switch (Opcode) {
313   case TargetOpcode::G_FPEXT:
314     return RTLIB::getFPEXT(FromMVT, ToMVT);
315   case TargetOpcode::G_FPTRUNC:
316     return RTLIB::getFPROUND(FromMVT, ToMVT);
317   case TargetOpcode::G_FPTOSI:
318     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
319   case TargetOpcode::G_FPTOUI:
320     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
321   case TargetOpcode::G_SITOFP:
322     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
323   case TargetOpcode::G_UITOFP:
324     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
325   }
326   llvm_unreachable("Unsupported libcall function");
327 }
328 
329 static LegalizerHelper::LegalizeResult
330 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
331                   Type *FromType) {
332   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
333   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
334                        {{MI.getOperand(1).getReg(), FromType}});
335 }
336 
337 LegalizerHelper::LegalizeResult
338 LegalizerHelper::libcall(MachineInstr &MI) {
339   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
340   unsigned Size = LLTy.getSizeInBits();
341   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
342 
343   MIRBuilder.setInstr(MI);
344 
345   switch (MI.getOpcode()) {
346   default:
347     return UnableToLegalize;
348   case TargetOpcode::G_SDIV:
349   case TargetOpcode::G_UDIV:
350   case TargetOpcode::G_SREM:
351   case TargetOpcode::G_UREM:
352   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
353     Type *HLTy = IntegerType::get(Ctx, Size);
354     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
355     if (Status != Legalized)
356       return Status;
357     break;
358   }
359   case TargetOpcode::G_FADD:
360   case TargetOpcode::G_FSUB:
361   case TargetOpcode::G_FMUL:
362   case TargetOpcode::G_FDIV:
363   case TargetOpcode::G_FMA:
364   case TargetOpcode::G_FPOW:
365   case TargetOpcode::G_FREM:
366   case TargetOpcode::G_FCOS:
367   case TargetOpcode::G_FSIN:
368   case TargetOpcode::G_FLOG10:
369   case TargetOpcode::G_FLOG:
370   case TargetOpcode::G_FLOG2:
371   case TargetOpcode::G_FEXP: {
372     if (Size > 64) {
373       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
374       return UnableToLegalize;
375     }
376     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
377     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
378     if (Status != Legalized)
379       return Status;
380     break;
381   }
382   case TargetOpcode::G_FPEXT: {
383     // FIXME: Support other floating point types (half, fp128 etc)
384     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
385     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
386     if (ToSize != 64 || FromSize != 32)
387       return UnableToLegalize;
388     LegalizeResult Status = conversionLibcall(
389         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
390     if (Status != Legalized)
391       return Status;
392     break;
393   }
394   case TargetOpcode::G_FPTRUNC: {
395     // FIXME: Support other floating point types (half, fp128 etc)
396     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
397     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
398     if (ToSize != 32 || FromSize != 64)
399       return UnableToLegalize;
400     LegalizeResult Status = conversionLibcall(
401         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
402     if (Status != Legalized)
403       return Status;
404     break;
405   }
406   case TargetOpcode::G_FPTOSI:
407   case TargetOpcode::G_FPTOUI: {
408     // FIXME: Support other types
409     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
410     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
411     if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
412       return UnableToLegalize;
413     LegalizeResult Status = conversionLibcall(
414         MI, MIRBuilder, Type::getInt32Ty(Ctx),
415         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
416     if (Status != Legalized)
417       return Status;
418     break;
419   }
420   case TargetOpcode::G_SITOFP:
421   case TargetOpcode::G_UITOFP: {
422     // FIXME: Support other types
423     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
424     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
425     if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
426       return UnableToLegalize;
427     LegalizeResult Status = conversionLibcall(
428         MI, MIRBuilder,
429         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
430         Type::getInt32Ty(Ctx));
431     if (Status != Legalized)
432       return Status;
433     break;
434   }
435   }
436 
437   MI.eraseFromParent();
438   return Legalized;
439 }
440 
441 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
442                                                               unsigned TypeIdx,
443                                                               LLT NarrowTy) {
444   MIRBuilder.setInstr(MI);
445 
446   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
447   uint64_t NarrowSize = NarrowTy.getSizeInBits();
448 
449   switch (MI.getOpcode()) {
450   default:
451     return UnableToLegalize;
452   case TargetOpcode::G_IMPLICIT_DEF: {
453     // FIXME: add support for when SizeOp0 isn't an exact multiple of
454     // NarrowSize.
455     if (SizeOp0 % NarrowSize != 0)
456       return UnableToLegalize;
457     int NumParts = SizeOp0 / NarrowSize;
458 
459     SmallVector<unsigned, 2> DstRegs;
460     for (int i = 0; i < NumParts; ++i)
461       DstRegs.push_back(
462           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
463 
464     unsigned DstReg = MI.getOperand(0).getReg();
465     if(MRI.getType(DstReg).isVector())
466       MIRBuilder.buildBuildVector(DstReg, DstRegs);
467     else
468       MIRBuilder.buildMerge(DstReg, DstRegs);
469     MI.eraseFromParent();
470     return Legalized;
471   }
472   case TargetOpcode::G_ADD: {
473     // FIXME: add support for when SizeOp0 isn't an exact multiple of
474     // NarrowSize.
475     if (SizeOp0 % NarrowSize != 0)
476       return UnableToLegalize;
477     // Expand in terms of carry-setting/consuming G_ADDE instructions.
478     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
479 
480     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
481     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
482     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
483 
484     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
485     MIRBuilder.buildConstant(CarryIn, 0);
486 
487     for (int i = 0; i < NumParts; ++i) {
488       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
489       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
490 
491       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
492                             Src2Regs[i], CarryIn);
493 
494       DstRegs.push_back(DstReg);
495       CarryIn = CarryOut;
496     }
497     unsigned DstReg = MI.getOperand(0).getReg();
498     if(MRI.getType(DstReg).isVector())
499       MIRBuilder.buildBuildVector(DstReg, DstRegs);
500     else
501       MIRBuilder.buildMerge(DstReg, DstRegs);
502     MI.eraseFromParent();
503     return Legalized;
504   }
505   case TargetOpcode::G_SUB: {
506     // FIXME: add support for when SizeOp0 isn't an exact multiple of
507     // NarrowSize.
508     if (SizeOp0 % NarrowSize != 0)
509       return UnableToLegalize;
510 
511     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
512 
513     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
514     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
515     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
516 
517     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
518     unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
519     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
520                           {Src1Regs[0], Src2Regs[0]});
521     DstRegs.push_back(DstReg);
522     unsigned BorrowIn = BorrowOut;
523     for (int i = 1; i < NumParts; ++i) {
524       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
525       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
526 
527       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
528                             {Src1Regs[i], Src2Regs[i], BorrowIn});
529 
530       DstRegs.push_back(DstReg);
531       BorrowIn = BorrowOut;
532     }
533     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
534     MI.eraseFromParent();
535     return Legalized;
536   }
537   case TargetOpcode::G_MUL:
538     return narrowScalarMul(MI, TypeIdx, NarrowTy);
539   case TargetOpcode::G_EXTRACT:
540     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
541   case TargetOpcode::G_INSERT:
542     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
543   case TargetOpcode::G_LOAD: {
544     const auto &MMO = **MI.memoperands_begin();
545     unsigned DstReg = MI.getOperand(0).getReg();
546     LLT DstTy = MRI.getType(DstReg);
547     if (DstTy.isVector())
548       return UnableToLegalize;
549 
550     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
551       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
552       auto &MMO = **MI.memoperands_begin();
553       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
554       MIRBuilder.buildAnyExt(DstReg, TmpReg);
555       MI.eraseFromParent();
556       return Legalized;
557     }
558 
559     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
560   }
561   case TargetOpcode::G_ZEXTLOAD:
562   case TargetOpcode::G_SEXTLOAD: {
563     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
564     unsigned DstReg = MI.getOperand(0).getReg();
565     unsigned PtrReg = MI.getOperand(1).getReg();
566 
567     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
568     auto &MMO = **MI.memoperands_begin();
569     if (MMO.getSize() * 8 == NarrowSize) {
570       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
571     } else {
572       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
573         : TargetOpcode::G_SEXTLOAD;
574       MIRBuilder.buildInstr(ExtLoad)
575         .addDef(TmpReg)
576         .addUse(PtrReg)
577         .addMemOperand(&MMO);
578     }
579 
580     if (ZExt)
581       MIRBuilder.buildZExt(DstReg, TmpReg);
582     else
583       MIRBuilder.buildSExt(DstReg, TmpReg);
584 
585     MI.eraseFromParent();
586     return Legalized;
587   }
588   case TargetOpcode::G_STORE: {
589     const auto &MMO = **MI.memoperands_begin();
590 
591     unsigned SrcReg = MI.getOperand(0).getReg();
592     LLT SrcTy = MRI.getType(SrcReg);
593     if (SrcTy.isVector())
594       return UnableToLegalize;
595 
596     int NumParts = SizeOp0 / NarrowSize;
597     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
598     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
599     if (SrcTy.isVector() && LeftoverBits != 0)
600       return UnableToLegalize;
601 
602     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
603       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
604       auto &MMO = **MI.memoperands_begin();
605       MIRBuilder.buildTrunc(TmpReg, SrcReg);
606       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
607       MI.eraseFromParent();
608       return Legalized;
609     }
610 
611     return reduceLoadStoreWidth(MI, 0, NarrowTy);
612   }
613   case TargetOpcode::G_CONSTANT: {
614     // FIXME: add support for when SizeOp0 isn't an exact multiple of
615     // NarrowSize.
616     if (SizeOp0 % NarrowSize != 0)
617       return UnableToLegalize;
618     int NumParts = SizeOp0 / NarrowSize;
619     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
620     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
621 
622     SmallVector<unsigned, 2> DstRegs;
623     for (int i = 0; i < NumParts; ++i) {
624       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
625       ConstantInt *CI =
626           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
627       MIRBuilder.buildConstant(DstReg, *CI);
628       DstRegs.push_back(DstReg);
629     }
630     unsigned DstReg = MI.getOperand(0).getReg();
631     if(MRI.getType(DstReg).isVector())
632       MIRBuilder.buildBuildVector(DstReg, DstRegs);
633     else
634       MIRBuilder.buildMerge(DstReg, DstRegs);
635     MI.eraseFromParent();
636     return Legalized;
637   }
638   case TargetOpcode::G_SELECT:
639     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
640   case TargetOpcode::G_AND:
641   case TargetOpcode::G_OR:
642   case TargetOpcode::G_XOR: {
643     // Legalize bitwise operation:
644     // A = BinOp<Ty> B, C
645     // into:
646     // B1, ..., BN = G_UNMERGE_VALUES B
647     // C1, ..., CN = G_UNMERGE_VALUES C
648     // A1 = BinOp<Ty/N> B1, C2
649     // ...
650     // AN = BinOp<Ty/N> BN, CN
651     // A = G_MERGE_VALUES A1, ..., AN
652 
653     // FIXME: add support for when SizeOp0 isn't an exact multiple of
654     // NarrowSize.
655     if (SizeOp0 % NarrowSize != 0)
656       return UnableToLegalize;
657     int NumParts = SizeOp0 / NarrowSize;
658 
659     // List the registers where the destination will be scattered.
660     SmallVector<unsigned, 2> DstRegs;
661     // List the registers where the first argument will be split.
662     SmallVector<unsigned, 2> SrcsReg1;
663     // List the registers where the second argument will be split.
664     SmallVector<unsigned, 2> SrcsReg2;
665     // Create all the temporary registers.
666     for (int i = 0; i < NumParts; ++i) {
667       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
668       unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
669       unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
670 
671       DstRegs.push_back(DstReg);
672       SrcsReg1.push_back(SrcReg1);
673       SrcsReg2.push_back(SrcReg2);
674     }
675     // Explode the big arguments into smaller chunks.
676     MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
677     MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
678 
679     // Do the operation on each small part.
680     for (int i = 0; i < NumParts; ++i)
681       MIRBuilder.buildInstr(MI.getOpcode(), {DstRegs[i]},
682                             {SrcsReg1[i], SrcsReg2[i]});
683 
684     // Gather the destination registers into the final destination.
685     unsigned DstReg = MI.getOperand(0).getReg();
686     if(MRI.getType(DstReg).isVector())
687       MIRBuilder.buildBuildVector(DstReg, DstRegs);
688     else
689       MIRBuilder.buildMerge(DstReg, DstRegs);
690     MI.eraseFromParent();
691     return Legalized;
692   }
693   case TargetOpcode::G_SHL:
694   case TargetOpcode::G_LSHR:
695   case TargetOpcode::G_ASHR:
696     return narrowScalarShift(MI, TypeIdx, NarrowTy);
697   case TargetOpcode::G_CTLZ:
698   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
699   case TargetOpcode::G_CTTZ:
700   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
701   case TargetOpcode::G_CTPOP:
702     if (TypeIdx != 0)
703       return UnableToLegalize; // TODO
704 
705     Observer.changingInstr(MI);
706     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
707     Observer.changedInstr(MI);
708     return Legalized;
709   case TargetOpcode::G_INTTOPTR:
710     if (TypeIdx != 1)
711       return UnableToLegalize;
712 
713     Observer.changingInstr(MI);
714     narrowScalarSrc(MI, NarrowTy, 1);
715     Observer.changedInstr(MI);
716     return Legalized;
717   case TargetOpcode::G_PTRTOINT:
718     if (TypeIdx != 0)
719       return UnableToLegalize;
720 
721     Observer.changingInstr(MI);
722     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
723     Observer.changedInstr(MI);
724     return Legalized;
725   }
726 }
727 
728 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
729                                      unsigned OpIdx, unsigned ExtOpcode) {
730   MachineOperand &MO = MI.getOperand(OpIdx);
731   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
732   MO.setReg(ExtB->getOperand(0).getReg());
733 }
734 
735 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
736                                       unsigned OpIdx) {
737   MachineOperand &MO = MI.getOperand(OpIdx);
738   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
739                                     {MO.getReg()});
740   MO.setReg(ExtB->getOperand(0).getReg());
741 }
742 
743 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
744                                      unsigned OpIdx, unsigned TruncOpcode) {
745   MachineOperand &MO = MI.getOperand(OpIdx);
746   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
747   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
748   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
749   MO.setReg(DstExt);
750 }
751 
752 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
753                                       unsigned OpIdx, unsigned ExtOpcode) {
754   MachineOperand &MO = MI.getOperand(OpIdx);
755   unsigned DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
756   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
757   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
758   MO.setReg(DstTrunc);
759 }
760 
761 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
762                                             unsigned OpIdx) {
763   MachineOperand &MO = MI.getOperand(OpIdx);
764   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
765   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
766   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
767   MO.setReg(DstExt);
768 }
769 
770 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
771                                             unsigned OpIdx) {
772   MachineOperand &MO = MI.getOperand(OpIdx);
773 
774   LLT OldTy = MRI.getType(MO.getReg());
775   unsigned OldElts = OldTy.getNumElements();
776   unsigned NewElts = MoreTy.getNumElements();
777 
778   unsigned NumParts = NewElts / OldElts;
779 
780   // Use concat_vectors if the result is a multiple of the number of elements.
781   if (NumParts * OldElts == NewElts) {
782     SmallVector<unsigned, 8> Parts;
783     Parts.push_back(MO.getReg());
784 
785     unsigned ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
786     for (unsigned I = 1; I != NumParts; ++I)
787       Parts.push_back(ImpDef);
788 
789     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
790     MO.setReg(Concat.getReg(0));
791     return;
792   }
793 
794   unsigned MoreReg = MRI.createGenericVirtualRegister(MoreTy);
795   unsigned ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
796   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
797   MO.setReg(MoreReg);
798 }
799 
800 LegalizerHelper::LegalizeResult
801 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
802                                         LLT WideTy) {
803   if (TypeIdx != 1)
804     return UnableToLegalize;
805 
806   unsigned DstReg = MI.getOperand(0).getReg();
807   LLT DstTy = MRI.getType(DstReg);
808   if (!DstTy.isScalar())
809     return UnableToLegalize;
810 
811   unsigned NumOps = MI.getNumOperands();
812   unsigned NumSrc = MI.getNumOperands() - 1;
813   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
814 
815   unsigned Src1 = MI.getOperand(1).getReg();
816   unsigned ResultReg = MIRBuilder.buildZExt(DstTy, Src1)->getOperand(0).getReg();
817 
818   for (unsigned I = 2; I != NumOps; ++I) {
819     const unsigned Offset = (I - 1) * PartSize;
820 
821     unsigned SrcReg = MI.getOperand(I).getReg();
822     assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
823 
824     auto ZextInput = MIRBuilder.buildZExt(DstTy, SrcReg);
825 
826     unsigned NextResult = I + 1 == NumOps ? DstReg :
827       MRI.createGenericVirtualRegister(DstTy);
828 
829     auto ShiftAmt = MIRBuilder.buildConstant(DstTy, Offset);
830     auto Shl = MIRBuilder.buildShl(DstTy, ZextInput, ShiftAmt);
831     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
832     ResultReg = NextResult;
833   }
834 
835   MI.eraseFromParent();
836   return Legalized;
837 }
838 
839 LegalizerHelper::LegalizeResult
840 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
841                                           LLT WideTy) {
842   if (TypeIdx != 0)
843     return UnableToLegalize;
844 
845   unsigned NumDst = MI.getNumOperands() - 1;
846   unsigned SrcReg = MI.getOperand(NumDst).getReg();
847   LLT SrcTy = MRI.getType(SrcReg);
848   if (!SrcTy.isScalar())
849     return UnableToLegalize;
850 
851   unsigned Dst0Reg = MI.getOperand(0).getReg();
852   LLT DstTy = MRI.getType(Dst0Reg);
853   if (!DstTy.isScalar())
854     return UnableToLegalize;
855 
856   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
857   LLT NewSrcTy = LLT::scalar(NewSrcSize);
858   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
859 
860   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
861 
862   for (unsigned I = 1; I != NumDst; ++I) {
863     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
864     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
865     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
866   }
867 
868   Observer.changingInstr(MI);
869 
870   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
871   for (unsigned I = 0; I != NumDst; ++I)
872     widenScalarDst(MI, WideTy, I);
873 
874   Observer.changedInstr(MI);
875 
876   return Legalized;
877 }
878 
879 LegalizerHelper::LegalizeResult
880 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
881                                     LLT WideTy) {
882   unsigned DstReg = MI.getOperand(0).getReg();
883   unsigned SrcReg = MI.getOperand(1).getReg();
884   LLT SrcTy = MRI.getType(SrcReg);
885 
886   LLT DstTy = MRI.getType(DstReg);
887   unsigned Offset = MI.getOperand(2).getImm();
888 
889   if (TypeIdx == 0) {
890     if (SrcTy.isVector() || DstTy.isVector())
891       return UnableToLegalize;
892 
893     SrcOp Src(SrcReg);
894     if (SrcTy.isPointer()) {
895       // Extracts from pointers can be handled only if they are really just
896       // simple integers.
897       const DataLayout &DL = MIRBuilder.getDataLayout();
898       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
899         return UnableToLegalize;
900 
901       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
902       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
903       SrcTy = SrcAsIntTy;
904     }
905 
906     if (DstTy.isPointer())
907       return UnableToLegalize;
908 
909     if (Offset == 0) {
910       // Avoid a shift in the degenerate case.
911       MIRBuilder.buildTrunc(DstReg,
912                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
913       MI.eraseFromParent();
914       return Legalized;
915     }
916 
917     // Do a shift in the source type.
918     LLT ShiftTy = SrcTy;
919     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
920       Src = MIRBuilder.buildAnyExt(WideTy, Src);
921       ShiftTy = WideTy;
922     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
923       return UnableToLegalize;
924 
925     auto LShr = MIRBuilder.buildLShr(
926       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
927     MIRBuilder.buildTrunc(DstReg, LShr);
928     MI.eraseFromParent();
929     return Legalized;
930   }
931 
932   if (!SrcTy.isVector())
933     return UnableToLegalize;
934 
935   if (DstTy != SrcTy.getElementType())
936     return UnableToLegalize;
937 
938   if (Offset % SrcTy.getScalarSizeInBits() != 0)
939     return UnableToLegalize;
940 
941   Observer.changingInstr(MI);
942   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
943 
944   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
945                           Offset);
946   widenScalarDst(MI, WideTy.getScalarType(), 0);
947   Observer.changedInstr(MI);
948   return Legalized;
949 }
950 
951 LegalizerHelper::LegalizeResult
952 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
953                                    LLT WideTy) {
954   if (TypeIdx != 0)
955     return UnableToLegalize;
956   Observer.changingInstr(MI);
957   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
958   widenScalarDst(MI, WideTy);
959   Observer.changedInstr(MI);
960   return Legalized;
961 }
962 
963 LegalizerHelper::LegalizeResult
964 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
965   MIRBuilder.setInstr(MI);
966 
967   switch (MI.getOpcode()) {
968   default:
969     return UnableToLegalize;
970   case TargetOpcode::G_EXTRACT:
971     return widenScalarExtract(MI, TypeIdx, WideTy);
972   case TargetOpcode::G_INSERT:
973     return widenScalarInsert(MI, TypeIdx, WideTy);
974   case TargetOpcode::G_MERGE_VALUES:
975     return widenScalarMergeValues(MI, TypeIdx, WideTy);
976   case TargetOpcode::G_UNMERGE_VALUES:
977     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
978   case TargetOpcode::G_UADDO:
979   case TargetOpcode::G_USUBO: {
980     if (TypeIdx == 1)
981       return UnableToLegalize; // TODO
982     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
983                                          {MI.getOperand(2).getReg()});
984     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
985                                          {MI.getOperand(3).getReg()});
986     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
987                           ? TargetOpcode::G_ADD
988                           : TargetOpcode::G_SUB;
989     // Do the arithmetic in the larger type.
990     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
991     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
992     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
993     auto AndOp = MIRBuilder.buildInstr(
994         TargetOpcode::G_AND, {WideTy},
995         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
996     // There is no overflow if the AndOp is the same as NewOp.
997     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
998                          AndOp);
999     // Now trunc the NewOp to the original result.
1000     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1001     MI.eraseFromParent();
1002     return Legalized;
1003   }
1004   case TargetOpcode::G_CTTZ:
1005   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1006   case TargetOpcode::G_CTLZ:
1007   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1008   case TargetOpcode::G_CTPOP: {
1009     if (TypeIdx == 0) {
1010       Observer.changingInstr(MI);
1011       widenScalarDst(MI, WideTy, 0);
1012       Observer.changedInstr(MI);
1013       return Legalized;
1014     }
1015 
1016     unsigned SrcReg = MI.getOperand(1).getReg();
1017 
1018     // First ZEXT the input.
1019     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1020     LLT CurTy = MRI.getType(SrcReg);
1021     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1022       // The count is the same in the larger type except if the original
1023       // value was zero.  This can be handled by setting the bit just off
1024       // the top of the original type.
1025       auto TopBit =
1026           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1027       MIBSrc = MIRBuilder.buildOr(
1028         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1029     }
1030 
1031     // Perform the operation at the larger size.
1032     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1033     // This is already the correct result for CTPOP and CTTZs
1034     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1035         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1036       // The correct result is NewOp - (Difference in widety and current ty).
1037       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1038       MIBNewOp = MIRBuilder.buildInstr(
1039           TargetOpcode::G_SUB, {WideTy},
1040           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1041     }
1042 
1043     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1044     MI.eraseFromParent();
1045     return Legalized;
1046   }
1047   case TargetOpcode::G_BSWAP: {
1048     Observer.changingInstr(MI);
1049     unsigned DstReg = MI.getOperand(0).getReg();
1050 
1051     unsigned ShrReg = MRI.createGenericVirtualRegister(WideTy);
1052     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
1053     unsigned ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1054     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1055 
1056     MI.getOperand(0).setReg(DstExt);
1057 
1058     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1059 
1060     LLT Ty = MRI.getType(DstReg);
1061     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1062     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1063     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1064       .addDef(ShrReg)
1065       .addUse(DstExt)
1066       .addUse(ShiftAmtReg);
1067 
1068     MIRBuilder.buildTrunc(DstReg, ShrReg);
1069     Observer.changedInstr(MI);
1070     return Legalized;
1071   }
1072   case TargetOpcode::G_ADD:
1073   case TargetOpcode::G_AND:
1074   case TargetOpcode::G_MUL:
1075   case TargetOpcode::G_OR:
1076   case TargetOpcode::G_XOR:
1077   case TargetOpcode::G_SUB:
1078     // Perform operation at larger width (any extension is fines here, high bits
1079     // don't affect the result) and then truncate the result back to the
1080     // original type.
1081     Observer.changingInstr(MI);
1082     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1083     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1084     widenScalarDst(MI, WideTy);
1085     Observer.changedInstr(MI);
1086     return Legalized;
1087 
1088   case TargetOpcode::G_SHL:
1089       Observer.changingInstr(MI);
1090 
1091     if (TypeIdx == 0) {
1092       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1093       widenScalarDst(MI, WideTy);
1094     } else {
1095       assert(TypeIdx == 1);
1096       // The "number of bits to shift" operand must preserve its value as an
1097       // unsigned integer:
1098       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1099     }
1100 
1101     Observer.changedInstr(MI);
1102     return Legalized;
1103 
1104   case TargetOpcode::G_SDIV:
1105   case TargetOpcode::G_SREM:
1106     Observer.changingInstr(MI);
1107     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1108     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1109     widenScalarDst(MI, WideTy);
1110     Observer.changedInstr(MI);
1111     return Legalized;
1112 
1113   case TargetOpcode::G_ASHR:
1114   case TargetOpcode::G_LSHR:
1115     Observer.changingInstr(MI);
1116 
1117     if (TypeIdx == 0) {
1118       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1119         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1120 
1121       widenScalarSrc(MI, WideTy, 1, CvtOp);
1122       widenScalarDst(MI, WideTy);
1123     } else {
1124       assert(TypeIdx == 1);
1125       // The "number of bits to shift" operand must preserve its value as an
1126       // unsigned integer:
1127       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1128     }
1129 
1130     Observer.changedInstr(MI);
1131     return Legalized;
1132   case TargetOpcode::G_UDIV:
1133   case TargetOpcode::G_UREM:
1134     Observer.changingInstr(MI);
1135     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1136     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1137     widenScalarDst(MI, WideTy);
1138     Observer.changedInstr(MI);
1139     return Legalized;
1140 
1141   case TargetOpcode::G_SELECT:
1142     Observer.changingInstr(MI);
1143     if (TypeIdx == 0) {
1144       // Perform operation at larger width (any extension is fine here, high
1145       // bits don't affect the result) and then truncate the result back to the
1146       // original type.
1147       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1148       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1149       widenScalarDst(MI, WideTy);
1150     } else {
1151       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1152       // Explicit extension is required here since high bits affect the result.
1153       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1154     }
1155     Observer.changedInstr(MI);
1156     return Legalized;
1157 
1158   case TargetOpcode::G_FPTOSI:
1159   case TargetOpcode::G_FPTOUI:
1160     if (TypeIdx != 0)
1161       return UnableToLegalize;
1162     Observer.changingInstr(MI);
1163     widenScalarDst(MI, WideTy);
1164     Observer.changedInstr(MI);
1165     return Legalized;
1166 
1167   case TargetOpcode::G_SITOFP:
1168     if (TypeIdx != 1)
1169       return UnableToLegalize;
1170     Observer.changingInstr(MI);
1171     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1172     Observer.changedInstr(MI);
1173     return Legalized;
1174 
1175   case TargetOpcode::G_UITOFP:
1176     if (TypeIdx != 1)
1177       return UnableToLegalize;
1178     Observer.changingInstr(MI);
1179     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1180     Observer.changedInstr(MI);
1181     return Legalized;
1182 
1183   case TargetOpcode::G_LOAD:
1184   case TargetOpcode::G_SEXTLOAD:
1185   case TargetOpcode::G_ZEXTLOAD:
1186     Observer.changingInstr(MI);
1187     widenScalarDst(MI, WideTy);
1188     Observer.changedInstr(MI);
1189     return Legalized;
1190 
1191   case TargetOpcode::G_STORE: {
1192     if (TypeIdx != 0)
1193       return UnableToLegalize;
1194 
1195     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1196     if (!isPowerOf2_32(Ty.getSizeInBits()))
1197       return UnableToLegalize;
1198 
1199     Observer.changingInstr(MI);
1200 
1201     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1202       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1203     widenScalarSrc(MI, WideTy, 0, ExtType);
1204 
1205     Observer.changedInstr(MI);
1206     return Legalized;
1207   }
1208   case TargetOpcode::G_CONSTANT: {
1209     MachineOperand &SrcMO = MI.getOperand(1);
1210     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1211     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1212     Observer.changingInstr(MI);
1213     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1214 
1215     widenScalarDst(MI, WideTy);
1216     Observer.changedInstr(MI);
1217     return Legalized;
1218   }
1219   case TargetOpcode::G_FCONSTANT: {
1220     MachineOperand &SrcMO = MI.getOperand(1);
1221     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1222     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1223     bool LosesInfo;
1224     switch (WideTy.getSizeInBits()) {
1225     case 32:
1226       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1227                   &LosesInfo);
1228       break;
1229     case 64:
1230       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1231                   &LosesInfo);
1232       break;
1233     default:
1234       return UnableToLegalize;
1235     }
1236 
1237     assert(!LosesInfo && "extend should always be lossless");
1238 
1239     Observer.changingInstr(MI);
1240     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1241 
1242     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1243     Observer.changedInstr(MI);
1244     return Legalized;
1245   }
1246   case TargetOpcode::G_IMPLICIT_DEF: {
1247     Observer.changingInstr(MI);
1248     widenScalarDst(MI, WideTy);
1249     Observer.changedInstr(MI);
1250     return Legalized;
1251   }
1252   case TargetOpcode::G_BRCOND:
1253     Observer.changingInstr(MI);
1254     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1255     Observer.changedInstr(MI);
1256     return Legalized;
1257 
1258   case TargetOpcode::G_FCMP:
1259     Observer.changingInstr(MI);
1260     if (TypeIdx == 0)
1261       widenScalarDst(MI, WideTy);
1262     else {
1263       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1264       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1265     }
1266     Observer.changedInstr(MI);
1267     return Legalized;
1268 
1269   case TargetOpcode::G_ICMP:
1270     Observer.changingInstr(MI);
1271     if (TypeIdx == 0)
1272       widenScalarDst(MI, WideTy);
1273     else {
1274       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1275                                MI.getOperand(1).getPredicate()))
1276                                ? TargetOpcode::G_SEXT
1277                                : TargetOpcode::G_ZEXT;
1278       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1279       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1280     }
1281     Observer.changedInstr(MI);
1282     return Legalized;
1283 
1284   case TargetOpcode::G_GEP:
1285     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1286     Observer.changingInstr(MI);
1287     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1288     Observer.changedInstr(MI);
1289     return Legalized;
1290 
1291   case TargetOpcode::G_PHI: {
1292     assert(TypeIdx == 0 && "Expecting only Idx 0");
1293 
1294     Observer.changingInstr(MI);
1295     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1296       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1297       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1298       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1299     }
1300 
1301     MachineBasicBlock &MBB = *MI.getParent();
1302     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1303     widenScalarDst(MI, WideTy);
1304     Observer.changedInstr(MI);
1305     return Legalized;
1306   }
1307   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1308     if (TypeIdx == 0) {
1309       unsigned VecReg = MI.getOperand(1).getReg();
1310       LLT VecTy = MRI.getType(VecReg);
1311       Observer.changingInstr(MI);
1312 
1313       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1314                                      WideTy.getSizeInBits()),
1315                      1, TargetOpcode::G_SEXT);
1316 
1317       widenScalarDst(MI, WideTy, 0);
1318       Observer.changedInstr(MI);
1319       return Legalized;
1320     }
1321 
1322     if (TypeIdx != 2)
1323       return UnableToLegalize;
1324     Observer.changingInstr(MI);
1325     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1326     Observer.changedInstr(MI);
1327     return Legalized;
1328   }
1329   case TargetOpcode::G_FADD:
1330   case TargetOpcode::G_FMUL:
1331   case TargetOpcode::G_FSUB:
1332   case TargetOpcode::G_FMA:
1333   case TargetOpcode::G_FNEG:
1334   case TargetOpcode::G_FABS:
1335   case TargetOpcode::G_FCANONICALIZE:
1336   case TargetOpcode::G_FDIV:
1337   case TargetOpcode::G_FREM:
1338   case TargetOpcode::G_FCEIL:
1339   case TargetOpcode::G_FFLOOR:
1340   case TargetOpcode::G_FCOS:
1341   case TargetOpcode::G_FSIN:
1342   case TargetOpcode::G_FLOG10:
1343   case TargetOpcode::G_FLOG:
1344   case TargetOpcode::G_FLOG2:
1345   case TargetOpcode::G_FSQRT:
1346   case TargetOpcode::G_FEXP:
1347     assert(TypeIdx == 0);
1348     Observer.changingInstr(MI);
1349 
1350     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1351       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1352 
1353     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1354     Observer.changedInstr(MI);
1355     return Legalized;
1356   case TargetOpcode::G_INTTOPTR:
1357     if (TypeIdx != 1)
1358       return UnableToLegalize;
1359 
1360     Observer.changingInstr(MI);
1361     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1362     Observer.changedInstr(MI);
1363     return Legalized;
1364   case TargetOpcode::G_PTRTOINT:
1365     if (TypeIdx != 0)
1366       return UnableToLegalize;
1367 
1368     Observer.changingInstr(MI);
1369     widenScalarDst(MI, WideTy, 0);
1370     Observer.changedInstr(MI);
1371     return Legalized;
1372   }
1373 }
1374 
1375 LegalizerHelper::LegalizeResult
1376 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1377   using namespace TargetOpcode;
1378   MIRBuilder.setInstr(MI);
1379 
1380   switch(MI.getOpcode()) {
1381   default:
1382     return UnableToLegalize;
1383   case TargetOpcode::G_SREM:
1384   case TargetOpcode::G_UREM: {
1385     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
1386     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1387         .addDef(QuotReg)
1388         .addUse(MI.getOperand(1).getReg())
1389         .addUse(MI.getOperand(2).getReg());
1390 
1391     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
1392     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1393     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1394                         ProdReg);
1395     MI.eraseFromParent();
1396     return Legalized;
1397   }
1398   case TargetOpcode::G_SMULO:
1399   case TargetOpcode::G_UMULO: {
1400     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1401     // result.
1402     unsigned Res = MI.getOperand(0).getReg();
1403     unsigned Overflow = MI.getOperand(1).getReg();
1404     unsigned LHS = MI.getOperand(2).getReg();
1405     unsigned RHS = MI.getOperand(3).getReg();
1406 
1407     MIRBuilder.buildMul(Res, LHS, RHS);
1408 
1409     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1410                           ? TargetOpcode::G_SMULH
1411                           : TargetOpcode::G_UMULH;
1412 
1413     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
1414     MIRBuilder.buildInstr(Opcode)
1415       .addDef(HiPart)
1416       .addUse(LHS)
1417       .addUse(RHS);
1418 
1419     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
1420     MIRBuilder.buildConstant(Zero, 0);
1421 
1422     // For *signed* multiply, overflow is detected by checking:
1423     // (hi != (lo >> bitwidth-1))
1424     if (Opcode == TargetOpcode::G_SMULH) {
1425       unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
1426       unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1427       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1428       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1429         .addDef(Shifted)
1430         .addUse(Res)
1431         .addUse(ShiftAmt);
1432       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1433     } else {
1434       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1435     }
1436     MI.eraseFromParent();
1437     return Legalized;
1438   }
1439   case TargetOpcode::G_FNEG: {
1440     // TODO: Handle vector types once we are able to
1441     // represent them.
1442     if (Ty.isVector())
1443       return UnableToLegalize;
1444     unsigned Res = MI.getOperand(0).getReg();
1445     Type *ZeroTy;
1446     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1447     switch (Ty.getSizeInBits()) {
1448     case 16:
1449       ZeroTy = Type::getHalfTy(Ctx);
1450       break;
1451     case 32:
1452       ZeroTy = Type::getFloatTy(Ctx);
1453       break;
1454     case 64:
1455       ZeroTy = Type::getDoubleTy(Ctx);
1456       break;
1457     case 128:
1458       ZeroTy = Type::getFP128Ty(Ctx);
1459       break;
1460     default:
1461       llvm_unreachable("unexpected floating-point type");
1462     }
1463     ConstantFP &ZeroForNegation =
1464         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1465     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1466     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
1467         .addDef(Res)
1468         .addUse(Zero->getOperand(0).getReg())
1469         .addUse(MI.getOperand(1).getReg());
1470     MI.eraseFromParent();
1471     return Legalized;
1472   }
1473   case TargetOpcode::G_FSUB: {
1474     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1475     // First, check if G_FNEG is marked as Lower. If so, we may
1476     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1477     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1478       return UnableToLegalize;
1479     unsigned Res = MI.getOperand(0).getReg();
1480     unsigned LHS = MI.getOperand(1).getReg();
1481     unsigned RHS = MI.getOperand(2).getReg();
1482     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1483     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1484     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
1485         .addDef(Res)
1486         .addUse(LHS)
1487         .addUse(Neg);
1488     MI.eraseFromParent();
1489     return Legalized;
1490   }
1491   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1492     unsigned OldValRes = MI.getOperand(0).getReg();
1493     unsigned SuccessRes = MI.getOperand(1).getReg();
1494     unsigned Addr = MI.getOperand(2).getReg();
1495     unsigned CmpVal = MI.getOperand(3).getReg();
1496     unsigned NewVal = MI.getOperand(4).getReg();
1497     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1498                                   **MI.memoperands_begin());
1499     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1500     MI.eraseFromParent();
1501     return Legalized;
1502   }
1503   case TargetOpcode::G_LOAD:
1504   case TargetOpcode::G_SEXTLOAD:
1505   case TargetOpcode::G_ZEXTLOAD: {
1506     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1507     unsigned DstReg = MI.getOperand(0).getReg();
1508     unsigned PtrReg = MI.getOperand(1).getReg();
1509     LLT DstTy = MRI.getType(DstReg);
1510     auto &MMO = **MI.memoperands_begin();
1511 
1512     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1513       // In the case of G_LOAD, this was a non-extending load already and we're
1514       // about to lower to the same instruction.
1515       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1516           return UnableToLegalize;
1517       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1518       MI.eraseFromParent();
1519       return Legalized;
1520     }
1521 
1522     if (DstTy.isScalar()) {
1523       unsigned TmpReg = MRI.createGenericVirtualRegister(
1524           LLT::scalar(MMO.getSize() /* in bytes */ * 8));
1525       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1526       switch (MI.getOpcode()) {
1527       default:
1528         llvm_unreachable("Unexpected opcode");
1529       case TargetOpcode::G_LOAD:
1530         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1531         break;
1532       case TargetOpcode::G_SEXTLOAD:
1533         MIRBuilder.buildSExt(DstReg, TmpReg);
1534         break;
1535       case TargetOpcode::G_ZEXTLOAD:
1536         MIRBuilder.buildZExt(DstReg, TmpReg);
1537         break;
1538       }
1539       MI.eraseFromParent();
1540       return Legalized;
1541     }
1542 
1543     return UnableToLegalize;
1544   }
1545   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1546   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1547   case TargetOpcode::G_CTLZ:
1548   case TargetOpcode::G_CTTZ:
1549   case TargetOpcode::G_CTPOP:
1550     return lowerBitCount(MI, TypeIdx, Ty);
1551   case G_UADDO: {
1552     unsigned Res = MI.getOperand(0).getReg();
1553     unsigned CarryOut = MI.getOperand(1).getReg();
1554     unsigned LHS = MI.getOperand(2).getReg();
1555     unsigned RHS = MI.getOperand(3).getReg();
1556 
1557     MIRBuilder.buildAdd(Res, LHS, RHS);
1558     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1559 
1560     MI.eraseFromParent();
1561     return Legalized;
1562   }
1563   case G_UADDE: {
1564     unsigned Res = MI.getOperand(0).getReg();
1565     unsigned CarryOut = MI.getOperand(1).getReg();
1566     unsigned LHS = MI.getOperand(2).getReg();
1567     unsigned RHS = MI.getOperand(3).getReg();
1568     unsigned CarryIn = MI.getOperand(4).getReg();
1569 
1570     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1571     unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1572 
1573     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1574     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1575     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1576     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1577 
1578     MI.eraseFromParent();
1579     return Legalized;
1580   }
1581   case G_USUBO: {
1582     unsigned Res = MI.getOperand(0).getReg();
1583     unsigned BorrowOut = MI.getOperand(1).getReg();
1584     unsigned LHS = MI.getOperand(2).getReg();
1585     unsigned RHS = MI.getOperand(3).getReg();
1586 
1587     MIRBuilder.buildSub(Res, LHS, RHS);
1588     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1589 
1590     MI.eraseFromParent();
1591     return Legalized;
1592   }
1593   case G_USUBE: {
1594     unsigned Res = MI.getOperand(0).getReg();
1595     unsigned BorrowOut = MI.getOperand(1).getReg();
1596     unsigned LHS = MI.getOperand(2).getReg();
1597     unsigned RHS = MI.getOperand(3).getReg();
1598     unsigned BorrowIn = MI.getOperand(4).getReg();
1599 
1600     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1601     unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1602     unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1603     unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1604 
1605     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1606     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1607     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1608     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1609     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1610     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1611 
1612     MI.eraseFromParent();
1613     return Legalized;
1614   }
1615   }
1616 }
1617 
1618 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1619     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1620   SmallVector<unsigned, 2> DstRegs;
1621 
1622   unsigned NarrowSize = NarrowTy.getSizeInBits();
1623   unsigned DstReg = MI.getOperand(0).getReg();
1624   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1625   int NumParts = Size / NarrowSize;
1626   // FIXME: Don't know how to handle the situation where the small vectors
1627   // aren't all the same size yet.
1628   if (Size % NarrowSize != 0)
1629     return UnableToLegalize;
1630 
1631   for (int i = 0; i < NumParts; ++i) {
1632     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1633     MIRBuilder.buildUndef(TmpReg);
1634     DstRegs.push_back(TmpReg);
1635   }
1636 
1637   if (NarrowTy.isVector())
1638     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1639   else
1640     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1641 
1642   MI.eraseFromParent();
1643   return Legalized;
1644 }
1645 
1646 LegalizerHelper::LegalizeResult
1647 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1648                                           LLT NarrowTy) {
1649   const unsigned Opc = MI.getOpcode();
1650   const unsigned NumOps = MI.getNumOperands() - 1;
1651   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1652   const unsigned DstReg = MI.getOperand(0).getReg();
1653   const unsigned Flags = MI.getFlags();
1654   const LLT DstTy = MRI.getType(DstReg);
1655   const unsigned Size = DstTy.getSizeInBits();
1656   const int NumParts = Size / NarrowSize;
1657   const LLT EltTy = DstTy.getElementType();
1658   const unsigned EltSize = EltTy.getSizeInBits();
1659   const unsigned BitsForNumParts = NarrowSize * NumParts;
1660 
1661   // Check if we have any leftovers. If we do, then only handle the case where
1662   // the leftover is one element.
1663   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1664     return UnableToLegalize;
1665 
1666   if (BitsForNumParts != Size) {
1667     unsigned AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1668     MIRBuilder.buildUndef(AccumDstReg);
1669 
1670     // Handle the pieces which evenly divide into the requested type with
1671     // extract/op/insert sequence.
1672     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1673       SmallVector<SrcOp, 4> SrcOps;
1674       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1675         unsigned PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1676         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1677         SrcOps.push_back(PartOpReg);
1678       }
1679 
1680       unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1681       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1682 
1683       unsigned PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1684       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1685       AccumDstReg = PartInsertReg;
1686     }
1687 
1688     // Handle the remaining element sized leftover piece.
1689     SmallVector<SrcOp, 4> SrcOps;
1690     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1691       unsigned PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1692       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1693                               BitsForNumParts);
1694       SrcOps.push_back(PartOpReg);
1695     }
1696 
1697     unsigned PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1698     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1699     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1700     MI.eraseFromParent();
1701 
1702     return Legalized;
1703   }
1704 
1705   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1706 
1707   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1708 
1709   if (NumOps >= 2)
1710     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1711 
1712   if (NumOps >= 3)
1713     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1714 
1715   for (int i = 0; i < NumParts; ++i) {
1716     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1717 
1718     if (NumOps == 1)
1719       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1720     else if (NumOps == 2) {
1721       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1722     } else if (NumOps == 3) {
1723       MIRBuilder.buildInstr(Opc, {DstReg},
1724                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1725     }
1726 
1727     DstRegs.push_back(DstReg);
1728   }
1729 
1730   if (NarrowTy.isVector())
1731     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1732   else
1733     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1734 
1735   MI.eraseFromParent();
1736   return Legalized;
1737 }
1738 
1739 // Handle splitting vector operations which need to have the same number of
1740 // elements in each type index, but each type index may have a different element
1741 // type.
1742 //
1743 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
1744 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1745 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1746 //
1747 // Also handles some irregular breakdown cases, e.g.
1748 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
1749 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1750 //             s64 = G_SHL s64, s32
1751 LegalizerHelper::LegalizeResult
1752 LegalizerHelper::fewerElementsVectorMultiEltType(
1753   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
1754   if (TypeIdx != 0)
1755     return UnableToLegalize;
1756 
1757   const LLT NarrowTy0 = NarrowTyArg;
1758   const unsigned NewNumElts =
1759       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
1760 
1761   const unsigned DstReg = MI.getOperand(0).getReg();
1762   LLT DstTy = MRI.getType(DstReg);
1763   LLT LeftoverTy0;
1764 
1765   int NumParts, NumLeftover;
1766   // All of the operands need to have the same number of elements, so if we can
1767   // determine a type breakdown for the result type, we can for all of the
1768   // source types.
1769   std::tie(NumParts, NumLeftover)
1770     = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1771   if (NumParts < 0)
1772     return UnableToLegalize;
1773 
1774   SmallVector<MachineInstrBuilder, 4> NewInsts;
1775 
1776   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
1777   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
1778 
1779   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1780     LLT LeftoverTy;
1781     unsigned SrcReg = MI.getOperand(I).getReg();
1782     LLT SrcTyI = MRI.getType(SrcReg);
1783     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
1784     LLT LeftoverTyI;
1785 
1786     // Split this operand into the requested typed registers, and any leftover
1787     // required to reproduce the original type.
1788     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
1789                       LeftoverRegs))
1790       return UnableToLegalize;
1791 
1792     if (I == 1) {
1793       // For the first operand, create an instruction for each part and setup
1794       // the result.
1795       for (unsigned PartReg : PartRegs) {
1796         unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1797         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1798                                .addDef(PartDstReg)
1799                                .addUse(PartReg));
1800         DstRegs.push_back(PartDstReg);
1801       }
1802 
1803       for (unsigned LeftoverReg : LeftoverRegs) {
1804         unsigned PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1805         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1806                                .addDef(PartDstReg)
1807                                .addUse(LeftoverReg));
1808         LeftoverDstRegs.push_back(PartDstReg);
1809       }
1810     } else {
1811       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
1812 
1813       // Add the newly created operand splits to the existing instructions. The
1814       // odd-sized pieces are ordered after the requested NarrowTyArg sized
1815       // pieces.
1816       unsigned InstCount = 0;
1817       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
1818         NewInsts[InstCount++].addUse(PartRegs[J]);
1819       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
1820         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
1821     }
1822 
1823     PartRegs.clear();
1824     LeftoverRegs.clear();
1825   }
1826 
1827   // Insert the newly built operations and rebuild the result register.
1828   for (auto &MIB : NewInsts)
1829     MIRBuilder.insertInstr(MIB);
1830 
1831   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
1832 
1833   MI.eraseFromParent();
1834   return Legalized;
1835 }
1836 
1837 LegalizerHelper::LegalizeResult
1838 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
1839                                           LLT NarrowTy) {
1840   if (TypeIdx != 0)
1841     return UnableToLegalize;
1842 
1843   unsigned DstReg = MI.getOperand(0).getReg();
1844   unsigned SrcReg = MI.getOperand(1).getReg();
1845   LLT DstTy = MRI.getType(DstReg);
1846   LLT SrcTy = MRI.getType(SrcReg);
1847 
1848   LLT NarrowTy0 = NarrowTy;
1849   LLT NarrowTy1;
1850   unsigned NumParts;
1851 
1852   if (NarrowTy.isVector()) {
1853     // Uneven breakdown not handled.
1854     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
1855     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
1856       return UnableToLegalize;
1857 
1858     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
1859   } else {
1860     NumParts = DstTy.getNumElements();
1861     NarrowTy1 = SrcTy.getElementType();
1862   }
1863 
1864   SmallVector<unsigned, 4> SrcRegs, DstRegs;
1865   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
1866 
1867   for (unsigned I = 0; I < NumParts; ++I) {
1868     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1869     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
1870       .addDef(DstReg)
1871       .addUse(SrcRegs[I]);
1872 
1873     NewInst->setFlags(MI.getFlags());
1874     DstRegs.push_back(DstReg);
1875   }
1876 
1877   if (NarrowTy.isVector())
1878     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1879   else
1880     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1881 
1882   MI.eraseFromParent();
1883   return Legalized;
1884 }
1885 
1886 LegalizerHelper::LegalizeResult
1887 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
1888                                         LLT NarrowTy) {
1889   unsigned DstReg = MI.getOperand(0).getReg();
1890   unsigned Src0Reg = MI.getOperand(2).getReg();
1891   LLT DstTy = MRI.getType(DstReg);
1892   LLT SrcTy = MRI.getType(Src0Reg);
1893 
1894   unsigned NumParts;
1895   LLT NarrowTy0, NarrowTy1;
1896 
1897   if (TypeIdx == 0) {
1898     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1899     unsigned OldElts = DstTy.getNumElements();
1900 
1901     NarrowTy0 = NarrowTy;
1902     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
1903     NarrowTy1 = NarrowTy.isVector() ?
1904       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
1905       SrcTy.getElementType();
1906 
1907   } else {
1908     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1909     unsigned OldElts = SrcTy.getNumElements();
1910 
1911     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
1912       NarrowTy.getNumElements();
1913     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
1914                             DstTy.getScalarSizeInBits());
1915     NarrowTy1 = NarrowTy;
1916   }
1917 
1918   // FIXME: Don't know how to handle the situation where the small vectors
1919   // aren't all the same size yet.
1920   if (NarrowTy1.isVector() &&
1921       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
1922     return UnableToLegalize;
1923 
1924   CmpInst::Predicate Pred
1925     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1926 
1927   SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
1928   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
1929   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
1930 
1931   for (unsigned I = 0; I < NumParts; ++I) {
1932     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1933     DstRegs.push_back(DstReg);
1934 
1935     if (MI.getOpcode() == TargetOpcode::G_ICMP)
1936       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1937     else {
1938       MachineInstr *NewCmp
1939         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1940       NewCmp->setFlags(MI.getFlags());
1941     }
1942   }
1943 
1944   if (NarrowTy1.isVector())
1945     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1946   else
1947     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1948 
1949   MI.eraseFromParent();
1950   return Legalized;
1951 }
1952 
1953 LegalizerHelper::LegalizeResult
1954 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
1955                                            LLT NarrowTy) {
1956   unsigned DstReg = MI.getOperand(0).getReg();
1957   unsigned CondReg = MI.getOperand(1).getReg();
1958 
1959   unsigned NumParts = 0;
1960   LLT NarrowTy0, NarrowTy1;
1961 
1962   LLT DstTy = MRI.getType(DstReg);
1963   LLT CondTy = MRI.getType(CondReg);
1964   unsigned Size = DstTy.getSizeInBits();
1965 
1966   assert(TypeIdx == 0 || CondTy.isVector());
1967 
1968   if (TypeIdx == 0) {
1969     NarrowTy0 = NarrowTy;
1970     NarrowTy1 = CondTy;
1971 
1972     unsigned NarrowSize = NarrowTy0.getSizeInBits();
1973     // FIXME: Don't know how to handle the situation where the small vectors
1974     // aren't all the same size yet.
1975     if (Size % NarrowSize != 0)
1976       return UnableToLegalize;
1977 
1978     NumParts = Size / NarrowSize;
1979 
1980     // Need to break down the condition type
1981     if (CondTy.isVector()) {
1982       if (CondTy.getNumElements() == NumParts)
1983         NarrowTy1 = CondTy.getElementType();
1984       else
1985         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
1986                                 CondTy.getScalarSizeInBits());
1987     }
1988   } else {
1989     NumParts = CondTy.getNumElements();
1990     if (NarrowTy.isVector()) {
1991       // TODO: Handle uneven breakdown.
1992       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
1993         return UnableToLegalize;
1994 
1995       return UnableToLegalize;
1996     } else {
1997       NarrowTy0 = DstTy.getElementType();
1998       NarrowTy1 = NarrowTy;
1999     }
2000   }
2001 
2002   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2003   if (CondTy.isVector())
2004     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2005 
2006   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2007   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2008 
2009   for (unsigned i = 0; i < NumParts; ++i) {
2010     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2011     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2012                            Src1Regs[i], Src2Regs[i]);
2013     DstRegs.push_back(DstReg);
2014   }
2015 
2016   if (NarrowTy0.isVector())
2017     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2018   else
2019     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2020 
2021   MI.eraseFromParent();
2022   return Legalized;
2023 }
2024 
2025 LegalizerHelper::LegalizeResult
2026 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2027                                         LLT NarrowTy) {
2028   const unsigned DstReg = MI.getOperand(0).getReg();
2029   LLT PhiTy = MRI.getType(DstReg);
2030   LLT LeftoverTy;
2031 
2032   // All of the operands need to have the same number of elements, so if we can
2033   // determine a type breakdown for the result type, we can for all of the
2034   // source types.
2035   int NumParts, NumLeftover;
2036   std::tie(NumParts, NumLeftover)
2037     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2038   if (NumParts < 0)
2039     return UnableToLegalize;
2040 
2041   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
2042   SmallVector<MachineInstrBuilder, 4> NewInsts;
2043 
2044   const int TotalNumParts = NumParts + NumLeftover;
2045 
2046   // Insert the new phis in the result block first.
2047   for (int I = 0; I != TotalNumParts; ++I) {
2048     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2049     unsigned PartDstReg = MRI.createGenericVirtualRegister(Ty);
2050     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2051                        .addDef(PartDstReg));
2052     if (I < NumParts)
2053       DstRegs.push_back(PartDstReg);
2054     else
2055       LeftoverDstRegs.push_back(PartDstReg);
2056   }
2057 
2058   MachineBasicBlock *MBB = MI.getParent();
2059   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2060   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2061 
2062   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
2063 
2064   // Insert code to extract the incoming values in each predecessor block.
2065   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2066     PartRegs.clear();
2067     LeftoverRegs.clear();
2068 
2069     unsigned SrcReg = MI.getOperand(I).getReg();
2070     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2071     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2072 
2073     LLT Unused;
2074     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2075                       LeftoverRegs))
2076       return UnableToLegalize;
2077 
2078     // Add the newly created operand splits to the existing instructions. The
2079     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2080     // pieces.
2081     for (int J = 0; J != TotalNumParts; ++J) {
2082       MachineInstrBuilder MIB = NewInsts[J];
2083       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2084       MIB.addMBB(&OpMBB);
2085     }
2086   }
2087 
2088   MI.eraseFromParent();
2089   return Legalized;
2090 }
2091 
2092 LegalizerHelper::LegalizeResult
2093 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2094                                       LLT NarrowTy) {
2095   // FIXME: Don't know how to handle secondary types yet.
2096   if (TypeIdx != 0)
2097     return UnableToLegalize;
2098 
2099   MachineMemOperand *MMO = *MI.memoperands_begin();
2100 
2101   // This implementation doesn't work for atomics. Give up instead of doing
2102   // something invalid.
2103   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2104       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2105     return UnableToLegalize;
2106 
2107   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2108   unsigned ValReg = MI.getOperand(0).getReg();
2109   unsigned AddrReg = MI.getOperand(1).getReg();
2110   LLT ValTy = MRI.getType(ValReg);
2111 
2112   int NumParts = -1;
2113   int NumLeftover = -1;
2114   LLT LeftoverTy;
2115   SmallVector<unsigned, 8> NarrowRegs, NarrowLeftoverRegs;
2116   if (IsLoad) {
2117     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2118   } else {
2119     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2120                      NarrowLeftoverRegs)) {
2121       NumParts = NarrowRegs.size();
2122       NumLeftover = NarrowLeftoverRegs.size();
2123     }
2124   }
2125 
2126   if (NumParts == -1)
2127     return UnableToLegalize;
2128 
2129   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2130 
2131   unsigned TotalSize = ValTy.getSizeInBits();
2132 
2133   // Split the load/store into PartTy sized pieces starting at Offset. If this
2134   // is a load, return the new registers in ValRegs. For a store, each elements
2135   // of ValRegs should be PartTy. Returns the next offset that needs to be
2136   // handled.
2137   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<unsigned> &ValRegs,
2138                              unsigned Offset) -> unsigned {
2139     MachineFunction &MF = MIRBuilder.getMF();
2140     unsigned PartSize = PartTy.getSizeInBits();
2141     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2142          Offset += PartSize, ++Idx) {
2143       unsigned ByteSize = PartSize / 8;
2144       unsigned ByteOffset = Offset / 8;
2145       unsigned NewAddrReg = 0;
2146 
2147       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2148 
2149       MachineMemOperand *NewMMO =
2150         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2151 
2152       if (IsLoad) {
2153         unsigned Dst = MRI.createGenericVirtualRegister(PartTy);
2154         ValRegs.push_back(Dst);
2155         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2156       } else {
2157         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2158       }
2159     }
2160 
2161     return Offset;
2162   };
2163 
2164   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2165 
2166   // Handle the rest of the register if this isn't an even type breakdown.
2167   if (LeftoverTy.isValid())
2168     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2169 
2170   if (IsLoad) {
2171     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2172                 LeftoverTy, NarrowLeftoverRegs);
2173   }
2174 
2175   MI.eraseFromParent();
2176   return Legalized;
2177 }
2178 
2179 LegalizerHelper::LegalizeResult
2180 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2181                                      LLT NarrowTy) {
2182   using namespace TargetOpcode;
2183 
2184   MIRBuilder.setInstr(MI);
2185   switch (MI.getOpcode()) {
2186   case G_IMPLICIT_DEF:
2187     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2188   case G_AND:
2189   case G_OR:
2190   case G_XOR:
2191   case G_ADD:
2192   case G_SUB:
2193   case G_MUL:
2194   case G_SMULH:
2195   case G_UMULH:
2196   case G_FADD:
2197   case G_FMUL:
2198   case G_FSUB:
2199   case G_FNEG:
2200   case G_FABS:
2201   case G_FCANONICALIZE:
2202   case G_FDIV:
2203   case G_FREM:
2204   case G_FMA:
2205   case G_FPOW:
2206   case G_FEXP:
2207   case G_FEXP2:
2208   case G_FLOG:
2209   case G_FLOG2:
2210   case G_FLOG10:
2211   case G_FCEIL:
2212   case G_FFLOOR:
2213   case G_INTRINSIC_ROUND:
2214   case G_INTRINSIC_TRUNC:
2215   case G_FCOS:
2216   case G_FSIN:
2217   case G_FSQRT:
2218   case G_BSWAP:
2219     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2220   case G_SHL:
2221   case G_LSHR:
2222   case G_ASHR:
2223   case G_CTLZ:
2224   case G_CTLZ_ZERO_UNDEF:
2225   case G_CTTZ:
2226   case G_CTTZ_ZERO_UNDEF:
2227   case G_CTPOP:
2228     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2229   case G_ZEXT:
2230   case G_SEXT:
2231   case G_ANYEXT:
2232   case G_FPEXT:
2233   case G_FPTRUNC:
2234   case G_SITOFP:
2235   case G_UITOFP:
2236   case G_FPTOSI:
2237   case G_FPTOUI:
2238   case G_INTTOPTR:
2239   case G_PTRTOINT:
2240   case G_ADDRSPACE_CAST:
2241     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2242   case G_ICMP:
2243   case G_FCMP:
2244     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2245   case G_SELECT:
2246     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2247   case G_PHI:
2248     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2249   case G_LOAD:
2250   case G_STORE:
2251     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2252   default:
2253     return UnableToLegalize;
2254   }
2255 }
2256 
2257 LegalizerHelper::LegalizeResult
2258 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2259                                              const LLT HalfTy, const LLT AmtTy) {
2260 
2261   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2262   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2263   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2264 
2265   if (Amt.isNullValue()) {
2266     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2267     MI.eraseFromParent();
2268     return Legalized;
2269   }
2270 
2271   LLT NVT = HalfTy;
2272   unsigned NVTBits = HalfTy.getSizeInBits();
2273   unsigned VTBits = 2 * NVTBits;
2274 
2275   SrcOp Lo(0), Hi(0);
2276   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2277     if (Amt.ugt(VTBits)) {
2278       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2279     } else if (Amt.ugt(NVTBits)) {
2280       Lo = MIRBuilder.buildConstant(NVT, 0);
2281       Hi = MIRBuilder.buildShl(NVT, InL,
2282                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2283     } else if (Amt == NVTBits) {
2284       Lo = MIRBuilder.buildConstant(NVT, 0);
2285       Hi = InL;
2286     } else {
2287       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2288       auto OrLHS =
2289           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2290       auto OrRHS = MIRBuilder.buildLShr(
2291           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2292       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2293     }
2294   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2295     if (Amt.ugt(VTBits)) {
2296       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2297     } else if (Amt.ugt(NVTBits)) {
2298       Lo = MIRBuilder.buildLShr(NVT, InH,
2299                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2300       Hi = MIRBuilder.buildConstant(NVT, 0);
2301     } else if (Amt == NVTBits) {
2302       Lo = InH;
2303       Hi = MIRBuilder.buildConstant(NVT, 0);
2304     } else {
2305       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2306 
2307       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2308       auto OrRHS = MIRBuilder.buildShl(
2309           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2310 
2311       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2312       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2313     }
2314   } else {
2315     if (Amt.ugt(VTBits)) {
2316       Hi = Lo = MIRBuilder.buildAShr(
2317           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2318     } else if (Amt.ugt(NVTBits)) {
2319       Lo = MIRBuilder.buildAShr(NVT, InH,
2320                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2321       Hi = MIRBuilder.buildAShr(NVT, InH,
2322                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2323     } else if (Amt == NVTBits) {
2324       Lo = InH;
2325       Hi = MIRBuilder.buildAShr(NVT, InH,
2326                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2327     } else {
2328       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2329 
2330       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2331       auto OrRHS = MIRBuilder.buildShl(
2332           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2333 
2334       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2335       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2336     }
2337   }
2338 
2339   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2340   MI.eraseFromParent();
2341 
2342   return Legalized;
2343 }
2344 
2345 // TODO: Optimize if constant shift amount.
2346 LegalizerHelper::LegalizeResult
2347 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2348                                    LLT RequestedTy) {
2349   if (TypeIdx == 1) {
2350     Observer.changingInstr(MI);
2351     narrowScalarSrc(MI, RequestedTy, 2);
2352     Observer.changedInstr(MI);
2353     return Legalized;
2354   }
2355 
2356   unsigned DstReg = MI.getOperand(0).getReg();
2357   LLT DstTy = MRI.getType(DstReg);
2358   if (DstTy.isVector())
2359     return UnableToLegalize;
2360 
2361   unsigned Amt = MI.getOperand(2).getReg();
2362   LLT ShiftAmtTy = MRI.getType(Amt);
2363   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2364   if (DstEltSize % 2 != 0)
2365     return UnableToLegalize;
2366 
2367   // Ignore the input type. We can only go to exactly half the size of the
2368   // input. If that isn't small enough, the resulting pieces will be further
2369   // legalized.
2370   const unsigned NewBitSize = DstEltSize / 2;
2371   const LLT HalfTy = LLT::scalar(NewBitSize);
2372   const LLT CondTy = LLT::scalar(1);
2373 
2374   if (const MachineInstr *KShiftAmt =
2375           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2376     return narrowScalarShiftByConstant(
2377         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2378   }
2379 
2380   // TODO: Expand with known bits.
2381 
2382   // Handle the fully general expansion by an unknown amount.
2383   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2384 
2385   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2386   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2387   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2388 
2389   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2390   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2391 
2392   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2393   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2394   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2395 
2396   unsigned ResultRegs[2];
2397   switch (MI.getOpcode()) {
2398   case TargetOpcode::G_SHL: {
2399     // Short: ShAmt < NewBitSize
2400     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2401 
2402     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2403     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2404     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2405 
2406     // Long: ShAmt >= NewBitSize
2407     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2408     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2409 
2410     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2411     auto Hi = MIRBuilder.buildSelect(
2412         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2413 
2414     ResultRegs[0] = Lo.getReg(0);
2415     ResultRegs[1] = Hi.getReg(0);
2416     break;
2417   }
2418   case TargetOpcode::G_LSHR: {
2419     // Short: ShAmt < NewBitSize
2420     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2421 
2422     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2423     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2424     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2425 
2426     // Long: ShAmt >= NewBitSize
2427     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2428     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2429 
2430     auto Lo = MIRBuilder.buildSelect(
2431         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2432     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2433 
2434     ResultRegs[0] = Lo.getReg(0);
2435     ResultRegs[1] = Hi.getReg(0);
2436     break;
2437   }
2438   case TargetOpcode::G_ASHR: {
2439     // Short: ShAmt < NewBitSize
2440     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2441 
2442     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2443     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2444     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2445 
2446     // Long: ShAmt >= NewBitSize
2447 
2448     // Sign of Hi part.
2449     auto HiL = MIRBuilder.buildAShr(
2450         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2451 
2452     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2453 
2454     auto Lo = MIRBuilder.buildSelect(
2455         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2456 
2457     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2458 
2459     ResultRegs[0] = Lo.getReg(0);
2460     ResultRegs[1] = Hi.getReg(0);
2461     break;
2462   }
2463   default:
2464     llvm_unreachable("not a shift");
2465   }
2466 
2467   MIRBuilder.buildMerge(DstReg, ResultRegs);
2468   MI.eraseFromParent();
2469   return Legalized;
2470 }
2471 
2472 LegalizerHelper::LegalizeResult
2473 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2474                                        LLT MoreTy) {
2475   assert(TypeIdx == 0 && "Expecting only Idx 0");
2476 
2477   Observer.changingInstr(MI);
2478   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2479     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2480     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2481     moreElementsVectorSrc(MI, MoreTy, I);
2482   }
2483 
2484   MachineBasicBlock &MBB = *MI.getParent();
2485   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2486   moreElementsVectorDst(MI, MoreTy, 0);
2487   Observer.changedInstr(MI);
2488   return Legalized;
2489 }
2490 
2491 LegalizerHelper::LegalizeResult
2492 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2493                                     LLT MoreTy) {
2494   MIRBuilder.setInstr(MI);
2495   unsigned Opc = MI.getOpcode();
2496   switch (Opc) {
2497   case TargetOpcode::G_IMPLICIT_DEF: {
2498     Observer.changingInstr(MI);
2499     moreElementsVectorDst(MI, MoreTy, 0);
2500     Observer.changedInstr(MI);
2501     return Legalized;
2502   }
2503   case TargetOpcode::G_AND:
2504   case TargetOpcode::G_OR:
2505   case TargetOpcode::G_XOR: {
2506     Observer.changingInstr(MI);
2507     moreElementsVectorSrc(MI, MoreTy, 1);
2508     moreElementsVectorSrc(MI, MoreTy, 2);
2509     moreElementsVectorDst(MI, MoreTy, 0);
2510     Observer.changedInstr(MI);
2511     return Legalized;
2512   }
2513   case TargetOpcode::G_EXTRACT:
2514     if (TypeIdx != 1)
2515       return UnableToLegalize;
2516     Observer.changingInstr(MI);
2517     moreElementsVectorSrc(MI, MoreTy, 1);
2518     Observer.changedInstr(MI);
2519     return Legalized;
2520   case TargetOpcode::G_INSERT:
2521     if (TypeIdx != 0)
2522       return UnableToLegalize;
2523     Observer.changingInstr(MI);
2524     moreElementsVectorSrc(MI, MoreTy, 1);
2525     moreElementsVectorDst(MI, MoreTy, 0);
2526     Observer.changedInstr(MI);
2527     return Legalized;
2528   case TargetOpcode::G_SELECT:
2529     if (TypeIdx != 0)
2530       return UnableToLegalize;
2531     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2532       return UnableToLegalize;
2533 
2534     Observer.changingInstr(MI);
2535     moreElementsVectorSrc(MI, MoreTy, 2);
2536     moreElementsVectorSrc(MI, MoreTy, 3);
2537     moreElementsVectorDst(MI, MoreTy, 0);
2538     Observer.changedInstr(MI);
2539     return Legalized;
2540   case TargetOpcode::G_PHI:
2541     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2542   default:
2543     return UnableToLegalize;
2544   }
2545 }
2546 
2547 LegalizerHelper::LegalizeResult
2548 LegalizerHelper::narrowScalarMul(MachineInstr &MI, unsigned TypeIdx, LLT NewTy) {
2549   unsigned DstReg = MI.getOperand(0).getReg();
2550   unsigned Src0 = MI.getOperand(1).getReg();
2551   unsigned Src1 = MI.getOperand(2).getReg();
2552   LLT Ty = MRI.getType(DstReg);
2553   if (Ty.isVector())
2554     return UnableToLegalize;
2555 
2556   unsigned Size = Ty.getSizeInBits();
2557   unsigned NewSize = Size / 2;
2558   if (Size != 2 * NewSize)
2559     return UnableToLegalize;
2560 
2561   LLT HalfTy = LLT::scalar(NewSize);
2562   // TODO: if HalfTy != NewTy, handle the breakdown all at once?
2563 
2564   unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
2565   unsigned Lo = MRI.createGenericVirtualRegister(HalfTy);
2566   unsigned Hi = MRI.createGenericVirtualRegister(HalfTy);
2567   unsigned ExtLo = MRI.createGenericVirtualRegister(Ty);
2568   unsigned ExtHi = MRI.createGenericVirtualRegister(Ty);
2569   unsigned ShiftedHi = MRI.createGenericVirtualRegister(Ty);
2570 
2571   SmallVector<unsigned, 2> Src0Parts;
2572   SmallVector<unsigned, 2> Src1Parts;
2573 
2574   extractParts(Src0, HalfTy, 2, Src0Parts);
2575   extractParts(Src1, HalfTy, 2, Src1Parts);
2576 
2577   MIRBuilder.buildMul(Lo, Src0Parts[0], Src1Parts[0]);
2578 
2579   // TODO: Use smulh or umulh depending on what the target has.
2580   MIRBuilder.buildUMulH(Hi, Src0Parts[1], Src1Parts[1]);
2581 
2582   MIRBuilder.buildConstant(ShiftAmt, NewSize);
2583   MIRBuilder.buildAnyExt(ExtHi, Hi);
2584   MIRBuilder.buildShl(ShiftedHi, ExtHi, ShiftAmt);
2585 
2586   MIRBuilder.buildZExt(ExtLo, Lo);
2587   MIRBuilder.buildOr(DstReg, ExtLo, ShiftedHi);
2588   MI.eraseFromParent();
2589   return Legalized;
2590 }
2591 
2592 
2593 LegalizerHelper::LegalizeResult
2594 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2595                                      LLT NarrowTy) {
2596   if (TypeIdx != 1)
2597     return UnableToLegalize;
2598 
2599   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2600 
2601   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2602   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2603   // NarrowSize.
2604   if (SizeOp1 % NarrowSize != 0)
2605     return UnableToLegalize;
2606   int NumParts = SizeOp1 / NarrowSize;
2607 
2608   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2609   SmallVector<uint64_t, 2> Indexes;
2610   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2611 
2612   unsigned OpReg = MI.getOperand(0).getReg();
2613   uint64_t OpStart = MI.getOperand(2).getImm();
2614   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2615   for (int i = 0; i < NumParts; ++i) {
2616     unsigned SrcStart = i * NarrowSize;
2617 
2618     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2619       // No part of the extract uses this subregister, ignore it.
2620       continue;
2621     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2622       // The entire subregister is extracted, forward the value.
2623       DstRegs.push_back(SrcRegs[i]);
2624       continue;
2625     }
2626 
2627     // OpSegStart is where this destination segment would start in OpReg if it
2628     // extended infinitely in both directions.
2629     int64_t ExtractOffset;
2630     uint64_t SegSize;
2631     if (OpStart < SrcStart) {
2632       ExtractOffset = 0;
2633       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2634     } else {
2635       ExtractOffset = OpStart - SrcStart;
2636       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2637     }
2638 
2639     unsigned SegReg = SrcRegs[i];
2640     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2641       // A genuine extract is needed.
2642       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2643       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2644     }
2645 
2646     DstRegs.push_back(SegReg);
2647   }
2648 
2649   unsigned DstReg = MI.getOperand(0).getReg();
2650   if(MRI.getType(DstReg).isVector())
2651     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2652   else
2653     MIRBuilder.buildMerge(DstReg, DstRegs);
2654   MI.eraseFromParent();
2655   return Legalized;
2656 }
2657 
2658 LegalizerHelper::LegalizeResult
2659 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2660                                     LLT NarrowTy) {
2661   // FIXME: Don't know how to handle secondary types yet.
2662   if (TypeIdx != 0)
2663     return UnableToLegalize;
2664 
2665   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2666   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2667 
2668   // FIXME: add support for when SizeOp0 isn't an exact multiple of
2669   // NarrowSize.
2670   if (SizeOp0 % NarrowSize != 0)
2671     return UnableToLegalize;
2672 
2673   int NumParts = SizeOp0 / NarrowSize;
2674 
2675   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2676   SmallVector<uint64_t, 2> Indexes;
2677   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2678 
2679   unsigned OpReg = MI.getOperand(2).getReg();
2680   uint64_t OpStart = MI.getOperand(3).getImm();
2681   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2682   for (int i = 0; i < NumParts; ++i) {
2683     unsigned DstStart = i * NarrowSize;
2684 
2685     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
2686       // No part of the insert affects this subregister, forward the original.
2687       DstRegs.push_back(SrcRegs[i]);
2688       continue;
2689     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2690       // The entire subregister is defined by this insert, forward the new
2691       // value.
2692       DstRegs.push_back(OpReg);
2693       continue;
2694     }
2695 
2696     // OpSegStart is where this destination segment would start in OpReg if it
2697     // extended infinitely in both directions.
2698     int64_t ExtractOffset, InsertOffset;
2699     uint64_t SegSize;
2700     if (OpStart < DstStart) {
2701       InsertOffset = 0;
2702       ExtractOffset = DstStart - OpStart;
2703       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
2704     } else {
2705       InsertOffset = OpStart - DstStart;
2706       ExtractOffset = 0;
2707       SegSize =
2708         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
2709     }
2710 
2711     unsigned SegReg = OpReg;
2712     if (ExtractOffset != 0 || SegSize != OpSize) {
2713       // A genuine extract is needed.
2714       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2715       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
2716     }
2717 
2718     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2719     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
2720     DstRegs.push_back(DstReg);
2721   }
2722 
2723   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2724   unsigned DstReg = MI.getOperand(0).getReg();
2725   if(MRI.getType(DstReg).isVector())
2726     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2727   else
2728     MIRBuilder.buildMerge(DstReg, DstRegs);
2729   MI.eraseFromParent();
2730   return Legalized;
2731 }
2732 
2733 LegalizerHelper::LegalizeResult
2734 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
2735                                     LLT NarrowTy) {
2736   if (TypeIdx != 0)
2737     return UnableToLegalize;
2738 
2739   unsigned CondReg = MI.getOperand(1).getReg();
2740   LLT CondTy = MRI.getType(CondReg);
2741   if (CondTy.isVector()) // TODO: Handle vselect
2742     return UnableToLegalize;
2743 
2744   unsigned DstReg = MI.getOperand(0).getReg();
2745   LLT DstTy = MRI.getType(DstReg);
2746 
2747   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2748   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2749   SmallVector<unsigned, 4> Src2Regs, Src2LeftoverRegs;
2750   LLT LeftoverTy;
2751   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
2752                     Src1Regs, Src1LeftoverRegs))
2753     return UnableToLegalize;
2754 
2755   LLT Unused;
2756   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
2757                     Src2Regs, Src2LeftoverRegs))
2758     llvm_unreachable("inconsistent extractParts result");
2759 
2760   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2761     auto Select = MIRBuilder.buildSelect(NarrowTy,
2762                                          CondReg, Src1Regs[I], Src2Regs[I]);
2763     DstRegs.push_back(Select->getOperand(0).getReg());
2764   }
2765 
2766   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2767     auto Select = MIRBuilder.buildSelect(
2768       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
2769     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
2770   }
2771 
2772   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2773               LeftoverTy, DstLeftoverRegs);
2774 
2775   MI.eraseFromParent();
2776   return Legalized;
2777 }
2778 
2779 LegalizerHelper::LegalizeResult
2780 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2781   unsigned Opc = MI.getOpcode();
2782   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2783   auto isSupported = [this](const LegalityQuery &Q) {
2784     auto QAction = LI.getAction(Q).Action;
2785     return QAction == Legal || QAction == Libcall || QAction == Custom;
2786   };
2787   switch (Opc) {
2788   default:
2789     return UnableToLegalize;
2790   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
2791     // This trivially expands to CTLZ.
2792     Observer.changingInstr(MI);
2793     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
2794     Observer.changedInstr(MI);
2795     return Legalized;
2796   }
2797   case TargetOpcode::G_CTLZ: {
2798     unsigned SrcReg = MI.getOperand(1).getReg();
2799     unsigned Len = Ty.getSizeInBits();
2800     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
2801       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
2802       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
2803                                              {Ty}, {SrcReg});
2804       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2805       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2806       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2807                                           SrcReg, MIBZero);
2808       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2809                              MIBCtlzZU);
2810       MI.eraseFromParent();
2811       return Legalized;
2812     }
2813     // for now, we do this:
2814     // NewLen = NextPowerOf2(Len);
2815     // x = x | (x >> 1);
2816     // x = x | (x >> 2);
2817     // ...
2818     // x = x | (x >>16);
2819     // x = x | (x >>32); // for 64-bit input
2820     // Upto NewLen/2
2821     // return Len - popcount(x);
2822     //
2823     // Ref: "Hacker's Delight" by Henry Warren
2824     unsigned Op = SrcReg;
2825     unsigned NewLen = PowerOf2Ceil(Len);
2826     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
2827       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
2828       auto MIBOp = MIRBuilder.buildInstr(
2829           TargetOpcode::G_OR, {Ty},
2830           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
2831                                      {Op, MIBShiftAmt})});
2832       Op = MIBOp->getOperand(0).getReg();
2833     }
2834     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
2835     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2836                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
2837     MI.eraseFromParent();
2838     return Legalized;
2839   }
2840   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
2841     // This trivially expands to CTTZ.
2842     Observer.changingInstr(MI);
2843     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
2844     Observer.changedInstr(MI);
2845     return Legalized;
2846   }
2847   case TargetOpcode::G_CTTZ: {
2848     unsigned SrcReg = MI.getOperand(1).getReg();
2849     unsigned Len = Ty.getSizeInBits();
2850     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
2851       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
2852       // zero.
2853       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
2854                                              {Ty}, {SrcReg});
2855       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2856       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2857       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2858                                           SrcReg, MIBZero);
2859       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2860                              MIBCttzZU);
2861       MI.eraseFromParent();
2862       return Legalized;
2863     }
2864     // for now, we use: { return popcount(~x & (x - 1)); }
2865     // unless the target has ctlz but not ctpop, in which case we use:
2866     // { return 32 - nlz(~x & (x-1)); }
2867     // Ref: "Hacker's Delight" by Henry Warren
2868     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
2869     auto MIBNot =
2870         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
2871     auto MIBTmp = MIRBuilder.buildInstr(
2872         TargetOpcode::G_AND, {Ty},
2873         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
2874                                        {SrcReg, MIBCstNeg1})});
2875     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
2876         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
2877       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
2878       MIRBuilder.buildInstr(
2879           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2880           {MIBCstLen,
2881            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
2882       MI.eraseFromParent();
2883       return Legalized;
2884     }
2885     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
2886     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
2887     return Legalized;
2888   }
2889   }
2890 }
2891